JP2927982B2 - 半導体装置 - Google Patents

半導体装置

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Publication number
JP2927982B2
JP2927982B2 JP3078561A JP7856191A JP2927982B2 JP 2927982 B2 JP2927982 B2 JP 2927982B2 JP 3078561 A JP3078561 A JP 3078561A JP 7856191 A JP7856191 A JP 7856191A JP 2927982 B2 JP2927982 B2 JP 2927982B2
Authority
JP
Japan
Prior art keywords
chip
layer
stress
semiconductor device
modulus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3078561A
Other languages
English (en)
Other versions
JPH04363032A (ja
Inventor
素直 福武
実 畠山
芳人 羽崎
明 浦上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JAPAN GOATETSUKUSU KK
Original Assignee
JAPAN GOATETSUKUSU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JAPAN GOATETSUKUSU KK filed Critical JAPAN GOATETSUKUSU KK
Priority to JP3078561A priority Critical patent/JP2927982B2/ja
Priority to DE69219509T priority patent/DE69219509T2/de
Priority to EP92103777A priority patent/EP0504669B1/en
Publication of JPH04363032A publication Critical patent/JPH04363032A/ja
Application granted granted Critical
Publication of JP2927982B2 publication Critical patent/JP2927982B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置に係り、実装
時および実使用時におけるなどの急激な温度変化により
生ずる熱応力や外部からの機械的応力による半導体素子
の誤動作及びクラックの発生ないし破壊を適切に防止し
優質な製品を提供しようとするものである。
【０００２】
【従来の技術】ＩＣパッケージと称される従来の半導体
装置は図６に示すようにＩＣチップ（１）をダイパッド
（３）に対し半田、Agペースト、硬質エポキシ樹脂など
のダイボンディング材（１８）によって接合し、これを
樹脂によって封止したものであって、近年における電子
機器の小型化、高性能化に伴い、薄型、且つ小型化され
た表面実装型ＩＣパッケージなどとして広く普及されて
いる。
【０００３】然し上記したような従来のものにおいては
そのダイボンディング材（１８）におけるヤング率が高
いため温度差によって生ずる図４の（ａ）（ｂ）のよう
にＩＣチップ（１）に大きな熱応力が生じ、該ＩＣチッ
プ（１）の誤動作および破壊が発生する。又図５の
（ａ）（ｃ）に示すようにパッケージ（１７）の下部お
よび上部から外力が加わった場合に、ダイボンディング
材（１８）がＩＣチップ（１）とダイパッド（３）を強
く拘束している為、ＩＣチップ（１）が反り易くＩＣチ
ップの破壊を招き易い。
【０００４】上記のような課題に対処すべく、特開昭６
２−２１０６３０および特開昭６２−２１０６３１にお
いては前記ダイボンディング材（１８）にヤング率の低
いゴム状弾性体を用い、熱応力については図４（ｃ）
（ｄ）に示すように温度差で生じた応力をＩＣチップに
伝えないようにし、又外部からの機械応力については図
５（ｂ）（ｄ）に示すようにダイボンディング材（１
８）自体が変形してＩＣチップに生ずる応力を緩和して
いる。
【０００５】
【発明が解決しようとする課題】ところが前記したよう
な特開昭６２−２１０６３０および同２１０６３１の技
術によるときは、ヤング率の低いゴム状弾性材であるダ
イボンディング材（１８）によるワイヤボンディングの
歩留りが低減する。更に、図７に示すようなＩＣチップ
裏面のバックグラインドにより生じるクラックの発生原
因となり易いノッチ（２１）を強固にカバーができない
ので、ＩＣチップ（１）の表面が凹み状態に反った場合
にノッチ（２１）からクラック（２０）が生じ易いとい
う欠点がある。
【０００６】
【課題を解決するための手段】本発明は上記したような
従来のものにおける課題を解決することについて検討を
重ね、熱的応力および機械的応力の如きの何れに対して
も有効に即応せしめ、ＩＣチップの誤動作及びクラック
の発生原因を解消することに成功したものであって，以
下の如くである。
【０００７】（１） ＩＣチップなどの半導体素子を基
材に支持せしめた半導体装置において、前記半導体素子
と基材との間に多孔質ポリテトラフルオロエチレン層を
設けたことを特徴とする半導体装置。
【０００８】（２） 多孔質ポリテトラフルオロエチレ
ン層に熱硬化型樹脂がコーティングまたは含浸の何れか
一方または双方によって附着されたダイボンディング層
を形成した前記（１）項に記載の半導体装置。
【０００９】（３） ダイボンディング層に無機質フィ
ラーを含有させてなる前記（２）項に記載の半導体装
置。
【００１０】
【作用】ＩＣチップなどの半導体素子を基材に支持せし
めた半導体装置において、前記半導体素子と基材との間
に多孔質ポリテトラフルオロエチレン層を設けることに
より多孔質ポリテトラフルオロエチレンによる比較的低
い２〜４０kgf/mm2 のヤング率の層が介在することにな
り、該層によってＩＣチップ内部に生ずる応力を低減
し、従って半導体装置の信頼性を向上する。
【００１１】多孔質ポリテトラフルオロエチレン層に熱
硬化型樹脂がコーティングまたは含浸の何れか一方また
は双方によって附着されたダイボンディング層を形成し
たことにより温度変化によるダイパッドのようなＩＣチ
ップ支持基材の伸びをこのダイボンディング層によって
吸収し、又、外力によるＩＣチップの曲がりなども同様
に緩和吸収する。
【００１２】前記ダイボンディング層としてヤング率の
比較的大きいエポキシレジン層を形成することにより、
ヤング率が低くて延伸などにより機械特性に優れたポリ
テトラフルオロエチレン多孔質材との併用によりＩＣチ
ップ裏面のバックグラインドなどに原因した粗度の大き
いノッチ部条件下において有効な接着状態形成と変形応
力緩和を共に達成する。
【００１３】前記ダイボンディング層に無機質フィラー
を含有させることにより熱伝導率や電気伝導性などの特
性を調整、向上させる。
【００１４】
【実施例】上記したような本発明によるものの具体的な
実施態様を添附図面に示すものについて説明すると、図
１に示すようにダイパッドのような基体（３）上に半導
体素子（ＩＣチップなど）（１）を設け、該半導体素子
（１）の電極とリードフレーム（２）とを金ワイヤ
（７）で結線し、これらのものをモールドレジン（４）
に被包することは前記した従来からのものと同じである
が、本発明においては前記のような基体（３）と半導体
素子（１）との間にフッ素樹脂多孔質体である多孔質ポ
リテトラフルオロエチレン層（５）を介装せしめたもの
である。
【００１５】前記した多孔質ポリテトラフルオロエチレ
ン層（５）としてはポリテトラフルオロエチレン膜を延
伸加工して多孔質化した部材が好ましく、このものは２
μm以下の微細な孔隙を形成し気孔率４０〜９５％、特
に６０〜８０％程度として適切に得られ、その微細な孔
隙は蒸気その他の気体を透過せしめるが、液体を透過せ
しめることがなく、しかも延伸による繊維化で機械特性
に優れ、そのヤング率は前記したように２〜４０kgf/mm
2 と比較的低いものとして得られる。
【００１６】前記した多孔質ポリテトラフルオロエチレ
ン層（５）による応力低減関係は、図４に示すようにSi
による半導体素子（１）の線膨脹係数αSi＝３×１０-6
deg-1に対してメタルより成る基材（３）の線膨脹係数
はαDi＝１７×１０-6 deg-1と大きく、この差により熱
応力が発生するが、斯様な熱応力を前記層（５）で適切
に吸収する。この層がヤング率の高いものであると、温
度上昇時に図４（ａ）に示すように半導体素子（１）の
裏面に大きな引張応力が生じ、素子（１）にクラックが
発生する。
【００１７】これを具体的に言うと、一般的にSiチップ
は圧縮応力についてはその破壊限が５０kgf/mm2 程度と
高いが、引張応力についての破壊限は１０kgf/mm2 程度
と低い。従ってSiチップのような半導体素子（１）はこ
の引張応力の破壊限を超えるとクラックが発生すること
になるが、上記のようにヤング率の低い層（５）を用い
ると温度が上昇した場合は図４（ｃ）に示すように基材
（３）の伸びを層（５）において吸収し、これによって
素子（１）の上面および下面の何れにおいても大きな応
力を生じさせない。温度が降下した場合においても同様
であって基材（３）の縮みを大きく縮減して素子（１）
に伝えチップを損傷することがない。
【００１８】外部からの機械的な力が加わった場合も同
様であって、ヤング率の大きい半田、エポキシレジンな
どのみの場合にはＩＣパッケージの下部からの外部力に
より基材（３）とＩＣチップのような半導体素子（１）
とが一体となって素子（１）の上面が凸状となるように
反り、素子（１）の表面に大きな引張応力を発生せしめ
クラックが発生する。又ＩＣパッージの上部からの外部
力によっては素子（１）と基材（３）が同様に一体的と
なって、素子（１）の裏面が凸状になるように反り、素
子（１）の裏面に大きな引張応力が発生してクラックが
生ずる。
【００１９】これに対しヤング率の低い多孔質ポリテト
ラフルオロエチレン層（５）が存在する本発明の場合に
はＩＣパッケージの下部から機械的な外力が加わり、基
材（３）が彎曲しても該層（５）において吸収し、素子
（１）が反るのを緩和できる。又ＩＣパッケージの上部
からの外部力に対しても前記層（５）によって素子
（１）の裏面が凸状に反ることを緩和することができ
る。
【００２０】なおＩＣチップの裏面は、その製造工程で
バックグラインドを行うことが一般的であり、表面に比
し粗さが大きく、そのノッチがクラック発生源となり易
いので、このＩＣチップ裏面に引張応力が生じた場合に
は表面の場合の半分程度で破壊に到る。このことからＩ
Ｃチップを強化するにはその裏面におけるノッチ部を接
着力が大で且つヤング率の比較的大きい材料で埋めるこ
とが有効となる。
【００２１】即ち本発明では図７（ｂ）のようにヤング
率の高いエポキシレジン層（８）とヤング率の低い前記
層（５）とサンドイッチ構造を採ったダイボンディング
部（１８）を形成し、素子（１）裏面のノッチ部はヤン
グ率の高いエポキシレジンで埋め、しかもＩＣチップの
変形は層（５）で緩和する相乗効果を得しめることは前
述の通りである。
【００２２】具体的な製造例として、図２に示すように
暑さ２０μm の多孔質ポリテトラフルオロエチレン層
（５）に対し、その表裏に暑さ５μm のエポキシレジン
層（８）を設けたものを用い、図１のような製品を得
た。素子（１）は基材（３）に対し上記層（５）を介し
て接着したもので、接合方法は加熱ステージ上にリード
フレーム（２）を乗せ、これに上記ダイボンディング材
（１８）およびＩＣチップである素子（１）を置いてエ
ポキシレジンを加熱硬化させた。
【００２３】これによって素子（１）裏面のノッチをカ
バーして強化し、しかも多孔質ポリテトラフルオロエチ
レンの変形作用で応力を緩和することは前記の如くで、
ＩＣチップの破壊限界を大幅に向上することができた。
【００２４】又前記層（５）およびエポキシレジン層
（８）の何れか一方または双方にSiO2などのセラミック
フィラーを混入して熱伝導率を向上させ、あるいはNi、
Ti、Cuなどの金属粉を混入して電気伝導性を有するよう
にした。
【００２５】更にワイヤボンディングおよびトランスフ
ァーモールドの歩留りを高めるべく、上記ボンディング
部（１８）全体のヤング率を若干高めるように多孔質ポ
リテトラフルオロエチレン層の孔隙の一部にエポキシレ
ジン、ポリイミド樹脂などを含浸させたものとした。
【００２６】図２に示すように両面にエポキシレジンを
コートした多孔質ポリテトラフルオロエチレンによるダ
イボンディング材（１８）を用いてプリント配線基板
（９）上に直接ＩＣチップをＣＯＢ（Chip on Board ）
方式で実装したところ、ＩＣチップ（１）に生ずる応力
を大幅に低減し、クラック発生などを見ない好ましい図
３に示すような実装製品を得ることができた。
【００２７】
【発明の効果】以上説明したような本発明によるとき
は、ＩＣチップに生じる熱的および機械的応力を適切に
解消し、素子の誤動作及びクラックの発生を的確に防止
し、良好な特性を維持し、信頼性の高い製品を提供し得
るものであるから工業的にその効果の大きい発明であ
る。
【図面の簡単な説明】
【図１】本発明による半導体装置の１例についての断面
図である。
【図２】図１中ダイボンディング部についての要部拡大
図である。
【図３】ＣＯＢ用配線基板において本発明を実施した例
についての断面図である。
【図４】と
【図５】本発明によるＩＣチップ応力緩和のメカニズム
についての説明図である。
【図６】従来のＩＣパッケージについての構造を示した
断面図である。
【図７】本発明によるＩＣチップなどの半導体素子破壊
限界応力向上を理論的に説明した説明図である。
【符号の説明】
１ ＩＣチップなどの半導体素子 ２ リードフレーム ３ ダイパッドなどの基材 ４ モールドレジン ５ 多孔質ポリテトラフルオロエチレン ６ 外部端子 ７ Auワイヤ ８ エポキシレジン １０ 配線パターン １１ 絶縁層 １２ スルーホール １３ チップ抵抗 １４ チップコンデンサー １５ チップダイオード １６ ハンダ接合部 １７ プラスチックＩＣパッケージ １８ ダイボンディング材 １９ シリコンゴム ２０ クラック ２１ ノッチ
フロントページの続き (56)参考文献 特開 昭59−32141（ＪＰ，Ａ) 特開 平１−129423（ＪＰ，Ａ) 特開 昭60−102750（ＪＰ，Ａ) 特開 昭58−112335（ＪＰ，Ａ) 特開 平３−44040（ＪＰ，Ａ) 特開 平４−726（ＪＰ，Ａ) 特開 平３−68149（ＪＰ，Ａ) 特開 平１−307236（ＪＰ，Ａ) 特開 平２−205332（ＪＰ，Ａ) 実開 平２−120840（ＪＰ，Ｕ) 実開 昭51−121173（ＪＰ，Ｕ) 実開 昭63−127129（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/52

Claims (3)

    (57)【特許請求の範囲】
  1. 【請求項１】 ＩＣチップなどの半導体素子を基材に支
    持せしめた半導体装置において、前記半導体素子と基材
    との間に多孔質ポリテトラフルオロエチレン層を設けた
    ことを特徴とする半導体装置。
  2. 【請求項２】 多孔質ポリテトラフルオロエチレン層に
    熱硬化型樹脂がコーティングまたは含浸の何れか一方ま
    たは双方によって附着されたダイボンディング層を形成
    した請求項１に記載の半導体装置。
  3. 【請求項３】 ダイボンディング層に無機質フィラーを
    含有させてなる請求項２に記載の半導体装置。
JP3078561A 1991-03-18 1991-03-18 半導体装置 Expired - Lifetime JP2927982B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP3078561A JP2927982B2 (ja) 1991-03-18 1991-03-18 半導体装置
DE69219509T DE69219509T2 (de) 1991-03-18 1992-03-05 Halbleiteranordnung mit Substrat
EP92103777A EP0504669B1 (en) 1991-03-18 1992-03-05 Semiconductor device comprising a substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3078561A JP2927982B2 (ja) 1991-03-18 1991-03-18 半導体装置

Publications (2)

Publication Number Publication Date
JPH04363032A JPH04363032A (ja) 1992-12-15
JP2927982B2 true JP2927982B2 (ja) 1999-07-28

Family

ID=13665322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3078561A Expired - Lifetime JP2927982B2 (ja) 1991-03-18 1991-03-18 半導体装置

Country Status (3)

Country Link
EP (1) EP0504669B1 (ja)
JP (1) JP2927982B2 (ja)
DE (1) DE69219509T2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014165459A (ja) * 2013-02-27 2014-09-08 Ngk Spark Plug Co Ltd 支持装置

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JPH0677447A (ja) * 1992-08-26 1994-03-18 Seiko Instr Inc 半導体薄膜素子の製造方法
CH686325A5 (de) * 1992-11-27 1996-02-29 Esec Sempac Sa Elektronikmodul und Chip-Karte.
KR100507584B1 (ko) * 1996-10-08 2005-08-10 히다치 가세고교 가부시끼가이샤 반도체 장치, 반도체칩 탑재용 기판, 이들의 제조법,접착제, 및 양면 접착 필름
JP3639088B2 (ja) 1997-06-06 2005-04-13 株式会社ルネサステクノロジ 半導体装置及び配線テープ
US6269690B1 (en) 1998-05-08 2001-08-07 Bridgestone Corporation Method for estimating a tire wear life
JP3661444B2 (ja) * 1998-10-28 2005-06-15 株式会社ルネサステクノロジ 半導体装置、半導体ウエハ、半導体モジュールおよび半導体装置の製造方法
DE10015964C2 (de) * 2000-03-30 2002-06-13 Infineon Technologies Ag Lotband für flexible und temperaturfeste Lotverbindungen
DE10015962C2 (de) * 2000-03-30 2002-04-04 Infineon Technologies Ag Hochtemperaturfeste Lotverbindung für Halbleiterbauelement
JP4545956B2 (ja) * 2001-01-12 2010-09-15 ローム株式会社 半導体装置、およびその製造方法
JP2003003134A (ja) * 2001-06-20 2003-01-08 Japan Gore Tex Inc Ｉｃチップ接着用シートおよびｉｃパッケージ
JP2003298196A (ja) 2002-04-03 2003-10-17 Japan Gore Tex Inc プリント配線板用誘電体フィルム、多層プリント基板および半導体装置

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EP0051165A1 (en) * 1980-11-03 1982-05-12 BURROUGHS CORPORATION (a Michigan corporation) Repairable IC package with thermoplastic chip attach
JPS61296749A (ja) * 1985-06-25 1986-12-27 Toray Silicone Co Ltd 半導体装置用リードフレームの製造方法
JPS62210630A (ja) * 1986-03-12 1987-09-16 Hitachi Ltd 半導体装置
JPS62210631A (ja) * 1986-03-12 1987-09-16 Hitachi Micro Comput Eng Ltd 半導体装置
CA1290676C (en) * 1987-03-30 1991-10-15 William Frank Graham Method for bonding integrated circuit chips
DE3907261C2 (de) * 1989-03-07 2001-04-05 Nematel Dr Rudolf Eidenschink Klebstoff
JP3061059B2 (ja) * 1989-08-07 2000-07-10 ジャパンゴアテックス株式会社 Ｉｃパッケージ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014165459A (ja) * 2013-02-27 2014-09-08 Ngk Spark Plug Co Ltd 支持装置

Also Published As

Publication number Publication date
JPH04363032A (ja) 1992-12-15
DE69219509D1 (de) 1997-06-12
DE69219509T2 (de) 1998-01-02
EP0504669B1 (en) 1997-05-07
EP0504669A1 (en) 1992-09-23

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