WO2022244802A1 - 半導体装置および製造方法 - Google Patents

半導体装置および製造方法 Download PDF

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Publication number
WO2022244802A1
WO2022244802A1 PCT/JP2022/020666 JP2022020666W WO2022244802A1 WO 2022244802 A1 WO2022244802 A1 WO 2022244802A1 JP 2022020666 W JP2022020666 W JP 2022020666W WO 2022244802 A1 WO2022244802 A1 WO 2022244802A1
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Prior art keywords
region
contact
trench
plug
plug portion
Prior art date
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Ceased
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PCT/JP2022/020666
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English (en)
French (fr)
Japanese (ja)
Inventor
晴司 野口
竜太郎 浜崎
大輔 尾崎
洋輔 桜井
拓弥 山田
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to DE112022000141.0T priority Critical patent/DE112022000141T5/de
Priority to CN202280007098.6A priority patent/CN116348995A/zh
Priority to JP2023522695A priority patent/JP7468786B2/ja
Publication of WO2022244802A1 publication Critical patent/WO2022244802A1/ja
Priority to US18/304,378 priority patent/US12527016B2/en
Anticipated expiration legal-status Critical
Priority to JP2024059803A priority patent/JP2024084795A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/133—Emitter regions of BJTs
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/231—Emitter or collector electrodes for bipolar transistors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/422—PN diodes having the PN junctions in mesas

Definitions

  • the present invention relates to semiconductor devices and manufacturing methods.
  • Patent Document 1 International Publication No. 2018/052099
  • a first aspect of the present invention provides a semiconductor device.
  • a semiconductor device may comprise a semiconductor substrate having a top surface and a bottom surface and having a drift region of a first conductivity type.
  • the semiconductor device may comprise a base region of the second conductivity type provided between the top surface and the drift region.
  • the semiconductor device may include a gate trench portion extending from the upper surface to the drift region and extending in the longitudinal direction on the upper surface.
  • the semiconductor device may include a first conductivity type emitter region provided between the upper surface and the base region and in contact with the gate trench portion.
  • the semiconductor device may include contact regions of the second conductivity type provided between the upper surface and the base region and alternately arranged with the emitter regions in the longitudinal direction of the gate trench portion.
  • the semiconductor device may comprise a first trench contact portion extending from the top surface to the inside of the contact region.
  • the semiconductor device may comprise a second trench contact extending from the top surface to the interior of the emitter region.
  • the semiconductor device may include a first plug portion of the second conductivity type provided in contact with the lower end of the first trench contact portion and having a higher concentration than the base region.
  • the semiconductor device includes a second plug portion of the second conductivity type having a concentration higher than that of the base region, the second plug portion being in contact with the lower end of the second trench contact portion and extending to the lower surface side than the first plug portion. you can
  • the contact region, the first plug portion and the second plug portion may contain acceptors of the same element.
  • the lower end of the second plug portion may be arranged on the lower surface side than the lower end of the emitter region.
  • the lower end of the second plug portion may be arranged on the upper surface side with respect to the lower end of the contact region.
  • the lower end of the first plug portion may be arranged at the same depth as the lower end of the contact region or above the lower end of the contact region.
  • the depth position of the lower end of the second plug portion may be arranged on the lower surface side by 0.1 ⁇ m or more from the depth position of the lower end of the first plug portion.
  • the depth position of the lower end of the second plug portion may be arranged on the lower surface side by 0.3 ⁇ m or more from the depth position of the lower end of the first plug portion.
  • the peak value of the acceptor concentration of the second plug portion may be smaller than the peak value of the acceptor concentration of the first plug portion.
  • the semiconductor device may include a trench section provided adjacent to the gate trench section in the arrangement direction perpendicular to the longitudinal direction, provided from the upper surface to the drift region, and extending in the longitudinal direction.
  • the semiconductor device may include a gate trench portion and a mesa portion sandwiched between the trench portions.
  • the width of the mesa portion in the arrangement direction may be smaller than the width of the gate trench portion.
  • the first plug portion may have a first portion in contact with the side surface of the first trench contact portion.
  • the second plug portion may have a second portion contacting a side surface of the second trench contact portion.
  • the width of the second portion may be smaller than the width of the first portion.
  • the first plug portion and the second plug portion may contain boron.
  • the semiconductor substrate may comprise silicon.
  • a silicide portion may be provided at a boundary between the first trench contact portion and the second trench contact portion and the semiconductor substrate.
  • the silicide portion may contain boron.
  • a second aspect of the present invention provides a semiconductor device.
  • the semiconductor device may comprise a semiconductor substrate having a top surface and a bottom surface and having a drift region of a first conductivity type.
  • the semiconductor device may comprise a base region of the second conductivity type provided between the upper surface and the drift region.
  • Any one of the above semiconductor devices may include a gate trench portion extending from the upper surface to the drift region and extending in the longitudinal direction on the upper surface.
  • Any one of the above semiconductor devices may include a first conductivity type emitter region provided between the upper surface and the base region and in contact with the gate trench portion.
  • Any one of the above semiconductor devices may include contact regions of the second conductivity type provided between the upper surface and the base region and alternately arranged with the emitter regions in the longitudinal direction of the gate trench portion.
  • any of the above semiconductor devices may comprise a trench contact portion provided from the top surface to the inside of the contact region and from the top surface to the inside of the emitter region.
  • Any one of the semiconductor devices described above may include a plug portion of the second conductivity type provided in contact with the lower end of the trench contact portion, having a higher concentration than the base region and provided shallower than the contact region.
  • the trench contact portion may include a first trench contact portion provided from the upper surface to the inside of the contact region. In any one of the semiconductor devices described above, the trench contact portion may include a second trench contact portion provided from the upper surface to the inside of the emitter region. In any one of the semiconductor devices described above, the plug portion may include a first plug portion provided in contact with a lower end of the first trench contact portion. In any one of the above semiconductor devices, the plug portion may include a second plug portion provided in contact with the lower end of the second trench contact portion and provided to the same depth as the first plug portion.
  • the trench contact portion may include a first trench contact portion provided from the upper surface to the inside of the contact region. In any one of the semiconductor devices described above, the trench contact portion may include a second trench contact portion provided from the upper surface to the inside of the emitter region. In any one of the semiconductor devices described above, the plug portion may include a first plug portion provided in contact with a lower end of the first trench contact portion. In any one of the semiconductor devices described above, the plug portion may include a second plug portion provided in contact with the lower end of the second trench contact portion and extending to a lower surface side than the first plug portion.
  • a third aspect of the present invention provides a method of manufacturing a semiconductor device.
  • a manufacturing method includes: a semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region; a second conductivity type base region provided between the upper surface and the drift region; and a drift region extending from the upper surface.
  • a gate trench portion provided on the upper surface and extending in the longitudinal direction; an emitter region of a first conductivity type provided between the upper surface and the base region and in contact with the gate trench portion; and forming contact regions of the second conductivity type interleaved with the emitter regions in the longitudinal direction of the gate trench portion.
  • the manufacturing method may comprise a trench forming step of forming a first trench contact extending from the top surface to the interior of the contact region and a second trench contact extending from the top surface to the interior of the emitter region.
  • the method may comprise a plug implant step of implanting a dopant of the second conductivity type into the semiconductor substrate through the first trench contact and the second trench contact.
  • the semiconductor substrate is annealed, and the first plug portion of the second conductivity type in contact with the lower end of the first trench contact portion and the lower end of the second trench contact portion are in contact with the lower surface side of the first plug portion.
  • a plug anneal step may be included to form a provided second plug portion of the second conductivity type.
  • FIG. 1 is an example of a top view of a semiconductor device 100;
  • FIG. 2 is an enlarged view of area A in FIG. 1;
  • FIG. 3 is a diagram showing an example of a cc cross section in FIG. 2;
  • FIG. 3 is a diagram showing an example of a bb cross section in FIG. 2; It is a diagram showing a bb cross section and a cc cross section side by side.
  • FIG. 3 is a diagram showing an example of a dd cross section in FIG. 2;
  • FIG. 10 is a diagram showing another example of the bb cross section and the cc cross section;
  • 3 is a diagram showing another example of the dd cross section in FIG. 2;
  • FIG. 3 is a diagram showing another example of the dd cross section in FIG. 2;
  • FIG. FIG. 10 is a diagram showing another example of the bb cross section and the cc cross section;
  • FIG. 4 is an enlarged view of the vicinity of a second trench contact portion 54-2 and a second plug portion 202;
  • 3 is an enlarged view of the vicinity of a first trench contact portion 54-1 and a first plug portion 201;
  • FIG. FIG. 10 is a diagram showing another example of the vicinity of the second trench contact portion 54-2 and the second plug portion 202;
  • 4A to 4C are diagrams illustrating an example of a method for manufacturing the semiconductor device 100;
  • FIG. 4A to 4C are diagrams illustrating an example of a method for manufacturing the semiconductor device 100;
  • FIG. 12C is a diagram showing an example of acceptor concentration distribution along the ee line and the ff line in FIG. 12B.
  • FIG. FIG. 3 is a diagram showing an example of an ee cross section in
  • the unit system in this specification is the SI unit system unless otherwise specified.
  • the unit of length is sometimes displayed in cm, but various calculations may be performed after converting to meters (m).
  • one side in a direction parallel to the depth direction of the semiconductor substrate is called “upper”, and the other side is called “lower”.
  • One of the two main surfaces of a substrate, layer or other member is called the upper surface and the other surface is called the lower surface.
  • the directions of “up” and “down” are not limited to the direction of gravity or the direction when the semiconductor device is mounted.
  • the Cartesian coordinate axes only specify the relative positions of the components and do not limit any particular orientation.
  • the Z axis does not limit the height direction with respect to the ground.
  • the +Z-axis direction and the ⁇ Z-axis direction are directions opposite to each other.
  • the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.
  • orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are defined as the X-axis and the Y-axis.
  • the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis.
  • the Z-axis direction may be referred to as the depth direction.
  • a direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis may be referred to as a horizontal direction.
  • the term "upper surface side of the semiconductor substrate” refers to a region from the center to the upper surface in the depth direction of the semiconductor substrate. When the lower surface side of the semiconductor substrate is referred to, it means a region from the center to the lower surface in the depth direction of the semiconductor substrate.
  • the conductivity type of the doping region doped with impurities is described as P-type or N-type.
  • impurities may specifically refer to either N-type donors or P-type acceptors, and may also be referred to as dopants.
  • doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.
  • doping concentration means the concentration of donors or the concentration of acceptors at thermal equilibrium.
  • the net doping concentration means the net concentration including charge polarity, where the donor concentration is the positive ion concentration and the acceptor concentration is the negative ion concentration.
  • the donor concentration is N D and the acceptor concentration is N A , then the net net doping concentration at any location is N D ⁇ N A.
  • a donor has the function of supplying electrons to a semiconductor.
  • the acceptor has the function of receiving electrons from the semiconductor.
  • Donors and acceptors are not limited to impurities per se. For example, VOH defects in which vacancies (V), oxygen (O), and hydrogen (H) are combined in semiconductors function as donors that supply electrons.
  • references herein to P-type or N-type refer to higher doping concentrations than P-type or N-type; references to P-type or N-type refer to higher doping than P-type or N-type. It means that the concentration is low.
  • the term P++ type or N++ type in this specification means that the doping concentration is higher than that of the P+ type or N+ type.
  • chemical concentration refers to the atomic density of impurities measured regardless of the state of electrical activation.
  • Chemical concentrations can be measured, for example, by secondary ion mass spectroscopy (SIMS).
  • the net doping concentrations mentioned above can be measured by the voltage-capacitance method (CV method).
  • the carrier density measured by the spreading resistance measurement method (SR method) may be used as the net doping concentration.
  • the carrier density measured by the CV method or SR method may be a value in thermal equilibrium.
  • the donor concentration is sufficiently higher than the acceptor concentration in the N-type region, the carrier density in the region may be used as the donor concentration.
  • the carrier density in that region may be used as the acceptor concentration.
  • the peak value may be the concentration of donors, acceptors, or net doping in the region.
  • the average value of the concentration of donors, acceptors or net doping in the region may be used as the concentration of donors, acceptors or net doping.
  • the carrier density measured by the SR method may be lower than the donor or acceptor concentration.
  • the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state.
  • a decrease in carrier mobility is caused by scattering of carriers due to disorder of the crystal structure due to lattice defects or the like.
  • the donor or acceptor concentration calculated from the carrier density measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor.
  • the donor concentration of phosphorus or arsenic as a donor or the acceptor concentration of boron (boron) as an acceptor in a silicon semiconductor is about 99% of these chemical concentrations.
  • the donor concentration of hydrogen serving as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.
  • FIG. 1 is a top view showing an example of a semiconductor device 100.
  • FIG. FIG. 1 shows the positions of each member projected onto the upper surface of the semiconductor substrate 10 .
  • FIG. 1 only some members of the semiconductor device 100 are shown, and some members are omitted.
  • a semiconductor device 100 includes a semiconductor substrate 10 .
  • the semiconductor substrate 10 is a substrate made of a semiconductor material.
  • the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.
  • the semiconductor substrate 10 has an edge 102 when viewed from above.
  • simply referring to a top view means viewing from the top side of the semiconductor substrate 10 .
  • the semiconductor substrate 10 of this example has two sets of edges 102 facing each other when viewed from above.
  • the X-axis and Y-axis are parallel to one of the edges 102 .
  • the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10 .
  • An active portion 160 is provided on the semiconductor substrate 10 .
  • the active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 operates.
  • An emitter electrode is provided above the active portion 160, but is omitted in FIG.
  • the active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor) and a diode section 80 including a diode element such as a FWD (Free Wheeling Diode).
  • the transistor portions 70 and the diode portions 80 are alternately arranged along a predetermined arrangement direction (X-axis direction in this example) on the upper surface of the semiconductor substrate 10 .
  • active portion 160 may include only one of transistor portion 70 and diode portion 80 .
  • the region where the transistor section 70 is arranged is denoted by the symbol "I”
  • the region where the diode section 80 is arranged is denoted by the symbol "F”.
  • the direction perpendicular to the arrangement direction in top view may be referred to as the stretching direction (the Y-axis direction in FIG. 1).
  • the transistor section 70 and the diode section 80 may each have a length in the extending direction. That is, the length in the Y-axis direction of the transistor section 70 is greater than the width in the X-axis direction. Similarly, the length in the Y-axis direction of the diode section 80 is greater than the width in the X-axis direction.
  • the extending direction of the transistor portion 70 and the diode portion 80 may be the same as the longitudinal direction of each trench portion described later.
  • the diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10 .
  • the region provided with the cathode region is referred to as the diode section 80 . That is, the diode portion 80 is a region that overlaps with the cathode region when viewed from above.
  • a P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in a region other than the cathode region.
  • the diode section 80 may also include an extension region 81 extending in the Y-axis direction from the diode section 80 to the gate wiring described later.
  • a collector region is provided on the lower surface of the extension region 81 .
  • the transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10 .
  • a gate structure having an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film is periodically arranged on the upper surface side of the semiconductor substrate 10 .
  • the semiconductor device 100 may have one or more pads above the semiconductor substrate 10 .
  • the semiconductor device 100 of this example has a gate pad 112 .
  • Semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is arranged near the edge 102 .
  • the vicinity of the edge 102 refers to a region between the edge 102 and the emitter electrode in top view.
  • each pad may be connected to an external circuit via a wiring such as a wire.
  • a gate potential is applied to the gate pad 112 .
  • Gate pad 112 is electrically connected to the conductive portion of the gate trench portion of active portion 160 .
  • the semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.
  • the gate wiring of this example has a peripheral gate wiring 130 and an active side gate wiring 131 .
  • the peripheral gate wiring 130 is arranged between the active portion 160 and the edge 102 of the semiconductor substrate 10 when viewed from above.
  • the peripheral gate wiring 130 of this example surrounds the active portion 160 when viewed from above.
  • a region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160 .
  • the peripheral gate wiring 130 is connected to the gate pad 112 .
  • the peripheral gate wiring 130 is arranged above the semiconductor substrate 10 .
  • the peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.
  • the active side gate wiring 131 is provided in the active portion 160 .
  • variations in wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10 .
  • the active side gate wiring 131 is connected to the gate trench portion of the active portion 160 .
  • the active-side gate wiring 131 is arranged above the semiconductor substrate 10 .
  • the active-side gate wiring 131 may be a wiring made of a semiconductor such as polysilicon doped with impurities.
  • the active side gate wiring 131 may be connected to the peripheral gate wiring 130 .
  • the active-side gate wiring 131 of this example extends in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 so as to traverse the active portion 160 .
  • the active-side gate wiring 131 may be provided substantially in the center of the active portion 160 in the Y-axis direction.
  • the transistor portions 70 and the diode portions 80 may be alternately arranged in the X-axis direction in each divided region.
  • the semiconductor device 100 also includes a temperature sensing portion (not shown), which is a PN junction diode made of polysilicon or the like, and a current detecting portion (not shown) that simulates the operation of the transistor portion provided in the active portion 160. good too.
  • a temperature sensing portion which is a PN junction diode made of polysilicon or the like
  • a current detecting portion (not shown) that simulates the operation of the transistor portion provided in the active portion 160. good too.
  • the semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the edge 102 in top view.
  • the edge termination structure 90 of this example is arranged between the peripheral gate line 130 and the edge 102 .
  • the edge termination structure 90 reduces electric field concentration on the upper surface side of the semiconductor substrate 10 .
  • the edge termination structure 90 may include at least one of a guard ring 92, a field plate, and a resurf annularly surrounding the active portion 160.
  • FIG. 2 is an enlarged view of area A in FIG. Region A is a region including transistor section 70 , diode section 80 , and active-side gate wiring 131 .
  • the semiconductor device 100 of this example includes a gate trench portion 40 , a dummy trench portion 30 , a well region 11 , an emitter region 12 , a base region 14 and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10 .
  • Each of the gate trench portion 40 and the dummy trench portion 30 is an example of the trench portion.
  • the semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10 . Emitter electrode 52 and active-side gate line 131 are provided separately from each other.
  • An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in FIG.
  • a trench contact portion 54 is provided through the interlayer insulating film.
  • the trench contact portion 54 of this example reaches the inside of the semiconductor substrate 10 .
  • the inside of the trench contact portion 54 is filled with a conductive material.
  • the conductive member inside the trench contact portion 54 may be described herein as part of the emitter electrode 52 .
  • Emitter electrode 52 is connected to semiconductor substrate 10 via trench contact portion 54 .
  • each trench contact portion 54 may be filled with the same material as the emitter electrode 52 provided on the interlayer insulating film, or may be filled with a material different from that of the emitter electrode 52 .
  • each trench contact portion 54 is hatched with oblique lines.
  • the emitter electrode 52 is provided above the gate trench portion 40 , the dummy trench portion 30 , the well region 11 , the emitter region 12 , the base region 14 and the contact region 15 .
  • Emitter electrode 52 is electrically connected to emitter region 12 , contact region 15 and base region 14 on the upper surface of semiconductor substrate 10 via trench contact portion 54 .
  • the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film.
  • the emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.
  • the active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film.
  • the active-side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction.
  • the active-side gate wiring 131 is not connected to the dummy conductive portion within the dummy trench portion 30 .
  • the emitter electrode 52 is made of a material containing metal.
  • FIG. 2 shows the range in which the emitter electrode 52 is provided.
  • the emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like under a region made of a material containing aluminum (Al) or the like.
  • Emitter electrode 52 may comprise tungsten filled within the trench contact. Inside the trench contact, a barrier metal and tungsten may be stacked in order from the side closer to the semiconductor substrate 10 .
  • the emitter electrode 52 on the tungsten and interlayer insulating film may be made of a material containing aluminum.
  • the well region 11 is provided so as to overlap with the active side gate wiring 131 .
  • the well region 11 is also provided extending with a predetermined width in a range not overlapping the active side gate wiring 131 .
  • the well region 11 of this example is provided away from the end of the trench contact portion 54 in the Y-axis direction toward the active-side gate wiring 131 side.
  • the well region 11 is a second conductivity type region having a higher doping concentration than the base region 14 .
  • the base region 14 in this example is of P ⁇ type and the well region 11 is of P+ type.
  • Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction.
  • one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction.
  • a plurality of dummy trench portions 30 are provided along the array direction in the diode portion 80 of this example.
  • the gate trench portion 40 is not provided in the diode portion 80 of this example.
  • the gate trench portion 40 of this example connects the two straight portions 39 extending along the extending direction perpendicular to the arrangement direction (the portion of the trench that is linear along the extending direction) and the two straight portions 39 . It may have a tip 41 .
  • the stretching direction in FIG. 2 is the Y-axis direction.
  • the longitudinal direction of the gate trench portion 40 is the same as the extending direction.
  • At least a portion of the tip portion 41 is preferably provided in a curved shape when viewed from above.
  • the dummy trench portions 30 are provided between the respective straight portions 39 of the gate trench portions 40 .
  • One dummy trench portion 30 may be provided between the straight portions 39, or a plurality of dummy trench portions 30 may be provided.
  • the dummy trench portion 30 may have a linear shape extending in the extending direction, and may have a linear portion 29 and a tip portion 31 like the gate trench portion 40 .
  • the semiconductor device 100 shown in FIG. 2 includes both linear dummy trench portions 30 without tip portions 31 and dummy trench portions 30 with tip portions 31 .
  • the diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30 .
  • Y-axis direction ends of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 when viewed from above. That is, the bottom of each trench in the depth direction is covered with the well region 11 at the end of each trench in the Y-axis direction. As a result, electric field concentration at the bottom of each trench can be relaxed.
  • a mesa portion is provided between each trench portion in the arrangement direction.
  • the mesa portion refers to a region sandwiched between trench portions inside the semiconductor substrate 10 .
  • the upper end of the mesa portion is the upper surface of the semiconductor substrate 10 .
  • the depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion.
  • the mesa portion of this example extends in the extension direction (Y-axis direction) along the trench on the upper surface of the semiconductor substrate 10 .
  • the transistor section 70 is provided with a mesa section 60 and the diode section 80 is provided with a mesa section 61 .
  • simply referring to the mesa portion refers to the mesa portion 60 and the mesa portion 61 respectively.
  • a base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region arranged closest to the active-side gate wiring 131 is referred to as a base region 14-e.
  • FIG. 2 shows the base region 14-e arranged at one end in the extending direction of each mesa, the base region 14-e is also arranged at the other end of each mesa. It is In each mesa portion, at least one of the first conductivity type emitter region 12 and the second conductivity type contact region 15 may be provided in a region sandwiched between the base regions 14-e when viewed from above.
  • the emitter region 12 in this example is of N+ type and the contact region 15 is of P+ type. Emitter region 12 and contact region 15 may be provided between base region 14 and the upper surface of semiconductor substrate 10 in the depth direction.
  • the mesa portion 60 of the transistor portion 70 has the emitter region 12 exposed on the upper surface of the semiconductor substrate 10 .
  • the emitter region 12 is provided in contact with the gate trench portion 40 .
  • the mesa portion 60 in contact with the gate trench portion 40 may be provided with the contact region 15 exposed to the upper surface of the semiconductor substrate 10 .
  • Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction.
  • the contact regions 15 and the emitter regions 12 of the mesa portion 60 are alternately arranged along the extension direction (Y-axis direction) of the trench portion.
  • the contact regions 15 and the emitter regions 12 of the mesa portion 60 may be provided in stripes along the extending direction (Y-axis direction) of the trench portion.
  • an emitter region 12 is provided in a region in contact with the trench portion, and a contact region 15 is provided in a region sandwiched between the emitter regions 12 .
  • the mesa portion 61 of the diode portion 80 is not provided with the emitter region 12 .
  • a base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61 .
  • a contact region 15 may be provided in a region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61 so as to be in contact with each base region 14-e.
  • a base region 14 may be provided in a region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61 .
  • the base region 14 may be arranged over the entire region sandwiched between the contact regions 15 .
  • a trench contact portion 54 is provided above each mesa portion.
  • the trench contact portion 54 is arranged in a region sandwiched between the base regions 14-e.
  • the trench contact portion 54 of this example is provided above each region of the contact region 15 , the base region 14 and the emitter region 12 .
  • Trench contact portion 54 is not provided in a region corresponding to base region 14 - e and well region 11 .
  • the trench contact portion 54 may be arranged at the center in the arrangement direction (X-axis direction) of the mesa portions 60 .
  • an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10 .
  • a P + -type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided.
  • Cathode region 82 and collector region 22 are provided between lower surface 23 of semiconductor substrate 10 and buffer region 20 . In FIG. 2, the boundary between cathode region 82 and collector region 22 is indicated by a dotted line.
  • the cathode region 82 is arranged apart from the well region 11 in the Y-axis direction. As a result, the distance between the P-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, and the cathode region 82 can be secured, and the withstand voltage can be improved.
  • the end of the cathode region 82 in the Y-axis direction in this example is arranged farther from the well region 11 than the end of the trench contact portion 54 in the Y-axis direction.
  • the Y-axis direction end of the cathode region 82 may be arranged between the well region 11 and the trench contact portion 54 .
  • FIG. 3 is a diagram showing an example of a cc cross section in FIG.
  • the cc section is the XZ plane passing through the contact region 15 at the mesa portion 60 .
  • the mesa portion 60 is a region sandwiched between two trench portions arranged adjacent to each other in the X-axis direction.
  • the mesa portion 60 in the example of FIG. 3 is sandwiched between the gate trench portion 40 and the dummy trench portion 30 .
  • the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52 and a collector electrode 24 in the cross section.
  • the interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10 .
  • the interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with an impurity such as boron or phosphorus, a thermal oxide film, and other insulating films.
  • the interlayer insulating film 38 is provided with the trench contact portion 54 described with reference to FIG.
  • the emitter electrode 52 is provided above the interlayer insulating film 38 .
  • Emitter electrode 52 is in contact with upper surface 21 of semiconductor substrate 10 through trench contact portion 54 of interlayer insulating film 38 .
  • a collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10 .
  • Emitter electrode 52 and collector electrode 24 are made of a metal material such as aluminum.
  • the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.
  • the semiconductor substrate 10 has an N-type or N ⁇ type drift region 18 .
  • the P+ type contact region 15 and the P ⁇ type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10 .
  • a drift region 18 is provided below the base region 14 .
  • the mesa portion 60 may be provided with an N+ type accumulation region 16 .
  • Accumulation region 16 is disposed between base region 14 and drift region 18 .
  • the contact region 15 is exposed on the upper surface 21 of the semiconductor substrate 10 and is in contact with trench portions on both sides of the mesa portion 60 .
  • the doping concentration of the contact region 15 is greater than or equal to the doping concentration of the base region 14 . That is, the doping concentration of the contact region 15 may be the same as the doping concentration of the base region 14 . In this case, base region 14 is exposed on top surface 21 as contact region 15 . Also, the doping concentration of the contact region 15 may be higher than the doping concentration of the base region 14 . In this case, a P-type region having a higher concentration than the base region 14 is exposed on the upper surface 21 .
  • the base region 14 is provided below the contact region 15 .
  • the base region 14 of this example is provided in contact with the contact region 15 .
  • the base region 14 may contact trench portions on both sides of the mesa portion 60 .
  • the accumulation region 16 is provided below the base region 14 .
  • the accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18 .
  • Accumulation region 16 may have a concentration peak of donors, such as phosphorus or hydrogen donors.
  • IE effect carrier injection promoting effect
  • the accumulation region 16 may be provided so as to cover the entire bottom surface of the base region 14 in each mesa portion 60 .
  • An N+ type buffer region 20 may be provided under the drift region 18 .
  • the doping concentration of buffer region 20 is higher than the doping concentration of drift region 18 .
  • Buffer region 20 may have a concentration peak with a higher doping concentration than drift region 18 .
  • the doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak.
  • an average value of doping concentrations in a region where the doping concentration distribution is substantially flat may be used as the doping concentration of the drift region 18.
  • the buffer region 20 may be formed by ion-implanting hydrogen (protons) or an N-type dopant such as phosphorus.
  • the buffer region 20 of this example is formed by implanting hydrogen ions.
  • Buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the bottom edge of base region 14 from reaching P + -type collector region 22 and N + -type cathode region 82 .
  • a P+ type collector region 22 is provided under the buffer region 20 .
  • the acceptor concentration of collector region 22 is higher than the acceptor concentration of base region 14 .
  • Collector region 22 may contain the same acceptor as base region 14 or may contain a different acceptor.
  • the acceptor of the collector region 22 is boron, for example.
  • the collector region 22 is exposed on the bottom surface 23 of the semiconductor substrate 10 and connected to the collector electrode 24 .
  • Collector electrode 24 may contact the entire bottom surface 23 of semiconductor substrate 10 .
  • Emitter electrode 52 and collector electrode 24 are made of a metal material such as aluminum.
  • One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10 .
  • Each trench extends from the upper surface 21 of the semiconductor substrate 10 through the base region 14 and reaches the drift region 18 .
  • the contact region 15 and/or the accumulation region 16 are provided, each trench also penetrates these doping regions and reaches the drift region 18.
  • FIG. The fact that the trench penetrates the doping region is not limited to the order of forming the doping region and then forming the trench.
  • a structure in which a doping region is formed between the trench portions after the trench portions are formed is also included in the structure in which the trench portion penetrates the doping regions.
  • the gate trench portion 40 has a gate trench provided in the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42 and a gate conductive portion 44.
  • a gate insulating film 42 is provided to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10 from each other.
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate conductive portion 44 may be provided longer than the base region 14 in the depth direction.
  • the gate trench portion 40 in the cross section is covered with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10 .
  • the gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44 , a channel is formed by an electron inversion layer in the surface layer of the interface contacting the gate trench portion 40 in the base region 14 .
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section.
  • the dummy trench section 30 has a dummy trench provided in the upper surface 21 of the semiconductor substrate 10 , a dummy insulating film 32 and a dummy conductive section 34 .
  • the dummy conductive portion 34 is electrically connected to the emitter electrode 52 .
  • a dummy insulating film 32 is provided to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is provided inside the dummy trench and inside the dummy insulating film 32 .
  • the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10 .
  • the dummy conductive portion 34 may be made of the same material as the gate conductive portion 44 .
  • the dummy conductive portion 34 is made of a conductive material such as polysilicon.
  • the dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.
  • the gate trench portion 40 and the dummy trench portion 30 of this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10 .
  • the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross section) convex downward.
  • a portion of the trench contact portion 54 located above the contact region 15 is defined as a first trench contact portion 54-1, and a portion located above the emitter region 12 is defined as a second trench contact portion 54-2 (see FIG. 4). reference).
  • the first trench contact portion 54 - 1 is provided at least from the upper surface 21 of the semiconductor substrate 10 to the inside of the contact region 15 .
  • the first trench contact portion 54 - 1 of this example is provided from the upper end of the interlayer insulating film 38 to the inside of the contact region 15 .
  • the depth position of the lower end of the first trench contact portion 54-1 is arranged between the depth position of the upper end of the contact region 15 and the depth position of the lower end.
  • the mesa portion 60 is provided with a first plug portion 201 in contact with the lower end of the first trench contact portion 54-1.
  • the first plug portion 201 is a region of the second conductivity type (P++ type in this example) having a higher concentration than the base region 14 .
  • the first plug portion 201 may be a higher concentration region than the contact region 15 .
  • the doping concentration of the first plug portion 201 is higher than the doping concentration of the contact region 15 when compared at the same depth position.
  • the first plug portion 201 may be formed by implanting an acceptor into the contact region 15 after forming the contact region 15 .
  • the first plug portion 201 may be shallower than the contact region 15 , may have the same depth as the contact region 15 , or may be deeper than the contact region 15 . In this example, the first plug portion 201 is shallower than the contact region 15 .
  • FIG. 4 is a diagram showing an example of a bb cross section in FIG.
  • the bb cross section is the XZ plane passing through the emitter region 12 at the mesa portion 60 .
  • the semiconductor device 100 has a second trench contact portion 54-2 instead of the first trench contact portion 54-1, and an emitter region instead of the contact region 15, in contrast to the structure shown in FIG. 12 and has a second plug portion 202 instead of the first plug portion 201 .
  • Other structures may be identical to the structure shown in FIG.
  • the second trench contact portion 54-2 is provided at least from the top surface 21 of the semiconductor substrate 10 to the inside of the emitter region 12.
  • the second trench contact portion 54 - 2 of this example is provided from the upper end of the interlayer insulating film 38 to the inside of the emitter region 12 .
  • the depth position of the lower end of the second trench contact portion 54-2 is arranged between the depth position of the upper end of the emitter region 12 and the depth position of the lower end.
  • the depth positions of the lower ends of the first trench contact portion 54-1 and the second trench contact portion 54-2 may be the same.
  • the mesa portion 60 is provided with a second plug portion 202 in contact with the lower end of the second trench contact portion 54-2.
  • the second plug portion 202 is a region of the second conductivity type (P++ type in this example) having a higher concentration than the base region 14 .
  • the second plug portion 202 may be formed by implanting an acceptor into the emitter region 12 after forming the emitter region 12 .
  • the first plug portion 201 and the second plug portion 202 may be regions formed by implanting acceptors at the same dose amount and at the same depth position.
  • the first plug portion 201 is a region obtained by further implanting an acceptor into the P-type contact region 15
  • the second plug portion 202 is formed by implanting an acceptor into the N-type emitter region 12 to make it P-type. This is the inverted area.
  • the second plug portion 202 may be a region with a lower net doping concentration than the first plug portion 201 .
  • FIG. 5 is a diagram showing the bb cross section and the cc cross section side by side.
  • the vicinity of the mesa portion 60 is enlarged, and the side of the lower surface 23 (see FIGS. 3 and 4) of the semiconductor substrate 10 is omitted.
  • the second plug portion 202 is provided from the first plug portion 201 to the lower surface 23 side.
  • the depth position Z202 of the lower end of the second plug portion 202 is located closer to the lower surface 23 than the depth position Z201 of the lower end of the first plug portion 201 is.
  • hole carriers traveling from below the emitter region 12 toward the upper surface 21 can be easily extracted to the emitter electrode 52 .
  • the depth position Z202 of the lower end of the second plug portion 202 may be positioned closer to the lower surface 23 by 0.1 ⁇ m or more than the depth position Z201 of the lower end of the first plug portion 201, and may be positioned closer to the lower surface 23 by 0.3 ⁇ m or more than the depth position Z201 of the lower end of the first plug portion 201. may be placed on the side.
  • the depth position Z202 of the lower end of the second plug portion 202 is preferably located closer to the lower surface 23 than the depth position Z12 of the lower end of the emitter region 12 is. Depth location Z202 may be located inside base region 14 . This makes it easier to extract hole carriers from the bottom of the emitter region 12 toward the upper surface 21 .
  • the contact region 15, the first plug portion 201 and the second plug portion 202 may contain acceptors of the same element.
  • the contact region 15, the first plug portion 201, and the second plug portion 202 may have the same acceptor element with the highest concentration (atoms/cm 3 ).
  • the element is, for example, boron, but is not limited thereto.
  • the greater the difference in impurity concentration the greater the diffusion coefficient of the impurity. That is, for example, when boron is implanted into a predetermined implanted region, the newly implanted boron diffuses more easily as the concentration of boron already existing in the vicinity of the implanted region is lower.
  • the contact region 15 contains not only the acceptor that forms the base region 14 but also the acceptor that forms the contact region 15 having a higher doping concentration than the base region 14 . exist. That is, an acceptor such as boron already exists at a high concentration.
  • the acceptor forming the contact region 15 having a higher concentration than the base region 14 exists at the lower end of the first trench contact portion 54-1. Therefore, the concentration difference between the injected acceptors and the acceptors existing before injection is small. Therefore, the concentration gradient becomes small, the flux when the acceptor diffuses is small, and the acceptor does not diffuse much.
  • acceptors such as boron exist only to the extent that base region 14 is formed. Furthermore, at the depth position of the lower end of the second trench contact portion 54-2, the acceptor concentration decreases toward the lower surface 23 side.
  • the concentration difference between the implanted acceptors and the acceptors in the base region 14 is the contact region 15 (that is, the second (lower end of trench contact portion 54-2). Therefore, the concentration gradient becomes relatively large, and the flux when the acceptors diffuse becomes large.
  • the implanted acceptors diffuse deep inside the emitter region 12 mainly toward the lower surface 23 side where the concentration is low, and may also diffuse into the base region 14 . Therefore, when the semiconductor substrate 10 is annealed, the acceptor implanted into the emitter region 12 diffuses over a wider range toward the lower surface 23 side than the acceptor implanted into the contact region 15 . Therefore, the second plug portion 202 can be provided from the first plug portion 201 to the lower surface 23 side.
  • L1 be the depth of the trench contact portion 54 in the Z-axis direction with respect to the upper surface 21 of the semiconductor substrate 10 .
  • the width of the emitter region 12 in the Z-axis direction is assumed to be L2.
  • L3 be the length in the Z-axis direction of the second plug portion 202 protruding below the emitter region 12 .
  • the depth L1 may be less than or equal to half the width L2.
  • the depth L1 may be 1/4 or less of the width L2.
  • the depth L1 may be 0.2 ⁇ m or more and 0.6 ⁇ m or less.
  • the depth L1 may be 0.3 ⁇ m or more and may be 0.5 ⁇ m or less.
  • the width L2 may be 0.3 ⁇ m or more and 0.7 ⁇ m or less.
  • the width L2 may be 0.4 ⁇ m or more and may be 0.6 ⁇ m or less.
  • the length L3 may be smaller than the width L2.
  • the length L3 may be less than or equal to half the width L2. If the length L3 is too large, the acceptors of the second plug portion 202 are likely to diffuse up to the interface between the gate trench portion 40 and the base region 14, and the threshold voltage of the transistor portion 70 may fluctuate. .
  • the length L3 may be greater than 0 ⁇ m and less than or equal to 0.4 ⁇ m.
  • the length L3 may be 0.1 ⁇ m or more and may be 0.3 ⁇ m or less.
  • Zp2 be the depth position of the upper end of the second plug portion 202 .
  • the upper end of the second plug portion 202 may be in contact with the sidewall of the second trench contact portion 54-2.
  • the width from the upper surface 21 to the depth position Zp2 of the upper end of the second plug portion 202 is defined as La2.
  • Lb2 be the width from the depth position Zp2 to the depth position Z12.
  • Width La2 may be smaller than width Lb2.
  • the depth position of the upper end of the first plug portion 201 is assumed to be Zp5.
  • the top end of the first plug portion 201 may be in contact with the sidewall of the first trench contact portion 54-1.
  • the width from the upper surface 21 to the depth position Zp5 of the upper end of the first plug portion 201 is defined as La5.
  • Lb5 be the width from the depth position Zp5 to the depth position Z15.
  • Width La5 may be smaller than width Lb5.
  • the width La2 may be smaller than the width La5.
  • the depth position Z201 of the lower end of the first plug portion 201 may be the same depth as the depth position Z15 of the lower end of the contact region 15, and may be arranged closer to the upper surface 21 than the depth position Z15.
  • the depth position Z15 of the lower end of the contact region 15 may be arranged closer to the lower surface 23 than the depth position Z12 of the lower end of the emitter region 12 .
  • the depth position Z202 of the lower end of the second plug portion 202 may be arranged closer to the lower surface 23 than the depth position Z15 of the lower end of the contact region 15 .
  • the depth position Z201 of the lower end of the first plug portion 201 may be arranged closer to the lower surface 23 than the depth position Z12 of the lower end of the emitter region 12 . This makes it easier to extract hole carriers from the lower surface 23 side, and suppresses latch-up.
  • the depth position Z201 may be arranged closer to the upper surface 21 than the depth position Z12.
  • the structure of the mesa portion 60 of the transistor portion 70 has been described.
  • Mesa portion 61 of diode portion 80 has base region 14 instead of emitter region 12 and contact region 15 in the structure of mesa portion 60 .
  • the mesa portion 61 has a cathode region 82 instead of the collector region 22 with respect to the structure of the mesa portion 60 .
  • the mesa portion 61 may have a trench contact portion 54 .
  • the trench contact portion 54 is provided to the same depth position as the first trench contact portion 54-1 and the second trench contact portion 54-2.
  • the mesa portion 61 may have a P++ type plug portion in contact with the lower end of the trench contact portion 54 .
  • the plug portion of the mesa portion 61 may be formed up to the same depth position as the first plug portion 201 or deeper than the first plug portion 201 .
  • the plug portion of the mesa portion 61 may be formed shallower than the second plug portion 202 .
  • the base region 14 and the plug portion may contain acceptors of the same element.
  • FIG. 6 is a diagram showing an example of a dd cross section in FIG.
  • the dd cross section is the YZ plane passing through the trench contact portion 54 at the mesa portion 60 .
  • the area on the lower surface 23 side is omitted as in FIG.
  • the interlayer insulating film 38 is omitted in FIG.
  • emitter regions 12 and contact regions 15 are alternately arranged along the Y-axis direction on the upper surface of the mesa portion 60 .
  • a region of the trench contact portion 54 located inside the contact region 15 when viewed from above is referred to as a first trench contact portion 54-1
  • a region located inside the emitter region 12 when viewed from above is referred to as a second trench contact portion 54-.
  • the first trench contact portions 54-1 and the second trench contact portions 54-2 are alternately arranged along the Y-axis direction.
  • a first plug portion 201 is arranged under the first trench contact portion 54-1
  • a second plug portion 202 is arranged under the second trench contact portion 54-2.
  • the first plug portions 201 and the second plug portions 202 are alternately arranged along the Y-axis direction. As described above, the depth position Z202 of the lower end of the second plug portion 202 is arranged closer to the lower surface 23 than the depth position Z201 of the lower end of the first plug portion 201. As shown in FIG.
  • FIG. 7A is a diagram showing another example of the bb cross section and the cc cross section.
  • the semiconductor device 100 of this example differs from the example shown in FIG.
  • Other structures are similar to the example shown in FIG.
  • the depth position Z202 of the lower end of the second plug portion 202 of this example is located closer to the upper surface 21 than the depth position Z15 of the lower end of the contact region 15 .
  • the depth position Z201 of the lower end of the first plug portion 201 may also be arranged closer to the upper surface 21 than the depth position Z15 of the lower end of the contact region 15 .
  • the depth position Z201 and the depth position Z202 can be formed shallower than the depth position Z15.
  • FIG. 7B is a diagram showing another example of the dd cross section in FIG.
  • the semiconductor device 100 of this example has the structure shown in FIG. 7A.
  • the plug portions that is, the first plug portion 201 and the second plug portion 202 of this example are provided shallower than the contact region 15.
  • both the depth position Z201 of the lower end of the first plug portion 201 and the depth position Z202 of the lower end of the second plug portion 202 are located closer to the upper surface 21 than the depth position Z15 of the lower end of the contact region 15.
  • the second plug portion 202 may be provided from the first plug portion 201 to the lower surface 23 side. In the example of FIG.
  • the depth position Z201 of the lower end of the first plug section 201, the depth position Z202 of the lower end of the second plug section 202, and the depth position Z15 of the lower end of the contact region 15 are arranged in order from the upper surface 21 side. They are arranged in order of depth position Z201, depth position Z202, and depth position Z15.
  • Y201 be the length of the first plug portion 201 in the Y-axis direction
  • Y202 be the length of the second plug portion 202 in the Y-axis direction.
  • the length of the emitter region 12 and the length of the contact region 15 on the upper surface 21 of the semiconductor substrate 10 may be length Y201 and length Y202.
  • the length of the emitter region 12 and the length of the contact region 15 on the top surface 21 may be measured at the location in contact with the trench contact portion 54 .
  • the positions in the Y-axis direction where the depth positions change are the first plug portion 201 and the second plug portion. 202 may be the boundary position.
  • the length Y201 of the first plug portion 201 may be longer than the length Y202 of the second plug portion 202, may be the same, or may be shorter. The same is true for each example disclosed in this specification.
  • FIG. 7C is a diagram showing another example of the dd cross section in FIG.
  • the plug portions that is, the first plug portion 201 and the second plug portion 202 are provided shallower than the contact region 15, as in the example of FIG. 7B.
  • the depth position Z201 of the lower end of the first plug portion 201 and the depth position Z202 of the lower end of the second plug portion 202 are the same.
  • Other structures are similar to the example of FIG. 7B.
  • the same depth position may include an error within ⁇ 10%. That is, the absolute value of the difference
  • each plug portion may be measured at the center of each plug portion in the Y-axis direction, or an average value measured at a plurality of locations in the Y-axis direction may be used. Values measured by other methods may also be used.
  • the contact region 15 of this example is formed by implanting dopant ions in the vicinity of the upper surface 21 and diffusing the dopant by heat treatment. For this reason, the doping concentration of the contact region 15 decreases with distance from the upper surface 21 in the Z-axis direction.
  • the depth position Z15 of the contact region 15 is sufficiently deeper than the depth position Z201 of the first plug portion 201 and the depth position Z202 of the second plug portion 202, the contact region 15 at the depth position Z201 and the depth position Z202. is low and approaches the doping concentration of the base region 14 .
  • the dopant injected into the contact region 15 from the lower end of the first trench contact portion 54-1 and the dopant injected into the emitter region 12 or the base region 14 from the lower end of the second trench contact portion 54-2 diffuse.
  • Depth may be similar. In this case, as in this example, the depths of the first plug portion 201 and the second plug portion 202 are substantially the same.
  • a distance D15 from the upper surface 21 to the lower end of the contact region 15 may be 1.5 times or more, or 1.75 times or more, the distance D20 from the upper surface 21 to the lower ends of the first plug portion 201 and the second plug portion 202. and may be two times or more.
  • An average value of the distance from the upper surface 21 to the lower end of the first plug portion 201 and the distance from the upper surface 21 to the lower end of the second plug portion 202 may be used as the distance D20.
  • the distance D15 from the upper surface 21 to the lower end of the contact region 15 may be measured at the center of the contact region 15 in the Y-axis direction, may be measured at a plurality of locations in the Y-axis direction, and may be measured by another method. Measured values may be used.
  • FIG. 8 is a diagram showing another example of the bb cross section and the cc cross section.
  • the width of the mesa portion 60 in the X-axis direction is X60
  • the width of the gate trench portion 40 is X40
  • the width of the trench contact portion 54 is X54.
  • Width X60 and width X40 may be widths in upper surface 21 of semiconductor substrate 10 .
  • the width X54 may be the width of the bottom surface of the trench contact portion 54 or the width at the height of the top surface 21 of the semiconductor substrate 10 .
  • the width X60 of the mesa portion 60 may be smaller than the width X40 of the gate trench portion 40.
  • the carrier injection promotion effect IE effect
  • the second trench contact portion 54-2 is formed shallow, the second plug portion 202 can be formed deep. Therefore, even if the mesa portion 60 is miniaturized, the trench contact portion 54 can be easily formed. can.
  • the width X60 of the mesa portion 60 may be 1 ⁇ m or less, 0.8 ⁇ m or less, or 0.6 ⁇ m or less.
  • the width X54 of the trench contact portion 54 may be less than half the width X60 of the mesa portion 60 .
  • the width X54 may be 0.15 ⁇ m or more and 0.4 ⁇ m or less.
  • FIG. 9 is an enlarged view of the vicinity of the second trench contact portion 54-2 and the second plug portion 202.
  • the second plug portion 202 of this example has a second portion 212 in contact with the side surface of the second trench contact portion 54-2.
  • the side surface of the trench contact portion 54 may refer to a surface having an inclination of 45 degrees or more and 90 degrees or less with respect to the XY plane.
  • the side surface of the trench contact portion 54 may refer to a surface extending from the upper surface 21 of the semiconductor substrate 10 to half the depth of the trench contact portion 54 .
  • the second plug portion 202 in this example is formed by injecting an acceptor through the second trench contact portion 54-2 before filling the second trench contact portion 54-2 with a metal material.
  • acceptors are also injected from the side surfaces of the second trench contact portion 54-2.
  • the P-type second portion 212 is formed on the side surface of the second trench contact portion 54-2. be done.
  • Second portion 212 may have a lower or higher doping concentration than base region 14 .
  • FIG. 10 is an enlarged view of the vicinity of the first trench contact portion 54-1 and the first plug portion 201.
  • Width X211 and width X212 may be widths in upper surface 21 of semiconductor substrate 10 .
  • the width X212 of the second portion 212 may be smaller than the width X211 of the first portion 211 .
  • the amount of acceptors injected from the side surface of each trench contact portion 54 is less than the amount of acceptors injected from the bottom surface of the trench contact portion 54 . Therefore, even if the acceptor reaches the emitter region 12 away from the side surface of the second trench contact portion 54-2, it is difficult to invert to the P-type.
  • the width X212 of the second portion 212 is reduced.
  • the P-type concentration in the range reached by the acceptors increases, so the width X211 of the first portion 211 becomes larger than the width X212.
  • the width of the first plug portion 201 in the X-axis direction is X201
  • the width of the second plug portion 202 in the X-axis direction is X202.
  • the maximum width of each plug portion in the X-axis direction may be the width of each plug portion. A relatively large amount of acceptors is implanted from the bottom surface of the trench contact portion 54 . Therefore, the depth position at which each plug portion exhibits the maximum width may be closer to the lower surface 23 than the lower end of the trench contact portion 54 .
  • the width X201 of the first plug portion 201 may be smaller than the width X202 of the second plug portion 202. As described above, acceptors diffuse more easily in the emitter region 12 than in the contact region 15 . Therefore, a large amount of acceptors implanted from the bottom surface of the second trench contact portion 54-2 diffuses widely in the X-axis direction in the emitter region 12, and the width X202 may become larger than the width X201.
  • FIG. 11 is a diagram showing another example of the vicinity of the second trench contact portion 54-2 and the second plug portion 202.
  • FIG. A semiconductor device 100 of this example includes a barrier metal 221 and a silicide portion 231 .
  • Other structures are the same as those of the semiconductor device 100 of any aspect described in FIGS.
  • the barrier metal 221 is provided along the bottom and side surfaces of the trench contact portion 54 .
  • a barrier metal 221 is arranged between the semiconductor substrate 10 and an electrode containing aluminum, tungsten, or the like.
  • the barrier metal 221 may be further provided along the side surface of the interlayer insulating film 38 and may be further provided along the upper surface of the interlayer insulating film 38 .
  • the barrier metal 221 may be made of metal containing titanium.
  • the barrier metal 221 may be a laminated film in which a titanium nitride film and a titanium film are laminated.
  • the silicide portion 231 is provided at the boundary between the second trench contact portion 54-2 and the semiconductor substrate 10.
  • the silicide portion 231 of this example is provided at the boundary between the barrier metal 221 and the semiconductor substrate 10 .
  • the silicide portion 231 may be a portion formed by siliciding the metal contained in the barrier metal 221 with the silicon contained in the semiconductor substrate 10 .
  • the silicide portion 231 in this example is titanium silicide.
  • the second plug portion 202 of this example contains boron.
  • the silicide portion 231 may also contain boron. Boron of the second plug portion 202 may diffuse inside the silicide portion 231 . A portion of the silicide portion 231 that contacts the second plug portion 202 may contain boron.
  • the second trench contact portion 54-2 and the second plug portion 202 are shown in FIG. may be provided. The entire interface of the silicide portion 231 of the first trench contact portion 54-1 on the semiconductor substrate 10 side is in contact with the contact region 15 or the first plug portion 201. FIG. Boron may be included in the entire interface of the silicide portion 231 of the first trench contact portion 54-1.
  • FIG. 12A and 12B are diagrams showing an example of a method for manufacturing the semiconductor device 100.
  • FIG. 12A and 12B show part of the manufacturing process.
  • 12A and 12B show a cross section passing through the emitter region 12 and a cross section passing through the contact region 15 side by side as in FIG. 12A and 12B show the structure of the mesa portion 60 on the upper surface 21 side.
  • the upper surface side structure forming step S1201 a structure near the upper surface 21 of the semiconductor substrate 10 is formed.
  • the base region 14, the emitter region 12, the contact region 15, the gate trench portion 40, the dummy trench portion 30, and the interlayer insulating film 38 are formed in the semiconductor substrate 10 having the drift region 18.
  • the accumulation region 16 may be further formed.
  • the interlayer insulating film 38 and the upper surface 21 of the semiconductor substrate 10 are etched to form the first trench contact portion 54-1 and the second trench contact portion 54-2.
  • the first trench contact portion 54-1 is provided to the inside of the contact region 15, and the second trench contact portion 54-2 is provided to the inside of the emitter region 12.
  • the insides of the first trench contact portion 54-1 and the second trench contact portion 54-2 are not filled with the metal material.
  • trenches formed in the interlayer insulating film 38 and the semiconductor substrate 10 are called trench contact portions 54 .
  • a dopant of a second conductivity type is injected into the semiconductor substrate 10 through each trench contact portion 54.
  • the dopant is preferably the same element as the dopant implanted to form contact region 15 .
  • the dopant in this example is boron.
  • the acceleration energy of dopant ions is set so that the concentration peak of the implanted dopant is located inside the emitter region 12 and the contact region 15 .
  • Dopant ions may be implanted at the same dose (ions/cm 2 ) into the first trench contact portion 54-1 and the second trench contact portion 54-2.
  • the semiconductor substrate 10 is annealed. Thereby, the first plug portion 201 and the second plug portion 202 are formed. As described above, the emitter region 12 has a larger acceptor diffusion coefficient than the contact region 15 . Therefore, the second plug portion 202 is formed in a wider range than the first plug portion 201 .
  • the entire semiconductor substrate 10 may be annealed in an annealing furnace.
  • the semiconductor substrate 10 may be annealed under temperature and time conditions that allow the second plug portion 202 to reach at least the base region 14 .
  • the inside of the trench contact portion 54 may be filled with a metal material.
  • the emitter electrode 52 may be formed after the plug annealing step S1204.
  • the buffer region 20, the collector region 22, the cathode region 82 and the collector electrode 24 on the lower surface 23 side of the semiconductor substrate 10 may be formed after the plug annealing step S1204.
  • FIG. 13 is a diagram showing an example of the acceptor concentration distribution along the ee line and the ff line in FIG. 12B.
  • Line ee is a line parallel to the Z-axis that passes through the second plug portion 202 and part of the base region 14 .
  • a line ff is a line parallel to the Z-axis passing through the first plug portion 201 and part of the base region 14 .
  • the dose amount of the acceptor such as boron for the first plug portion 201 and the second plug portion 202 is the same.
  • the peak value D2 of the acceptor concentration of the second plug portion 202 may be smaller than the peak value D1 of the acceptor concentration of the first plug portion 201 .
  • the depth position Z1 at which the acceptor concentration peaks in the first plug portion 201 and the depth position Z2 at which the acceptor concentration peaks in the second plug portion 202 may be the same or different.
  • the acceptor concentration at the position in contact with the lower end of the trench contact portion 54 may exhibit the maximum value.
  • the depth position Z202 of the lower end of the second plug portion 202 is located closer to the lower surface 23 than the depth position Z201 of the lower end of the first plug portion 201.
  • the depth position Z202 and the depth position Z201 may be positions of change points where the absolute value of the slope of the acceptor concentration first decreases from the lower end of the trench contact portion 54 toward the lower surface 23 side.
  • the acceptor injected into the second plug portion 202 diffuses widely toward the bottom surface 23 , so the position showing the minimum value is located closer to the bottom surface 23 than the first plug portion 201 .
  • the acceptor concentration peak value D1 of the first plug portion 201 may be 1 ⁇ 10 20 /cm 3 or more.
  • the peak value D1 may be 1 ⁇ 10 21 /cm 3 or less.
  • the peak value of the acceptor concentration in the contact region 15 may be smaller than the peak value D1.
  • the peak acceptor concentration in contact region 15 may be 1 ⁇ 10 19 /cm 3 or more and less than 1 ⁇ 10 20 /cm 3 .
  • the acceptor concentration peak value D2 of the second plug portion 202 may be higher than the acceptor concentration peak value of the contact region 15 .
  • the acceptor concentration D3 of the base region 14 at the depth position Z201 and the acceptor concentration D4 of the base region 14 at the depth position Z202 are, for example, 1 ⁇ 10 16 /cm 3 or more and 5 ⁇ 10 17 /cm 3 or less.
  • the acceptor density D4 may be lower than the acceptor density D3.
  • the peak value D2 of the second plug portion 202 is smaller than the peak value D1 of the first plug portion 201 .
  • the acceptor concentration (/cm 3 ) at the lower end of the second trench contact portion 54-2 is higher than that at the lower end of the first trench contact portion 54-1. At least one order of magnitude lower than the acceptor concentration. Therefore, inside the emitter region 12 , the implanted acceptors diffuse mainly toward the lower surface 23 side. Therefore, the peak value D2 is smaller than the peak value D1.
  • diffusion of acceptors in the direction horizontal to the upper surface 21 can be made relatively small, and variations in the threshold voltage of the transistor section 70 can be suppressed. Further, by increasing the peak value D2 of the second plug portion 202, it becomes easier to extract hole carriers.
  • FIG. 14 is a diagram showing an example of the ee cross section in FIG.
  • the structure other than the ee section is the same as any of the forms described with reference to FIGS. 1 to 13.
  • FIG. The ee cross section is the YZ plane passing through the vicinity of the gate trench portion 40 in the mesa portion 60 .
  • the first plug portion 201 and the second plug portion 202 are not formed.
  • the distance between the ee section and the gate trench portion 40 may be 1/10 or less of the distance between the gate trench portion 40 and the trench contact portion 54 .
  • the area on the lower surface 23 side is omitted as in FIG. Further, the interlayer insulating film 38 is omitted in FIG.
  • emitter regions 12 and contact regions 15 are alternately provided on the upper surface 21 of the semiconductor substrate 10 along the Y-axis direction.
  • Contact region 15 may be formed deeper than emitter region 12 .
  • Y12 be the length of the emitter region 12 and Y15 be the length of the contact region 15 in the Y-axis direction.
  • the boundary locations of emitter region 12 and contact region 15 on top surface 21 may be used to measure the length of each region.
  • the length Y12 of the emitter region 12 may be shorter than, the same as, or longer than the length Y15 of the contact region 15 .
  • Reference Signs List 10 Semiconductor substrate 11 Well region 12 Emitter region 14 Base region 15 Contact region 16 Accumulation region 18 Drift region 20 Buffer region 21 Top surface 22 Collector region 23 Bottom surface 24 Collector electrode 29 Linear portion 30 Dummy trench portion 31 Tip portion 32 Dummy insulating film 34 Dummy conductive portion 38 Interlayer insulating film 39 Straight portion 40 Gate trench portion 41 Tip portion 42 Gate insulating film 44 Gate conductive portion 52 Emitter electrode 54 Trench contact portion 60, 61 Mesa portion 70 Transistor portion 80 Diode portion 81 Extension region 82 Cathode region 90 Edge termination structure 92 Guard ring 100 Semiconductor device 102 Edge 112. Gate pad 130 Perimeter gate wiring 131 Active side gate wiring 160 Active portion 201 First plug portion 202 Second plug portion 211 1st portion 212 2nd portion 221 barrier metal 231 silicide portion

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024024290A (ja) * 2022-08-09 2024-02-22 株式会社東芝 半導体装置
WO2024142638A1 (ja) * 2022-12-27 2024-07-04 富士電機株式会社 半導体装置および半導体装置の製造方法
JP2024099875A (ja) * 2023-01-13 2024-07-26 三菱電機株式会社 半導体装置
WO2024166493A1 (ja) * 2023-02-07 2024-08-15 富士電機株式会社 半導体装置
WO2024166492A1 (ja) * 2023-02-07 2024-08-15 富士電機株式会社 半導体装置
WO2024236880A1 (ja) * 2023-05-16 2024-11-21 富士電機株式会社 半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018052098A1 (ja) * 2016-09-14 2018-03-22 富士電機株式会社 半導体装置およびその製造方法
WO2018052099A1 (ja) * 2016-09-14 2018-03-22 富士電機株式会社 Ｒｃ－ｉｇｂｔおよびその製造方法
JP2018195798A (ja) * 2017-05-16 2018-12-06 富士電機株式会社 半導体装置
WO2019244485A1 (ja) * 2018-06-22 2019-12-26 富士電機株式会社 半導体装置の製造方法および半導体装置
WO2020213254A1 (ja) * 2019-04-16 2020-10-22 富士電機株式会社 半導体装置および製造方法
WO2021210293A1 (ja) * 2020-04-16 2021-10-21 富士電機株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008160039A (ja) 2006-12-26 2008-07-10 Nec Electronics Corp 半導体装置及びその製造方法
JP4577425B2 (ja) 2007-11-07 2010-11-10 株式会社デンソー 半導体装置
JP5317560B2 (ja) 2008-07-16 2013-10-16 株式会社東芝 電力用半導体装置
JP2010147380A (ja) 2008-12-22 2010-07-01 Denso Corp 半導体装置の製造方法
JP2010147381A (ja) 2008-12-22 2010-07-01 Denso Corp 半導体装置の製造方法
JP2012059873A (ja) 2010-09-08 2012-03-22 Renesas Electronics Corp 半導体装置
JP2012174989A (ja) 2011-02-23 2012-09-10 Toshiba Corp 半導体装置の製造方法
JP5562917B2 (ja) 2011-09-16 2014-07-30 株式会社東芝 半導体装置及びその製造方法
JP2014011418A (ja) * 2012-07-03 2014-01-20 Hitachi Ltd 半導体装置およびその製造方法
WO2014041808A1 (ja) 2012-09-13 2014-03-20 パナソニック株式会社 半導体装置
JP5831526B2 (ja) 2013-01-17 2015-12-09 株式会社デンソー 半導体装置およびその製造方法
JP6871316B2 (ja) * 2014-04-15 2021-05-12 ローム株式会社 半導体装置および半導体装置の製造方法
JP6420175B2 (ja) * 2014-05-22 2018-11-07 ルネサスエレクトロニクス株式会社 半導体装置
JP6302767B2 (ja) 2014-06-27 2018-03-28 株式会社日立製作所 半導体装置及びそれを用いた電力変換装置
JP5975543B2 (ja) 2014-08-22 2016-08-23 ローム株式会社 半導体装置および半導体装置の製造方法
DE102014226161B4 (de) 2014-12-17 2017-10-26 Infineon Technologies Ag Halbleitervorrichtung mit Überlaststrombelastbarkeit
DE102014119543B4 (de) 2014-12-23 2018-10-11 Infineon Technologies Ag Halbleitervorrichtung mit transistorzellen und anreicherungszellen sowie leistungsmodul
JP2017022311A (ja) * 2015-07-14 2017-01-26 ルネサスエレクトロニクス株式会社 半導体装置
US10636877B2 (en) * 2016-10-17 2020-04-28 Fuji Electric Co., Ltd. Semiconductor device
JP6972691B2 (ja) * 2017-06-19 2021-11-24 富士電機株式会社 半導体装置および半導体装置の製造方法
JP6963982B2 (ja) * 2017-12-07 2021-11-10 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6911941B2 (ja) 2017-12-14 2021-07-28 富士電機株式会社 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018052098A1 (ja) * 2016-09-14 2018-03-22 富士電機株式会社 半導体装置およびその製造方法
WO2018052099A1 (ja) * 2016-09-14 2018-03-22 富士電機株式会社 Ｒｃ－ｉｇｂｔおよびその製造方法
JP2018195798A (ja) * 2017-05-16 2018-12-06 富士電機株式会社 半導体装置
WO2019244485A1 (ja) * 2018-06-22 2019-12-26 富士電機株式会社 半導体装置の製造方法および半導体装置
WO2020213254A1 (ja) * 2019-04-16 2020-10-22 富士電機株式会社 半導体装置および製造方法
WO2021210293A1 (ja) * 2020-04-16 2021-10-21 富士電機株式会社 半導体装置および半導体装置の製造方法

Cited By (13)

* Cited by examiner, † Cited by third party
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JP7779813B2 (ja) 2022-08-09 2025-12-03 株式会社東芝 半導体装置
JP2024024290A (ja) * 2022-08-09 2024-02-22 株式会社東芝 半導体装置
WO2024142638A1 (ja) * 2022-12-27 2024-07-04 富士電機株式会社 半導体装置および半導体装置の製造方法
JPWO2024142638A1 (https=) * 2022-12-27 2024-07-04
JP2024099875A (ja) * 2023-01-13 2024-07-26 三菱電機株式会社 半導体装置
JP7834038B2 (ja) 2023-01-13 2026-03-23 三菱電機株式会社 半導体装置
WO2024166492A1 (ja) * 2023-02-07 2024-08-15 富士電機株式会社 半導体装置
JPWO2024166493A1 (https=) * 2023-02-07 2024-08-15
JPWO2024166492A1 (https=) * 2023-02-07 2024-08-15
WO2024166493A1 (ja) * 2023-02-07 2024-08-15 富士電機株式会社 半導体装置
JP7845515B2 (ja) 2023-02-07 2026-04-14 富士電機株式会社 半導体装置
JP7845516B2 (ja) 2023-02-07 2026-04-14 富士電機株式会社 半導体装置
WO2024236880A1 (ja) * 2023-05-16 2024-11-21 富士電機株式会社 半導体装置

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