JP7468786B2 - 半導体装置および製造方法 - Google Patents
半導体装置および製造方法 Download PDFInfo
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- JP7468786B2 JP7468786B2 JP2023522695A JP2023522695A JP7468786B2 JP 7468786 B2 JP7468786 B2 JP 7468786B2 JP 2023522695 A JP2023522695 A JP 2023522695A JP 2023522695 A JP2023522695 A JP 2023522695A JP 7468786 B2 JP7468786 B2 JP 7468786B2
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
Description
特許文献1 国際公開第2018/052099号
Claims (17)
- 上面および下面を有し、第1導電型のドリフト領域を有する半導体基板と、
前記上面と前記ドリフト領域との間に設けられた第2導電型のベース領域と、
前記上面から前記ドリフト領域まで設けられ、且つ、前記上面において長手方向に延伸して設けられたゲートトレンチ部と、
前記上面と前記ベース領域との間に設けられ、且つ、前記ゲートトレンチ部と接する第1導電型のエミッタ領域と、
前記上面と前記ベース領域との間に設けられ、且つ、前記ゲートトレンチ部の長手方向において前記エミッタ領域と交互に配置された第2導電型のコンタクト領域と、
前記上面から前記コンタクト領域の内部まで設けられた第1トレンチコンタクト部と、
前記上面から前記エミッタ領域の内部まで設けられた第2トレンチコンタクト部と、
前記第1トレンチコンタクト部の下端に接して設けられ、前記ベース領域よりも高濃度の第2導電型の第1プラグ部と、
前記第2トレンチコンタクト部の下端に接して設けられ、且つ、前記第1プラグ部よりも前記下面側まで設けられた、前記ベース領域よりも高濃度の第2導電型の第2プラグ部と
を備える半導体装置。 - 前記コンタクト領域、前記第1プラグ部および前記第2プラグ部は、同一元素のアクセプタを含む
請求項1に記載の半導体装置。 - 前記第2プラグ部の下端は、前記エミッタ領域の下端よりも下面側に配置されている
請求項1に記載の半導体装置。 - 前記第2プラグ部の下端は、前記コンタクト領域の下端よりも上面側に配置されている
請求項3に記載の半導体装置。 - 前記第1プラグ部の下端は、前記コンタクト領域の下端と同じ深さ位置か、または、前記コンタクト領域の下端よりも上面側に配置されている
請求項1から4のいずれか一項に記載の半導体装置。 - 前記第2プラグ部の下端の深さ位置は、前記第1プラグ部の下端の深さ位置よりも0.1μm以上、下面側に配置されている
請求項1から4のいずれか一項に記載の半導体装置。 - 前記第2プラグ部の下端の深さ位置は、前記第1プラグ部の下端の深さ位置よりも0.3μm以上、下面側に配置されている
請求項6に記載の半導体装置。 - 前記第2プラグ部のアクセプタ濃度のピーク値は、前記第1プラグ部のアクセプタ濃度のピーク値よりも小さい
請求項1から4のいずれか一項に記載の半導体装置。 - 前記長手方向と垂直な配列方向において前記ゲートトレンチ部と隣り合って設けられ、前記上面から前記ドリフト領域まで設けられ、且つ、前記長手方向に延伸して設けられたトレンチ部と、
前記ゲートトレンチ部および前記トレンチ部に挟まれたメサ部と
を更に備え、
前記配列方向における前記メサ部の幅が、前記ゲートトレンチ部の幅よりも小さい
請求項1から4のいずれか一項に記載の半導体装置。 - 前記第1プラグ部は、前記第1トレンチコンタクト部の側面に接する第1部分を有し、
前記第2プラグ部は、前記第2トレンチコンタクト部の側面に接する第2部分を有し、
前記第2部分の幅は、前記第1部分の幅よりも小さい
請求項1から4のいずれか一項に記載の半導体装置。 - 前記第1プラグ部および前記第2プラグ部はボロンを含み、
前記半導体基板はシリコンを含み、
前記第1トレンチコンタクト部および前記第2トレンチコンタクト部と、前記半導体基板との境界にはシリサイド部が設けられ、
前記シリサイド部は、ボロンを含む
請求項1から4のいずれか一項に記載の半導体装置。 - 上面および下面を有し、第1導電型のドリフト領域を有する半導体基板と、
前記上面と前記ドリフト領域との間に設けられた第2導電型のベース領域と、
前記上面から前記ドリフト領域まで設けられ、且つ、前記上面において長手方向に延伸して設けられたゲートトレンチ部と、
前記上面と前記ベース領域との間に設けられ、且つ、前記ゲートトレンチ部と接する第1導電型のエミッタ領域と、
前記上面と前記ベース領域との間に設けられ、且つ、前記ゲートトレンチ部の長手方向において前記エミッタ領域と交互に配置された第2導電型のコンタクト領域と、
前記上面から前記コンタクト領域の内部まで、および、前記上面から前記エミッタ領域の内部まで設けられたトレンチコンタクト部と、
前記エミッタ領域および前記コンタクト領域の両方において、前記トレンチコンタクト部の下端に接して設けられ、前記ベース領域よりも高濃度であり、前記コンタクト領域よりも浅く設けられた第2導電型のプラグ部と、
を備える半導体装置。 - 前記トレンチコンタクト部は、
前記上面から前記コンタクト領域の内部まで設けられた第1トレンチコンタクト部と、
前記上面から前記エミッタ領域の内部まで設けられた第2トレンチコンタクト部と、
を備え、
前記プラグ部は、
前記第1トレンチコンタクト部の下端に接して設けられた第1プラグ部と、
前記第2トレンチコンタクト部の下端に接して設けられ、前記第1プラグ部と同じ深さまで設けられた第2プラグ部と、
を備える請求項12に記載の半導体装置。 - 前記第1プラグ部および前記第2プラグ部の両方が、前記コンタクト領域よりも浅く設けられている
請求項13に記載の半導体装置。 - 前記半導体基板の前記上面から前記コンタクト領域の下端までの距離は、前記半導体基板の前記上面から前記第1プラグ部および前記第2プラグ部の下端までの距離の1.5倍以上である
請求項14に記載の半導体装置。 - 前記トレンチコンタクト部は、
前記上面から前記コンタクト領域の内部まで設けられた第1トレンチコンタクト部と、
前記上面から前記エミッタ領域の内部まで設けられた第2トレンチコンタクト部と、
を備え、
前記プラグ部は、
前記第1トレンチコンタクト部の下端に接して設けられた第1プラグ部と、
前記第2トレンチコンタクト部の下端に接して設けられ、前記第1プラグ部よりも前記下面側まで設けられた第2プラグ部と、
を備える請求項12に記載の半導体装置。 - 上面および下面を有し、第1導電型のドリフト領域を有する半導体基板に、前記上面と前記ドリフト領域との間に設けられた第2導電型のベース領域と、前記上面から前記ドリフト領域まで設けられ、且つ、前記上面において長手方向に延伸して設けられたゲートトレンチ部と、前記上面と前記ベース領域との間に設けられ、且つ、前記ゲートトレンチ部と接する第1導電型のエミッタ領域と、前記上面と前記ベース領域との間に設けられ、且つ、前記ゲートトレンチ部の長手方向において前記エミッタ領域と交互に配置された第2導電型のコンタクト領域とを形成する上面側構造形成段階と、
前記上面から前記コンタクト領域の内部まで設けられた第1トレンチコンタクト部と、前記上面から前記エミッタ領域の内部まで設けられた第2トレンチコンタクト部を形成するトレンチ形成段階と、
前記第1トレンチコンタクト部および前記第2トレンチコンタクト部を介して前記半導体基板に第2導電型のドーパントを注入するプラグ注入段階と、
前記半導体基板をアニールして、前記第1トレンチコンタクト部の下端に接する第2導電型の第1プラグ部と、前記第2トレンチコンタクト部の下端に接し、前記第1プラグ部よりも前記下面側まで設けられた第2導電型の第2プラグ部とを形成するプラグアニール段階と
を備える製造方法。
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WO2018052099A1 (ja) | 2016-09-14 | 2018-03-22 | 富士電機株式会社 | Rc-igbtおよびその製造方法 |
JP2018195798A (ja) | 2017-05-16 | 2018-12-06 | 富士電機株式会社 | 半導体装置 |
WO2019244485A1 (ja) | 2018-06-22 | 2019-12-26 | 富士電機株式会社 | 半導体装置の製造方法および半導体装置 |
WO2020213254A1 (ja) | 2019-04-16 | 2020-10-22 | 富士電機株式会社 | 半導体装置および製造方法 |
WO2021210293A1 (ja) | 2020-04-16 | 2021-10-21 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
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WO2018052099A1 (ja) | 2016-09-14 | 2018-03-22 | 富士電機株式会社 | Rc-igbtおよびその製造方法 |
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