WO2021031836A1 - 像素阵列基板 - Google Patents

像素阵列基板 Download PDF

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Publication number
WO2021031836A1
WO2021031836A1 PCT/CN2020/106658 CN2020106658W WO2021031836A1 WO 2021031836 A1 WO2021031836 A1 WO 2021031836A1 CN 2020106658 W CN2020106658 W CN 2020106658W WO 2021031836 A1 WO2021031836 A1 WO 2021031836A1
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WO
WIPO (PCT)
Prior art keywords
data line
pads
line pads
scan line
scan
Prior art date
Application number
PCT/CN2020/106658
Other languages
English (en)
French (fr)
Chinese (zh)
Inventor
李仰淳
郑圣谚
钟岳宏
李珉泽
廖光祥
连翔琳
王彦凯
徐雅玲
廖烝贤
Original Assignee
友达光电股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 友达光电股份有限公司 filed Critical 友达光电股份有限公司
Priority to DE112020003937.4T priority Critical patent/DE112020003937B4/de
Priority to KR1020217005464A priority patent/KR102524241B1/ko
Publication of WO2021031836A1 publication Critical patent/WO2021031836A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure

Definitions

  • the present invention relates to a pixel array substrate, and more particularly to a pixel array substrate in which scan line pads and data line pads are arranged along an arrangement direction.
  • the display panel Since the display panel has the advantages of small size and low radiation, the display panel has been widely used in various electronic products.
  • a large area of the driving circuit area is usually reserved at the periphery of the display area to install the driving circuit, and the sub-pixels are controlled by the driving circuit.
  • the driving circuit area located outside the display area makes the display panel have a very wide frame and limits the screen-to-body ratio of the product.
  • consumers With the advancement of technology, consumers have higher and higher requirements for the appearance of display panels. In order to increase consumers' willingness to buy, how to increase the screen-to-body ratio of display panels has become one of the problems that manufacturers want to solve.
  • the invention provides a pixel array substrate, which can improve the problem of signal mutual interference between scan line pads and data line pads.
  • At least one embodiment of the present invention provides a pixel array substrate including multiple scan line pads, multiple data line pads, multiple scan lines, multiple data lines, multiple gate transmission lines, multiple pixels, data Line signal chip and scan line signal chip.
  • the scan line pads and the data line pads are located on the substrate.
  • the scan line extends along the first direction.
  • the data line and the gate transmission line extend along the second direction.
  • the data line is electrically connected to the data line pad.
  • the scan line is electrically connected to the scan line pad through the gate transmission line.
  • the pixels are located on the substrate.
  • the ratio of the number of rows of pixels arranged along the first direction to the number of rows of pixels arranged along the second direction is X:Y.
  • Each pixel includes m sub-pixels, and the sub-pixels are electrically connected to the scan line and the data line.
  • the data line signal chip is electrically connected to the data line pad, and the scan line signal chip is electrically connected to the scan line pad.
  • At least one embodiment of the present invention provides a pixel array substrate including a plurality of scan line pads, a plurality of first data line pads, a plurality of second data line pads, a plurality of third data line pads, and a plurality of Scan lines, multiple data lines, multiple gate transmission lines, multiple red sub-pixels, multiple green sub-pixels, multiple blue sub-pixels, and at least one thin-film-on-chip packaging circuit.
  • the scan line pads, the first data line pads, the second data line pads and the third data line pads are located on the substrate.
  • the scan line pads, the first data line pads, the second data line pads, and the third data line pads are arranged in the arrangement direction.
  • the scan line extends along the first direction.
  • the data line and the gate transmission line extend along the second direction.
  • the scan line is electrically connected to the scan line pad through the gate transmission line.
  • the data line is electrically connected to the first data line pad, the second data line pad and the third data line pad.
  • the red sub-pixel, the green sub-pixel, and the blue sub-pixel are electrically connected to the scan line and the data line.
  • the red sub-pixel is electrically connected to the first data line pad.
  • the green sub-pixel is electrically connected to the second data line pad.
  • the blue sub-pixel is electrically connected to the third data line pad.
  • the number of scan line pads located between the first data line pads and the second data line pads or between the third data line pads and the second data line pads in the arrangement direction is less than that of the first data line pads.
  • the chip on film package circuit includes a data line signal chip and a scan line signal chip.
  • the data line signal chip is electrically connected to the first data line pad, the second data line pad and the third data line pad.
  • the scan line signal chip is electrically connected to the scan line pad.
  • FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • FIG. 2A is a schematic top view of a display area of a pixel array substrate according to an embodiment of the invention.
  • 2B is a schematic top view of a sub-pixel according to an embodiment of the invention.
  • 3A is a schematic top view of a chip-on-film package circuit according to an embodiment of the invention.
  • 3B is a schematic top view of a chip-on-film package circuit according to an embodiment of the invention.
  • FIG. 4 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • FIG. 6 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • FIG. 8 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 3 of the present invention.
  • FIG. 9 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • Fig. 10A is a schematic cross-sectional view taken along line aa' in Fig. 9.
  • Fig. 10B is a schematic cross-sectional view taken along line bb' of Fig. 9.
  • GI Gate insulating layer
  • PE pixel electrode
  • first and second may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not Subject to these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.
  • FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • 2A is a schematic top view of a display area of a pixel array substrate according to an embodiment of the invention.
  • FIG. 2B is a schematic top view of the sub-pixel in FIG. 2A.
  • 3A is a schematic top view of a chip-on-film package circuit according to an embodiment of the present invention.
  • FIG. 3A is, for example, an enlarged schematic diagram of the chip-on-film package circuit COF of FIG. 3B is a schematic top view of a chip-on-film package circuit according to an embodiment of the invention.
  • the pixel array substrate 10 includes a plurality of scan line pads G and a plurality of data line pads (such as a first data line pad D1, a second data line pad D2, and a third data line pad D3) , A plurality of scan lines 110, a plurality of data lines 210, a plurality of gate transmission lines 120, a plurality of pixels (not shown in FIG. 1), and at least one COF.
  • the pixel array substrate 10 further includes a plurality of first fan-out lines 130 and a plurality of second fan-out lines 220.
  • the substrate SB has a display area AA and a peripheral area BA located outside the display area AA.
  • the material of the substrate SB can be glass, quartz, organic polymer, or opaque/reflective material (for example, conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive material or metal is used, an insulating layer (not shown) is covered on the carrier board SB to avoid short circuit problems.
  • the scan line pad G is located on the substrate SB. In this embodiment, the scan line pad G is located on the peripheral area BA.
  • the first fan-out line 130 electrically connects the scan line pad G to the gate transmission line 120.
  • the scan line 110 and the gate transmission line 120 are located on the display area AA.
  • the scan line 110 extends along the first direction E1, and the gate transmission line 120 extends along the second direction E2.
  • the gate transmission line 120 is electrically connected to the scan line 110 through the switching structure CS, and the scan line 110 is electrically connected to the scan line pad G through the gate transmission line 120 and the first fan-out line 130.
  • each scan line pad G is electrically connected to the corresponding two scan lines 110, thereby reducing the number of scan line pads G, but the invention is not limited thereto. In other embodiments, different scan lines 110 do not share the same scan line pad G.
  • the data line pads (such as the first data line pad D1, the second data line pad D2, and the third data line pad D3) are located on the substrate SB. In this embodiment, the data line pads are located on the peripheral area BA.
  • the second fan-out line 220 is electrically connected to the data line pad to the data line 210.
  • the data line 210 extends along the second direction E2.
  • each pixel 300 includes a red sub-pixel P1, a green sub-pixel P2, and a blue sub-pixel P3, but the invention is not limited to this. In other embodiments, each pixel PX further includes sub-pixels of other colors.
  • the pixel array substrate 10 is driven in a HG2D (half-gate two-data line) manner, and each sub-pixel (red sub-pixel P1, green sub-pixel P2) And the blue sub-pixel P3) overlaps the corresponding two of the data lines 210 and the corresponding one of the scan lines 110.
  • HG2D half-gate two-data line
  • the sub-pixels are electrically connected to the scan line 110 and the data line 210.
  • the red sub-pixel P1, the green sub-pixel P2, and the blue sub-pixel P3 are electrically connected to the scan line 110 and the data line 210.
  • the red sub-pixel P1 is electrically connected to the first data line pad D1.
  • the green sub-pixel P2 is electrically connected to the second data line pad D2.
  • the blue sub-pixel P3 is electrically connected to the third data line pad D3.
  • Each sub-pixel includes a switching element T and a pixel electrode PE.
  • the switching element T includes a gate GE, a channel layer CH, a source SE, and a drain DE.
  • the gate GE is located on the substrate SB and is electrically connected to the corresponding scan line 110.
  • the channel layer CH overlaps the gate GE, and a gate insulating layer is sandwiched between the channel layer CH and the gate GE (illustration omitted in the figure).
  • the source SE and the drain DE are electrically connected to the channel layer CH.
  • the source SE is electrically connected to the data line 210.
  • the flat layer (illustration omitted in the figure) is located on the source SE and the drain DE.
  • the pixel electrode PE is located on the flat layer and is electrically connected to the drain electrode DE through the opening O penetrating the flat layer.
  • the pixel array substrate 10 further includes a common signal line CL1, a common signal line CL2, and a common signal line CL3.
  • the common signal line CL1, the common signal line CL2, and the scan line 110 all extend along the first direction E1, and the common signal line CL1, the common signal line CL2, and the scan line 110 belong to the same conductive layer (for example, the first metal layer).
  • the common signal line CL3, the data line 210, and the gate transmission line 120 all extend along the second direction E2, and the common signal line CL3, the data line 210, and the gate transmission line 120 belong to the same conductive layer (for example, a second metal layer).
  • the scan line pads G and the data line pads are arranged in the arrangement direction RD.
  • the scan line pads G and the data line pads are arranged in a first row L1 and a second row L2 in the arrangement direction RD.
  • the pads in the first row L1 are aligned with each other, and the pads in the second row L2 are aligned with each other.
  • the pads located in the first row L1 and the pads located in the second row L2 belong to different metal layers.
  • the pads located in the first row L1 belong to the first metal layer
  • the pads located in the second row L1 belong to the first metal layer
  • the pads of the two rows L2 belong to the second metal layer, and an insulating layer is provided between the first metal layer and the second metal layer, so as to avoid short circuits between adjacent pads.
  • the scan line connected between the first data line pad D1 and the second data line pad D2 or between the third data line pad D3 and the second data line pad D2 in the arrangement direction RD The number of pads G is less than the number of scan line pads G located between the first data line pad D1 and the third data line pad D3, thereby improving the gap between the scan line pads G and the data line pads. The effect of signal interference on the display screen.
  • the chip on film package circuit COF is electrically connected to the scan line pad G and the data line pad D (for example, the first data line pad D1, the second data line pad D2, and the third data line pad D3).
  • the COF includes a data line signal chip DC, a scan line signal chip GC, a first insulating layer I1, a second insulating layer I2, a third insulating layer I3, and a first wire layer CC1.
  • the second wire layer CC2 a plurality of first connection structures CH1, a plurality of second connection structures CH2, a plurality of third connection structures CH3, and a plurality of fourth connection structures CH4.
  • the first insulating layer I1, the second insulating layer I2, and the third insulating layer I3 overlap in order.
  • the data line signal chip DC and the scan line signal chip GC are located on the first insulating layer I1.
  • the first wire layer CC1 is located between the second insulating layer I2 and the first conductive layer I1.
  • the plurality of first connection structures CH1 penetrate the first insulating layer I1 and are electrically connected to the first wire layer CC1.
  • the second wire layer CC2 is located between the second insulating layer I2 and the third conductive layer I3.
  • the plurality of second connecting structures CH2 penetrate the first insulating layer I1 and the second insulating layer I2, and are electrically connected to the second conductive layer CC2.
  • the wiring space of the first wire layer CC1 and the second wire layer CC2 can be effectively increased.
  • the third connection structure CH3 penetrates the second insulating layer I2 and the third conductive layer I3, and is electrically connected to the first wire layer CC1.
  • the plurality of fourth connection structures CH4 penetrate the third insulating layer I3 and are electrically connected to the second wire layer CC2.
  • the data line signal chip DC is electrically connected to one of the first conductive layer CC1 and the second conductive layer CC2, and the scan line signal chip GC is electrically connected to the other of the first conductive layer CC1 and the second conductive layer CC2 By.
  • the data line signal chip DC is electrically connected to the first conductive layer CC1
  • the scan line signal chip GC is electrically connected to the second conductive layer CC2.
  • the data line signal chip DC is electrically connected to the data line pads (for example, the first data line pad D1, the second data line pad D2, and the third data line pad D3 of FIG. 1), and the scan line signal chip GC is electrically connected Connect to the scan line pad G.
  • the data line signal chip DC and the scan line signal chip GC are both located on the same side of the display area AA. Therefore, the frame of the display panel can be reduced, thereby increasing the screen-to-body ratio of the display device.
  • the width between the side of the display area AA where the COF is not provided and the edge of the pixel array substrate 10 is less than 2 mm.
  • a chip-on-film package circuit COF includes a data line signal chip DC and a scan line signal chip GC. Therefore, the first fan-out line 130 and the second fan-out line 220 may not overlap each other, thereby improving the first The signal interference between one fan-out line 130 and the second fan-out line 220 affects the display image.
  • the pixel array substrate 10 includes n scan line signal chips GC.
  • the pixel array substrate 10 includes two chip-on-film packages COF, and each chip-on-film package circuit COF has one scan line signal chip GC. Therefore, the pixel array substrate 10 includes two scan line signal chips.
  • GC that is, n is 2. In other embodiments, n is greater than 2.
  • each scan line 110 is electrically connected to multiple scan line signal chips GC, so that the signal on the scan line 110 can be distributed more evenly.
  • the pixel array substrate 10 includes n scan line signal chips GC, and each scan line 110 is electrically connected to the n scan line signal chips GC.
  • FIG. 4 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 1 of the present invention.
  • the scan line pads G and the data line pads D are arranged into a plurality of repeating units PU in the arrangement direction RD, and each The total number of scan line pads G and data line pads D in the repeating unit PU is U.
  • the scan line pads G and the data line pads D in the repeating unit PU can be divided into a first row L1 and a second row L2 as shown in FIG. 1.
  • the first pad in the first row L1 in Figure 1 is the first pad in Figure 4
  • the first pad in the second row L2 in Figure 1 is the second pad in Figure 4.
  • the second pad in the first row L1 in FIG. 1 is the third pad in FIG. 4, and the arrangement order of the other pads is similarly deduced.
  • the ratio of the number of rows of pixels PX arranged along the first direction E1 to the number of rows of pixels PX arranged along the second direction E2 is X:Y.
  • X:Y is 16:9.
  • each pixel PX includes m sub-pixels, where m is a positive integer.
  • the scan line pad G and the data line pad D conform to the rule of Formula 1.
  • n is the number of scan line signal chips, and a, k, and h are positive integers.
  • the pixel array substrate is driven in HG2D mode, and each sub-pixel overlaps two data lines and one scan line.
  • each scan line pad G is electrically connected to two corresponding scan lines.
  • part of the scan line pads G is located in the first row L1
  • another part of the scan line pads G is located in the second row L2 (as shown in FIG. 1)
  • part of the scan line pads G belongs to the first metal layer
  • another part of the scan line pad G belongs to the second metal layer.
  • a is 1
  • k is 4
  • h is 1.
  • Each pixel PX includes 3 sub-pixels, that is, m is 3.
  • the pixel array substrate has 3 scan line signal chips, that is, n is 3.
  • Embodiment 1 in order to make the scan line pads G and the data line pads D more uniformly dispersed, the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of formula 2.
  • N is an integer between 1 and k+1.
  • R 2 ⁇ 3 ⁇ 1 to 2 ⁇ 3 ⁇ 5, which means that the number of data line pads D between two adjacent scan line pads G is between 6 and 30.
  • FIG. 5 is a schematic top view of a pixel array substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 5 uses the element numbers and part of the content of the embodiment of FIG. 1, wherein the same or similar reference numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.
  • the difference between the pixel array substrate 20 of FIG. 5 and the pixel array substrate 10 of FIG. 1 is that in the pixel array substrate 20, different scan lines 110 do not share the same scan line pad G.
  • each gate transmission line 120 is electrically connected to a corresponding scan line pad G to a corresponding scan line 110.
  • FIG. 6 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 2 of the present invention.
  • the scan line pads G and the data line pads D are arranged into a plurality of repeating units PU in the arrangement direction RD, and each The total number of scan line pads G and data line pads D in the repeating unit PU is U.
  • the scan line pads G and the data line pads D in the repeating unit PU can be divided into a first row L1 and a second row L2 as shown in FIG. 5.
  • the first pad in the first row L1 in Figure 5 is the first pad in Figure 6, and the first pad in the second row L2 in Figure 5 is the second pad in Figure 6,
  • the second pad in the first row L1 in FIG. 5 is the third pad in FIG. 6, and the arrangement order of the other pads is similarly deduced.
  • each pixel PX includes m sub-pixels, where m is a positive integer.
  • the scan line pad G and the data line pad D conform to the rule of Formula 1.
  • the pixel array substrate is driven in HG2D mode, and each sub-pixel overlaps two data lines and one scan line.
  • each scan line pad G is electrically connected to a corresponding scan line, and different scan lines are not directly electrically connected through the scan line pad or the gate transmission line.
  • part of the scan line pads G is located in the first row L1
  • another part of the scan line pads G is located in the second row L2 (as shown in FIG. 5)
  • part of the scan line pads G belongs to the first metal layer
  • And another part of the scan line pad G belongs to the second metal layer.
  • a 1, k is 2, and h is 1.
  • Each pixel PX includes 3 sub-pixels, that is, m is 3.
  • the pixel array substrate has 3 scan line signal chips, that is, n is 3.
  • the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of formula 2.
  • R 2 ⁇ 3 ⁇ 1 to 2 ⁇ 3 ⁇ 3, which means that the number of data line pads D between two adjacent scan line pads G is between 6 to 18.
  • FIG. 7 is a schematic top view of a pixel array substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 7 uses the element numbers and part of the content of the embodiment of FIG. 2A, wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.
  • the difference between the pixel array substrate 30 of FIG. 7 and the pixel array substrate 10 of FIG. 2A is that the pixel array substrate 30 is driven in a 1G1D (one-gate one-data line) manner, and each sub-pixel (red sub-pixel P1, green sub-pixel The sub-pixel P2 and the blue sub-pixel P3) overlap the corresponding one of the data lines 210 and the corresponding one of the scan lines 110.
  • 1G1D one-gate one-data line
  • Fig. 8 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 3 of the present invention.
  • the scan line pads G and the data line pads D are arranged into a plurality of repeating units PU in the arrangement direction RD, and each The total number of scan line pads G and data line pads D in the repeating unit PU is U.
  • FIG. 8 is used to show the arrangement sequence of the scan line pads G and the data line pads D in the repeating unit PU, and the scan line pads G and the data line pads D in the repeating unit PU are not completely aligned.
  • the scan line pads G and the data line pads D in the repeating unit PU can be divided into a first row L1 and a second row L2 as shown in FIG. 5.
  • the first pad in the first row L1 in Figure 1 is the first pad in Figure 8
  • the first pad in the second row L2 in Figure 5 is the second pad in Figure 8.
  • the second pad in the first row L1 in FIG. 5 is the third pad in FIG. 8, and the arrangement order of the other pads is similarly deduced.
  • each pixel PX includes m sub-pixels, where m is a positive integer.
  • the scan line pad G and the data line pad D conform to the rule of Formula 1.
  • the pixel array substrate is driven in a 1G1D manner, and each sub-pixel overlaps a data line and a scan line.
  • each scan line pad G is electrically connected to a corresponding scan line, and different scan lines are not directly electrically connected through the scan line pad or the gate transmission line.
  • part of the scan line pads G is located in the first row L1, another part of the scan line pads G is located in the second row L2 (as shown in FIG. 5), and part of the scan line pads G belongs to the first metal layer , And another part of the scan line pad G belongs to the second metal layer.
  • a is 1
  • k is 1
  • h is 1.
  • Each pixel PX includes 3 sub-pixels, that is, m is 3.
  • the pixel array substrate has 3 scan line signal chips, that is, n is 3.
  • Embodiment 3 in order to make the scan line pads G and the data line pads D more evenly dispersed, the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of formula 2.
  • R 2 ⁇ 3 ⁇ 1 to 2 ⁇ 3 ⁇ 2, which means that the number of data line pads D between two adjacent scan line pads G is between 6 and 12.
  • FIG. 9 is a schematic top view of a pixel array substrate according to an embodiment of the invention.
  • Fig. 10A is a schematic cross-sectional view taken along line aa' in Fig. 9.
  • Fig. 10B is a schematic cross-sectional view taken along line bb' of Fig. 9.
  • the embodiment of FIG. 9 uses the element numbers and part of the content of the embodiment of FIG. 5, wherein the same or similar reference numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.
  • the scan line pads G are all located in the same row.
  • the scan line pads G are all located in the first row L1 or the scan line pads G are all located in the second row.
  • the pads located in the first row L1 (including the scan line pads G and the data line pads D) belong to the first metal layer M1
  • the pads located in the second row L2 (including the data line pads) D) belongs to the second metal layer M2.
  • the pads in the second row L2 belong to the first metal layer M1
  • the pads in the first row L1 belong to the second metal layer M2.
  • all the scan line pads G are aligned with each other in the arrangement direction RD.
  • the scan line pads G belong to the first metal layer M1. Therefore, it is possible to reduce the number of different scan lines 110 due to the transfer structure (for example, the transfer from the first metal layer M1 to the second metal layer M2). Connection structure) and cause the signal to be offset.
  • the transfer structure for example, the transfer from the first metal layer M1 to the second metal layer M2. Connection structure
  • the first metal layer M1 is located on the substrate SB.
  • the gate insulating layer GI covers the first metal layer M1.
  • the gate insulating layer GI on the pad (such as the scan line pad G) belonging to the first metal layer M1 has a through hole TH1.
  • the flat layer PL is located on the gate insulating layer GI, and on the pads belonging to the first metal layer M1 (such as the scan line pad G) and on the pads belonging to the second metal layer M2 (such as the third data line pad D3). ) Has through holes TH2.
  • a plurality of conductive structures CP are filled in the through hole TH1 and the through hole TH2 to be electrically connected to the corresponding scan line pad G and the third data line pad D3, respectively.
  • the material of the conductive structure CP includes, for example, metal oxide.
  • the pixel array substrate is driven in HG2D, and each sub-pixel overlaps two data lines and one scan line.
  • each scan line pad G is electrically connected to two corresponding scan lines.
  • all the scan line pads G belong to the same metal layer (for example, the first metal layer or the second metal layer).
  • a is 2
  • k is 4
  • h is 1.
  • Each pixel PX includes 3 sub-pixels, that is, m is 3.
  • the pixel array substrate has 3 scan line signal chips, that is, n is 3.
  • Embodiment 4 in order to make the scan line pads G and the data line pads D more evenly dispersed, the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of Equation 3.
  • N is an integer between 1 and k+1.
  • R 2 ⁇ 3 ⁇ 1+1 to 2 ⁇ 3 ⁇ 5+1, which means that the number of data line pads D between two adjacent scan line pads G is between 7 and 31.
  • the invention provides a pixel array substrate, which can improve the problem of signal mutual interference between scan line pads and data line pads.

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