TWI352958B - Liquid crystal display panel and the driving metho - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel and a method of driving the same, and more particularly to a liquid crystal display panel and a method of driving the same for improving the manner of providing a signal line signal and compensating for a related parasitic capacitance effect. [Prior Art] With the wide application of liquid crystal display panels, users are increasingly demanding the quality of liquid crystal display panels such as high brightness, high contrast, high resolution, high color saturation, and #fast time response. . In particular, as the panel area is increased, the use of a liquid crystal display panel to form a home flat panel display, such as a liquid crystal television, has become an important application of the liquid crystal display panel. Generally, there are many conventional liquid crystal display panels. For the viewing angle, only the front side of the liquid crystal display panel can be viewed as a normal picture. If viewed from a larger viewing angle, there will be color distortion, and even a gray-inversion will occur. The phenomenon, that is, the situation where the light and the dark are reversed. Therefore, how to widen the viewing angle has become an important issue to be solved when manufacturing a liquid crystal display panel. In many ways to increase the viewing angle, vertical alignment of liquid crystal (Vertical A11 gnmen t; VA) is still one of the mainstream technologies on the market. However, when the liquid crystal molecules are arranged vertically in a single direction (m〇n〇_d〇main VA), as the liquid crystal molecules rotate in the direction, since all the liquid crystal molecules are parallel, the angle of view of the opposite angle is still limited and cannot be viewed. Therefore, multi-domain VA technology is widely used and improved to enhance the visual quality of various angles. Among them, Fujitsu of Japan tried to set a bump (bump or bump) on the color light-emitting sheet to use the tilting electric field generated by the bump to control the 1352958 liquid helium molecule to automatically align according to the region. However, due to the design of the bumps, precise alignment between the color filter and the active matrix substrate is required, and an additional cover (〇ver(10)(4)) is added to the color light-emitting sheet, resulting in poor yield and cost. In order to improve the shortcomings of the above-described multi-region vertical alignment liquid crystal display, a liquid crystal display panel in which a diagonal torsion vertical alignment (Blas_Bending Verticai (5); BBVA) is proposed. Fig. 1 is a cross-sectional view of a liquid crystal display panel in which a diagonally perpendicularly arranged φ is diagonally arranged. The liquid crystal display panel 10 includes a color filter 11, a liquid crystal layer 12, and an active matrix substrate 13. The color filter 11 and the active substrate 13 have a transparent substrate 丨丨i and a 丨3 color filter 11 respectively. There is a common electrode 112 and a pixel electrode 134' on the active substrate 13, and a main electric field is formed between the common electrode 112 and the pixel electrode 134, and the control electrode 133 and the pixel electrode on the active substrate 13 are formed. 134 generates an electric field which causes the liquid crystal molecules 121 to form a tilt angle symmetry. Another insulating layer 132 is disposed between the control electrode 133 and the pixel electrode 134. _ 仁疋田< Vc〇n <Vp, a disclination line is generated in the center of the area a, where vCE and VP represent the potentials of the control electrode, the common electrode and the pixel electrode, respectively. This kind of two-eye outward disc (disclinati〇n) line causes a decrease in the light transmittance of the liquid crystal layer 12, a slow reaction time, and instability of the liquid crystal molecules. In order to avoid this undesirable phenomenon, it is desirable to satisfy the following conditions in polarity inversion: When the halogen is a positive frame, Vu > Vp > Vc. TM .... (Condition 1); and

When the halogen is a negative frame, then K 6 • (Condition 2). The book = map? The equivalent circuit diagram of the pixel structure proposed by Samsung Electronics, the circuit of ~ will eliminate the shortcomings of the external line of the two eyes. Also available as item - and condition 2. However, since each pixel contains three ==: truncations, as long as one of the thin films is damaged, the pixel is = :, so the manufacturing yield is still unable to meet acceptable standards. Another aspect

The number of (4) transistors connected to the scanning line is too large, causing severe RC delay in scanning signal transmission.

(5) In view of the shortcomings of the various wide-angle liquid crystal display products mentioned above, the author proposed a vertically arranged wide viewing angle liquid crystal display technology in 2004 (see Taiwan Patent Publication No. 1239424 for details). Fig. 3 is a diagram showing the equivalent circuit diagram of the pixel structure of such a vertically arranged liquid crystal display panel. Only four phases are listed; the elements are respectively composed of scan lines 36 362 and 363 (representing I" k and G „, respectively) and data lines 351, 352 and 353 (representing ^^ and 仉, respectively) Formed again. Each of the pixels includes a first thin film transistor T|, a second thin germanium transistor T2, a control electrode 34, and a pixel electrode 33. The first thin film transistor T has a first terminal connected to a data line 353 and a second terminal connected to the pixel electrode 33, and a gate connected to a scan line 363. The first terminal of the second thin germanium transistor τ2 is connected to another adjacent data line 352, the second terminal of which is connected to the control electrode 34, and the gate thereof is connected to another adjacent scan line 3 62 ^ A liquid crystal capacitor c is formed between the pixel electrode 33 and the common electrode 37. The control electrode 34 and the pixel electrode 33 form a diagonal torsional capacitance c2, and a capacitor C3 is formed between the control electrode 34 and the common electrode 37. In Figure 3, 1 and Gm intersect with the pixel β (the pixel in the lower right corner is 1 1352958), and the data lines 352 and 353 and the upper scanning lines 362 and 363 are hunted by the left and right sides. Control, wherein during the operation of the halogen element, the 'signal number is in two adjacent horizontal scanning periods or - vertical scanning period, -" the control electrode 34 and the pixel electrode 33 can be written to the potential of the wave and the control 34 The potential change of the pixel electrode 33 generates a -coupled position such that the polarity of the potential of the control electrode 34 can be changed with the pixel polarity 33, and when the pixel is positive, the control electrode 34

: controlling the potential Vp higher than the halogen electrode 33; and the pixel 6 is the negative electrode: the potential VcE of the control electrode 34 can be controlled to be lower than the potential of the halogen electrode μ: ' Condition 2 requirements. And as in (10), each of the alizarin contains only two thin film transistors (I and L), so that the yield of the panel process can be improved and the aperture ratio of the pixels can be improved. On the other hand, the reduction in the number of thin film transistors connected to the same scanning line also reduces the problem of scanning the RC delay of the §100 million transmission. However, as in the pixel design of Figure 3, each of the elements is controlled by the data lines on the left and right sides and the scanning lines on the upper and lower sides, that is, each element must be electrically coupled to two data lines. And two scan lines; in other words, according to the entire panel I pixel matrix area, if the pixel matrix contains n pixel rows and a pixel column (ie, a pixel matrix of 1Ι1), as shown in FIG. As shown, the pixel matrix will require η + 1 data lines (D, Dn+1) & m + i scan lines (G1 ~ GmH) to drive each element. That is, the left and right sides of the outermost periphery of the pixel matrix 4〇〇 each have a data line, which is a data line D, and a data line DnH, and the upper and lower sides of the outer periphery each have a scan line, which is a scan line G| And scan lines. However, in the case of an nxm pixel matrix in a conventional panel, if each pixel has only one 8 1352958 Å film-forming transistor, it generally requires only n data lines and m scanning lines. It is a combination of a source driver that provides n data signals and a gate driver that provides m scan signals. For example, the matrix structure of Figure 4 has η+ι data lines and! „+1 scan lines' so it needs to be equipped with a source driver that can provide one data signal and a gate driver that can provide m+1 scan signals. In other words, the traditional/this provides n lean materials. Source and gate drive of signal and m scan signals

The actuator will no longer be suitable for 'an additional design' - a new source and gate driver with it. For example, in the case of an XGV panel of 1024 χ768, a conventional source driver provides 1024 data signals. However, if the pixel matrix of Figure 4 is used, it will need to provide a source of 1 to 25 data signals. driver. However, as we know, to redesign a driver, especially a source driver, will cost a considerable amount of money, and in view of this, an improved liquid crystal display panel and driver will be proposed for the pixel matrix of FIG. The method to solve this problem. SUMMARY OF THE INVENTION The purpose of the viewing angle is to provide a liquid crystal display panel, which has a wide potential when the positive polarity is used, and the potential of the control electrode will be asked about the potential of the pixel electrode, and the potential is lower than the book oscillating electrode. When the L element is a negative polarity, the control electrode - the conventional source driver I and "the data signal of the material line can be provided by the matrix = : = system provides a liquid crystal display panel with 3 pixels per pixel and (4) pixel columns. And the state-controlled pixels are controlled by the state-owned 9 丄乃烈58 material line and m+l scanning line, and the n-data signal can be driven by the n-data source to drive the n+ 1 data line. Another object of the present invention is to provide a liquid crystal display panel having Γ1 + 1 /{"in the middle! LL·"" inch deep used to control the pixels in the panel, and its n +1 The signal line of the data line can be provided by a JL ancient / / traditional source driver with n tributary signal output sources, without the need to design a new source driver. A further object of the present invention is to provide a liquid crystal display panel having a

Once, the total number of internal data lines is larger than the total number of pixels, and it can operate the internal elements without changing the structure of the traditional source driver. The signal transmission RC delay that may be caused is not symmetrical to the parasitic capacitance. According to the above object, the present invention provides a liquid crystal display panel, wherein the liquid crystal display panel comprises a plurality of elements, wherein the plurality of data lines and the plurality of scanning lines intersect each other. Each of the halogens includes a first thin film transistor and a second thin film

A ~ control electrode and - halogen electrode. The first terminal of the first thin film transistor is connected to :==! The two terminals are connected to the pixel electrode, and the gate is connected to the - scan line. The first end of the crystal is connected to the other adjacent data line, and the second end is connected to the other adjacent scan line. Wherein, the pixel matrix takes the _ of the two peripheral lean lines, and shakes the adjacent read line, and the boundary is a non-phased read line finger, and the boundary: the frequency is closely related to the line f line. The liquid crystal age panel, in addition to Caiguang*... is connected with another non-adjacent data line, and the shape is sneaked out of the 14th, because the money will be used by the border line, it can be matched with the traditional source driver; Can be reduced as a result; new source drivers. At the same time, _ _ ', without the need to separately design a precision line set between the boundary data line and its adjacent pixel 10 1352958 electrode, thereby improving the signal RC that may be generated during the transmission of the data signal The problem of delay and asymmetry of parasitic capacitance. [Embodiment]

5 is a schematic diagram of an equivalent circuit of a liquid crystal display panel according to a first embodiment of the present invention, wherein the liquid crystal display panel 5 includes a pixel matrix 5 of -nxm, and the overall structure is the same as that of the fourth figure. The pixel matrix is 4〇〇, with n pixel lines and! 1! A series of pixels, and n + 1 data lines and m + 1 scanning lines control the internal pixels, and the connection between each thin film transistor and the capacitor in each pixel is the same as the fourth picture The connection is the same, and therefore will not be described again, and the same components are denoted by the same symbols. A source driver 5〇2 has n signal source output pins PrPn, which provide (10) n+1 data lines of the data source signal T-cell matrix 500. In order to solve the problem that the source driver 5〇2 data signal cannot match the total number of data lines, the present invention is

As shown in Fig. 5, the data line ^, called the boundary data line on the leftmost side of the left side of the pixel matrix 5, is electrically connected to another non-adjacent data line, as shown in Fig. 2, data line D, ^ It is connected to the data line D3. In other words, the data signal of the data line is provided by the data line D3. In this way, the state data line will only need n data sources, so it will be matched—the traditional source driver that only provides n data sources, and then redesigned—the source driver; The data line connection method of the embodiment of FIG. 5 will also make the data line (1) corresponding to the prime line (ie, the " the line of the line) in the display operation of the element, satisfy the requirements of the condition - and condition 2, This point and the pixel display operation mode of the liquid crystal display panel 511 will be explained as follows. ...the diagram shows that there are any six adjacent pixel units in Figure 5, and the _ contains two pixels in the first *^ 怿 仃 及 及 and four in the second

Articles and Articles 3 are full of sounds M - Dan. The six adjacent pixels shown in Figure 6 are scanned lines 561, 562 ^, '' and 563 (for the scan lines G!, G2 and G3, respectively) and data lines 551, 552, b ' M3 And 554 (representing the data line, the Dz, the 仏 and the DO intersection respectively. Each book - u den f early contains the first film transistor T 丨, the first thin film transistor Τζ, a control 啻 right Q / 4 ^ . The electrode 34, the pixel electrode 33, the same electrode 37, the liquid crystal, the diagonal torsion capacitance and the capacitance are connected as described above. Take the picture on the sixth line of the first financial line, for example, take the 2nd ι, _ 仃 仃 旦 旦 D 为 ' ' ' ' 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第Examples: ^ and ν〇3 represent the data signals acting on data lines 552 and 553, respectively, and Vu represents the known signals applied to scan lines 562 and 563, respectively. Scanning waves in each vertical scanning period include The first waveform and the second waveform during the time of Tp. Figure 7 takes the potential change of the relevant electrode of the waveform of the lower-column, where L and V4 represent D of the pixel electrode 33 and the pixel electrode 34, the potential of the control. Referring to Figure 7, when the time is in the first half of Vc2, the second thin film transistor D is turned on by VG2, and the data signal VD2 is written to the control electrode %, as shown in the figure. The potential of the control electrode is changed from the original potential (below VCQ01) to the same potential as vD2 (higher than D. At the same time, the potential of the data signal VD3 is turned on because the first-thin film transistor T1 is selected by VG3. V(10)) is thus written into the halogen electrode 33. In the second half of the L, β τ, the first 溥 film transistor T| is selected and turned on, and the potential of the data signal Vm between 12 1352958 (higher than vct) B) will therefore be written to the halogen electrode 33. Since the second thin film transistor T2 is turned off at this time, the control electrode 34 is in a floating state, and the control electrode 34 is lifted to a greater extent by the effect of capacitive coupling. High potential. As is clear from Fig. 7, when the pixel is positive, it satisfies ^ &gt; VP &gt; L. When the period of the vertical-sweeping cat is over, the polarity of the pixel changes to the negative polarity, and then VcKVKV^ is satisfied. Therefore, the pixel structure of Fig. 6 and the control waveform of Fig. 7 will make the operation of each pixel unit satisfy the condition one (vCE&gt;vP&gt; and condition two (VcE<Vp&lt;v one, and thus eliminate The problem of the two-eye chsdination 1 is that the driving signal of the pixel of the present invention is not limited to the driving mode of the seventh figure, and any driving mode tb that satisfies the condition 1 and the condition 2 can be made. $ ' is white for application. In addition, it should be noted that, in the case of pixel D, the potential of the pixel electrode 33 is provided by the data signal VD3, = to show the desired picture 'so for the pixel electrode 33 The potential of the potential = that is: the size of the material ... size value) will have more stringent requirements; and • control the potential of the Tingji 34 by the data 吒妒 V 裎祉 eight early m... Beko several Vd2 &amp; for ' The purpose is to generate an electric field that causes the liquid crystal knife to form a tilt angle. The purpose is only to generate a -pour angle electric field, and the potential supply is not required to be as precise as the potential I of the book oscillating electrode: the magnitude of the potential requires the quasi-position requirement. In general, the potential of the control electrode is required to be oral. Conversely (such as the dry b of Figure 7 and the pole W of the pixel electrode 33) and P, the pixel operation can satisfy the condition - (~&gt; ^ σ... (Vp&gt;V_). Therefore, the same figure, as shown in Fig. 6. As shown, Tian Hong’s singer’s singularity on the line of D2’s D π π , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , (ie, boundary data 13 1352958 line) The data line Da connected, the polarity of the signal provided must be opposite to the polarity of the data line D2. In addition, as mentioned above, the potential requirement of the control electrode is not as pixel The requirements of the electrode 33 are rigorous. Therefore, in the present invention, the potential of the control electrode 34 is mainly provided by other data lines (for example, the potential of the data line (1) is provided by the data line h), but in other embodiments, the drawing is not excluded. The potential of the element electrode 33 is provided by other data lines. In general, the liquid crystal display panel is used to solve the problem of crosstalk (cr〇ss talking) φ or flicker (f 1 icker), and usually takes a face inversion (frame) Inversion), column inversion (row inversi〇n), line inversion (c〇lumn inversion) or dot inversion Inverted driving technology (dot inversion), in which point inversion driving technology is most commonly used. One of the characteristics of dot inversion driving is that the signal polarities of two adjacent data lines are opposite to each other. Therefore, Figure 5 or - In the liquid crystal display panel of Fig. 6, if the dot inversion drive operation is performed, the signal polarities of the data line D2 and the data line Da will be opposite to each other. Therefore, the embodiment of Fig. 5 will be the boundary data line (data line (1) ) Connected to the data line Da electrically connected to c, • will make the boundary data line obtain the voltage opposite to the polarity of the data line D2. Since the span of the boundary material line and the data line Da is the shortest, the boundary data line is better connected with the data line D3, which not only saves the required wire cost, but also makes the data line short due to the short transmission path. The overall resistance value is small, which reduces the problem of signal delay. However, it is worth noting that the boundary data line is not limited to being connected to the data line Da, and may be connected to any data line that provides a signal polarity opposite to the data line I (ie, the data line adjacent to the boundary data line). . As shown in Fig. 8, in another embodiment, the boundary data line and the data line h are connected to E. In addition, although the connection between the boundary data line and the data line I in Fig. 5 is located outside the 昼素"_, the present invention does not limit the connection (which may be located in the pixel matrix 500). In any position. In addition, although the scanning line end (gate extreme) of the panel of Figure 5 corresponds to the (four) scanning lines, it is also necessary to provide a scanning signal for driving the pixels. The closed-circuit driver for the scan signal will no longer be suitable. However, since the circuit design of the gate driver is generally easier than the circuit design of the source driver, the redesign - the gate driver will be redesigned than the Lu - The cost of the source driver is much lower. Therefore, the signal of the m+H scanning line provides a suggestion that a gate driver can be redesigned and the present invention will mainly focus on the way the information signal of the panel is provided. However, in other implementations, the manner in which the source signal of the source of the invention is provided can also be extended to the provision of the gate extreme scanning signal. In the embodiment, the outermost data line D on the left side of the pixel matrix 500 is defined as a boundary data line, and the boundary data line is electrically connected to the data line Da, and the signal output pin of the source driver 5〇2 is used. h simultaneously provides a data signal to the boundary data line and the data line m. Thus, the pixel matrix 5 can match a conventional source driver to control the panel. Similarly, in another embodiment, As shown in Fig. 9, the outermost data line D„h on the right side of the pixel matrix 6〇〇 can also be defined as a boundary data line, and the boundary data line and the data line are electrically connected to the F, or any energy The data line of the signal polarity opposite to the data line Dn is electrically connected, so that the panel which originally needs n+1 data signals will only need n data signals, so it can match a conventional source driver. As for the signal waveform operation mode of the pixel matrix 6〇〇, it is similar to the first embodiment, and will not be described here. However, it is particularly noted that '15 1352958 is designed to match the data line connection design of FIG. The connection of the components within the unit The connection between the components in Figure 5 and the left is reversed, that is, the pixel in the last data line is taken as an example. The second transistor T2 is located on the right side of the pixel and is connected to the boundary data line (data line). Nt,) is connected, and the first transistor τi is located on the left side of the pixel and is connected to the data line Dn, so that the control electrode 34 can be provided by connecting the boundary lean line to the data line at F. The potential required. Φ However, as shown in Fig. 10, during the operation of the panel picture of the fifth figure, a parasitic capacitance will be generated between the parental electrode 33 of the mother pixel and the adjacent data line. A parasitic capacitance C2 is also generated between Ci, and the control power of each pixel, 34, and its adjacent data line. However, as shown in the first diagram, taking an mxn pixel matrix as an example, each elementary line system contains m elements, and each pixel element and its adjacent two sides of the pixel electrode generate one. The parasitic capacitances C1 and ο, so the data lines corresponding to each output pin of the source driver 5〇2 are respectively coupled with 2m Ci and 2m G. However, since the output pin P2 is connected to the data line D3 and the boundary data line, the data line corresponding to the output pin P3 is different from the other output pins and coupled with 3m and C. Therefore, the total parasitic capacitance value of its coupling will be greater than the other output pins. As a result, in the panel screen operation, the total load of the capacitor corresponding to the output pin P2 will be much larger than the other output pins, and the signal outputted by the output pin &amp; causes a serious RC delay problem in the transmission process. For example, comparing the data signal transmission on the data line 〇2/, the boundary bedding line (the lean line Di), the 11th and 11b are according to the first embodiment (Fig. 5 or i) In the figure, the sub-J is the $ map for the signal delay on the data, line and boundary data lines. U a 16 1352958 In the figure, G represents a scanning signal of a scanning line, w. The original signal waveform is sent from the output pin ρι, and the signal waveform will be transmitted through the data line 〇2 and driven by the corresponding scan lines to be received by the corresponding pixels of the line. However, as mentioned above, due to the parasitic capacitance effect on the data line h, the RC delay phenomenon occurs when the signal is transmitted to the end of the data line, so that the signal waveform received by the pixel at the end of the corresponding pixel line is deformed. If w·, the effective charging time of the element will be shortened to Tu. Similarly, in Fig. 11b, Wfl is an original signal waveform of φ from the output pin p2. However, since the total value of the parasitic capacitance connected to the output pin P2 is larger than that of other output pins, the RC delay effect will be It is more serious than other data lines, so the signal waveform L received by the terminal element is lost; the true degree (degree of deformation) will be worse than that in the Ua diagram, and its effective charging time T. 2 will be shorter than Τ ει, resulting in insufficient charging of the sputum, 'and affect the display quality. In order to solve the problem of the delay of the data line signal as in the lib diagram, the present invention is based on the structure of the embodiment of Fig. 5, which is further improved, as shown in Fig. 12. Figure 12 is a second embodiment of the present invention, the majority of which is the same as in Figure 5, and the same elements are denoted by the same reference numerals, except that the difference is in the pixel matrix area in Fig. 12. Each of the leftmost ith pixel rows is incremented by 6 additional auxiliary lines L, and the auxiliary line 1 is located between the boundary data line and the thin film transistor Tz adjacent to the boundary data line. Preferably, the auxiliary, the spring L system is in the boundary between the impurity line and its adjacent halogen electrode or control electrode 34 ^, and its structure is not intended to be as shown in the figure j3. The first part of the structure of the elementary structure in the 昼素仃, however, it should be noted that the structure of the second element of the figure 2 is not limited to the figure shown in Figure 3, and any circuit with the second dynasty is 17 1352958. The effect of the pixel structure is suitable in Figure 13, in the first pixel structure of the pixel structure, the auxiliary 蟑τΑ ^ W subscription line L is located in the boundary data line (D〇 and - painting pole 3 3 and Preferably, the ^' land' auxiliary line L is substantially parallel to the pixel electrode 33 and the control Thunder w city J pole 34. The auxiliary line L· can be a floating green red Knocking a time-varying signal or a non-time-varying signal, .", /S even a message, where the non-time-changing signal can be a pole

Sexuality is a positive signal, for example, the auxiliary rib starts at the I position. The auxiliary line L can be directly connected - the common electrode is the same as the morpheme of the 12th figure, when the display operation is performed on the panel, the auxiliary line L· and the halogen electrode 33 are _ , *» ' - Parasitic capacitance Ο and a parasitic voltage between the control electrode 34 and p 2 are as shown in Fig. 14. By the design of the auxiliary line L - ', it is possible to avoid the parasitic capacitance between the boundary data recording gamma + main line /, the denier electrode 3 3 and the control electrode 3 4 , that is, the boundary data line will not be connected to the parasitic electric power - And CP further greatly reduces the capacitive load of the boundary data line. However, as shown in Fig. 14, if the interval between the auxiliary line l'TM' and the through-line line is too small, a parasitic capacitance Ο will be generated between the auxiliary line L and the boundary data line. As shown in the phantom line) 'and the capacitor C3 will also be wei;}, the capacitance load of the real field of the sacred boundary line of the sacred field is increased, and finally, the boundary cannot be improved, and the RC load of the 介 枓 line is given. Too big a problem. Therefore, at the time of design, the distance between the auxiliary line L and the border of the ancestors and the sacred line should be maintained at least an appropriate distance d (as shown in Fig. 14), and hi is prepared to avoid d being too small, preferably, The choice of d is such that the capacitance value of C3 is much smaller than that of (^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^盘Λ Λ 10, 杲 only the auxiliary line L parasitic capacitance (^ and 〇 and C2 can be neglected. Bu private ratio 1 and brother 14 map and the first map can be seen, the boundary data line of Figure 14 and Uncoupling, as in the case of the first], still recovers the parasitic capacitance of the 10th figure (^ and C2, because 18 1352958 will greatly reduce the capacitance of the output line of the output pin p2, and thus greatly improve the signal delay as in the claw diagram Question. It is also known from Figure 14 that the design of the auxiliary line L has the following two main functions: (1) Separating the boundary data line from its adjacent pixel electrode and control electrode to make the boundary data line imaginary, No parasitic capacitance is generated between the pole and the control electrode, thereby improving the output pin P3 RC delay problem of transmission (2) • By the setting of the auxiliary line L, the auxiliary line L and its adjacent pixel electrode 33 and the control electrode % can respectively generate a snap-coupling capacitance, and C2' to make the ... The parasitic capacitance effect on the left and right sides of the pixel line is symmetrical, so as to avoid the brightness unevenness of the pixel line and other pixel lines, which affects the display quality of the picture. However, in another embodiment, in order to design: To improve the delay of the signal, the design of the pixel panel can also be...., u, as shown in Figure 12, the auxiliary line 'L' and the distance between the boundary data line and the pixel electrode and the control electrode are pulled A, so that the boundary data line It does not cause parasitic capacitance or only tiny parasitic capacitance between the pixel electrode and the control electrode, which can also improve the delay of the team. However, as mentioned above, the design is made of ®; and the auxiliary line L, which will make The capacitances on the left and right sides of the halogen electrode are not known, which affects the display product f. Similarly, as described above, in the other embodiment, the right data line DnH is the boundary data line, and the same can be said. Two μ know the truth The method of applying 'in the 帛 + + ι 昼 行 — — 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助 辅助The matrix area 6〇〇 can also be defined as a display area of the panel. However, as described in the second embodiment, since the boundary between the boundary line I &gt; and the auxiliary line L must be maintained at an appropriate distance d, therefore, In another embodiment, we can directly set the boundary data line outside the display area of the panel 19 1352958, and the straw is widened _, and the taste line of the Xianxing auxiliary line is as shown in the figure. Figure 16 is the present invention. The third embodiment of the Chu ^ month brother, in which the dotted line portion does not represent the display area s of the entire panel, and the boundary data line is disposed outside the display area S. In Fig. 16, the entire book +# # 素 素 matrix is still a coffee pixel matrix composed of n + 1 data (four) sweeping lines, which is the tth ith book line; divided into two sub-picture lines , the width of the CU - the first - book Xin disk width is one of the second d2 lines. - Gyeonggi and 仃第-次画素行系 are located in the display area s

Inside 'and contains a pixel electrode 33 盥 control electrode 34 for displaying the book Xin. And the second pixel line is outside the display area s -&quot;, ^ ^ _ 卜 where the 'auxiliary line L is at the first - People are in the line. However, in another example, the auxiliary line L· and the boundary data line may also be located in the second pixel line, wherein the auxiliary line L and the boundary data line are located outside the display area S. . In another case of paralysis, ' ^ ^ only court, as shown in Figure 16, the -: human line is the area defined by the auxiliary line L and the data, &quot;2, and the first-order pixel The area defined by the behavior auxiliary line L and the boundary data line, that is, the area where the S line is defined by the auxiliary line L and the data line IW. Preferably, in the embodiment of Fig. 16, a ^ d1 ^ ^ . The width of the first pixel line - the width of the first - person pixel line d2 A j day Chu A_. See Looking for, and equal to the other pixels of the line of view, the layout of the picture area, the whole process of the ρ foot - the size specifications of the lysin Q and the photographic element auxiliary 9 force a column of the ease, and because of the boundary The distance between the data line and the = is kept at least as wide as the width of the element, so that no parasitic capacitance is generated between the boundary data and the control electrode. In addition, in the other example, the second transistor τ2 in the maiden 仃 里 里 第 第 第 第 第 第 第 第 亦可 亦可 亦可 第二 第二 第二 第二 第二 第二17 _ | is also placed outside the display area S, as shown. Similarly, if the definition data line is defined as the boundary data 20 1352958 line, the design of the third embodiment can be modeled as shown in the figure. As described above, the present invention is characterized in that it provides a liquid crystal display panel having a pixel matrix whose total number of internal data lines is larger than the total number of pixel lines, and which can be used without changing the structure of the conventional source driver. Down the operation panel pixel's data signal required for its data line can be provided by the traditional source driver, so there is no need to redesign - the new driver matches it. The invention also proposes a solution The problem of signal delay and the asymmetry of parasitic capacitance result in poor display quality. However, the design of the present invention is not limited to the application to the halogen structure as shown in Fig. 6, but it can also be applied to any panel having the following structural features: (丨) having n pixel rows and m 昼a pixel matrix region of the prime column, wherein a plurality of pixels are formed at intersections of n + 1 data lines and mH scanning lines in the pixel matrix region (2) each pixel unit includes at least two transistors And a halogen electrode, and each of the pixel units is controlled by signals provided by the data lines on the left and right sides thereof. Therefore, the present invention can also be applied to a pixel panel having three thin film transistors as shown in Fig. 2, as in the pixel structure characteristics of the above two points (1) and (2). The technical contents and technical features of the present invention have been disclosed as above, but those skilled in the art can still make various substitutions and modifications of the present invention based on the teachings and disclosures of the present invention. Therefore, the scope of the invention should be construed as being limited by the scope of the invention, and the invention is intended to BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional liquid crystal display panel with diagonally twisted vertical alignment; 21 1352958 Fig. 2 is a pixel equivalent circuit diagram proposed by Samsung Electronics, Korea; Fig. 3 is a diagram of the present invention A pixel equivalent circuit diagram of a liquid crystal display panel; a fourth circle is a pixel matrix diagram of the liquid crystal display panel of the present invention; and FIG. 5 is a schematic diagram of a pixel matrix structure and a source driver of the liquid crystal display panel of the first embodiment of the present invention; 6 is a schematic diagram of a pixel unit according to FIG. 5; FIG. 7 is a driving signal waveform diagram of a pixel acting on FIG. 6; FIG. 8 is another embodiment according to the first embodiment of the present invention; A schematic diagram of a liquid crystal display panel; FIG. 9 is a liquid crystal display panel according to another embodiment of the first embodiment of the present invention; 'The first diagram shows the parasitic capacitance generated by the liquid crystal display panel of FIG. 5 during operation. FIG. 1 is a schematic diagram showing a signal delay phenomenon generated during operation of a liquid crystal display panel according to FIG. 1; FIG. 12 is a schematic diagram of a liquid crystal display panel according to a second embodiment of the present invention; Figure 13 is a schematic view showing the structure of a pixel unit according to Fig. 12; Figure 14 is a schematic diagram showing the parasitic capacitance generated during operation of the liquid crystal display panel of Fig. 12; Fig. 15 is a second embodiment of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 16 is a schematic view of a liquid crystal display panel according to a third embodiment of the present invention: FIG. 17 is a schematic view showing another embodiment of a third embodiment of the present invention; and FIG. 18 is a diagram according to the present invention. Another embodiment of the third embodiment is shown in FIG. 22 1352958 [Description of main component symbols]

10 LCD display panel 11 color filter 111 '131 transparent substrate 112 common electrode 12 liquid crystal layer 121 liquid crystal molecule 13 active substrate 132 insulating layer 133 control electrode 134 halogen electrode 20 昼素ΊΥ 'first transistor TV, second Transistor C/, Liquid crystal capacitor c2', Diagonal torsion capacitance CV' Capacitor 24 Pixel electrode 251, 252 Scan line 261, 262 Data line 27 Common electrode T. First thin film transistor T2 Second thin film transistor C. Liquid crystal Electric valley C2 diagonal torsion capacitance 〇3 capacitance 33 pixel electrode 34 control electrode 351, 352, 353 data line 361, 362, 363 scanning line 37 common electrode D l~ D η + 1 breeding line G1 ~ G m +1 Scan line 400 pixel matrix P.~ Pnn output pin c connection 500 pixel matrix 501 LCD display panel 551. ~554 data line 561- -5 6 3 scan line B, 1) halogen unit Vi) 2 ~ VD3 Lean signal potential VG2 ~ VG 3 scan signal potential V com common electrode potential TcE J drive time 23 1352958

Tp driving time VCE control electrode potential 600 pixel matrix F connection W 〇 original signal waveform W-delay signal waveform 700 pixel matrix d, cl·, d2 separation distance S display area VP element electrode potential E connection 6 0 1 Liquid crystal display panel Cl~ C3 parasitic capacitance G knows the waveform TC1, TC2 effect charging time L auxiliary line 800 pixel matrix

twenty four

Claims (1)

(10) Year 2 Correction Replacement Page 10, Patent Application Scope: Contains 1 · A plurality of scanning lines of a liquid crystal display panel; a plurality of data lines for transmitting data signals; a line drawing and the Fudan matrix package 3 bribes (four) prime, each - the halogen is formed at the intersection of the plurality of scanning data lines, the halogen comprising: a halogen electrode; a control electrode; - a first transistor - a gate, a - terminal and a first end, the first end is connected to the -the first data line and the second end is connected to the halogen electrode, and the gate is connected to - the first scan line; / - the second transistor 'with a gate, a first end, and a second end, the first end being connected to the second data line adjacent to the data line and the second end connected to the control electrode, and the gate Connecting to the second scan line adjacent to the first scan line; wherein 'the outermost two of the data lines are - the - boundary data line, and the boundary lean line is opposite There is a line between the neighboring electrodes. 2. The liquid crystal display panel of claim 7, wherein the boundary data line is connected to another non-adjacent data line. 3. The liquid crystal display panel of claim 2, wherein the boundary data line and the data signal of the adjacent one of the data lines are opposite in polarity. 25!352958 Revised replacement page of August 2, pp. pp. pp. pp. ii. </ RTI> The liquid crystal display panel of claim i, wherein the auxiliary line is located between the boundary data line and the adjacent control electrode. i Apply for the liquid _ panel of the first item of patent, shoot the _ wire connection - time-varying signal, a non-time-varying signal or a common voltage signal. The liquid crystal display panel of claim i, wherein the area between the auxiliary line and the other outermost two of the data lines is the display area of the liquid crystal display panel. 7. The liquid crystal display panel of claim 6, wherein the electro-ceramic system is located inside or outside the display area. The boundary data lines are connected. 8. For example, the patented Fan Mail 4 crystal display panel electrodes constitute the two extremes of a first capacitor. The liquid crystal display panel of the auxiliary line is adjacent to the two electrodes of the third capacitor. /, the auxiliary line and the boundary data line 26 1352958 100 years 8 j 2 correction replacement page 11. The liquid crystal display panel of claim 1, wherein the auxiliary line and the boundary data exist between The distance is such that when the pixel matrix is in an active state, the third capacitance is smaller than the capacitance or the second capacitance. 12. The liquid crystal display panel of claim 11, wherein the appropriate distance is substantially equal to the width of each of the pixels. 13. A liquid crystal display panel comprising: a halogen matrix comprising n number of pixel rows and m number of pixel columns; - n+ of a plurality of halogens formed in the matrix The intersection of the l data line and the m+1 scan line is again - at least two transistors and - 昼 "poles are placed in each element, and each "mechanism" is used by the data lines on the left and right sides Controlled by the information signal provided, where: • $1 of the data is mixed with n+l. The data is called the boundary data line. The boundary data line has an auxiliary line between its adjacent elemental electrode and 11 111 is a positive integer. 14. The liquid crystal display panel of claim 13, wherein the boundary data line is connected to another non-adjacent data line. 15. The liquid crystal display panel of claim </ RTI> wherein the boundary data line and the data signal of the data line adjacent to the adjacent replacement page of the August 2, pp. 16. The liquid crystal display panel of claim 4, wherein the boundary point of the boundary data line and the other non-adjacent data line are located outside the halogen matrix. 17. If the liquid crystal display panel of the 13th patent application scope is included, it also contains the information signal to the data line from Article 2 to Article n+1, which is called the poor, aan 〒5hai 1st article The line is the boundary data line. 18. For the liquid crystal display panel of claim 13 of the patent application scope, the contention-a ant further includes - the driver provides n data signals respectively to the data lines of the first to the nth, wherein the '^th+1th data The line is the boundary line. ....... Where the Article 1 of the data line is the n+1th data line is the outermost _ data line of the halogen matrix, and the auxiliary line 19. If the patent scope is 14th Liquid crystal The other area between the two outermost data lines is the display area of the liquid crystal display panel. 20. The liquid crystal display panel of claim 19, wherein the electro-crystalline system connected to the boundary data line is located inside or outside the display area. 28 13.52958 Revised replacement page on August 2, 100 2!. For the liquid crystal_sulfur of item 13 of the claim, the distance between the line and the adjacent line is equal to the width of the other line. 22. If the liquid crystal display sulfur of claim 13 is applied, the distance between the towel axis and the boundary data line is equal to the width of the other pixels. 23_ The liquid crystal display panel of claim 13, wherein the auxiliary line is a time-changing Φ signal, a non-time-varying signal or a common voltage signal. 24. The liquid crystal display panel of claim 13, wherein the auxiliary line is adjacent to the auxiliary line. The halogen element forms two extremes of a first capacitance. 25. The liquid crystal display panel of claim 24, wherein the auxiliary line and the boundary data line form a terminal of a second capacitance. 26. The liquid crystal display panel of claim 25, wherein an appropriate distance exists between the auxiliary line and the boundary data line, such that the second capacitance is smaller than the first capacitance when the pixel matrix is in an active state. 27. The liquid crystal display panel of claim 13, wherein each of the pixels further comprises a further electrode coupled to one of the two transistors, and the other electrode exists between the boundary and the boundary data line 29 1352958 August 2, 100 revised the replacement page for the auxiliary line. 28. The liquid crystal display panel of claim 27, wherein the auxiliary line and the adjacent one of the other electrodes form a terminal of a third capacitance. A driving method of a liquid crystal display panel, the liquid crystal display panel comprising a pixel matrix, wherein the pixel matrix comprises n number of pixel rows and a number of pixel columns, each of the pixel matrix The pixel is formed at the intersection of the n+1 data line and the m+1 scan line, and each of the pixels is respectively connected to the tilt line on the left and right sides thereof and the sweeping furnace on the upper and lower sides thereof. The outermost two of the prime matrix regions are the "feed line-, called-boundary line, where the boundary: #feed line and its adjacent----------------- η data signals respectively to the n+1 data lines, wherein the boundary data lines of the other data lines are shared with the other non-adjacent data lines - the data signal; providing - auxiliary signals to the auxiliary a line, wherein the auxiliary line forms a first capacitance between the adjacent pixel electrodes; and the data signal of the data line on each of the left and right sides of the pixel and the scan line on the upper and lower sides The signal is scanned to control each of the pixels. 30. The method of driving a liquid crystal display panel according to claim 29, wherein the auxiliary signal is a time-varying signal, a non-time-varying signal or a common voltage signal. 1352958 - Revised replacement page on August 2, 1970; 31. The liquid crystal display panel driving method of claim 29, wherein the boundary data line and the polarity of the data signal of the adjacent data line The liquid crystal display panel driving method of claim 29, wherein each of the pixels further comprises at least two thin mode transistors respectively reducing the scan lines on the upper and lower sides and the control electrode turns Connected to one of the two thin film transistors. The method of driving a liquid crystal display panel according to claim 32, wherein a second capacitor is formed between the auxiliary line and the control electrode. 34. The liquid crystal display panel driving method of claim 33, wherein a third capacitor is formed between the auxiliary line and the boundary data line. The liquid crystal display panel driving method of claim 34, wherein the first: the first capacitor or the second capacitor.