WO2021031836A1

WO2021031836A1 - Pixel array substrate

Info

Publication number: WO2021031836A1
Application number: PCT/CN2020/106658
Authority: WO
Inventors: 李仰淳; 郑圣谚; 钟岳宏; 李珉泽; 廖光祥; 连翔琳; 王彦凯; 徐雅玲; 廖烝贤
Original assignee: 友达光电股份有限公司
Priority date: 2019-08-20
Filing date: 2020-08-03
Publication date: 2021-02-25
Also published as: TW202109495A; DE112020003937B4; TW202109493A; TWI738389B; CN112419885B; KR20210038670A; TWI718021B; DE112020003937T5; KR102409301B1; DE112020003935T5; KR102524241B1; TW202109499A; WO2021031838A1; TWI753482B; CN112419885A; KR20210033039A; TWI729815B; DE112020003935B4; TW202109476A

Abstract

A pixel array substrate (10, 20, 30), comprising a plurality of scan line pads (G), a plurality of data line pads (D1, D2, D3), a plurality of scan lines (110), a plurality of data lines (210), a plurality of gate transmission lines (120), a plurality of pixels (PX), a data line signal chip (DC) and a scan line signal chip (GC). The scan lines (110) extend in a first direction (E1). The data lines (210) and the gate transmission lines (120) extend in a second direction (E2). The data lines (210) are electrically connected to the data line pads (D1, D2, D3). The scan lines (110) are electrically connected to the scan line pads (G) by means of the gate transmission lines (120). The ratio of the number of rows of the pixels (PX) arranged in the first direction (E1) to the number of rows of the pixels (PX) arranged in the second direction (E2) is X : Y. Each pixel (PX) comprises m sub-pixels (P1, P2, P3).

Description

Pixel array substrate

Technical field

The present invention relates to a pixel array substrate, and more particularly to a pixel array substrate in which scan line pads and data line pads are arranged along an arrangement direction.

Background technique

Since the display panel has the advantages of small size and low radiation, the display panel has been widely used in various electronic products. In the existing display panel, a large area of the driving circuit area is usually reserved at the periphery of the display area to install the driving circuit, and the sub-pixels are controlled by the driving circuit. However, the driving circuit area located outside the display area makes the display panel have a very wide frame and limits the screen-to-body ratio of the product. With the advancement of technology, consumers have higher and higher requirements for the appearance of display panels. In order to increase consumers' willingness to buy, how to increase the screen-to-body ratio of display panels has become one of the problems that manufacturers want to solve.

Invention Disclosure

The invention provides a pixel array substrate, which can improve the problem of signal mutual interference between scan line pads and data line pads.

At least one embodiment of the present invention provides a pixel array substrate including multiple scan line pads, multiple data line pads, multiple scan lines, multiple data lines, multiple gate transmission lines, multiple pixels, data Line signal chip and scan line signal chip. The scan line pads and the data line pads are located on the substrate. The scan line extends along the first direction. The data line and the gate transmission line extend along the second direction. The data line is electrically connected to the data line pad. The scan line is electrically connected to the scan line pad through the gate transmission line. The pixels are located on the substrate. The ratio of the number of rows of pixels arranged along the first direction to the number of rows of pixels arranged along the second direction is X:Y. Each pixel includes m sub-pixels, and the sub-pixels are electrically connected to the scan line and the data line. The data line signal chip is electrically connected to the data line pad, and the scan line signal chip is electrically connected to the scan line pad. The scan line pads and data line pads are arranged in a plurality of repeating units in an arrangement direction, and the number of scan line pads and data line pads in each repeating unit is U. U=a×(k×m×X+h×n×Y), where n is the number of scan line signal chips, and a, k, and h are positive integers.

At least one embodiment of the present invention provides a pixel array substrate including a plurality of scan line pads, a plurality of first data line pads, a plurality of second data line pads, a plurality of third data line pads, and a plurality of Scan lines, multiple data lines, multiple gate transmission lines, multiple red sub-pixels, multiple green sub-pixels, multiple blue sub-pixels, and at least one thin-film-on-chip packaging circuit. The scan line pads, the first data line pads, the second data line pads and the third data line pads are located on the substrate. The scan line pads, the first data line pads, the second data line pads, and the third data line pads are arranged in the arrangement direction. The scan line extends along the first direction. The data line and the gate transmission line extend along the second direction. The scan line is electrically connected to the scan line pad through the gate transmission line. The data line is electrically connected to the first data line pad, the second data line pad and the third data line pad. The red sub-pixel, the green sub-pixel, and the blue sub-pixel are electrically connected to the scan line and the data line. The red sub-pixel is electrically connected to the first data line pad. The green sub-pixel is electrically connected to the second data line pad. The blue sub-pixel is electrically connected to the third data line pad. The number of scan line pads located between the first data line pads and the second data line pads or between the third data line pads and the second data line pads in the arrangement direction is less than that of the first data line pads. The number of scan line pads between the pad and the third data line pad. The chip on film package circuit includes a data line signal chip and a scan line signal chip. The data line signal chip is electrically connected to the first data line pad, the second data line pad and the third data line pad. The scan line signal chip is electrically connected to the scan line pad.

Brief description of the drawings

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention.

2A is a schematic top view of a display area of a pixel array substrate according to an embodiment of the invention.

2B is a schematic top view of a sub-pixel according to an embodiment of the invention.

3A is a schematic top view of a chip-on-film package circuit according to an embodiment of the invention.

3B is a schematic top view of a chip-on-film package circuit according to an embodiment of the invention.

4 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 1 of the present invention.

FIG. 5 is a schematic top view of a pixel array substrate according to an embodiment of the invention.

6 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 2 of the present invention.

FIG. 7 is a schematic top view of a pixel array substrate according to an embodiment of the invention.

8 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 3 of the present invention.

FIG. 9 is a schematic top view of a pixel array substrate according to an embodiment of the invention.

Fig. 10A is a schematic cross-sectional view taken along line aa' in Fig. 9.

Fig. 10B is a schematic cross-sectional view taken along line bb' of Fig. 9.

Among them, the reference signs:

10, 20, 30: pixel array substrate

110: scan line

120: gate transmission line

130: The first fanout line

210: data cable

220: second fanout line

AA: Display area

BA: Surrounding area

CC1: The first wire layer

CC2: second wire layer

CH: Channel layer

CH1: The first connection structure

CH2: second connection structure

CH3: third connection structure

CH4: Fourth connection structure

CS: transfer structure

COF: Chip on Film Package Circuit

D1: The first data line pad

D2: The second data line pad

D3: third data line pad

DC: Data line signal chip

DE: drain

E1: First direction

E2: second direction

G: Scan line pad

GC: Scan line signal chip

GE: grid

GI: Gate insulating layer

I1: first insulating layer

I2: second insulating layer

I3: third insulating layer

L1: first row

L2: second row

M1: The first metal layer

M2: second metal layer

P1: Red sub pixel

P2: Green sub pixel

P3: blue sub pixel

O: opening

PE: pixel electrode

PL: Flat layer

PU: Repeating unit

PX: pixel

RD: Arrangement direction

SB: substrate

SE: Source

T: switching element

TH1, TH2: Through hole

The best way to implement the invention

The following describes the present invention in detail with reference to the accompanying drawings and specific embodiments, but not as a limitation to the present invention.

Throughout the specification, the same reference numerals indicate the same or similar elements. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. It should be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to another element", it can be directly on or connected to another element, or There may be other elements between the element and the other element. In contrast, when an element is referred to as being “directly on” or “directly connected to another element”, there are no other elements between the element and the other element. As used herein, "connected" can refer to physical and/or electrical connection. Furthermore, the “electrical connection” or “coupling” between two elements may mean that there are other elements between the two elements.

It should be understood that although the terms "first" and "second" etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, and/or parts should not Subject to these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention. 2A is a schematic top view of a display area of a pixel array substrate according to an embodiment of the invention. FIG. 2B is a schematic top view of the sub-pixel in FIG. 2A. 3A is a schematic top view of a chip-on-film package circuit according to an embodiment of the present invention. FIG. 3A is, for example, an enlarged schematic diagram of the chip-on-film package circuit COF of FIG. 3B is a schematic top view of a chip-on-film package circuit according to an embodiment of the invention.

Please refer to FIG. 1, the pixel array substrate 10 includes a plurality of scan line pads G and a plurality of data line pads (such as a first data line pad D1, a second data line pad D2, and a third data line pad D3) , A plurality of scan lines 110, a plurality of data lines 210, a plurality of gate transmission lines 120, a plurality of pixels (not shown in FIG. 1), and at least one COF. In this embodiment, the pixel array substrate 10 further includes a plurality of first fan-out lines 130 and a plurality of second fan-out lines 220.

The substrate SB has a display area AA and a peripheral area BA located outside the display area AA. The material of the substrate SB can be glass, quartz, organic polymer, or opaque/reflective material (for example, conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive material or metal is used, an insulating layer (not shown) is covered on the carrier board SB to avoid short circuit problems.

The scan line pad G is located on the substrate SB. In this embodiment, the scan line pad G is located on the peripheral area BA. The first fan-out line 130 electrically connects the scan line pad G to the gate transmission line 120. The scan line 110 and the gate transmission line 120 are located on the display area AA. The scan line 110 extends along the first direction E1, and the gate transmission line 120 extends along the second direction E2. In this embodiment, the gate transmission line 120 is electrically connected to the scan line 110 through the switching structure CS, and the scan line 110 is electrically connected to the scan line pad G through the gate transmission line 120 and the first fan-out line 130.

In this embodiment, each scan line pad G is electrically connected to the corresponding two scan lines 110, thereby reducing the number of scan line pads G, but the invention is not limited thereto. In other embodiments, different scan lines 110 do not share the same scan line pad G.

The data line pads (such as the first data line pad D1, the second data line pad D2, and the third data line pad D3) are located on the substrate SB. In this embodiment, the data line pads are located on the peripheral area BA. The second fan-out line 220 is electrically connected to the data line pad to the data line 210. The data line 210 extends along the second direction E2.

Please refer to FIG. 1 and FIG. 2A, the pixel PX is located on the substrate SB. In this embodiment, each pixel 300 includes a red sub-pixel P1, a green sub-pixel P2, and a blue sub-pixel P3, but the invention is not limited to this. In other embodiments, each pixel PX further includes sub-pixels of other colors.

Please refer to FIGS. 1, 2B, and 2A. In this embodiment, the pixel array substrate 10 is driven in a HG2D (half-gate two-data line) manner, and each sub-pixel (red sub-pixel P1, green sub-pixel P2) And the blue sub-pixel P3) overlaps the corresponding two of the data lines 210 and the corresponding one of the scan lines 110.

The sub-pixels are electrically connected to the scan line 110 and the data line 210. In this embodiment, the red sub-pixel P1, the green sub-pixel P2, and the blue sub-pixel P3 are electrically connected to the scan line 110 and the data line 210. The red sub-pixel P1 is electrically connected to the first data line pad D1. The green sub-pixel P2 is electrically connected to the second data line pad D2. The blue sub-pixel P3 is electrically connected to the third data line pad D3.

Each sub-pixel includes a switching element T and a pixel electrode PE. The switching element T includes a gate GE, a channel layer CH, a source SE, and a drain DE.

The gate GE is located on the substrate SB and is electrically connected to the corresponding scan line 110. The channel layer CH overlaps the gate GE, and a gate insulating layer is sandwiched between the channel layer CH and the gate GE (illustration omitted in the figure).

The source SE and the drain DE are electrically connected to the channel layer CH. The source SE is electrically connected to the data line 210. The flat layer (illustration omitted in the figure) is located on the source SE and the drain DE. The pixel electrode PE is located on the flat layer and is electrically connected to the drain electrode DE through the opening O penetrating the flat layer.

In some embodiments, the pixel array substrate 10 further includes a common signal line CL1, a common signal line CL2, and a common signal line CL3. The common signal line CL1, the common signal line CL2, and the scan line 110 all extend along the first direction E1, and the common signal line CL1, the common signal line CL2, and the scan line 110 belong to the same conductive layer (for example, the first metal layer). The common signal line CL3, the data line 210, and the gate transmission line 120 all extend along the second direction E2, and the common signal line CL3, the data line 210, and the gate transmission line 120 belong to the same conductive layer (for example, a second metal layer).

The scan line pads G and the data line pads (such as the first data line pad D1, the second data line pad D2, and the third data line pad D3) are arranged in the arrangement direction RD. In this embodiment, the scan line pads G and the data line pads are arranged in a first row L1 and a second row L2 in the arrangement direction RD. The pads in the first row L1 are aligned with each other, and the pads in the second row L2 are aligned with each other. By arranging the scan line pads G and the data line pads in two rows in the arrangement direction RD, the wiring space can be used more effectively. In some embodiments, the pads located in the first row L1 and the pads located in the second row L2 belong to different metal layers. For example, the pads located in the first row L1 belong to the first metal layer, and the pads located in the second row L1 belong to the first metal layer. The pads of the two rows L2 belong to the second metal layer, and an insulating layer is provided between the first metal layer and the second metal layer, so as to avoid short circuits between adjacent pads.

In some embodiments, the scan line connected between the first data line pad D1 and the second data line pad D2 or between the third data line pad D3 and the second data line pad D2 in the arrangement direction RD The number of pads G is less than the number of scan line pads G located between the first data line pad D1 and the third data line pad D3, thereby improving the gap between the scan line pads G and the data line pads. The effect of signal interference on the display screen.

The chip on film package circuit COF is electrically connected to the scan line pad G and the data line pad D (for example, the first data line pad D1, the second data line pad D2, and the third data line pad D3).

Please refer to FIGS. 3A and 3B. The COF includes a data line signal chip DC, a scan line signal chip GC, a first insulating layer I1, a second insulating layer I2, a third insulating layer I3, and a first wire layer CC1. , The second wire layer CC2, a plurality of first connection structures CH1, a plurality of second connection structures CH2, a plurality of third connection structures CH3, and a plurality of fourth connection structures CH4.

The first insulating layer I1, the second insulating layer I2, and the third insulating layer I3 overlap in order. The data line signal chip DC and the scan line signal chip GC are located on the first insulating layer I1.

The first wire layer CC1 is located between the second insulating layer I2 and the first conductive layer I1. The plurality of first connection structures CH1 penetrate the first insulating layer I1 and are electrically connected to the first wire layer CC1.

The second wire layer CC2 is located between the second insulating layer I2 and the third conductive layer I3. The plurality of second connecting structures CH2 penetrate the first insulating layer I1 and the second insulating layer I2, and are electrically connected to the second conductive layer CC2. In this embodiment, since the first wire layer CC1 and the second wire layer CC2 belong to different film layers, respectively, the wiring space of the first wire layer CC1 and the second wire layer CC2 can be effectively increased.

The third connection structure CH3 penetrates the second insulating layer I2 and the third conductive layer I3, and is electrically connected to the first wire layer CC1. The plurality of fourth connection structures CH4 penetrate the third insulating layer I3 and are electrically connected to the second wire layer CC2.

The data line signal chip DC is electrically connected to one of the first conductive layer CC1 and the second conductive layer CC2, and the scan line signal chip GC is electrically connected to the other of the first conductive layer CC1 and the second conductive layer CC2 By. In this embodiment, the data line signal chip DC is electrically connected to the first conductive layer CC1, and the scan line signal chip GC is electrically connected to the second conductive layer CC2.

The data line signal chip DC is electrically connected to the data line pads (for example, the first data line pad D1, the second data line pad D2, and the third data line pad D3 of FIG. 1), and the scan line signal chip GC is electrically connected Connect to the scan line pad G.

In this embodiment, the data line signal chip DC and the scan line signal chip GC are both located on the same side of the display area AA. Therefore, the frame of the display panel can be reduced, thereby increasing the screen-to-body ratio of the display device. In some embodiments, the width between the side of the display area AA where the COF is not provided and the edge of the pixel array substrate 10 is less than 2 mm.

In this embodiment, a chip-on-film package circuit COF includes a data line signal chip DC and a scan line signal chip GC. Therefore, the first fan-out line 130 and the second fan-out line 220 may not overlap each other, thereby improving the first The signal interference between one fan-out line 130 and the second fan-out line 220 affects the display image.

Please refer to FIG. 1, in this embodiment, the pixel array substrate 10 includes n scan line signal chips GC. For example, the pixel array substrate 10 includes two chip-on-film packages COF, and each chip-on-film package circuit COF has one scan line signal chip GC. Therefore, the pixel array substrate 10 includes two scan line signal chips. GC, that is, n is 2. In other embodiments, n is greater than 2.

In this embodiment, each scan line 110 is electrically connected to multiple scan line signal chips GC, so that the signal on the scan line 110 can be distributed more evenly. For example, the pixel array substrate 10 includes n scan line signal chips GC, and each scan line 110 is electrically connected to the n scan line signal chips GC.

The scan line pads G and the data line pads D (for example, the first data line pad, the second data line pad, and the third data line pad) are arranged into a plurality of repeating units PU in the arrangement direction RD, and each The total number of scan line pads G and data line pads D in the repeating unit PU is U.

4 is used to show the sequence of the scan line pads G and the data line pads D in the repeating unit PU, and the scan line pads G and the data line pads D in the repeating unit PU are not completely aligned. For example, the scan line pads G and the data line pads D in the repeating unit PU can be divided into a first row L1 and a second row L2 as shown in FIG. 1. The first pad in the first row L1 in Figure 1 is the first pad in Figure 4, and the first pad in the second row L2 in Figure 1 is the second pad in Figure 4. The second pad in the first row L1 in FIG. 1 is the third pad in FIG. 4, and the arrangement order of the other pads is similarly deduced.

In this embodiment, as shown in FIG. 2A, the ratio of the number of rows of pixels PX arranged along the first direction E1 to the number of rows of pixels PX arranged along the second direction E2 is X:Y. For example, in a display panel with a resolution of 1920×1080, X:Y is 16:9. In this embodiment, each pixel PX includes m sub-pixels, where m is a positive integer. In this embodiment, in order to improve the signal interference problem between the scan line pad G and the data line pad D, the scan line pad G and the data line pad D conform to the rule of Formula 1.

Formula 1:

U=a×(k×m×X+h×n×Y)

In Formula 1, n is the number of scan line signal chips, and a, k, and h are positive integers.

Example 1

In Embodiment 1, the pixel array substrate is driven in HG2D mode, and each sub-pixel overlaps two data lines and one scan line. In Embodiment 1, each scan line pad G is electrically connected to two corresponding scan lines. In Embodiment 1, part of the scan line pads G is located in the first row L1, another part of the scan line pads G is located in the second row L2 (as shown in FIG. 1), and part of the scan line pads G belongs to the first metal layer , And another part of the scan line pad G belongs to the second metal layer. In Example 1, a is 1, k is 4, and h is 1.

X: Y is 16:9. Each pixel PX includes 3 sub-pixels, that is, m is 3. The pixel array substrate has 3 scan line signal chips, that is, n is 3.

In Embodiment 1, the sum U of the number of scan line pads G and data line pads D in each repeating unit PU is calculated by formula 1, U=1×(4×3×16+1×3×9 )=219, which means that the total number U of scan line pads G and data line pads D in each repeating unit PU is 219.

In Embodiment 1, in order to make the scan line pads G and the data line pads D more uniformly dispersed, the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of formula 2.

Formula 2:

R=2×m×N

In Formula 2, N is an integer between 1 and k+1.

In Embodiment 1, R=2×3×1 to 2×3×5, which means that the number of data line pads D between two adjacent scan line pads G is between 6 and 30.

FIG. 5 is a schematic top view of a pixel array substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 5 uses the element numbers and part of the content of the embodiment of FIG. 1, wherein the same or similar reference numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.

The difference between the pixel array substrate 20 of FIG. 5 and the pixel array substrate 10 of FIG. 1 is that in the pixel array substrate 20, different scan lines 110 do not share the same scan line pad G.

Please refer to FIG. 5, in this embodiment, each gate transmission line 120 is electrically connected to a corresponding scan line pad G to a corresponding scan line 110.

6 is used to show the sequence of the scan line pads G and the data line pads D in the repeating unit PU, and the scan line pads G and the data line pads D in the repeating unit PU are not completely aligned. For example, the scan line pads G and the data line pads D in the repeating unit PU can be divided into a first row L1 and a second row L2 as shown in FIG. 5. The first pad in the first row L1 in Figure 5 is the first pad in Figure 6, and the first pad in the second row L2 in Figure 5 is the second pad in Figure 6, The second pad in the first row L1 in FIG. 5 is the third pad in FIG. 6, and the arrangement order of the other pads is similarly deduced.

In this embodiment, as shown in FIG. 2A, the ratio of the number of rows of pixels PX arranged along the first direction E1 to the number of rows of pixels PX arranged along the second direction E2 is X:Y. In this embodiment, each pixel PX includes m sub-pixels, where m is a positive integer. In this embodiment, in order to improve the signal interference problem between the scan line pad G and the data line pad D, the scan line pad G and the data line pad D conform to the rule of Formula 1.

Example 2

In the second embodiment, the pixel array substrate is driven in HG2D mode, and each sub-pixel overlaps two data lines and one scan line. In Embodiment 2, each scan line pad G is electrically connected to a corresponding scan line, and different scan lines are not directly electrically connected through the scan line pad or the gate transmission line. In Embodiment 2, part of the scan line pads G is located in the first row L1, another part of the scan line pads G is located in the second row L2 (as shown in FIG. 5), and part of the scan line pads G belongs to the first metal layer , And another part of the scan line pad G belongs to the second metal layer. In Example 2, a is 1, k is 2, and h is 1.

In Embodiment 2, the sum U of the number of scan line pads G and data line pads D in each repeating unit PU is calculated by formula 1, U=1×(2×3×16+1×3×9 )=123, which means that the total number U of scan line pads G and data line pads D in each repeating unit PU is 123.

In Embodiment 2, in order to make the scan line pads G and the data line pads D more evenly dispersed, the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of formula 2.

In Embodiment 2, R=2×3×1 to 2×3×3, which means that the number of data line pads D between two adjacent scan line pads G is between 6 to 18.

FIG. 7 is a schematic top view of a pixel array substrate according to an embodiment of the invention. It must be noted here that the embodiment of FIG. 7 uses the element numbers and part of the content of the embodiment of FIG. 2A, wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.

The difference between the pixel array substrate 30 of FIG. 7 and the pixel array substrate 10 of FIG. 2A is that the pixel array substrate 30 is driven in a 1G1D (one-gate one-data line) manner, and each sub-pixel (red sub-pixel P1, green sub-pixel The sub-pixel P2 and the blue sub-pixel P3) overlap the corresponding one of the data lines 210 and the corresponding one of the scan lines 110.

Fig. 8 is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to Embodiment 3 of the present invention.

FIG. 8 is used to show the arrangement sequence of the scan line pads G and the data line pads D in the repeating unit PU, and the scan line pads G and the data line pads D in the repeating unit PU are not completely aligned. For example, the scan line pads G and the data line pads D in the repeating unit PU can be divided into a first row L1 and a second row L2 as shown in FIG. 5. The first pad in the first row L1 in Figure 1 is the first pad in Figure 8, and the first pad in the second row L2 in Figure 5 is the second pad in Figure 8. The second pad in the first row L1 in FIG. 5 is the third pad in FIG. 8, and the arrangement order of the other pads is similarly deduced.

In this embodiment, as shown in FIG. 7, the ratio of the number of rows of pixels PX arranged along the first direction E1 to the number of rows of pixels PX arranged along the second direction E2 is X:Y. In this embodiment, each pixel PX includes m sub-pixels, where m is a positive integer. In this embodiment, in order to improve the signal interference problem between the scan line pad G and the data line pad D, the scan line pad G and the data line pad D conform to the rule of Formula 1.

Example 3

In Embodiment 3, the pixel array substrate is driven in a 1G1D manner, and each sub-pixel overlaps a data line and a scan line. In Embodiment 3, each scan line pad G is electrically connected to a corresponding scan line, and different scan lines are not directly electrically connected through the scan line pad or the gate transmission line. In Embodiment 3, part of the scan line pads G is located in the first row L1, another part of the scan line pads G is located in the second row L2 (as shown in FIG. 5), and part of the scan line pads G belongs to the first metal layer , And another part of the scan line pad G belongs to the second metal layer. In Example 3, a is 1, k is 1, and h is 1.

In Embodiment 3, the sum U of the number of scan line pads G and data line pads D in each repeating unit PU is calculated by formula 1, U=1×(1×3×16+1×3×9 )=75, which means that the total number of scan line pads G and data line pads D in each repeating unit PU is 75.

In Embodiment 3, in order to make the scan line pads G and the data line pads D more evenly dispersed, the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of formula 2.

In Embodiment 3, R=2×3×1 to 2×3×2, which means that the number of data line pads D between two adjacent scan line pads G is between 6 and 12.

FIG. 9 is a schematic top view of a pixel array substrate according to an embodiment of the invention. Fig. 10A is a schematic cross-sectional view taken along line aa' in Fig. 9. Fig. 10B is a schematic cross-sectional view taken along line bb' of Fig. 9. It must be noted here that the embodiment of FIG. 9 uses the element numbers and part of the content of the embodiment of FIG. 5, wherein the same or similar reference numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiment, which is not repeated here.

9, in the pixel array substrate 30, the scan line pads G are all located in the same row. For example, the scan line pads G are all located in the first row L1 or the scan line pads G are all located in the second row. In this embodiment, the pads located in the first row L1 (including the scan line pads G and the data line pads D) belong to the first metal layer M1, and the pads located in the second row L2 (including the data line pads) D) belongs to the second metal layer M2. In other embodiments, the pads in the second row L2 belong to the first metal layer M1, and the pads in the first row L1 belong to the second metal layer M2. In this embodiment, all the scan line pads G are aligned with each other in the arrangement direction RD.

In this embodiment, the scan line pads G belong to the first metal layer M1. Therefore, it is possible to reduce the number of different scan lines 110 due to the transfer structure (for example, the transfer from the first metal layer M1 to the second metal layer M2). Connection structure) and cause the signal to be offset.

The first metal layer M1 is located on the substrate SB. The gate insulating layer GI covers the first metal layer M1. The gate insulating layer GI on the pad (such as the scan line pad G) belonging to the first metal layer M1 has a through hole TH1. The flat layer PL is located on the gate insulating layer GI, and on the pads belonging to the first metal layer M1 (such as the scan line pad G) and on the pads belonging to the second metal layer M2 (such as the third data line pad D3). ) Has through holes TH2.

In some embodiments, a plurality of conductive structures CP are filled in the through hole TH1 and the through hole TH2 to be electrically connected to the corresponding scan line pad G and the third data line pad D3, respectively. The material of the conductive structure CP includes, for example, metal oxide.

Example 4

In Embodiment 4, the pixel array substrate is driven in HG2D, and each sub-pixel overlaps two data lines and one scan line. In Embodiment 4, each scan line pad G is electrically connected to two corresponding scan lines. In Embodiment 4, all the scan line pads G belong to the same metal layer (for example, the first metal layer or the second metal layer). In Example 4, a is 2, k is 4, and h is 1.

In Embodiment 4, the sum U of the number of scan line pads G and data line pads D in each repeating unit PU is calculated by formula 1, U=2×(4×3×16+1×3×9 )=438, which means that the total number U of scan line pads G and data line pads D in each repeating unit PU is 438.

In Embodiment 4, in order to make the scan line pads G and the data line pads D more evenly dispersed, the number of data line pads D between two adjacent scan line pads G in the arrangement direction RD R conforms to the rules of Equation 3.

Formula 3:

R=2×m×N+1

In Formula 3, N is an integer between 1 and k+1.

In Embodiment 4, R=2×3×1+1 to 2×3×5+1, which means that the number of data line pads D between two adjacent scan line pads G is between 7 and 31.

Industrial applicability

Claims

A pixel array substrate, characterized in that it comprises:

A plurality of scan line pads and a plurality of data line pads are located on a substrate;

Multiple scan lines extending along a first direction;

A plurality of data lines and a plurality of gate transmission lines extend along a second direction, wherein the data lines are electrically connected to the data line pads, and the scan lines are electrically connected to the gate transmission lines The scan line pads;

A plurality of pixels are located on the substrate, wherein the ratio of the number of rows of the pixels arranged along the first direction to the number of rows of the pixels arranged along the second direction is X:Y, wherein each pixel Comprising m sub-pixels, and the sub-pixels are electrically connected to the scan lines and the data lines;

At least one data line signal chip and at least one scan line signal chip, the at least one data line signal chip is electrically connected to the data line pads, and the at least one scan line signal chip is electrically connected to the scan line pads ,among them

The scan line pads and the data line pads are arranged in a plurality of repeating units in an arrangement direction, and the number of the scan line pads and the data line pads in each repeating unit is summed as U, where U=a×(k×m×X+h×n×Y), where n is the number of the at least one scan line signal chip, and a, k, and h are positive integers.
4. The pixel array substrate of claim 1, wherein each of the sub-pixels overlaps corresponding two of the data lines and a corresponding one of the scan lines, and each scan line pad is electrically connected To the corresponding two scan lines.
3. The pixel array substrate of claim 2, wherein a part of the scan line pads and a part of the data line pads belong to the first metal layer, and another part of the scan line pads and another part of the The data line pads belong to the second metal layer, where a is 1, k is 4, and h is 1.
3. The pixel array substrate of claim 3, wherein there are R data line pads between two adjacent scan line pads in the arrangement direction, R=2×m×N , And N is an integer between 1 and k+1.
3. The pixel array substrate of claim 2, wherein the scan line pads all belong to the same metal layer, wherein a is 2, k is 4, and h is 1.
7. The pixel array substrate of claim 5, wherein there are R data line pads between two adjacent scan line pads in the arrangement direction, R=2×m×N +1, and N is an integer between 1 and k+1.
5. The pixel array substrate of claim 5, wherein the scan line pads are aligned with each other in the arrangement direction.
3. The pixel array substrate of claim 1, wherein each of the sub-pixels overlaps the corresponding two of the data lines and the corresponding one of the scan lines, and the different scan lines are not directly connected to each other. It is electrically connected through the scan line pads or the gate transmission lines, where a is 1, k is 2, and h is 1.
8. The pixel array substrate of claim 8, wherein there are R data line pads between two adjacent scan line pads in the arrangement direction, R=2×m×N , And N is an integer between 1 and k+1.
3. The pixel array substrate of claim 1, wherein each of the sub-pixels overlaps a corresponding one of the data lines and a corresponding one of the scan lines, wherein a is 1, k is 1, and h is 1. .
10. The pixel array substrate of claim 10, wherein there are R data line pads between two adjacent scan line pads in the arrangement direction, R=2×m×N , And N is an integer between 1 and k+1.
5. The pixel array substrate of claim 1, further comprising:

A plurality of first fan-out lines, electrically connecting the scan line pads to the gate transmission lines; and

A plurality of second fan-out lines are electrically connected to the data line pads to the data lines, wherein the first fan-out lines and the second fan-out lines do not overlap each other.
A pixel array substrate, characterized in that it comprises:

A plurality of scan line pads, a plurality of first data line pads, a plurality of second data line pads, and a plurality of third data line pads are located on a substrate, wherein the scan line pads, the second data line pads A data line pad, the second data line pads, and the third data line pads are arranged in an arrangement direction;

Multiple scan lines extending along a first direction;

A plurality of data lines and a plurality of gate transmission lines extend along a second direction, wherein the scan lines are electrically connected to the scan line pads through the gate transmission lines, and the data lines are electrically connected to The first data line pads, the second data line pads, and the third data line pads;

A plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels are electrically connected to the scan lines and the data lines, wherein the red sub-pixels are electrically connected to the first data line connections Pads, the green sub-pixels are electrically connected to the second data line pads, and the blue sub-pixels are electrically connected to the third data line pads, wherein the second data line pads are located in the arrangement direction The number of scan line pads between a data line pad and the second data line pads or between the third data line pads and the second data line pads is less than that of the scan line pads located in the first data line pads. The number of the scan line pads between a data line pad and the third data line pads;

At least one chip-on-film package circuit includes at least one data line signal chip and at least one scan line signal chip. The at least one data line signal chip is electrically connected to the first data line pads and the second data line connections. Pad and the third data line pads, and the at least one scan line signal chip is electrically connected to the scan line pads.
15. The pixel array substrate of claim 13, wherein the at least one chip-on-film package circuit comprises:

A first insulating layer, a second insulating layer, and a third insulating layer are sequentially overlapped, and the at least one data line signal chip and the at least one scan line signal chip are located on the first insulating layer;

A first wire layer located between the second insulating layer and the first conductive layer;

A second wire layer located between the second insulating layer and the third conductive layer

A plurality of first connection structures penetrate the first insulating layer and are electrically connected to the first wire layer;

A plurality of second connection structures penetrate the first insulating layer and the second insulating layer, and are electrically connected to the second wire layer;

A plurality of third connection structures penetrate through the second insulating layer and the third conductive layer, and are electrically connected to the first wire layer; and

A plurality of fourth connection structures penetrate the third insulating layer and are electrically connected to the second wire layer, wherein the at least one data line signal chip is electrically connected to the first conductive layer and the second conductive layer One, and the at least one scan line signal chip is electrically connected to the other of the first conductive layer and the second conductive layer.