TWI600947B - Pixel structure and active device array substrate for display panel - Google Patents

Description

Pixel structure and active device array for display panel Substrate

The present invention relates to a pixel structure and an active device array substrate for a display panel.

Due to its advantages of lightness, thinness, and energy saving, liquid crystal display panels have been widely used in various electronic products such as smart phones, notebook computers, tablet computers, and televisions. In general, a liquid crystal display panel mainly includes a first substrate such as an array substrate, a second substrate such as a counter substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. In addition, the liquid crystal display panel further includes a spacer disposed between the first substrate and the second substrate for maintaining uniform flatness when the array substrate is bonded to the opposite substrate, and providing a fixed liquid crystal gap of the liquid crystal distribution.

However, in order to achieve a finer display screen, the resolution required of the display panel is higher and higher, and the ratio of the arrangement area of the pixel electrodes on the first substrate is higher and higher, and the spacer overlaps the pixel electrode in the direction perpendicular to the first substrate. . Under the impact of external force, the spacer may rub against the alignment film on the first substrate, and the pixel electrode covered by the alignment film is partially peeled off, thereby causing a slight bright spot. In view of Therefore, how to design a pixel structure that can avoid the peeling of the pixel electrode due to the friction of the spacer to eliminate the above defects and deficiencies in the prior art is an extremely problem to be solved by those skilled in the art.

In various embodiments of the present invention, in the display panel to which the spacer is applied, the integration of the spacer and the internal via of the pixel structure (for example, the first opening of the insulating layer) can be designed without sacrificing additional space. Separating the spacer from the first pixel electrode to prevent the two from being slightly bright due to friction. In addition, the projection relationship between the via holes and the spacers in the pixel structure can be designed such that the first pixel electrode is disposed as much as possible in a larger range while maintaining the support of the spacer.

According to some embodiments of the present invention, a pixel structure for a display panel includes a first substrate, a second substrate, a display medium, a first switching element, an insulating layer, a first pixel electrode, and a spacer. The second substrate is disposed opposite to the first substrate. The display medium is disposed between the first substrate and the second substrate. The first switching element is disposed on the first substrate, wherein the first switching element includes a gate, a source, and a drain. The insulating layer covers the first switching element, wherein the insulating layer has a first opening to correspond to the drain of the first switching element. The first pixel electrode is disposed on the insulating layer and extends into the first opening to electrically connect the drain, wherein the first pixel electrode covers the first portion of the sidewall of the first opening and does not cover the second portion of the sidewall of the first opening . The spacer is disposed between the first substrate and the second substrate, wherein the surface of the insulating layer adjacent to the second substrate comprises a region corresponding to the spacer, and the second portion of the sidewall is located between the region and the first portion of the sidewall.

In some embodiments of the invention, the first portion of the sidewall is coupled to the bottom of the first opening and the first portion of the sidewall is between the second portion of the sidewall and the bottom of the first opening.

In some embodiments of the invention, the second portion of the sidewall is connected to the region of the surface of the insulating layer.

In some embodiments of the present invention, the spacer has a top surface adjacent to the second substrate and a bottom surface adjacent to the first substrate, and the second portion of the sidewall of the first opening is projected on the bottom surface of the second substrate and the spacer The projections of the second substrate at least partially overlap, wherein the area of the top surface of the spacer is greater than the area of the bottom surface of the spacer.

In some embodiments of the invention, the insulating layer comprises a spacer adjacent the surface of the surface such that the area of the surface protrudes from other areas of the insulating layer.

In some embodiments of the invention, the height of the first portion of the sidewall is from about 90% to about 95% of the height of the sidewall.

In some embodiments of the invention, the spacer is adjacent to the bottom surface of the first substrate in a direction greater than 10 microns in length.

In some embodiments of the present invention, the first substrate includes a pixel region for the first switching element and the first pixel electrode, wherein the width of the pixel region in the direction is less than 30 microns.

In some embodiments of the invention, the projection of the bottom of the first opening to the second substrate at least partially overlaps the projection of the top surface of the spacer on the second substrate.

In some embodiments of the present invention, the pixel structure further includes a second switching element and a second pixel electrode. The second switching element is disposed on the first base a board, wherein the second switching element includes a gate, a source, and a drain, wherein the insulating layer includes a second opening to expose a drain of the second switching element. The second pixel electrode is disposed on the insulating layer and extends into the second opening to electrically connect the drain of the second switching element, wherein the second pixel electrode covers the first portion of the sidewall of the second opening and does not cover the second opening a second portion of the sidewall, wherein the second portion of the sidewall of the second opening is between the region and the first portion of the sidewall of the second opening.

In some embodiments of the present invention, the pixel structure further includes a data line electrically connected to the source of the first switching element, wherein sidewalls of the first opening and sidewalls of the second opening are respectively disposed on opposite sides of the data line.

In some embodiments of the invention, the projection of the data line on the second substrate overlaps with the projection of the spacer on the second substrate.

In some embodiments of the invention, the insulating layer comprises a planar layer and a dielectric layer, and the dielectric layer is disposed on the planar layer.

According to some embodiments of the present invention, an active device array substrate includes a substrate, at least one data line and at least one scan line, at least one switching element, an insulating layer, and at least one first pixel electrode disposed on the substrate. The data lines are interleaved with the scan lines to define at least one pixel area. The switching element is disposed on a pixel area of the substrate, wherein the switching element includes a gate, a source, and a drain. The insulating layer covers the switching element, wherein the insulating layer includes at least one opening to correspond to the drain of the switching element. The pixel electrode is disposed on the surface of the insulating layer and located in the pixel region, wherein the pixel electrode extends into the opening to electrically connect the drain, wherein the pixel electrode covers the first portion of the sidewall of the opening and does not cover the second sidewall of the opening a portion, wherein the first portion of the sidewall is adjacent to the bottom of the opening and away from the surface of the insulating layer, and the second portion of the sidewall is adjacent to the surface of the insulating layer and away from the bottom of the opening unit.

In some embodiments of the invention, the height of the first portion of the sidewall is from about 90% to about 95% of the height of the sidewall.

In some embodiments of the present invention, the insulating layer includes a planar layer and a dielectric layer, the dielectric layer is disposed on the planar layer, and the second portion is formed by a portion of the sidewall of the planar layer and a sidewall of the dielectric layer.

In some embodiments of the present invention, the insulating layer includes a planar layer and a dielectric layer, and the dielectric layer is disposed on the planar layer and is a sidewall of the dielectric layer.

100‧‧‧ pixel structure

110‧‧‧First substrate

120‧‧‧second substrate

130‧‧‧Display media

140‧‧‧First switching element

144‧‧‧ source

146‧‧‧汲polar

150‧‧‧Insulation

151‧‧‧ first opening

151a‧‧‧ Sidewall

151b‧‧‧ bottom

153‧‧‧ surface

153a‧‧‧Area

154‧‧‧ second opening

154a‧‧‧ sidewall

156‧‧‧flat layer

157‧‧‧ dielectric layer

158‧‧‧ pads

160‧‧‧first pixel electrode

170‧‧‧ spacers

172‧‧‧ top surface

174‧‧‧ bottom

180‧‧‧Second switching element

184‧‧‧ source

186‧‧‧汲polar

190‧‧‧second pixel electrode

P1‧‧‧Part 1

P2‧‧‧ Part II

D1‧‧ Direction

PA‧‧‧ pixel area

DL‧‧‧ data line

BM‧‧‧ Black Matrix

SE‧‧‧Semiconductor layer

HA‧‧‧ Height

H1‧‧‧ Height

H2‧‧‧ Height

1B-1B‧‧‧ line

3B-3B‧‧‧ line

L1‧‧‧ length

GI‧‧‧ gate dielectric layer

1A is a top plan view of a pixel structure in accordance with an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view taken along line 1B-1B of Fig. 1A.

Fig. 1C is a partial enlarged view of the pixel structure of Fig. 1B.

Fig. 2 is a schematic cross-sectional view showing a pixel structure according to another embodiment of the present invention.

Fig. 3A is a top plan view showing a pixel structure according to still another embodiment of the present invention.

Figure 3B is a schematic cross-sectional view taken along line 3B-3B of Figure 3A.

Fig. 3C is a partially enlarged view of the pixel structure of Fig. 3B.

Fig. 4 is a schematic cross-sectional view showing a pixel structure according to another embodiment of the present invention.

The various embodiments of the present invention are disclosed in the drawings, and in the claims However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified manner.

1A is a top plan view of a pixel structure 100 in accordance with an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along line 1B-1B of Fig. 1A. Refer to both Figure 1A and Figure 1B. A part of the embodiments of the present invention provides a pixel structure 100 for a display panel, including a first substrate 110, a second substrate 120, a display medium 130, a first switching element 140, an insulating layer 150, a first pixel electrode 160, and a spacer. Object 170. The first substrate 110 is disposed opposite to the second substrate 120. The display medium 130 and the spacer 170 are disposed between the first substrate 110 and the second substrate 120. The first switching element 140 is disposed on the first substrate 110. The insulating layer 150 covers the first switching element 140 and has a first opening 151 to expose the drain 146 of the first switching element 140. The first pixel electrode 160 is disposed on the insulating layer 150 and extends into the first opening 151 to electrically connect the drain 146. The surface 153 of the insulating layer 150 facing the second substrate 120 has a region 153a corresponding to the spacer 170, and the first opening 151 has a sidewall 151a adjacent to the region 153a, which includes a first portion P1 and a second portion P2, and the second portion P2 will region 153a is spaced apart from the first portion P1 of the sidewall 151a, wherein the first pixel electrode 160 covers only the first portion P1 of the sidewall 151a and does not cover the second portion P2 of the sidewall 151a, and further, at the first pixel electrode 160 and not Insulation covered by a pixel electrode 160 On layer 150, there may be a more alignment film (not shown).

Fig. 1C is a partial enlarged view of the pixel structure of Fig. 1B. Reference is also made to Figures 1B and 1C. In some embodiments of the present invention, the first pixel electrode 160 may be designed to cover about 90% to about 95% of the sidewall 151a, that is, the height H1 of the first portion P1 of the sidewall 151a is about 90 of the total height HA of the sidewall 151a. % to about 95%. In other words, the height H2 of the second portion P2 where the side wall 151a is not covered by the first pixel electrode 160 is about 5% to about 10% of the total height HA of the side wall 151a. Within this height range, the first pixel electrode 160 can be disposed as large as possible.

Herein, for convenience of explanation, in the full text of the description, the side wall 151a is divided into a first portion P1 and a second portion P2 by being covered by the first pixel electrode 160, wherein the first portion P1 is connected to the bottom portion 151b of the first opening 151. And the second portion P2 is separated from the bottom 151b of the first opening 151. More specifically, the first portion P1 of the sidewall 151a is adjacent to the bottom 151b of the first opening 151 and away from the surface 153 of the insulating layer 150, and the second portion P2 of the sidewall 151a is adjacent to the surface 153 of the insulating layer 150 and away from the first opening. The bottom 151b of 151. Detailed elements of the pixel structure 100 in various embodiments of the present invention are described in detail below.

Returning to FIGS. 1A and 1B, in various embodiments of the present invention, the first substrate 110 may be an active device array substrate. The first substrate 110 is provided with the foregoing insulating layer 150, the first pixel electrode 160, and other elements for controlling the potential, such as the data line DL, the scan line GL, and the aforementioned first switching element 140, wherein the plurality of data lines DL and plural The scanning lines GL are alternately arranged with each other to define a complex pixel area PA. For example, the first switching element 140 includes a gate a pole (not shown), a source 144 and a drain 146, wherein a gate (not shown) is electrically connected to the scan line GL, a source 144 is electrically connected to the data line DL, and a drain 146 is electrically connected to the first pixel electrode. 160. In this way, the scan line GL can control the first switching element 140 to turn on the data line DL and the first pixel electrode 160.

In some embodiments of the present invention, the region 153a of the surface 153 of the insulating layer 150 is in contact with the spacer 170, and the contact range of the surface 153 with the spacer 170 is the region 153a. In some embodiments of the invention, the second portion P2 of the sidewall 151a is coupled to the region 153a of the surface 153 of the insulating layer 150. Of course, the scope of the invention should not be limited thereby. In other embodiments, the spacer 170 may be smaller in size such that the second portion P2 of the sidewall 151a is not connected to the region 153a of the surface 153 of the insulating layer 150.

In some embodiments of the present invention, the spacer 170 is used to support the spacing between the first substrate 110 and the second substrate 120 to strengthen the structure against external stress. The area of the spacer 170 on the top surface 172 near the second substrate 120 side is larger than the area of the spacer 170 on the bottom surface 174 near the first substrate 110 side. The spacer 170 is provided in advance on the second substrate 120 and is disposed between the first substrate 110 and the second substrate 120 by being bonded to the first substrate 110. The spacer 170 is used to maintain a uniform thickness between the first substrate 110 and the second substrate 120.

In some embodiments of the present invention, in order to make the area of the first pixel electrode 160 as large as possible, the distance between the first opening 151 and the center of the spacer 170 can be reduced as much as possible. For example, the projection of the second portion P2 of the sidewall 151a of the first opening 151 on the second substrate 120 and the projection of the top surface 172 of the spacer 170 on the second substrate 120 may at least partially overlap. Moreover, in some embodiments, the bottom 151b of the first opening 151 is projected between the second substrate 120 and the second substrate 120. The projection of the top surface 172 of the spacer 170 on the second substrate 120 may at least partially overlap. In some embodiments, the projection of the second portion P2 of the sidewall 151a of the first opening 151 on the second substrate 120 and the projection of the bottom surface 174 of the spacer 170 on the second substrate 120 may at least partially overlap. Here, it should be understood that the spacer 170 depicted in the top view of FIG. 1A is substantially the top surface 172 of the spacer 170 in FIG. 1B.

In addition, in some embodiments, in order to maintain the supporting effect of the spacer 170, the projection of the sidewall 151a and the bottom 151b of the first opening 151 on the first substrate 110 may not be designed to be the projection of the center of the spacer 170 on the first substrate 110. overlapping. In this way, it can be ensured that the center of the spacer 170 can be supported by the insulating layer 150 while still supporting the separation of the first substrate 110 and the second substrate 120.

Through the above arrangement, a buffer region (for example, the second portion P2) can be provided between the region 153a where the spacer 170 is in contact with the first pixel electrode 160 without an additional mask or process, and the first pixel electrode is avoided. 160 produces a slight bright spot due to friction.

In some embodiments of the present invention, the pixel structure 100 further includes a second switching element 180 and a second pixel electrode 190 disposed in another pixel area PA. The second switching element 180 is disposed on the first substrate 110, wherein the second switching element 180 includes a gate (not shown), a source 184 and a drain 186, and the insulating layer 150 includes a second opening 154 to expose the second switching element. 180 poles 186. The second pixel electrode 190 is disposed on the insulating layer 150 and extends to the second opening 154 to electrically connect the drain 186. The second opening 154 has a sidewall 154a adjacent to the region 153a, and includes a first portion P1 and a second portion P2. Second part The portion P2 separates the region 153a from the first portion P1 of the sidewall 154a of the second opening 154, wherein the second pixel electrode 190 covers only the first portion P1 of the sidewall 154a and does not cover the second portion P2 of the sidewall 154a. The configuration of the second switching element 180 and the second pixel electrode 190 is substantially the same as the configuration of the first switching element 140 and the first pixel electrode 160, and details are not described herein again.

In some embodiments of the present invention, one of the data lines DL is electrically connected to the first switching element 140, wherein the data line DL is on the first substrate 110 of the first substrate 110 and the region 153a of the surface 153 of the insulating layer 150. The projections partially overlap. The sidewall 151a of the first opening 151 and the sidewall 154a of the second opening 154 are respectively disposed under opposite sides of the spacer 170, that is, respectively on opposite sides of the data line DL, so that the first pixel electrode 160 A buffer (for example, the second portion P2) is spaced apart from the second pixel electrode 190 by a region 153a.

Here, the first pixel electrode 160 and the second pixel electrode 190 may cover about 90% to about 95% of the sidewall 151a and the sidewall 154a, respectively. The range of the present invention should not be limited by this. In other embodiments, only the first pixel electrode 160 may be disposed to cover about 90% to about 95% of the sidewall 151a, and the second pixel electrode 190 may cover 0% of the sidewall 154a. Up to 90% or 95% to 100%. In other words, in some embodiments, the first pixel electrode 160 covers about 90% to about 95% of the sidewall 151a, and the first pixel electrode 160 can be disposed in a larger range as much as possible while avoiding the occurrence of the micro-bright spots. The second pixel electrode 190 covers 0% to 90% of the sidewall 154a, and the second pixel electrode 190 avoids the occurrence of a slight bright spot but is disposed only in a small range. Alternatively, in other embodiments, the first pixel electrode 160 covers about 90% to about 95% of the sidewall 151a, and the first pixel electrode 160 can be disposed as large as possible while avoiding the occurrence of micro-bright spots. The second pixel electrode 190 covers 90% to 100% of the sidewall 154a, and the second pixel electrode 190 can avoid generating a slight bright spot.

Referring to FIG. 1B, in various embodiments of the present invention, the second substrate 120 may be a color filter substrate. That is, the second substrate 120 may be provided with a color filter (not shown) and a black matrix BM, wherein the black matrix BM covers the plurality of data lines DL, the scan lines GL, and the plurality of switching elements, and the color filters ( Not shown) are respectively disposed in the respective pixel areas PA. The spacer 170 is disposed between adjacent plurality of pixel areas PA to avoid reducing the aperture ratio of the display panel. For example, Figure 1A depicts four pixel regions PA. The spacer 170 is designed between adjacent four pixel areas PA.

Here, for convenience of explanation, the black matrix BM is not depicted in FIG. 1A. Actually, the black matrix BM substantially shields the first opening 151, the second opening 154, the first switching element 140, and the second switching element. 180, the spacer 170, the scanning line GL and the data line DL, to reduce the reflection or scattering of light caused by the above components, thereby affecting the visual effect.

In some embodiments of the present invention, at least one of the first substrate 110 and the second substrate 120 may comprise glass, quartz, or a polymer material (eg, polyimide (PI), benzocyclobutene). Benzocyclobutene (BCB), polycarbonate (PC), or other suitable materials), or other suitable materials, or a combination of at least two of the foregoing.

The material of display medium 130 comprises a self-luminous material (eg, an organic light-emitting material, an inorganic light-emitting material, or other suitable material, or a combination thereof) or a non-self-luminous material (eg, liquid crystal, electrophoresis, electrowetting, or other suitable Material, or a combination of the foregoing). The display medium 130 can change its optical characteristics, such as transmittance or phase, depending on the external electric field, thereby causing the user to observe a pattern of light and dark variations, even color.

In some embodiments of the present invention, the data line DL, the drain 146, and the drain 186 are formed by patterning the same layer, and the layer may be various materials with good electrical conductivity, such as metal, alloy, and conductive adhesive. Or other suitable materials, or a combination of at least two of the foregoing.

In some embodiments of the present invention, the first pixel electrode 160 and the second pixel electrode 190 may be composed of various materials having good conductivity and transparency, such as indium tin oxide (ITO) and indium zinc oxide (indium tin oxide). Indium zinc oxide; IZO) and zinc indium oxide (Zinc oxide; ZnO). Alternatively, the first pixel electrode 160 and the second pixel electrode 190 may be composed of a material having good reflectance and conductivity, such as silver, copper, aluminum, or the like.

In some embodiments of the present invention, the insulating layer 150 may be a single layer or a multilayer structure, and the material thereof includes (for example, yttrium oxide, tantalum nitride, ytterbium oxynitride, or other suitable materials), and an organic material (for example, light). Resist, polyimide (PI), benzocyclobutene (BCB), or other suitable material, or other suitable material. Other insulating layer layers may also include other openings to facilitate electrical connection of the first pixel electrode 160 with the drain 146 and electrical connection of the second pixel electrode 190 with the drain 186.

In some embodiments of the present invention, the first switching element 140 and the second switching element 180 may be various semiconductor elements, such as a transistor, a diode, or other suitable element, and the material of the semiconductor element includes polycrystalline germanium, single crystal germanium. , microcrystalline germanium, amorphous germanium, organic semiconductor materials, metal oxide semiconductors A material, or other suitable material, or a combination of at least two of the foregoing. For example, in FIG. 1B, the first switching element 140 and the second switching element 180 respectively include a semiconductor layer SE. Here, the first switching element 140 and the second switching element 180 are top gate semiconductor elements, that is, the scanning line GL is located above the semiconductor layer SE and used as a gate. Of course, the first switching element 140 and the second switching element 180 may be bottom gate semiconductor elements, that is, the scanning line GL is located below the semiconductor layer SE. In some embodiments of the present invention, the first substrate 110 is further provided with a plurality of insulating layer bodies, such as a gate dielectric layer GI between the semiconductor layer SE and the gate, to assist the first switching element 140 and the first The setting of the two switching elements 180. It will be appreciated that the first switching element 140 and the second switching element 180 can be arranged in a variety of conventional manners in the art and should not be construed as limiting the scope of the invention.

While the various embodiments of the invention above have been presented in terms of active device array substrates and color filter substrates, the scope of the invention should not be limited thereby. In other embodiments, the first substrate 110 may be an array on a chip on-column (COA) substrate, and the second substrate 120 may be a general transparent substrate.

For a high-order resolution or a display panel having a high withstand voltage requirement, since the space is limited or the spacer 170 is large in size, if the first pixel electrode 160 is too close to the spacer 170, the spacer 170 may be brought into contact with the first The alignment film (not shown) on the pixel electrode 160 may cause the first pixel electrode 160 to partially fall off under the external force collision friction to generate a slight bright spot. Accordingly, the pixel structure 100 of some embodiments of the present invention is suitable for a high-order resolution display panel or a display panel having a high withstand voltage requirement to solve the above-mentioned micro-brightness problem. question. In particular, the width of the pixel area PA in the direction D1 may be less than about 30 microns to achieve a high-order resolution display panel. Alternatively, in various embodiments of the invention, the length L1 of the bottom surface 174 of the spacer 170 in the direction D1 is greater than 10 microns.

Although not illustrated in detail herein, it should be understood that some embodiments of the present invention disclose an active device array substrate including a plurality of pixel structures 100 thereon. The active device array substrate includes a first substrate 110, at least one data line DL and at least one scan line GL, a first switching element 140, an insulating layer 150, and at least one first pixel electrode 160. The data line DL is interleaved with the scan line GL to define at least one pixel area PA. The first switching element 140 is disposed on the pixel area PA of the substrate 110. The first switching element 140 includes a gate (not shown), a source 144, and a drain 146. The insulating layer 150 covers the switching element 140, wherein the insulating layer 150 includes a first opening 151 to correspond to the drain 146 of the first switching element 140. The first pixel electrode 160 is disposed on the surface 153 of the insulating layer 150 and located in the pixel region PA, wherein the first pixel electrode 160 extends into the first opening 151 to electrically connect the drain 146, and the first pixel electrode 160 Covering the bottom portion 151b of the first opening 151 and at least one sidewall, the first pixel electrode 160 covers the first portion P1 of the sidewall 151a of the first opening 151 and does not cover the second portion P2 of the sidewall 151a of the 151, wherein the first portion P1 of the sidewall 151a Adjacent to the bottom 151b of the first opening 151 and away from the surface 153 of the insulating layer 150, and the second portion P2 of the sidewall 151a is adjacent to the surface 153 of the insulating layer 150 and away from the bottom 151b of the first opening 151a. Other details of the active device array substrate are substantially as described above and will not be described herein.

It should be understood that, in practical applications, various embodiments of the present invention The application is not limited to the aforementioned high-order resolution display panel or display panel having higher withstand voltage requirements, and any embodiment of the display panel in which spacers and pixel electrodes are required to be disposed at the same time may be employed.

2 is a schematic cross-sectional view of a pixel structure 100 in accordance with another embodiment of the present invention. This embodiment is similar to the embodiment of FIG. 1B except that in the present embodiment, the insulating layer 150 is a composite layer structure including the flat layer 156 and the dielectric layer 157. The dielectric layer 157 is disposed on the planar layer 156. Here, the flat layer 156 is used to overcome the surface (not shown) which is not flat due to the arrangement of the first switching element 140. Therefore, the flat layer 156 is designed to be thicker than the dielectric layer 157.

Here, the first pixel electrode 160 on the sidewall 151a covers only a portion of the sidewall of the planarization layer 156, and exposes the other portion of the planarization layer 156 and the sidewall of the complete dielectric layer 157 such that the first portion P1 of the sidewall 151a is flattened. The layer 156 is formed, and the second portion P2 of the sidewall 151a is formed by the planarization layer 156 and the dielectric layer 157. In other embodiments, the second portion P2 of the sidewall 151a may be formed only by the dielectric layer 157, that is, the planar layer 156 that the first pixel electrode 160 may completely cover, or even partially cover the dielectric layer 157.

The material of the dielectric layer 157 and the flat layer 156 includes (for example, hafnium oxide, tantalum nitride, hafnium oxynitride, or other suitable materials), organic materials (for example, photoresist, polyimide, PI), Benzocyclobutenc (BCB), or other suitable material), or other suitable material. Other details of the present embodiment are substantially as described above, and are not described herein again.

3A is a pixel junction according to still another embodiment of the present invention. A top view of the structure 100. Figure 3B is a schematic cross-sectional view taken along line 3B-3B of Figure 3A. Fig. 3C is a partially enlarged view of the pixel structure of Fig. 3B. This embodiment is similar to the embodiment of FIGS. 1A to 1C described above, except that in the present embodiment, the insulating layer 150 includes a flat layer 156, a dielectric layer 157, and a spacer 158. The dielectric layer 157 is disposed on the planar layer 156, and the spacer 158 is disposed on the dielectric layer 157.

The dielectric layer 157 is disposed on the flat layer 156. The flat layer 156 is used to overcome the surface that is not flattened by the first switching element 140 (not shown here). Therefore, the flat layer 156 is designed to be a dielectric layer. 157 is thick. The spacer 158 is adjacent to the region 153a of the surface 153, such as on the region 153a, and the spacer 158 can at least make the region 153a more prominent than other regions of the surface 153 (for example, the height of the region 153a is greater than the height of other regions of the surface 153). ) so that the spacer 170 contacts the spacer 158.

Here, although the spacer 158 covers the dielectric layer 157 under the spacer 170 almost completely, in fact, the spacer 158 may expose a portion of the dielectric layer 157. In some embodiments, the dielectric layer 157 can cover the spacer 158, that is, the spacer 158 is disposed between the planar layer 156 and the dielectric layer 157, while still enabling the region 153a of the corresponding spacer 170 to be more than other regions. protruding.

Here, the second portion P2 of the sidewall 151a of the first opening 151 is formed by the flat layer 156, the dielectric layer 157, and the sidewalls of the spacer 158, that is, the first pixel electrode 160 on the sidewall 151a covers only a portion of the surface. The sidewalls of the planarization layer 156 do not cover the other portion of the planarization layer 156, the dielectric layer 157, and the spacers 158. In other embodiments, the second portion P2 of the sidewall 151a may be formed only by the dielectric layer 157 and the sidewall of the spacer 158 or only the sidewall of the spacer 158. That is, the first pixel electrode 160 may completely cover the sidewall of the planarization layer 156 or the sidewalls of both the planarization layer 156 and the dielectric layer 157. Other details of the present embodiment are substantially as described above, and are not described herein again.

4 is a cross-sectional view of a pixel structure 100 in accordance with another embodiment of the present invention. In the present embodiment, the dielectric layer 157 is similar to the embodiment of the above-mentioned FIG. 3B, and constitutes the surface 153 of the insulating layer 150. The difference is that in the present embodiment, the dielectric layer 157 also constitutes the sidewall 151a of the first opening 151.

Specifically, the dielectric layer 157 extends over the opening of the planarization layer 156 such that the first portion P1 and the second portion P2 are both formed by the dielectric layer 157. The dielectric layer 157 covers the first opening 151 but does not cover the bottom 151b of the first opening 151, and the first pixel electrode 160 is connected to the drain 146 through the opening. The dielectric layer 157 separates the first pixel electrode 160 from the planarization layer 156 such that the first pixel electrode 160 does not contact the planarization layer 156. Other details of the present embodiment are substantially as described above, and are not described herein again.

In various embodiments of the present invention, in the display panel to which the spacer is applied, the integration of the spacer and the internal via of the pixel structure (for example, the first opening of the insulating layer) can be designed without sacrificing additional space and In the case of an additional process, the spacer is separated from the first pixel electrode to prevent the two from being slightly bright due to friction. In addition, the projection relationship between the via holes and the spacers in the pixel structure can be designed such that the first pixel electrode is disposed as much as possible in a larger range while maintaining the support of the spacer.

While the invention has been described above in terms of various embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. Protection The scope defined in the patent application scope is subject to the definition of patent application.

100‧‧‧ pixel structure

110‧‧‧First substrate

120‧‧‧second substrate

130‧‧‧Display media

140‧‧‧First switching element

144‧‧‧ source

146‧‧‧汲polar

150‧‧‧Insulation

151‧‧‧ first opening

151a‧‧‧ Sidewall

151b‧‧‧ bottom

158‧‧‧ pads

160‧‧‧first pixel electrode

170‧‧‧ spacers

172‧‧‧ top surface

174‧‧‧ bottom

180‧‧‧Second switching element

184‧‧‧ source

186‧‧‧汲polar

190‧‧‧second pixel electrode

P1‧‧‧Part 1

P2‧‧‧ Part II

153‧‧‧ surface

153a‧‧‧Area

154‧‧‧ second opening

154a‧‧‧ sidewall

156‧‧‧flat layer

157‧‧‧ dielectric layer

D1‧‧ Direction

PA‧‧‧ pixel area

DL‧‧‧ data line

BM‧‧‧ Black Matrix

SE‧‧‧Semiconductor layer

L1‧‧‧ length

GI‧‧‧ gate dielectric layer

Claims (16)

A pixel structure for a display panel, comprising: a first substrate; a second substrate disposed opposite to the first substrate; a display medium disposed between the first substrate and the second substrate; a switching element and a second switching element are disposed on the first substrate, wherein each of the first switching element and the second switching element comprises a gate, a source and a drain; an insulating layer covering the a first switching element and the second switching element, wherein the insulating layer has a first opening and a second opening to respectively correspond to the drain of the first switching element and the drain of the second switching element; a first pixel electrode and a second pixel electrode are disposed on the insulating layer and extend into the first opening and the second opening respectively to electrically connect the drain of the first switching element and the second a drain of the switching element, wherein the first pixel electrode covers a first portion of one of the sidewalls of the first opening and does not cover a second portion of the sidewall of the first opening, the second pixel electrode covering the first portion a first portion of one of the sidewalls of the opening and not covering a second portion of the sidewall of the second opening; a spacer disposed between the first substrate and the second substrate, wherein the insulating layer is adjacent to the second One surface of the substrate includes a region corresponding to the spacer, and the second portion of the sidewall of the first opening is located between the region and the first portion of the sidewall of the first opening, the second opening The second portion of the sidewall is located between the region and the first portion of the sidewall of the second opening; An information line is disposed between the first switching element and the second switching element, wherein the sidewall of the first opening and the sidewall of the second opening are respectively disposed on opposite sides of the data line. The pixel structure of claim 1, wherein the first portion of the sidewall of the first opening is connected to a bottom of one of the first openings, and the first portion of the sidewall of the first opening is located at the first opening The second portion of the sidewall is between the bottom portion of the first opening. The pixel structure of claim 1, wherein the second portion of the sidewall of the first opening is connected to the region of the surface of the insulating layer, the second portion of the sidewall of the second opening The region of the surface of the insulating layer is connected. The pixel structure of claim 1, wherein the spacer has a top surface adjacent to the second substrate and a bottom surface adjacent to the first substrate, the second portion of the sidewall of the first opening is The projection of the two substrates at least partially overlaps the projection of the bottom surface of the spacer on the second substrate, wherein an area of the top surface of the spacer is larger than an area of the bottom surface of the spacer. The pixel structure of claim 1, wherein the insulating layer comprises: a spacer adjacent to the region of the surface such that the region of the surface protrudes from other regions of the insulating layer. The pixel structure of claim 1, wherein the height of the first portion of the sidewall of the first opening is between 90% and 95% of the height of the sidewall of the first opening. The pixel structure of claim 1, wherein the spacer is greater than 10 microns in length in a direction adjacent to a bottom surface of the first substrate. The pixel structure of claim 7, wherein the first substrate comprises a pixel region for the first switching element and the first pixel electrode, wherein a width of the pixel region in the direction is less than 30 Micron. The pixel structure of claim 1, wherein a projection of one of the first openings at the bottom of the second substrate at least partially overlaps a projection of a top surface of the spacer on the second substrate. The pixel structure of claim 1, wherein the data line is electrically connected to the source of the first switching element. The pixel structure of claim 1, wherein the projection of the data line on the second substrate overlaps with the projection of the spacer on the second substrate. The pixel structure of claim 1, wherein the insulating layer comprises a flat layer and a dielectric layer, and the dielectric layer is disposed on the planar layer. An active device array substrate includes: a substrate; a plurality of data lines and a plurality of scan lines disposed on the substrate, wherein the data lines are interlaced with the scan lines to define a first pixel area and a second a first switching element and a second switching element respectively disposed on the first pixel area and the second pixel area of the substrate, wherein each of the first switching element and the second switch The device includes a gate, a source, and a drain; an insulating layer covering the first switching element and the second switching element, wherein the insulating layer includes a first opening and a second opening to respectively correspond to The drain of the first switching element and the drain of the second switching element; and a first pixel electrode and a second pixel electrode respectively disposed on a surface of the insulating layer and located in the first pixel region And the second pixel electrode and the second pixel electrode respectively extending into the first opening and the second opening to electrically connect the first switching element respectively a drain and a drain of the second switching element, wherein the first pixel electrode covers a first portion of one of the sidewalls of the first opening and does not cover a second portion of the sidewall of the first opening, the second The pixel electrode covers a first portion of one of the sidewalls of the second opening and does not cover a second portion of the sidewall of the second opening, wherein the second portion of the sidewall of the first opening is located in one of the data lines Between the first portion of the sidewall of the first opening and the first portion The second portion of the sidewall of the second opening is between the one of the data lines and the first portion of the sidewall of the second opening, the first side of the first and second openings a portion adjacent to a bottom of each of the first and second openings and away from the surface of the insulating layer, and the second portion of the sidewalls of each of the first and second openings is adjacent to the surface of the insulating layer and away from The bottom of each of the first and second openings. The active device array substrate of claim 13, wherein the height of the first portion of the sidewall of the first opening is between 90% and 95% of the height of the sidewall of the first opening. The active device array substrate of claim 13, wherein the insulating layer comprises a flat layer and a dielectric layer, the dielectric layer is disposed on the flat layer, and the second portion of the first opening is covered by the flat layer A portion of the sidewall is formed together with a sidewall of the dielectric layer. The active device array substrate of claim 13, wherein the insulating layer comprises a flat layer and a dielectric layer, the dielectric layer is disposed on the flat layer, and the second portion of the first opening is the dielectric One side wall of the layer.