TW201820001A - Pixel structure and active device array substrate for display panel - Google Patents

Abstract

A pixel structure for display panels includes a first substrate, a second substrate opposite to the first substrate, a display medium and a spacer disposed therebetween, a switch device, an insulating layer, and a pixel electrode disposed on the first substrate. The insulating layer covers the switch device and has an opening corresponding to a drain electrode of the switch device. The pixel electrode is disposed on the insulating layer and extends to the opening to electrically connect the drain electrode, and the pixel electrode covers a first portion of a sidewall of the opening and does not cover a second portion of the sidewall of the opening. A surface of the insulating layer proximate to the second substrate includes a region corresponding to the spacer, and the second portion of the sidewall is disposed between the region and the first portion of the sidewall.

Description

   Pixel structure for display panel and active element array substrate   

The invention relates to a pixel structure and an active element array substrate for a display panel.

Liquid crystal display panels have been widely used in various electronic products, such as smart phones, notebook computers, tablet computers, and televisions, due to their advantages such as lightness, thinness, shortness, and energy saving. Generally speaking, a liquid crystal display panel mainly includes a first substrate such as an array substrate, a second substrate such as an opposite substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. In addition, the liquid crystal display panel further includes a spacer disposed between the first substrate and the second substrate, for maintaining uniform flatness when the array substrate and the opposite substrate are bonded, and providing a fixed liquid crystal gap for liquid crystal distribution.

However, in order to achieve a more detailed display screen, the required resolution of the display panel is getting higher and higher, and the proportion of the area of the pixel electrodes on the first substrate is getting higher and higher. . Under the impact of an external force, the spacer may rub against the alignment film on the first substrate, so that the pixel electrode covered by the alignment film is partially peeled off, thereby causing micro-bright spots. In view of this, how to design a pixel structure that can prevent the pixel electrode from peeling off due to the friction of the spacers, in order to eliminate the above defects and deficiencies in the prior art, is an issue that is highly to be solved by those skilled in the industry.

In various embodiments of the present invention, in a display panel using a spacer, by designing the spacer and a through hole (such as a first opening of an insulating layer) inside the pixel structure, it is possible to sacrifice additional space without sacrificing extra space. , Separating the spacer from the first pixel electrode to avoid micro-bright spots due to friction. In addition, the projection relationship between the through holes and the spacers in the pixel structure can be designed, so that the first pixel electrode can be arranged in a large range as much as possible while maintaining the support effect of the spacers.

According to some embodiments of the present invention, a pixel structure for a display panel includes a first substrate, a second substrate, a display medium, a first switching element, an insulating layer, a first pixel electrode, and a spacer. The second substrate is disposed opposite the first substrate. The display medium is disposed between the first substrate and the second substrate. The first switching element is disposed on the first substrate. The first switching element includes a gate, a source, and a drain. The insulating layer covers the first switching element, wherein the insulating layer has a first opening to correspond to the drain of the first switching element. The first pixel electrode is disposed on the insulating layer and extends into the first opening to electrically connect the drain electrode, wherein the first pixel electrode covers a first portion of a sidewall of the first opening and does not cover a second portion of a sidewall of the first opening. . The spacer is disposed between the first substrate and the second substrate, wherein the surface of the insulating layer adjacent to the second substrate includes a region corresponding to the spacer, and the second portion of the sidewall is located between the region and the first portion of the sidewall.

In some embodiments of the present invention, the first portion of the sidewall is connected to the bottom of the first opening, and the first portion of the sidewall is located between the second portion of the sidewall and the bottom of the first opening.

In some embodiments of the present invention, the second portion of the sidewall is connected to a region on the surface of the insulating layer.

In some embodiments of the present invention, the spacer has a top surface adjacent to the second substrate and a bottom surface adjacent to the first substrate, and the second portion of the sidewall of the first opening is projected on the second substrate and the bottom surface of the spacer is on The projections of the second substrate overlap at least partially, wherein the area of the top surface of the spacer is larger than the area of the bottom surface of the spacer.

In some embodiments of the present invention, the insulating layer includes a pad, and a region adjacent to the surface makes the region of the surface more prominent than other regions of the insulating layer.

In some embodiments of the present invention, the height of the first portion of the sidewall is about 90% to about 95% of the height of the sidewall.

In some embodiments of the present invention, the length of the spacer adjacent to the bottom surface of the first substrate in a direction is greater than 10 microns.

In some embodiments of the present invention, the first substrate includes a pixel region for the first switching element and the first pixel electrode to be disposed, and the width of the pixel region in the direction is less than 30 microns.

In some embodiments of the present invention, the projection of the bottom of the first opening on the second substrate and the projection of the top surface of the spacer on the second substrate at least partially overlap.

In some embodiments of the present invention, the pixel structure further includes a second switching element and a second pixel electrode. The second switching element is disposed on the first substrate. The second switching element includes a gate, a source, and a drain. The insulating layer includes a second opening to expose the drain of the second switching element. The second pixel electrode is disposed on the insulating layer and extends into the second opening to electrically connect the drain electrode of the second switching element, wherein the second pixel electrode covers a first portion of a sidewall of the second opening and does not cover the second opening. The second portion of the sidewall, wherein the second portion of the sidewall of the second opening is located between the region and the first portion of the sidewall of the second opening.

In some embodiments of the present invention, the pixel structure further includes a data line for electrically connecting the source of the first switching element, wherein the sidewall of the first opening and the sidewall of the second opening are respectively disposed on opposite sides of the data line.

In some embodiments of the present invention, the projection of the data line on the second substrate and the projection of the spacer on the second substrate overlap.

In some embodiments of the present invention, the insulating layer includes a flat layer and a dielectric layer, and the dielectric layer is disposed on the flat layer.

According to some embodiments of the present invention, an active device array substrate includes a substrate, at least one data line and at least one scan line, at least one switching element, an insulating layer, and at least one first pixel electrode disposed on the substrate. The data lines are interleaved with the scan lines to define at least one pixel area. The switching element is disposed on a pixel region of the substrate. The switching element includes a gate electrode, a source electrode, and a drain electrode. The insulating layer covers the switching element, wherein the insulating layer includes at least one opening to correspond to the drain of the switching element. The pixel electrode is disposed on the surface of the insulating layer and located in the pixel area. The pixel electrode extends into the opening to electrically connect the drain electrode. The pixel electrode covers a first portion of the sidewall of the opening and a second portion of the sidewall that does not cover the opening. Part, wherein a first part of the side wall is adjacent to the bottom of the opening and away from the surface of the insulating layer, and a second part of the side wall is adjacent to the surface of the insulating layer and away from the bottom of the opening.

In some embodiments of the present invention, the height of the first portion of the sidewall is about 90% to about 95% of the height of the sidewall.

In some embodiments of the present invention, the insulating layer includes a flat layer and a dielectric layer, the dielectric layer is disposed on the flat layer, and the second part is formed by a part of a sidewall of the flat layer and a side wall of the dielectric layer.

In some embodiments of the present invention, the insulating layer includes a flat layer and a dielectric layer. The dielectric layer is disposed on the flat layer and is a sidewall of the dielectric layer.

100‧‧‧ pixel structure

110‧‧‧first substrate

120‧‧‧second substrate

130‧‧‧Display media

140‧‧‧first switching element

144‧‧‧Source

146‧‧‧Drain

150‧‧‧ Insulation

151‧‧‧First opening

151a‧‧‧ sidewall

151b‧‧‧ bottom

153‧‧‧ surface

153a‧‧‧area

154‧‧‧Second Opening

154a‧‧‧ sidewall

156‧‧‧ flat layer

157‧‧‧Dielectric layer

158‧‧‧ spacer

160‧‧‧first pixel electrode

170‧‧‧ spacer

172‧‧‧Top

174‧‧‧underside

180‧‧‧Second switching element

184‧‧‧Source

186‧‧‧Drain

190‧‧‧second pixel electrode

P1‧‧‧Part I

P2‧‧‧Part Two

D1‧‧‧ direction

PA‧‧‧Pixel Area

DL‧‧‧Data Line

BM‧‧‧Black Matrix

SE‧‧‧Semiconductor Layer

HA‧‧‧height

H1‧‧‧ height

H2‧‧‧ height

1B-1B‧‧‧line

3B-3B‧‧‧line

L1‧‧‧ length

GI‧‧‧Gate dielectric layer

FIG. 1A is a schematic top view of a pixel structure according to an embodiment of the present invention.

Figure 1B is a schematic cross-sectional view taken along line 1B-1B of Figure 1A.

Figure 1C is a partial enlarged view of the pixel structure of Figure 1B.

FIG. 2 is a schematic cross-sectional view of a pixel structure according to another embodiment of the present invention.

FIG. 3A is a schematic top view of a pixel structure according to another embodiment of the present invention.

Figure 3B is a schematic cross-sectional view taken along line 3B-3B of Figure 3A.

Figure 3C is a partial enlarged view of the pixel structure of Figure 3B.

FIG. 4 is a schematic cross-sectional view of a pixel structure according to another embodiment of the present invention.

Several embodiments of the present invention will be disclosed in the following drawings. For the sake of clear description, many practical details will be described in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and elements will be shown in the drawings in a simple and schematic manner.

FIG. 1A is a schematic top view of a pixel structure 100 according to an embodiment of the present invention. Figure 1B is a schematic cross-sectional view taken along line 1B-1B of Figure 1A. Refer to FIG. 1A and FIG. 1B at the same time. Some embodiments of the present invention provide a pixel structure 100 for a display panel, which includes a first substrate 110, a second substrate 120, a display medium 130, a first switching element 140, an insulating layer 150, a first pixel electrode 160, and a spacer.物 170。 170. The first substrate 110 is disposed opposite the second substrate 120. The display medium 130 and the spacer 170 are disposed between the first substrate 110 and the second substrate 120. The first switching element 140 is disposed on the first substrate 110. The insulating layer 150 covers the first switching element 140 and has a first opening 151 to expose the drain electrode 146 of the first switching element 140. The first pixel electrode 160 is disposed on the insulating layer 150 and extends into the first opening 151, and is electrically connected to the drain electrode 146. The surface 153 of the insulating layer 150 facing the second substrate 120 has a region 153a corresponding to the spacer 170, and the first opening 151 has a side wall 151a adjacent to the region 153a, which includes a first portion P1 and a second portion P2, and the second portion P2 is an area 153a is separated from the first portion P1 of the side wall 151a. The first pixel electrode 160 only covers the first portion P1 of the side wall 151a and does not cover the second portion P2 of the side wall 151a. In addition, the first pixel electrode 160 and An alignment film (not shown) may be provided on the insulating layer 150 covered by a pixel electrode 160.

Figure 1C is a partial enlarged view of the pixel structure of Figure 1B. Refer to Figures 1B and 1C at the same time. In some embodiments of the present invention, the first pixel electrode 160 may be designed to cover about 90% to about 95% of the side wall 151a, that is, the height H1 of the first portion P1 of the side wall 151a accounts for about 90% of the total height HA of the side wall 151a. % To about 95%. In other words, the height H2 of the second portion P2 of the side wall 151a not covered by the first pixel electrode 160 is about 5% to about 10% of the total height HA of the side wall 151a. Within this height range, the first pixel electrode 160 can be arranged as large as possible.

Here, for the convenience of explanation, in the description of this article, the side wall 151a is divided into a first part P1 and a second part P2, with the first part P1 connected to the bottom part 151b of the first opening 151. The second portion P2 is separated from the bottom portion 151 b of the first opening 151. More specifically, the first portion P1 of the side wall 151a is adjacent to the bottom 151b of the first opening 151 and away from the surface 153 of the insulating layer 150, and the second portion P2 of the side wall 151a is adjacent to the surface 153 of the insulating layer 150 and away from the first opening 151's bottom 151b. The detailed elements of the pixel structure 100 in various embodiments of the present invention are described in detail below.

Returning to FIG. 1A and FIG. 1B again, in various embodiments of the present invention, the first substrate 110 may be an active device array substrate. The first substrate 110 is provided with the aforementioned insulating layer 150, the first pixel electrode 160, and other elements for controlling potential, such as the data line DL, the scan line GL, and the aforementioned first switching element 140, wherein the plurality of data lines DL and the plurality of data lines The scanning lines GL are staggered with each other to define a complex pixel area PA. For example, the first switching element 140 includes a gate (not shown), a source 144, and a drain 146. The gate (not shown) is electrically connected to the scan line GL, and the source 144 is electrically connected to the data line DL. The drain electrode 146 is electrically connected to the first pixel electrode 160. In this way, the scan line GL can control the first switching element 140 to make the data line DL and the first pixel electrode 160 conductive.

In some embodiments of the present invention, the region 153a of the surface 153 of the insulating layer 150 is in contact with the spacer 170, and the contact range between the surface 153 and the spacer 170 is the region 153a. In some embodiments of the present invention, the second portion P2 of the side wall 151 a is connected to the region 153 a of the surface 153 of the insulating layer 150. Of course, the scope of the present invention should not be limited in this way. In other embodiments, the size of the spacer 170 may be small, so that the second portion P2 of the side wall 151 a is not connected to the region 153 a of the surface 153 of the insulating layer 150.

In some embodiments of the present invention, the spacer 170 is used to support the space between the first substrate 110 and the second substrate 120 to strengthen the structure against external pressure. The area of the top surface 172 of the spacer 170 near the second substrate 120 side is larger than the area of the bottom surface 174 of the spacer 170 near the first substrate 110 side. The spacer 170 is disposed on the second substrate 120 in advance, and is then disposed between the first substrate 110 and the second substrate 120 by being bonded to the first substrate 110. The spacer 170 is used to maintain a uniform thickness between the first substrate 110 and the second substrate 120.

In some embodiments of the present invention, in order to make the area of the first pixel electrode 160 as large as possible, the distance between the first opening 151 and the center of the spacer 170 may be reduced as much as possible. For example, the projection of the second portion P2 of the side wall 151 a of the first opening 151 on the second substrate 120 and the projection of the top surface 172 of the spacer 170 on the second substrate 120 may at least partially overlap. Furthermore, in some embodiments, the projection of the bottom 151b of the first opening 151 on the second substrate 120 and the projection of the top surface 172 of the spacer 170 on the second substrate 120 may at least partially overlap. In some embodiments, the projection of the second portion P2 of the side wall 151 a of the first opening 151 on the second substrate 120 and the projection of the bottom surface 174 of the spacer 170 on the second substrate 120 may at least partially overlap. Here, it should be understood that the spacer 170 depicted in the top view in FIG. 1A is substantially the top surface 172 of the spacer 170 in FIG. 1B.

In addition, in some embodiments, in order to maintain the supporting effect of the spacer 170, the projection of the side wall 151a and the bottom 151b of the first opening 151 on the first substrate 110 may be designed to be different from the projection of the center of the spacer 170 on the first substrate 110. overlapping. In this way, it can be ensured that the center of the spacer 170 can be supported by the insulating layer 150 while still supporting the separation between the first substrate 110 and the second substrate 120.

Through the above setting, a buffer (for example, the second portion P2) can be provided between the area 153a contacted by the spacer 170 and the first pixel electrode 160 without the need for an additional mask or process, thereby avoiding the first pixel electrode 160 has a slight bright spot due to friction.

In some embodiments of the present invention, the pixel structure 100 further includes a second switching element 180 and a second pixel electrode 190, and is disposed in another pixel region PA. The second switching element 180 is disposed on the first substrate 110. The second switching element 180 includes a gate (not shown), a source 184, and a drain 186. The insulating layer 150 includes a second opening 154 to expose the second switching element. The drain of 180 is 186. The second pixel electrode 190 is disposed on the insulating layer 150 and extends to the second opening 154 to electrically connect the drain electrode 186. The second opening 154 has a side wall 154a adjacent to the region 153a and includes a first portion P1 and a second portion P2. The second portion P2 separates the region 153a from the first portion P1 of the side wall 154a of the second opening 154. The second pixel electrode 190 covers only the first portion P1 of the side wall 154a and does not cover the second portion P2 of the side wall 154a. The configuration of the second switching element 180 and the second pixel electrode 190 is substantially the same as the configuration of the first switching element 140 and the first pixel electrode 160, and details are not described herein again.

In some embodiments of the present invention, one of the data lines DL is electrically connected to the first switching element 140, wherein the data line DL is projected on the first substrate 110 and an area 153 a of the surface 153 of the insulation layer 150 on the first substrate 110. The projections partially overlap. Here, the side wall 151a of the first opening 151 and the side wall 154a of the second opening 154 are respectively disposed below the opposite sides of the spacer 170, that is, located on the opposite sides of the data line DL, respectively, so that the first pixel electrode 160 A buffer (for example, the second portion P2) is separated from the second pixel electrode 190 and the region 153a.

Here, the first pixel electrode 160 and the second pixel electrode 190 may cover approximately 90% to approximately 95% of the sidewall 151a and the sidewall 154a, respectively. Of course, the scope of the present invention should not be limited in this way. In other embodiments, only the first pixel electrode 160 can cover about 90% to about 95% of the side wall 151a, and the second pixel electrode 190 can cover 0% of the side wall 154a. To 90% or 95% to 100%. In other words, in some embodiments, the first pixel electrode 160 covers about 90% to about 95% of the side wall 151a. The first pixel electrode 160 can be arranged in a large range as much as possible while avoiding the occurrence of micro-bright spots. The second pixel electrode 190 covers 0% to 90% of the side wall 154a. Although the second pixel electrode 190 avoids the generation of micro-bright spots, it is only arranged in a small area. Alternatively, in other embodiments, the first pixel electrode 160 covers about 90% to about 95% of the side wall 151a. The first pixel electrode 160 can be arranged in a wide range as much as possible while avoiding the occurrence of micro-bright spots. The pixel electrode 190 covers 90% to 100% of the side wall 154a, and the second pixel electrode 190 can avoid micro-bright spots.

Referring to FIG. 1B, in various embodiments of the present invention, the second substrate 120 may be a color filter substrate. That is, the second substrate 120 may be provided with a color filter (not shown) and a black matrix BM. The black matrix BM covers a plurality of data lines DL, scan lines GL, and a plurality of switching elements. The color filter ( (Not shown) are provided in each pixel area PA. The spacer 170 is disposed between a plurality of adjacent pixel regions PA to avoid reducing the aperture ratio of the display panel. For example, FIG. 1A illustrates four pixel regions PA. The spacer 170 is designed between four adjacent pixel regions PA.

Here, for convenience of explanation, the black matrix BM is not shown in FIG. 1A. In actual settings, the black matrix BM substantially shields the first opening 151, the second opening 154, the first switching element 140, and the second switching element. 180, the spacer 170, the scanning line GL, and the data line DL, so as to reduce the reflection or scattering of light caused by the above components and affect the visual effect.

In some embodiments of the present invention, the material of at least one of the first substrate 110 and the second substrate 120 may include glass, quartz, polymer materials (for example, polyimide (PI), benzocyclobutane Benzocyclobutene (BCB), polycarbonate (PC), or other suitable materials), or other suitable materials, or a combination of at least two of the foregoing.

The material of the display medium 130 includes a self-luminous material (for example, an organic light-emitting material, an inorganic light-emitting material, or another suitable material, or a combination thereof) or a non-self-luminous material (for example, liquid crystal, electrophoresis, electrowetting, or other suitable materials). Materials, or a combination of the foregoing). The display medium 130 can change its optical characteristics, such as transmittance or phase, depending on the external electric field, so that the user can observe the light and dark changes, or even the patterns of color.

In some embodiments of the present invention, the data line DL, the drain electrode 146, and the drain electrode 186 are formed by patterning the same layer body. The layer body may be various materials with good conductivity, such as metals, alloys, and conductive adhesives. Or other suitable materials, or a combination of at least two of the foregoing.

In some embodiments of the present invention, the first pixel electrode 160 and the second pixel electrode 190 may be composed of various materials with good conductivity and transparency, such as indium tin oxide (ITO), indium zinc oxide (ITO indium zinc oxide (IZO) and indium zinc oxide (Zinc oxide; ZnO). Alternatively, the first pixel electrode 160 and the second pixel electrode 190 may be made of a material with good reflectivity and conductivity, such as silver, copper, aluminum, and the like.

In some embodiments of the present invention, the insulating layer 150 may be a single-layer or multi-layer structure, and its material includes (for example: silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials), organic materials (for example, light Polyimide (PI), benzocyclobutene (BCB), or other suitable materials), or other suitable materials. Other insulation layers may also include other openings to help the first pixel electrode 160 and the drain electrode 146 be electrically connected, and the second pixel electrode 190 and the drain electrode 186 to be electrically connected.

In some embodiments of the present invention, the first switching element 140 and the second switching element 180 may be various semiconductor elements, such as transistors, diodes, or other suitable elements, and the materials of the semiconductor elements include polycrystalline silicon and single crystal silicon. , Microcrystalline silicon, amorphous silicon, organic semiconductor materials, metal oxide semiconductor materials, or other suitable materials, or a combination of at least two of the foregoing. For example, in FIG. 1B, the first switching element 140 and the second switching element 180 each include a semiconductor layer SE. Here, the first switching element 140 and the second switching element 180 are top-gate semiconductor elements, that is, the scan line GL is located above the semiconductor layer SE and is used as a gate. Of course, it should not be limited to this. In other embodiments, the first switching element 140 and the second switching element 180 may be bottom-gate semiconductor elements, that is, the scan line GL is located below the semiconductor layer SE. In some embodiments of the present invention, the first substrate 110 is further provided with a plurality of insulating layer bodies, such as a gate dielectric layer GI located between the semiconductor layer SE and the gate, to assist the first switching element 140 and the first The setting of the two switching elements 180. It should be understood that the first switching element 140 and the second switching element 180 can be provided in various common methods in the field, and the scope of the present invention should not be limited by the drawings.

Although the above embodiments of the present invention are described in terms of an active element array substrate and a color filter substrate, the scope of the present invention should not be limited by this. In other embodiments, the first substrate 110 may be a Chip On Array (COA) substrate, and the second substrate 120 is a general transparent substrate, which may also be used.

For a display panel with a high-order resolution or a high withstand voltage requirement, because the space is limited or the size of the spacer 170 is large, if the first pixel electrode 160 is too close to the spacer 170, the spacer 170 may contact the first The alignment film (not shown) on the pixel electrode 160 may cause part of the first pixel electrode 160 to fall off due to collision and friction with an external force, resulting in micro-bright spots. Accordingly, the pixel structure 100 in some embodiments of the present invention is suitable for a high-resolution display panel or a display panel with a higher withstand voltage requirement, so as to solve the above-mentioned problem of micro-bright spots. Specifically, the width of the pixel area PA in the direction D1 may be less than about 30 microns to achieve a high-resolution display panel. Alternatively, in various embodiments of the present invention, the length L1 of the bottom surface 174 of the spacer 170 in the direction D1 is greater than 10 microns.

Although it is not illustrated in detail here, it should be understood that some embodiments of the present invention disclose an active device array substrate including a plurality of pixel structures 100 thereon. The active device array substrate includes a first substrate 110, at least one data line DL and at least one scan line GL, a first switching element 140, an insulating layer 150, and at least one first pixel electrode 160. The data lines DL and the scan lines GL are interleaved to define at least one pixel area PA. The first switching element 140 is disposed on a pixel area PA of the substrate 110. The first switching element 140 includes a gate (not shown), a source 144, and a drain 146. The insulating layer 150 covers the switching element 140. The insulating layer 150 includes a first opening 151 to correspond to the drain electrode 146 of the first switching element 140. The first pixel electrode 160 is disposed on the surface 153 of the insulating layer 150 and is located in the pixel area PA. The first pixel electrode 160 extends into the first opening 151 to electrically connect the drain electrode 146 and the first pixel electrode 160 The first pixel electrode 160 covers the first portion P1 of the sidewall 151a of the first opening 151 and the second portion P2 of the sidewall 151a of the first opening 151, and the first pixel electrode 160 covers the first portion P1 of the sidewall 151a of the first opening 151. The bottom portion 151b of the first opening 151 is adjacent to the bottom surface 153 of the insulating layer 150, and the second portion P2 of the side wall 151a is adjacent to the surface 153 of the insulating layer 150 and far from the bottom portion 151b of the first opening 151a. Other details of the active device array substrate are substantially as described above, and are not repeated here.

It should be understood that, in practical applications, the application of the embodiments of the present invention is not limited to the aforementioned high-resolution display panel or display panel with higher withstand voltage requirements, and any need to configure spacers and pixel electrodes simultaneously The display panel can adopt the embodiments of the present invention.

FIG. 2 is a schematic cross-sectional view of a pixel structure 100 according to another embodiment of the present invention. This embodiment mode is similar to the embodiment shown in FIG. 1B except that, in this embodiment mode, the insulating layer 150 has a composite layer structure and includes a flat layer 156 and a dielectric layer 157. A dielectric layer 157 is disposed on the flat layer 156. Here, the flat layer 156 is used to overcome a surface that is not flat due to the arrangement of the first switching element 140 (not shown here). Therefore, the flat layer 156 is designed to be thicker than the dielectric layer 157.

Here, the first pixel electrode 160 on the sidewall 151a only covers the sidewall of a portion of the flat layer 156, and exposes the sidewall of the other portion of the flat layer 156 and the complete dielectric layer 157, so that the first portion P1 of the sidewall 151a is flat. The second portion P2 of the sidewall 151a is formed by the flat layer 156 and the dielectric layer 157. In other embodiments, the second portion P2 of the side wall 151 a may be formed only by the dielectric layer 157, that is, the flat layer 156 that the first pixel electrode 160 may completely cover, or even the dielectric layer 157 may be partially covered.

The materials of the dielectric layer 157 and the flat layer 156 include (for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials), organic materials (for example, photoresist, polyimide (PI), Benzocyclobutenc (BCB), or other suitable materials), or other suitable materials. The other details of this embodiment are substantially as described above, and are not repeated here.

FIG. 3A is a schematic top view of a pixel structure 100 according to another embodiment of the present invention. Figure 3B is a schematic cross-sectional view taken along line 3B-3B of Figure 3A. Figure 3C is a partial enlarged view of the pixel structure of Figure 3B. This embodiment mode is similar to the foregoing embodiments shown in FIGS. 1A to 1C, except that in this embodiment, the insulating layer 150 includes a flat layer 156, a dielectric layer 157, and a pad 158. A dielectric layer 157 is disposed on the flat layer 156, and a pad 158 is disposed on the dielectric layer 157.

The dielectric layer 157 is disposed on the flat layer 156. The flat layer 156 is used to overcome the uneven surface (not shown here) due to the arrangement of the first switching element 140. Therefore, the flat layer 156 is more designed than the dielectric layer. 157 is thick. The pad 158 is adjacent to the area 153a of the surface 153, for example, on the area 153a. The pad 158 can make the area 153a at least more prominent than other areas of the surface 153 (for example, the height of the area 153a is greater than the height of other areas of the surface 153) ) So that the spacer 170 contacts the spacer 158.

Here, although the spacer 158 almost completely covers the dielectric layer 157 under the spacer 170, in fact, the spacer 158 may also expose a part of the dielectric layer 157. In some embodiments, the dielectric layer 157 can cover the spacer 158, that is, the spacer 158 is disposed between the flat layer 156 and the dielectric layer 157, while still making the region 153a of the corresponding spacer 170 more than other regions. protruding.

Here, the second portion P2 of the side wall 151a of the first opening 151 is formed by the flat layer 156, the dielectric layer 157, and the side wall of the pad 158, that is, the first pixel electrode 160 located on the side wall 151a only covers part of the The sidewalls of the flat layer 156 are not covered by another portion of the flat layer 156, the dielectric layer 157, and the spacer 158. In other embodiments, the second portion P2 of the sidewall 151a may be formed only by the dielectric layer 157 and the sidewall of the pad 158 or only the sidewall of the pad 158, that is, the flat layer that the first pixel electrode 160 can completely cover. The sidewalls of 156 or the sidewalls of both the planar layer 156 and the dielectric layer 157. The other details of this embodiment are substantially as described above, and are not repeated here.

FIG. 4 is a schematic cross-sectional view of a pixel structure 100 according to another embodiment of the present invention. This embodiment is similar to the embodiment shown in FIG. 3B described above. The dielectric layer 157 forms the surface 153 of the insulating layer 150. The difference is that, in this embodiment, the dielectric layer 157 also constitutes the side wall 151a of the first opening 151.

Specifically, the dielectric layer 157 extends to cover the opening of the flat layer 156, so that the first portion P1 and the second portion P2 are both formed by the dielectric layer 157. The dielectric layer 157 covers the first opening 151 but does not cover the bottom 151 b of the first opening 151. The first pixel electrode 160 is connected to the drain electrode 146 through the opening. The dielectric layer 157 separates the first pixel electrode 160 from the flat layer 156, so that the first pixel electrode 160 is not in contact with the flat layer 156. The other details of this embodiment are substantially as described above, and are not repeated here.

In various embodiments of the present invention, in a display panel using a spacer, by integrating the design of the spacer and a through hole (such as a first opening of an insulating layer) inside the pixel structure, the additional space can be obtained without sacrificing extra space and In the case of an additional process, the spacer is separated from the first pixel electrode to prevent micro bright spots caused by friction between the two. In addition, the projection relationship between the through holes and the spacers in the pixel structure can be designed, so that the first pixel electrode can be arranged in a large range as much as possible while maintaining the support effect of the spacers.

Although the present invention has been disclosed in various embodiments as above, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

Claims (17)

    A pixel structure for a display panel includes: a first substrate; a second substrate disposed opposite the first substrate; a display medium disposed between the first substrate and the second substrate; a first A switching element is disposed on the first substrate. The first switching element includes a gate, a source, and a drain. An insulating layer covers the first switching element. The insulating layer has a first opening. To correspond to the drain electrode of the first switching element; a first pixel electrode is disposed on the insulating layer and extends into the first opening to electrically connect the drain electrode, wherein the first pixel electrode covers the A first portion of a side wall of the first opening and not covering a second portion of the side wall of the first opening; and a spacer disposed between the first substrate and the second substrate, wherein the insulating layer is adjacent A surface of the second substrate includes a region corresponding to the spacer, and the second portion of the sidewall is located between the region and the first portion of the sidewall.         The pixel structure according to claim 1, wherein the first portion of the sidewall is connected to a bottom of the first opening, and the first portion of the sidewall is located at the second portion of the sidewall and the first opening of the first opening. Between the bottom.         The pixel structure according to claim 1, wherein the second portion of the sidewall is connected to the region of the surface of the insulating layer.         The pixel structure according to claim 1, wherein the spacer has a top surface adjacent to the second substrate and a bottom surface adjacent to the first substrate, and the second portion of the side wall of the first opening is in the first The projection of the two substrates at least partially overlaps the projection of the bottom surface of the spacer on the second substrate, wherein the area of the top surface of the spacer is larger than the area of the bottom surface of the spacer.         The pixel structure according to claim 1, wherein the insulating layer comprises: a pad, adjacent to the region of the surface, so that the region of the surface is more prominent than other regions of the insulating layer.         The pixel structure according to claim 1, wherein the height of the first portion of the sidewall is 90% to 95% of the height of the sidewall.         The pixel structure according to claim 1, wherein a length of the spacer in a direction adjacent to a bottom surface of the first substrate is greater than 10 microns.         The pixel structure according to claim 7, wherein the first substrate includes a pixel area for the first switching element and the first pixel electrode to be disposed, and the width of the pixel area in the direction is less than 30. Microns.         The pixel structure according to claim 1, wherein a projection of a bottom of the first opening on the second substrate and a projection of a top surface of the spacer on the second substrate at least partially overlap.         The pixel structure according to claim 1, further comprising: a second switching element disposed on the first substrate, wherein the second switching element includes a gate, a source, and a drain, wherein the insulating layer Including a second opening to correspond to the drain of the second switching element; and a second pixel electrode disposed on the insulating layer and extending into the second opening to electrically connect the second switching element The drain electrode, wherein the second pixel electrode covers a first portion of a side wall of the second opening and does not cover a second portion of the side wall of the second opening, wherein the second portion of the side wall of the second opening A portion is located between the region and the first portion of the sidewall of the second opening.         The pixel structure according to claim 10, further comprising: a data line electrically connected to the source of the first switching element, wherein the sidewall of the first opening and the sidewall of the second opening are respectively disposed at Opposite sides of the data line.         The pixel structure according to claim 11, wherein the projection of the data line on the second substrate and the projection of the spacer on the second substrate partially overlap.         The pixel structure according to claim 1, wherein the insulating layer includes a flat layer and a dielectric layer, and the dielectric layer is disposed on the flat layer.         An active element array substrate includes: a substrate; at least one data line and at least one scan line are disposed on the substrate, wherein the data line and the scan line are staggered to define at least one pixel area; at least one switching element is provided On the pixel region of the substrate, the switching element includes a gate, a source, and a drain; the data line is electrically connected to the source of the switching element; and the scanning line is electrically connected to the switching element. The gate electrode; an insulating layer covering the switching element, wherein the insulating layer includes at least one opening to correspond to the drain electrode of the switching element; and at least one pixel electrode disposed on a surface of the insulating layer and located on In the pixel region, wherein the pixel electrode extends into the opening to electrically connect the drain electrode, wherein the pixel electrode covers a first portion of a sidewall of the opening and does not cover a second portion of the sidewall of the opening Wherein the first portion of the sidewall is adjacent to a bottom of the opening and away from the surface of the insulating layer, and the second portion of the sidewall is adjacent to the surface of the insulating layer Away from the opening of the base.         The active device array substrate according to claim 14, wherein a height of the first portion of the sidewall is 90% to 95% of a height of the sidewall.         The active device array substrate according to claim 14, wherein the insulating layer includes a flat layer and a dielectric layer, the dielectric layer is disposed on the flat layer, and the second portion is formed by a part of a sidewall of the flat layer and the One side wall of the dielectric layer is formed together.         The active device array substrate according to claim 14, wherein the insulating layer includes a flat layer and a dielectric layer, the dielectric layer is disposed on the flat layer, and the second portion is a sidewall of the dielectric layer.