JPH11305681A - Display device - Google Patents
Display deviceInfo
- Publication number
- JPH11305681A JPH11305681A JP10122727A JP12272798A JPH11305681A JP H11305681 A JPH11305681 A JP H11305681A JP 10122727 A JP10122727 A JP 10122727A JP 12272798 A JP12272798 A JP 12272798A JP H11305681 A JPH11305681 A JP H11305681A
- Authority
- JP
- Japan
- Prior art keywords
- line
- lines
- signal line
- auxiliary
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13456—Cell terminals located on one side of the display only
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は液晶表示装置等の
表示装置に関する。The present invention relates to a display device such as a liquid crystal display device.
【０００２】[0002]
【従来の技術】図１３は従来のアクティブマトリクス型
の液晶表示装置の一例の一部の等価回路的平面図を示
し、図１４はそのＦ−Ｆ線に沿う一部の断面図を示した
ものである。この液晶表示装置は、ガラスや樹脂等から
なる下側と上側の２枚の基板１、２が互いに貼り合わさ
れ、その間に液晶（図示せず）が封入された構造となっ
ている。この場合、下側基板１の図１３における右辺部
及び下辺部は上側基板２から突出され、端子配列領域を
形成する突出部１ａ、１ｂとなっている。そして、上側
基板２の下側における下側基板１上の表示領域には複数
の走査信号ライン（下部ライン）３と複数のデータ信号
ライン（上部ライン）４とがその間に絶縁膜５を介在さ
れた状態で互いに直交して設けられ、両ライン３、４に
接続された薄膜トランジスタ（スイッチング素子）６及
びこの薄膜トランジスタ６によって駆動される画素電極
（表示要素、図示せず）がマトリクス状に配列されてい
る。この場合、図１３に示すように、走査信号ライン３
は行方向に延びて配置され、その右端部は下側基板１の
突出部１ａ上の一点鎖線で示す半導体チップ搭載領域７
内に設けられた出力側接続端子８に接続されている。デ
ータ信号ライン４は列方向に延びて配置され、その下端
部は下側基板１の突出部１ｂ上の一点鎖線で示す半導体
チップ搭載領域９内に設けられた出力側接続端子１０に
接続されている。半導体チップ搭載領域７、９内に設け
られた入力側接続端子１１、１２は、下側基板１上の下
辺部の右側に設けられた外部接続端子１３、１４に引き
回し線１５、１６を介して接続されている。なお、図示
していないが、半導体チップ搭載領域７上には走査信号
ライン３に走査信号を供給する半導体チップが搭載さ
れ、半導体チップ搭載領域９上にはデータ信号ライン４
にデータ信号を供給する半導体チップが搭載され、外部
接続端子１３、１４の部分にはフレキシブル配線基板の
一端部が接合されている。2. Description of the Related Art FIG. 13 is a plan view of a part of an example of a conventional active matrix type liquid crystal display device, which is equivalent to an equivalent circuit, and FIG. 14 is a sectional view of a part thereof taken along line FF. It is. This liquid crystal display device has a structure in which two lower and upper substrates 1 and 2 made of glass, resin, or the like are bonded to each other, and a liquid crystal (not shown) is sealed therebetween. In this case, the right side portion and the lower side portion of the lower substrate 1 in FIG. 13 protrude from the upper substrate 2 to form protrusions 1a and 1b that form a terminal array region. In the display area on the lower substrate 1 below the upper substrate 2, a plurality of scanning signal lines (lower lines) 3 and a plurality of data signal lines (upper lines) 4 are provided with an insulating film 5 interposed therebetween. The thin film transistors (switching elements) 6 and the pixel electrodes (display elements, not shown) driven by the thin film transistors 6 are provided orthogonal to each other and connected to both lines 3 and 4 in a matrix state. I have. In this case, as shown in FIG.
Are arranged extending in the row direction, and the right end thereof is a semiconductor chip mounting area 7 indicated by a dashed line on the protrusion 1a of the lower substrate
Connected to an output-side connection terminal 8 provided therein. The data signal line 4 extends in the column direction, and its lower end is connected to an output-side connection terminal 10 provided in a semiconductor chip mounting area 9 indicated by a dashed line on the protrusion 1 b of the lower substrate 1. I have. The input-side connection terminals 11 and 12 provided in the semiconductor chip mounting regions 7 and 9 are connected to external connection terminals 13 and 14 provided on the right side of the lower side of the lower substrate 1 via lead lines 15 and 16. It is connected. Although not shown, a semiconductor chip for supplying a scanning signal to the scanning signal line 3 is mounted on the semiconductor chip mounting area 7, and a data signal line 4 is mounted on the semiconductor chip mounting area 9.
A semiconductor chip for supplying a data signal is mounted on one end, and one end of a flexible wiring board is joined to the external connection terminals 13 and 14.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
このような液晶表示装置では、図１３に示すように、下
側基板１の右辺部からなる突出部１ａ上に行方向に延び
る走査信号ライン３の出力側接続端子８等を設け、下側
基板１の下辺部からなる突出部１ｂ上に列方向に延びる
データ信号ライン４の出力側接続端子１０等を設けてい
るので、下側基板１の右辺部及び下辺部を上側基板２か
ら突出させる必要があり、下側基板１のサイズが比較的
大きくなり、ひいては額縁の幅が大きくなってしまうと
いう問題があった。この発明の課題は、額縁の幅を小さ
くすることである。However, in such a conventional liquid crystal display device, as shown in FIG. 13, a scanning signal line 3 extending in the row direction on a projection 1a formed on the right side of the lower substrate 1 is provided. Are provided, and the output-side connection terminals 10 of the data signal lines 4 extending in the column direction are provided on the protruding portions 1b formed on the lower side of the lower substrate 1. The right side and the lower side need to protrude from the upper substrate 2, which causes a problem that the size of the lower substrate 1 becomes relatively large, and the width of the frame becomes large. An object of the present invention is to reduce the width of a frame.
【０００４】[0004]
【課題を解決するための手段】この発明は、基板上に複
数の下部ラインと複数の上部ラインとがその間に絶縁膜
が介在された状態で互いに直交して設けられ、前記両ラ
インに接続されたスイッチング素子及び該スイッチング
素子によて駆動される表示要素がマトリクス状に配列さ
れた表示領域を有する表示装置において、前記基板の表
示領域の一辺側に前記両ラインの接続端子が配列された
端子配列領域を設けたものである。この発明によれば、
基板の表示領域の一辺側に両ラインの接続端子が配列さ
れた端子配列領域を設けているので、基板の表示領域の
二辺側に端子配列領域を設ける場合と比較して、基板の
サイズを小さくすることができ、ひいては額縁の幅を小
さくすることができる。According to the present invention, a plurality of lower lines and a plurality of upper lines are provided on a substrate at right angles to each other with an insulating film interposed therebetween, and are connected to the two lines. Device having a display area in which switching elements and display elements driven by the switching elements are arranged in a matrix, a terminal in which the connection terminals of the two lines are arranged on one side of the display area of the substrate An array region is provided. According to the invention,
Since the terminal arrangement area in which the connection terminals of both lines are arranged on one side of the display area of the substrate is provided, the size of the substrate is reduced as compared with the case where the terminal arrangement area is provided on two sides of the display area of the substrate. The width of the frame can be reduced.
【０００５】[0005]
【発明の実施の形態】図１はこの発明の第１実施形態に
おける液晶表示装置の要部の等価回路的平面図を示し、
図２はそのＣ−Ｃ線に沿う一部の断面図を示したもので
ある。これらの図において、図１３及び図１４と同一名
称部分には同一の符合を付し、その説明を適宜省略す
る。この液晶表示装置では、下側基板１の図１における
下辺部のみが上側基板２から突出され、端子配列領域を
形成する突出部１ｂとなっている。そして、基本的に
は、データ信号ライン４の各間における絶縁膜５の上面
には補助走査信号ライン２１がデータ信号ライン４と平
行に且つデータ信号ライン４の形成と同時に形成されて
設けられている。この場合、図２に示すように、補助走
査信号ライン２１の上端部は、対応する走査信号ライン
３に、絶縁膜５に形成されたコンタクトホール２２を介
して接続されている。補助走査信号ライン２１の下端部
は、下側基板１の突出部１ｂ上の所定の領域からなる半
導体チップ搭載領域７内に設けられた出力側接続端子８
に接続されている。これにより、走査信号ライン３は補
助走査信号ライン２１を介して半導体チップ搭載領域７
内に設けられた出力側接続端子８に接続されている。デ
ータ信号ライン４の下端部は、下側基板１の突出部１ｂ
上の他の所定の領域からなる半導体チップ搭載領域９内
に設けられた出力側接続端子１０に接続されている。こ
の場合、２種類の出力側接続端子８、１０は１つおきで
千鳥状に配列されている。半導体チップ搭載領域７、９
内に設けられた入力側接続端子１１、１２は、下側基板
１の突出部１ｂ上の右側に設けられた外部接続端子１
３、１４に引き回し線１５、１６を介して接続されてい
る。FIG. 1 is a plan view showing an equivalent circuit of a main part of a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 shows a partial cross-sectional view along the line CC. In these figures, the same reference numerals are given to the same parts as in FIGS. 13 and 14, and the description thereof will be omitted as appropriate. In this liquid crystal display device, only the lower side of the lower substrate 1 in FIG. 1 protrudes from the upper substrate 2 to form a protrusion 1b that forms a terminal array region. Basically, an auxiliary scanning signal line 21 is provided on the upper surface of the insulating film 5 between the data signal lines 4 so as to be formed in parallel with the data signal line 4 and at the same time as the formation of the data signal line 4. I have. In this case, as shown in FIG. 2, the upper end of the auxiliary scanning signal line 21 is connected to the corresponding scanning signal line 3 via a contact hole 22 formed in the insulating film 5. The lower end of the auxiliary scanning signal line 21 is connected to an output-side connection terminal 8 provided in a semiconductor chip mounting area 7 formed of a predetermined area on the protruding portion 1b of the lower substrate 1.
It is connected to the. As a result, the scanning signal line 3 is connected to the semiconductor chip mounting area 7 via the auxiliary scanning signal line 21.
Connected to an output-side connection terminal 8 provided therein. The lower end of the data signal line 4 is connected to the protrusion 1 b of the lower substrate 1.
It is connected to an output-side connection terminal 10 provided in a semiconductor chip mounting area 9 composed of another predetermined area above. In this case, the two types of output-side connection terminals 8, 10 are alternately arranged in a staggered manner. Semiconductor chip mounting areas 7, 9
The input connection terminals 11 and 12 provided inside the external connection terminal 1 provided on the right side on the protrusion 1 b of the lower substrate 1.
3 and 14 are connected via lead wires 15 and 16.
【０００６】このように、この液晶表示装置では、下側
基板１の図１における下辺部のみを上側基板２から突出
させ、この突出部１ｂ上に走査信号ライン３及びデータ
信号ライン４の出力側接続端子８、１０を設けているの
で、図１３に示す従来のように、下側基板１の二辺部１
ａ、１ｂを上側基板２から突出させる場合と比較して、
下側基板１のサイズを小さくすることができ、ひいては
額縁の幅を小さくすることができる。ところで、データ
信号ライン４及び補助走査信号ライン２１をアルミニウ
ム等の非透過性金属によって形成する場合には、開口率
がなるべく低下しないようにするために、補助走査信号
ライン２１をデータ信号ライン４になるべく近づけて配
置するのが望ましい。As described above, in this liquid crystal display device, only the lower side portion of the lower substrate 1 in FIG. 1 is projected from the upper substrate 2, and the output side of the scanning signal line 3 and the data signal line 4 is provided on the projected portion 1b. Since the connection terminals 8 and 10 are provided, the two side portions 1 of the lower substrate 1 are different from the related art shown in FIG.
a and 1b are protruded from the upper substrate 2,
The size of the lower substrate 1 can be reduced, and thus the width of the frame can be reduced. When the data signal line 4 and the auxiliary scanning signal line 21 are formed of a non-transmissive metal such as aluminum, the auxiliary scanning signal line 21 is connected to the data signal line 4 in order to minimize the aperture ratio. It is desirable to arrange as close as possible.
【０００７】なお、上記第１実施形態では、データ信号
ライン４の各間における絶縁膜５の上面に補助走査信号
ライン２１を設けた場合について説明したが、これに限
らず、次に説明するこの発明の第２実施形態のように、
データ信号ライン４の各下における絶縁膜５中に補助走
査信号ライン２１を設けるようにしてもよい。すなわ
ち、図３はこの発明の第２実施形態における液晶表示装
置の要部の等価回路的平面図を示し、図４（Ａ）はその
一部の平面図を示し、図５は図４（Ａ）のＤ−Ｄ線に沿
う断面図を示したものである。これらの図において、図
１及び図２と同一名称部分には同一の符合を付し、その
説明を適宜省略する。ただし、図３においては、図示の
都合上、データ信号ライン４と補助走査信号ライン２１
とを離間させているが、実際は、データ信号ライン４下
に補助走査信号ライン２１が設けられている。In the first embodiment, the case where the auxiliary scanning signal line 21 is provided on the upper surface of the insulating film 5 between the data signal lines 4 has been described. However, the present invention is not limited to this. As in the second embodiment of the invention,
The auxiliary scanning signal line 21 may be provided in the insulating film 5 below each of the data signal lines 4. That is, FIG. 3 shows an equivalent circuit plan view of a main part of the liquid crystal display device according to the second embodiment of the present invention, FIG. 4A shows a partial plan view thereof, and FIG. 3) is a cross-sectional view taken along line DD of FIG. In these drawings, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. However, in FIG. 3, for convenience of illustration, the data signal line 4 and the auxiliary scanning signal line 21 are not shown.
However, in practice, an auxiliary scanning signal line 21 is provided below the data signal line 4.
【０００８】この第２実施形態では、絶縁膜５は下層絶
縁膜５Ａと上層絶縁膜５Ｂとからなっている。そして、
走査信号ライン３を含む下側基板１の上面には下層絶縁
膜５Ａが設けられ、下層絶縁膜５Ａの上面の所定の箇所
（データ信号ライン４下となる部分）には補助走査信号
ライン２１が設けられており、この状態の平面図の一部
を図４（Ｂ）に示す。この場合、図４（Ｂ）及び図５に
示すように、補助走査信号ライン２１の上端部は、対応
する走査信号ライン３に、下層絶縁膜５Ａに形成された
コンタクトホール２２Ａを介して接続されている。補助
走査信号ライン２１の下端部は、下側基板１の突出部１
ｂ上の所定の領域からなる半導体チップ搭載領域７内に
設けられた出力側接続端子８に接続されている。これに
より、走査信号ライン３は補助走査信号ライン２１を介
して半導体チップ搭載領域７内に設けられた出力側接続
端子８に接続されている。補助走査信号ライン２１を含
む下層絶縁膜５Ａの上面には上層絶縁膜５Ｂが設けら
れ、上層絶縁膜５Ｂの上面の所定の箇所（補助走査信号
ライン２１及びその延長線上）にはデータ信号ライン４
が設けられている（図４（Ａ）、（Ｂ）及び図５参
照）。In the second embodiment, the insulating film 5 comprises a lower insulating film 5A and an upper insulating film 5B. And
A lower insulating film 5A is provided on the upper surface of the lower substrate 1 including the scanning signal line 3, and an auxiliary scanning signal line 21 is provided at a predetermined position (a portion below the data signal line 4) on the upper surface of the lower insulating film 5A. FIG. 4B shows a part of a plan view in this state. In this case, as shown in FIGS. 4B and 5, the upper end of the auxiliary scanning signal line 21 is connected to the corresponding scanning signal line 3 via a contact hole 22A formed in the lower insulating film 5A. ing. The lower end of the auxiliary scanning signal line 21 is
b, and is connected to an output-side connection terminal 8 provided in a semiconductor chip mounting area 7 consisting of a predetermined area on the semiconductor chip mounting area b. Thus, the scanning signal line 3 is connected to the output side connection terminal 8 provided in the semiconductor chip mounting area 7 via the auxiliary scanning signal line 21. An upper insulating film 5B is provided on the upper surface of the lower insulating film 5A including the auxiliary scanning signal line 21, and a data signal line 4 is provided at a predetermined position on the upper surface of the upper insulating film 5B (on the auxiliary scanning signal line 21 and an extension thereof).
(See FIGS. 4A, 4B and 5).
【０００９】このように、この第２実施形態では、補助
走査信号ライン２１上に上層絶縁膜５Ｂを介してデータ
信号ライン４を設けているので、つまりデータ信号ライ
ン４下に補助走査信号ライン２１をその間に上層絶縁膜
５Ｂを介在させて設けているので、データ信号ライン４
及び補助走査信号ライン２１をアルミニウム等の非透過
性金属によって形成しても、開口率が低下しないように
することができる。As described above, in the second embodiment, the data signal line 4 is provided on the auxiliary scanning signal line 21 via the upper insulating film 5B, that is, the auxiliary scanning signal line 21 is provided below the data signal line 4. Are provided with the upper insulating film 5B interposed therebetween, so that the data signal line 4
Even if the auxiliary scanning signal line 21 is formed of a non-transmissive metal such as aluminum, the aperture ratio can be prevented from lowering.
【００１０】ところで、上記第２実施形態では、絶縁膜
５を下層絶縁膜５Ａと上層絶縁膜５Ｂの２層構造とし、
且つ、下層絶縁膜５Ａの上面に補助走査信号ライン２１
を設けているので、製造工程数が増加することになる。
そこで、次に、製造工程数を増加することなく、開口率
が低下しないようにすることができるこの発明の第３実
施形態について説明する。図６はこの発明の第３実施形
態における液晶表示装置の要部の等価回路的平面図を示
し、図７（Ａ）はその一部の平面図を示し、図８は図７
（Ａ）のＥ−Ｅ線に沿う断面図を示したものである。こ
れらの図において、図１及び図２と同一名称部分には同
一の符合を付し、その説明を適宜省略する。ただし、図
６においては、図示の都合上、データ信号ライン４と符
合２１Ａで示す補助走査信号ラインとを離間させている
が、実際は、データ信号ライン４下に符合２１Ａで示す
補助走査信号ラインが設けられている。In the second embodiment, the insulating film 5 has a two-layer structure of a lower insulating film 5A and an upper insulating film 5B.
Further, the auxiliary scanning signal line 21 is provided on the upper surface of the lower insulating film 5A.
Is provided, the number of manufacturing steps increases.
Therefore, a third embodiment of the present invention will now be described which can prevent the aperture ratio from decreasing without increasing the number of manufacturing steps. FIG. 6 is an equivalent circuit plan view of a main part of a liquid crystal display device according to a third embodiment of the present invention, FIG. 7A is a plan view of a part thereof, and FIG.
FIG. 3A is a cross-sectional view taken along line EE of FIG. In these drawings, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. However, in FIG. 6, the data signal line 4 is separated from the auxiliary scanning signal line indicated by reference numeral 21A for the sake of illustration, but actually, the auxiliary scanning signal line indicated by reference numeral 21A is located below the data signal line 4. Is provided.
【００１１】この第３実施形態では、下側基板１の上面
の所定の箇所（データ信号ライン４下となる部分）に第
１補助走査信号ライン２１Ａが走査信号ライン３の形成
と同時に形成されて設けられ、その上面に絶縁膜５が設
けられており、この状態の平面図の一部を図７（Ｂ）に
示す。すなわち、まず下側基板１の上面にライン形成用
の金属膜を成膜し、次いでフォトリソグラフィによりこ
の金属膜から走査信号ライン３及び第１補助走査信号ラ
イン２１Ａを同時に形成し、次いでその上面に絶縁膜５
を形成する。この場合、第１補助走査信号ライン２１Ａ
は、対応する走査信号ライン３と直接接続され、対応し
ない走査信号ライン３とは分離されている。また、第１
補助走査信号ライン２１Ａの各分離部には走査信号ライ
ン３と平行な方向に延びる平行部２１ａが設けられ、こ
れらの平行部２１ａの先端部に対応する部分における絶
縁膜５にはコンタクトホール２２Ｂが設けられている。
そして、データ信号ライン４の近傍における絶縁膜５の
上面の所定の箇所には第２補助走査信号ライン２１Ｂが
データ信号ライン４と平行に且つデータ信号ライン４の
形成と同時に形成されて設けられている。すなわち、こ
の場合も、まず絶縁膜５の上面にライン形成用の金属膜
を成膜し、次いでフォトリソグラフィによりこの金属膜
からデータ信号ライン４及び第２補助走査信号ライン２
１Ｂを同時に形成する。この場合、第２補助走査信号ラ
イン２１Ｂの両端部は、第１補助走査信号ライン２１Ａ
の分離部における２つの平行部２１ａにコンタクトホー
ル２２Ｂを介して接続されている（図７（Ａ）、（Ｂ）
及び図８参照）。つまり、第２補助走査信号ライン２１
Ｂは第１補助走査信号ライン２１Ａの分離された領域に
橋渡しされている。In the third embodiment, a first auxiliary scanning signal line 21A is formed at a predetermined position (a portion below the data signal line 4) on the upper surface of the lower substrate 1 simultaneously with the formation of the scanning signal line 3. The insulating film 5 is provided on the upper surface thereof, and a part of a plan view in this state is illustrated in FIG. That is, first, a metal film for forming a line is formed on the upper surface of the lower substrate 1, then the scanning signal line 3 and the first auxiliary scanning signal line 21A are simultaneously formed from this metal film by photolithography, and then the upper surface is formed. Insulating film 5
To form In this case, the first auxiliary scanning signal line 21A
Are directly connected to the corresponding scanning signal line 3 and separated from the non-corresponding scanning signal line 3. Also, the first
Each separation portion of the auxiliary scanning signal line 21A is provided with a parallel portion 21a extending in a direction parallel to the scanning signal line 3, and a contact hole 22B is formed in the insulating film 5 at a portion corresponding to the tip of these parallel portions 21a. Is provided.
A second auxiliary scanning signal line 21B is provided at a predetermined position on the upper surface of the insulating film 5 near the data signal line 4 so as to be formed in parallel with the data signal line 4 and simultaneously with the formation of the data signal line 4. I have. That is, also in this case, first, a metal film for forming a line is formed on the upper surface of the insulating film 5, and then the data signal line 4 and the second auxiliary scanning signal line 2 are formed from the metal film by photolithography.
1B are simultaneously formed. In this case, both ends of the second auxiliary scanning signal line 21B are connected to the first auxiliary scanning signal line 21A.
(FIGS. 7A and 7B) are connected to two parallel portions 21a in the separation portion of FIG.
And FIG. 8). That is, the second auxiliary scanning signal line 21
B is bridged to a separated area of the first auxiliary scanning signal line 21A.
【００１２】このように、この第３実施形態では、絶縁
膜５を１層とし、且つ、第１補助走査信号ライン２１Ａ
を走査信号ライン３の形成と同時に形成するとともに、
第２補助走査信号ライン２１Ｂをデータ信号ライン４の
形成と同時に形成しているので、製造工程数が増加しな
いようにすることができる。また、補助走査信号ライン
の大部分を占める第１補助走査信号ライン２１Ａをデー
タ信号ライン４下に設け、この第１補助走査信号ライン
２１Ａの分離部である２つの平行部２１ａを接続する第
２補助走査信号ライン２１Ｂをデータ信号ライン４の近
傍に該データ信号ライン４と平行に設けているので、開
口率がほとんど低下しないようにすることができる。As described above, in the third embodiment, the insulating film 5 is formed as one layer, and the first auxiliary scanning signal line 21A is formed.
Is formed simultaneously with the formation of the scanning signal line 3,
Since the second auxiliary scanning signal line 21B is formed simultaneously with the formation of the data signal line 4, the number of manufacturing steps can be prevented from increasing. Further, a first auxiliary scanning signal line 21A which occupies most of the auxiliary scanning signal line is provided below the data signal line 4, and a second connecting portion which connects two parallel portions 21a which are separated portions of the first auxiliary scanning signal line 21A. Since the auxiliary scanning signal line 21B is provided in the vicinity of the data signal line 4 and in parallel with the data signal line 4, the aperture ratio can be hardly reduced.
【００１３】なお、上記第１〜第３実施形態では、例え
ば図１に示すように、下側基板１の突出部１ｂ上に２つ
の半導体チップ搭載領域７、８を設け、２種類の出力側
接続端子８、１０を１つおきに千鳥状に配列した場合に
ついて説明したが、これに限定されるものではない。例
えば、図９に示すこの発明の第４実施形態のように、下
側基板１の突出部１ｂ上に１つの半導体チップ搭載領域
２３を設け、この半導体チップ搭載領域２３内の所定の
箇所に２種類の出力側接続端子８、１０を１つおきで直
線状に配列し、且つ、半導体チップ搭載領域２３内の他
の所定の箇所に２種類の入力側接続端子１１、１２を配
置し、半導体チップ搭載領域２３に走査信号及びデータ
信号を供給する１つの半導体チップ（図示せず）を搭載
するようにしてもよい。このようにした場合には、半導
体チップを１つ搭載すればよいので、半導体チップ搭載
工程を簡略化することができる。In the first to third embodiments, for example, as shown in FIG. 1, two semiconductor chip mounting regions 7 and 8 are provided on the protruding portion 1b of the lower substrate 1 to provide two types of output sides. Although the case where the connection terminals 8 and 10 are alternately arranged in a staggered manner has been described, the present invention is not limited to this. For example, as in the fourth embodiment of the present invention shown in FIG. 9, one semiconductor chip mounting region 23 is provided on the projecting portion 1b of the lower substrate 1, and two semiconductor chip mounting regions 23 are provided at predetermined positions in the semiconductor chip mounting region 23. The output terminal connection terminals 8 and 10 are alternately arranged in a straight line at every other position, and the input terminal connection terminals 11 and 12 are disposed at other predetermined positions in the semiconductor chip mounting area 23. One semiconductor chip (not shown) for supplying a scanning signal and a data signal may be mounted on the chip mounting area 23. In such a case, since only one semiconductor chip needs to be mounted, the semiconductor chip mounting process can be simplified.
【００１４】また、上記第２及び第３実施形態では、例
えば図３に示すように、２種類の出力側接続端子８、１
０を１つおきに千鳥状に配列し、この２種類の出力側接
続端子８、１０にそれぞれ接続されるデータ信号ライン
４の下端側と補助走査信号ライン２１（図６の場合に
は、第２補助走査信号ライン２１Ｂ）の下端側とが互い
に交差しないように配置した場合について説明したが、
これに限定されるものではない。例えば、図１０に示す
この発明の第５実施形態のように、データ信号ライン４
の下端側と補助走査信号ライン２１（図６の場合には、
第２補助走査信号ライン２１Ｂ）の下端側とが互いに交
差するように配置してもよい。なお、図１０において、
図３と同一名称部分には同一の符合を付し、その説明を
適宜省略する。In the second and third embodiments, for example, as shown in FIG. 3, two types of output side connection terminals 8, 1
0 are alternately arranged in a staggered manner, and the lower end of the data signal line 4 connected to the two types of output side connection terminals 8 and 10 and the auxiliary scanning signal line 21 (in FIG. The case where the lower end sides of the 2 auxiliary scanning signal lines 21B) are arranged so as not to cross each other has been described.
It is not limited to this. For example, as in the fifth embodiment of the present invention shown in FIG.
And the auxiliary scanning signal line 21 (in the case of FIG. 6,
The lower ends of the second auxiliary scanning signal lines 21B) may be arranged to cross each other. In FIG. 10,
The same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
【００１５】この第５実施形態を説明するに、まず、図
３〜図５に示す第２実施形態の場合には、上述したよう
に、絶縁膜５を下層絶縁膜５Ａと上層絶縁膜５Ｂの２層
構造とし、データ信号ライン４と補助走査信号ライン２
１とをその間に介在された上層絶縁膜５Ｂによって互い
に絶縁しているので、データ信号ライン４と補助走査信
号ライン２１とを互いに交差させても短絡することはな
い。したがって、図１０に示すように、データ信号ライ
ン４の下端側と補助走査信号ライン２１の下端側とを互
いに交差するように配置することができる。一方、図６
〜図８に示す第３実施形態の場合には、上述したよう
に、絶縁膜５下に第１補助走査信号ライン２１Ａを設
け、データ信号ライン４と第１補助走査信号ライン２１
Ａとをその間に介在された絶縁膜５によって互いに絶縁
しているので、データ信号ライン４と第１補助走査信号
ライン２１Ａとを互いに交差させても短絡することはな
い。したがって、この場合も、データ信号ライン４の下
端側と第１補助走査信号ライン２１Ａの下端側とを互い
に交差するように配置することができる。To explain the fifth embodiment, first, in the case of the second embodiment shown in FIGS. 3 to 5, as described above, the insulating film 5 is formed of the lower insulating film 5A and the upper insulating film 5B. The data signal line 4 and the auxiliary scanning signal line 2 have a two-layer structure.
1 are insulated from each other by the upper insulating film 5B interposed therebetween, so that even if the data signal line 4 and the auxiliary scanning signal line 21 cross each other, no short circuit occurs. Therefore, as shown in FIG. 10, the lower end of the data signal line 4 and the lower end of the auxiliary scanning signal line 21 can be arranged so as to intersect each other. On the other hand, FIG.
8, the first auxiliary scanning signal line 21A is provided under the insulating film 5, and the data signal line 4 and the first auxiliary scanning signal line 21 are provided as described above.
A are insulated from each other by the insulating film 5 interposed therebetween, so that even if the data signal line 4 and the first auxiliary scanning signal line 21A cross each other, no short circuit occurs. Therefore, also in this case, the lower end of the data signal line 4 and the lower end of the first auxiliary scanning signal line 21A can be arranged so as to intersect each other.
【００１６】ところで、図１０に示す半導体チップ搭載
領域９においては、上辺部に出力側接続端子１０を設
け、右辺部に入力側接続端子１２を設けており、図１３
に示す従来の場合と同じ配列である。ただし、図示の都
合上、半導体チップ搭載領域９のサイズを異ならせてい
るが、実際は同じである。したがって、図１０に示す半
導体チップ搭載領域９上に、図１３に示す従来の場合と
同じ半導体チップを搭載することができる。また、図１
０に示す半導体チップ搭載領域７においては、上辺部に
出力側接続端子８を設け、左辺部に入力側接続端子１１
を設けており、図１３に示す従来の場合の半導体チップ
搭載領域７を時計方向に９０°回転させると、同じ配列
となる。ただし、この場合も、図示の都合上、半導体チ
ップ搭載領域７のサイズを異ならせているが、実際は同
じである。したがって、この場合も、図１０に示す半導
体チップ搭載領域７上に、図１３に示す従来の場合と同
じ半導体チップを搭載することができる。なお、図１０
において、２つの半導体チップ搭載領域７、９上に１つ
の半導体チップを搭載するようにしてもよい。この場
合、例えば図９に示すように、２種類の入力側接続端子
１１、１２を右側に集めてもよい。In the semiconductor chip mounting area 9 shown in FIG. 10, an output-side connection terminal 10 is provided on the upper side, and an input-side connection terminal 12 is provided on the right side.
This is the same arrangement as the conventional case shown in FIG. However, for convenience of illustration, the size of the semiconductor chip mounting area 9 is different, but it is actually the same. Therefore, the same semiconductor chip as the conventional case shown in FIG. 13 can be mounted on the semiconductor chip mounting area 9 shown in FIG. FIG.
In the semiconductor chip mounting area 7 shown in FIG. 0, the output side connection terminal 8 is provided on the upper side, and the input side connection terminal 11
When the conventional semiconductor chip mounting area 7 shown in FIG. 13 is rotated clockwise by 90 °, the same arrangement is obtained. However, also in this case, the size of the semiconductor chip mounting area 7 is different for the sake of illustration, but the size is actually the same. Therefore, also in this case, the same semiconductor chip as the conventional case shown in FIG. 13 can be mounted on the semiconductor chip mounting area 7 shown in FIG. Note that FIG.
In the above, one semiconductor chip may be mounted on the two semiconductor chip mounting areas 7 and 9. In this case, for example, as shown in FIG. 9, two types of input side connection terminals 11 and 12 may be collected on the right side.
【００１７】次に、図１１はこの発明の第６実施形態に
おける液晶表示装置の要部の等価回路的平面図を示した
ものである。この図において、図１と同一名称部分には
同一の符合を付し、その説明を適宜省略する。この液晶
表示装置でも、下側基板１の図１１における下辺部のみ
が上側基板２から突出され、端子配列領域を形成する突
出部１ｂとなっている。そして、データ信号ライン４の
下端部及び補助走査信号ライン２１の下端部は、下側基
板１の突出部１ｂ上の下辺部の中央部に設けられた外部
接続端子３１、３２に接続されている。この場合、外部
接続端子３１、３２は、基本的には、交互に配列されて
いる。FIG. 11 is a plan view showing an equivalent circuit of a main part of a liquid crystal display device according to a sixth embodiment of the present invention. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. Also in this liquid crystal display device, only the lower side portion of the lower substrate 1 in FIG. 11 protrudes from the upper substrate 2 to form a protruding portion 1b that forms a terminal array region. The lower end of the data signal line 4 and the lower end of the auxiliary scanning signal line 21 are connected to external connection terminals 31 and 32 provided at the center of the lower side on the protruding portion 1b of the lower substrate 1. . In this case, the external connection terminals 31 and 32 are basically arranged alternately.
【００１８】このように、この液晶表示装置では、下側
基板１の図１１における下辺部のみを上側基板２から突
出させ、この突出部１ｂ上に２種類の外部接続端子３
１、３２を設けているので、下側基板１の２辺部を上側
基板２から突出させる場合と比較して、下側基板１のサ
イズを小さくすることができ、ひいては額縁の幅を小さ
くすることができる。As described above, in this liquid crystal display device, only the lower side of the lower substrate 1 in FIG. 11 is projected from the upper substrate 2, and two types of external connection terminals 3 are provided on the projected portion 1b.
Since the lower substrate 1 and the lower substrate 1 are provided, the size of the lower substrate 1 can be reduced as compared with the case where two sides of the lower substrate 1 protrude from the upper substrate 2, and the width of the frame can be reduced. be able to.
【００１９】次に、図１２は図１１に示す液晶表示装置
に接合するフレキシブル配線基板の一例の平面図を示し
たものである。このフレキシブル配線基板４１はフィル
ム基板４２を備えている。フィルム基板４２の一端部の
下面には、図１１に示す外部接続端子３１、３２の配列
に応じて、出力側接続端子４３、４４が設けられてい
る。フィルム基板４２の下面及び上面の各所定の箇所に
は半導体チップ４５、４６が搭載されている。フィルム
基板４２の他端部に形成されたアウタリードホール４７
の部分の下面及び上面の各所定の箇所には入力側接続端
子４８、４９が架け渡されて設けられている。出力側接
続端子４３と半導体チップ４５とは、フィルム基板４２
の下面に設けられた引き回し線５０を介して接続されて
いる。出力側接続端子４４と半導体チップ４６とは、フ
ィルム基板４２の下面に設けられた引き回し線５１、フ
ィルム基板４２の所定の箇所に設けられたスルーホール
導通部５２、フィルム基板４２の上面に設けられた引き
回し線５３を介して接続されている。半導体チップ４５
と入力側接続端子４８とは、フィルム基板４２の下面に
設けられた引き回し線５４を介して接続されている。半
導体チップ４６と入力側接続端子４９とは、フィルム基
板４２の上面に設けられた引き回し線５５を介して接続
されている。Next, FIG. 12 is a plan view showing an example of a flexible wiring board to be joined to the liquid crystal display device shown in FIG. This flexible wiring board 41 includes a film board 42. Output-side connection terminals 43 and 44 are provided on the lower surface of one end of the film substrate 42 in accordance with the arrangement of the external connection terminals 31 and 32 shown in FIG. Semiconductor chips 45 and 46 are mounted on predetermined positions on the lower surface and the upper surface of the film substrate 42, respectively. Outer lead hole 47 formed at the other end of film substrate 42
Input-side connection terminals 48 and 49 are provided so as to extend over predetermined portions of the lower surface and the upper surface of the portion. The output side connection terminal 43 and the semiconductor chip 45 are
Are connected via a routing wire 50 provided on the lower surface of the. The output-side connection terminal 44 and the semiconductor chip 46 are provided on a wiring line 51 provided on the lower surface of the film substrate 42, a through-hole conducting portion 52 provided on a predetermined portion of the film substrate 42, and on the upper surface of the film substrate 42. It is connected via a leading line 53. Semiconductor chip 45
The input side connection terminal 48 is connected to the input side connection terminal 48 via a lead wire 54 provided on the lower surface of the film substrate 42. The semiconductor chip 46 and the input-side connection terminal 49 are connected via a wiring 55 provided on the upper surface of the film substrate 42.
【００２０】そして、フレキシブル配線基板４１の一端
部下面つまり出力側接続端子４３、４４の部分は、図１
１に示す液晶表示パネルの下側基板１の突出部１ｂの外
部接続端子３１、３２の部分に図示しない異方導電性接
着剤を介して接合される。また、フレキシブル配線基板
４１の他端部つまり入力側接続端子４８、４９の部分
は、図示しない回路基板に半田等を介して接合される。
このように、１つのフレキシブル配線基板４１を介し
て、液晶表示パネルと回路基板とを電気的に接続するこ
とができるので、フレキシブル配線基板４１と液晶表示
パネルとの接合及びフレキシブル配線基板４１と回路基
板との接合は共に１回で済むことになる。The lower surface of one end portion of the flexible wiring board 41, that is, the portion of the output-side connection terminals 43 and 44 is shown in FIG.
1 are connected to the external connection terminals 31 and 32 of the projecting portion 1b of the lower substrate 1 of the liquid crystal display panel 1 via an anisotropic conductive adhesive (not shown). The other end of the flexible wiring board 41, that is, the input connection terminals 48 and 49 are joined to a circuit board (not shown) via solder or the like.
As described above, since the liquid crystal display panel and the circuit board can be electrically connected via one flexible wiring board 41, the connection between the flexible wiring board 41 and the liquid crystal display panel and the connection between the flexible wiring board 41 and the circuit board can be performed. The bonding with the substrate only needs to be performed once.
【００２１】なお、上記第６実施形態では、補助走査信
号ライン２１の部分を図１に示す第１実施形態の場合と
同じとした場合について説明したが、これに限らず、図
３〜図５に示す第２実施形態の場合と同じとしてもよ
く、また図６〜図８に示す第３実施形態の場合と同じと
してもよく、さらに図１０に示す第５実施形態の場合と
同じとしてもよいことはもちろんである。In the sixth embodiment, the case where the portion of the auxiliary scanning signal line 21 is the same as that of the first embodiment shown in FIG. 1 has been described. However, the present invention is not limited to this, and FIGS. May be the same as the case of the second embodiment shown in FIG. 6, may be the same as the case of the third embodiment shown in FIGS. 6 to 8, and may be the same as the case of the fifth embodiment shown in FIG. Of course.
【００２２】また、上記各実施形態では、下側基板１の
下辺部のみを上側基板２から突出させ、この突出部１ｂ
上に端子配列領域を設けた場合について説明したが、こ
れに限らず、下側基板１の右辺部のみを上側基板２から
突出させ、この突出部上に端子配列領域を設けるように
してもよい。例えば、図１を参照して説明すると、下側
基板１の上面に補助データ信号ラインを走査信号ライン
３と平行に設け、補助データ信号ラインの左端部を対応
するデータ信号ライン４に接続し、補助データ信号ライ
ンの右端部及び走査信号ライン３の右端部を下側基板１
の右辺突出部上の端子配列領域に設けられた２種類の出
力側接続端子に接続するようにしてもよい。また、図３
を参照して説明すると、絶縁膜を上層と下層の２層構造
とし、上層絶縁膜の上面にデータ信号ライン４を設け、
下層絶縁膜の上面に補助データ信号ラインを走査信号ラ
イン３と平行に設け、補助データ信号ラインの左端部を
対応するデータ信号ライン４に接続し、補助データ信号
ラインの右端部及び走査信号ライン３の右端部を下側基
板１の右辺突出部上の端子配列領域に設けられた２種類
の出力側接続端子に接続するようにしてもよい。また、
図６を参照して説明すると、絶縁膜の上面に第１補助デ
ータ信号ラインを、データ信号ライン４と直交させて、
且つ、対応するデータ信号ライン４に直接接続するとと
もに、対応しないデータ信号ライン４とは分離させて設
け、走査信号ライン３と同一面に第２補助データ信号ラ
インを設けて各第１補助データ信号ラインの分離された
領域を橋渡しし、第１補助データ信号ラインの右端部及
び走査信号ライン３の右端部を下側基板１の右辺突出部
上の端子配列領域に設けられた２種類の出力側接続端子
に接続するようにしてもよい。さらに、上記第４〜第６
実施形態の場合と同様にすることもできる。加えて、こ
の発明は、液晶表示装置に限らず、エレクトロルミネセ
ンス表示装置等の他の表示装置にも適用することができ
る。In each of the above embodiments, only the lower side of the lower substrate 1 is protruded from the upper substrate 2, and the protruding portion 1b
Although the case where the terminal array region is provided above has been described, the present invention is not limited to this, and only the right side portion of the lower substrate 1 may protrude from the upper substrate 2 and the terminal array region may be provided on this protruding portion. . For example, referring to FIG. 1, an auxiliary data signal line is provided on the upper surface of the lower substrate 1 in parallel with the scanning signal line 3, and the left end of the auxiliary data signal line is connected to the corresponding data signal line 4. The right end of the auxiliary data signal line and the right end of the scanning signal line 3 are connected to the lower substrate 1
May be connected to two types of output-side connection terminals provided in the terminal array area on the right-side protruding part of the above. FIG.
In the description, the insulating film has a two-layer structure of an upper layer and a lower layer, and the data signal line 4 is provided on the upper surface of the upper insulating film.
An auxiliary data signal line is provided on the upper surface of the lower insulating film in parallel with the scanning signal line 3. The left end of the auxiliary data signal line is connected to the corresponding data signal line 4, and the right end of the auxiliary data signal line and the scanning signal line 3 are connected. May be connected to two types of output-side connection terminals provided in a terminal array region on the right-side protruding portion of the lower substrate 1. Also,
Referring to FIG. 6, the first auxiliary data signal line is formed on the upper surface of the insulating film so as to be orthogonal to the data signal line 4.
Each of the first auxiliary data signals is connected directly to the corresponding data signal line 4 and provided separately from the non-corresponding data signal line 4, and provided with the second auxiliary data signal line on the same surface as the scanning signal line 3. The right and left ends of the first auxiliary data signal line and the scanning signal line 3 are bridged in the separated areas of the lines, and two types of output sides provided in the terminal array area on the right side protrusion of the lower substrate 1 You may make it connect to a connection terminal. Further, the above fourth to sixth embodiments
The same can be applied to the case of the embodiment. In addition, the present invention can be applied not only to the liquid crystal display device but also to other display devices such as an electroluminescence display device.
【００２３】[0023]
【発明の効果】以上説明したように、この発明によれ
ば、基板の表示領域の一辺側に両ラインの接続端子が配
列された端子配列領域を設けているので、基板の表示領
域の二辺側に端子配列領域を設ける場合と比較して、基
板のサイズを小さくすることができ、ひいては額縁の幅
を小さくすることができる。As described above, according to the present invention, a terminal array area in which connection terminals of both lines are arranged on one side of the display area of the substrate is provided, so that two sides of the display area of the substrate are provided. Compared with the case where the terminal array region is provided on the side, the size of the substrate can be reduced, and the width of the frame can be reduced.
【図１】この発明の第１実施形態における液晶表示装置
の要部の等価回路的平面図。FIG. 1 is an equivalent circuit plan view of a main part of a liquid crystal display device according to a first embodiment of the present invention.
【図２】図１のＣ−Ｃ線に沿う断面図。FIG. 2 is a sectional view taken along line CC of FIG. 1;
【図３】この発明の第２実施形態における液晶表示装置
の要部の等価回路的平面図。FIG. 3 is an equivalent circuit plan view of a main part of a liquid crystal display device according to a second embodiment of the present invention.
【図４】（Ａ）は図３の一部の平面図、（Ｂ）は図
（Ａ）中のデータ信号ライン及び上層絶縁膜を取り除い
た状態の平面図。4 (A) is a plan view of a part of FIG. 3, and FIG. 4 (B) is a plan view of a state where a data signal line and an upper insulating film in FIG. 3 (A) are removed.
【図５】図４（Ａ）のＤ−Ｄ線に沿う断面図。FIG. 5 is a sectional view taken along line DD in FIG.
【図６】この発明の第３実施形態における液晶表示装置
の要部の等価回路的平面図。FIG. 6 is an equivalent circuit plan view of a main part of a liquid crystal display device according to a third embodiment of the present invention.
【図７】（Ａ）は図６の一部の平面図、（Ｂ）は図
（Ａ）中のデータ信号ライン及び第２補助走査信号ライ
ンを取り除いた状態の平面図。FIG. 7A is a plan view of a part of FIG. 6, and FIG. 7B is a plan view of a state where a data signal line and a second auxiliary scanning signal line in FIG.
【図８】図７（Ａ）のＥ−Ｅ線に沿う断面図。FIG. 8 is a sectional view taken along line EE in FIG.
【図９】この発明の第４実施形態における液晶表示装置
の要部の等価回路的平面図。FIG. 9 is an equivalent circuit plan view of a main part of a liquid crystal display device according to a fourth embodiment of the present invention.
【図１０】この発明の第５実施形態における液晶表示装
置の要部の等価回路的平面図。FIG. 10 is an equivalent circuit plan view of a main part of a liquid crystal display device according to a fifth embodiment of the present invention.
【図１１】この発明の第６実施形態における液晶表示装
置の要部の等価回路的平面図。FIG. 11 is an equivalent circuit plan view of a main part of a liquid crystal display device according to a sixth embodiment of the present invention.
【図１２】図１１に示す液晶表示装置に接合するフレキ
シブル配線基板の一例の平面図。FIG. 12 is a plan view of an example of a flexible wiring board bonded to the liquid crystal display device shown in FIG.
【図１３】従来の液晶表示装置の一例の一部の等価回路
的平面図。FIG. 13 is an equivalent circuit plan view of a part of an example of a conventional liquid crystal display device.
【図１４】図１３のＦ−Ｆ線に沿う一部の断面図。FIG. 14 is a partial cross-sectional view along the line FF in FIG. 13;
１ 下側基板 １ｂ 突出部 ２ 上側基板 ３ 走査信号ライン ４ データ信号ライン ５ 絶縁膜 ５Ａ 下層絶縁膜 ５Ｂ 上層絶縁膜 ６ 薄膜トランジスタ ７、９ 半導体チップ搭載領域 ８、１０ 出力側接続端子 １１、１２ 入力側接続端子 １３、１４ 外部接続端子 ２１ 補助走査信号ライン ２１Ａ 第１補助走査信号ライン ２１Ｂ 第２補助走査信号ライン DESCRIPTION OF SYMBOLS 1 Lower substrate 1b Projection 2 Upper substrate 3 Scan signal line 4 Data signal line 5 Insulating film 5A Lower insulating film 5B Upper insulating film 6 Thin film transistor 7, 9 Semiconductor chip mounting area 8, 10 Output connection terminal 11, 12 Input side Connection terminals 13, 14 External connection terminals 21 Auxiliary scanning signal line 21A First auxiliary scanning signal line 21B Second auxiliary scanning signal line
Claims (10)
ラインとがその間に絶縁膜が介在された状態で互いに直
交して設けられ、前記両ラインに接続されたスイッチン
グ素子及び該スイッチング素子によって駆動される表示
要素がマトリクス状に配列された表示領域を有する表示
装置において、前記基板の表示領域の一辺側に前記両ラ
インの接続端子が配列された端子配列領域を設けたこと
を特徴とする表示装置。1. A plurality of lower lines and a plurality of upper lines are provided on a substrate so as to be orthogonal to each other with an insulating film interposed therebetween, and a switching element connected to the two lines and a switching element In a display device having a display area in which driven display elements are arranged in a matrix, a terminal array area in which connection terminals of the two lines are arranged is provided on one side of the display area of the substrate. Display device.
膜上に前記上部ラインと平行に形成され、前記下部ライ
ンのいずれかに接続された複数の補助ラインを設け、前
記補助ライン及び前記上部ラインの接続端子を前記端子
配列領域に設けたことを特徴とする表示装置。2. The invention according to claim 1, further comprising a plurality of auxiliary lines formed on said insulating film in parallel with said upper line and connected to one of said lower lines, wherein said auxiliary line and said upper line are provided. A display device comprising a line connection terminal provided in the terminal arrangement region.
ラインと同一面に前記下部ラインと平行に形成され、前
記上部ラインのいずれかに接続された複数の補助ライン
を設け、前記補助ライン及び前記下部ラインの接続端子
を前記端子配列領域に設けたことを特徴とする表示装
置。3. The invention according to claim 1, further comprising a plurality of auxiliary lines formed on the same plane as the lower line and parallel to the lower line and connected to any one of the upper lines. A display device, wherein a connection terminal of the lower line is provided in the terminal arrangement region.
膜を上層と下層の層構造とし、上層絶縁膜上に前記上部
ラインを設け、下層絶縁膜上に複数の補助ラインを設
け、前記各補助ラインを前記下部ラインのいずれかに接
続し、前記補助ライン及び前記上部ラインの接続端子を
前記端子配列領域に設けたことを特徴とする表示装置。4. The invention according to claim 1, wherein the insulating film has an upper layer structure and a lower layer structure, wherein the upper line is provided on the upper insulating film, and a plurality of auxiliary lines are provided on the lower insulating film. A display device, wherein an auxiliary line is connected to one of the lower lines, and connection terminals for the auxiliary line and the upper line are provided in the terminal arrangement region.
膜を上層と下層の層構造とし、上層絶縁膜上に前記上部
ラインを設け、下層絶縁膜上に複数の補助ラインを設
け、前記各補助ラインを前記上部ラインのいずれかに接
続し、前記補助ライン及び前記下部ラインの接続端子を
前記端子配列領域に設けたことを特徴とする表示装置。5. The invention according to claim 1, wherein the insulating film has an upper layer structure and a lower layer structure, wherein the upper line is provided on the upper insulating film, and a plurality of auxiliary lines are provided on the lower insulating film. A display device, wherein an auxiliary line is connected to one of the upper lines, and connection terminals for the auxiliary line and the lower line are provided in the terminal arrangement region.
ラインと同一面に前記下部ラインと直交する方向に延出
され、前記下部ラインのいずれかと接続され残りのもの
とは分離された複数の第１補助ラインを設け、前記各第
１補助ラインの分離された領域を橋渡しする第２補助ラ
インを設け、前記上部ライン及び前記第１または第２補
助ラインの接続端子を前記端子配列領域に設けたことを
特徴とする表示装置。6. A method according to claim 1, wherein the plurality of lower lines extend on the same plane as the lower lines in a direction orthogonal to the lower lines, are connected to one of the lower lines, and are separated from the rest. A first auxiliary line is provided, a second auxiliary line bridging a separated area of each first auxiliary line is provided, and a connection terminal of the upper line and the first or second auxiliary line is provided in the terminal arrangement area. A display device, characterized in that:
膜上に前記上部ラインと直交する方向に延出され、前記
上部ラインのいずれかと接続され残りのものとは分離さ
れた複数の第１補助ラインを設け、前記各第１補助ライ
ンの分離された領域を橋渡しする第２補助ラインを設
け、前記下部ライン及び前記第１または第２補助ライン
の接続端子を前記端子配列領域に設けたことを特徴とす
る表示装置。7. The method according to claim 1, wherein the plurality of first lines extend on the insulating film in a direction orthogonal to the upper lines, are connected to any one of the upper lines, and are separated from the rest. An auxiliary line is provided, a second auxiliary line bridging the separated area of each of the first auxiliary lines is provided, and connection terminals of the lower line and the first or second auxiliary line are provided in the terminal arrangement area. A display device characterized by the above-mentioned.
おいて、前記各接続端子に接続され、前記下部ラインに
信号を供給する半導体チップ及び前記上部ラインに信号
を供給する半導体チップのすくなくとも一方を前記基板
の前記端子配列領域上に搭載したことを特徴とする表示
装置。8. The semiconductor device according to claim 1, wherein at least one of a semiconductor chip connected to each of said connection terminals and supplying a signal to said lower line and a semiconductor chip supplying a signal to said upper line is provided. A display device, wherein one is mounted on the terminal arrangement region of the substrate.
おいて、前記接続端子に接続され、前記下部ライン及び
前記上部ラインに信号を供給する半導体チップを前記基
板の前記端子配列領域上に搭載したことを特徴とする表
示装置。9. The semiconductor device according to claim 1, wherein a semiconductor chip connected to the connection terminal and supplying a signal to the lower line and the upper line is provided on the terminal array region of the substrate. A display device characterized by being mounted.
において、一面側に前記上部ライン及び前記下部ライン
の接続端子に接続される端子が形成されたフレキシブル
配線基板により駆動回路を接合したことを特徴とする表
示装置。10. The driving circuit according to claim 1, wherein the driving circuit is joined by a flexible wiring board having terminals connected to connection terminals of the upper line and the lower line on one surface side. A display device characterized by the above-mentioned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10122727A JPH11305681A (en) | 1998-04-17 | 1998-04-17 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10122727A JPH11305681A (en) | 1998-04-17 | 1998-04-17 | Display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11305681A true JPH11305681A (en) | 1999-11-05 |
Family
ID=14843100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10122727A Abandoned JPH11305681A (en) | 1998-04-17 | 1998-04-17 | Display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11305681A (en) |
Cited By (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001356359A (en) * | 2000-06-13 | 2001-12-26 | Citizen Watch Co Ltd | Liquid crystal display device |
| EP1194810A1 (en) * | 2000-01-21 | 2002-04-10 | Rainbow Displays, Inc. | Construction of large, robust, monolithic and monolithic-like, amlcd displays with wide view angle |
| WO2002063387A1 (en) * | 2001-02-08 | 2002-08-15 | Koninklijke Philips Electronics N.V. | Display device |
| WO2002063385A1 (en) * | 2001-02-08 | 2002-08-15 | Koninklijke Philips Electronics N.V. | Method of manufacturing display cells |
| EP1242848A1 (en) * | 2000-08-28 | 2002-09-25 | Rainbow Displays, Inc. | Construction of large, robust, monolithic and monolithic-like, amlcd displays with wide view angle |
| JP2003058075A (en) * | 2001-08-08 | 2003-02-28 | Semiconductor Energy Lab Co Ltd | Display device |
| WO2002061723A3 (en) * | 2001-02-02 | 2004-02-05 | Koninkl Philips Electronics Nv | Display device |
| WO2004063803A1 (en) * | 2003-01-15 | 2004-07-29 | Philips Intellectual Property & Standards Gmbh | Device comprising an array of electronic elements, based on diagonal line routing |
| KR100449437B1 (en) * | 2000-07-28 | 2004-09-21 | 샤프 가부시키가이샤 | Image display device |
| KR100469505B1 (en) * | 2001-12-29 | 2005-02-02 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display device and method for reparing thereof |
| KR100473614B1 (en) * | 2001-04-19 | 2005-03-08 | 세이코 엡슨 가부시키가이샤 | Electrode driving apparatus and electronic equipment |
| JP2005276029A (en) * | 2004-03-26 | 2005-10-06 | Casio Comput Co Ltd | Reader |
| KR100534673B1 (en) * | 2001-04-19 | 2005-12-07 | 세이코 엡슨 가부시키가이샤 | Electrode driving apparatus and electronic equipment |
| WO2005121881A1 (en) * | 2004-06-09 | 2005-12-22 | Koninklijke Philips Electronics N.V. | Non-rectangular display device |
| KR100604299B1 (en) * | 2001-10-02 | 2006-07-28 | 가부시키가이샤 히타치세이사쿠쇼 | Liquid crystal display device |
| KR100914782B1 (en) * | 2002-12-20 | 2009-08-31 | 엘지디스플레이 주식회사 | Substrate of thin film transistor and liquid crystal display using the same |
| US20100171687A1 (en) * | 2009-01-08 | 2010-07-08 | Yi-Chen Chiang | Display device having slim border-area architecture and driving method thereof |
| JP2010160279A (en) * | 2009-01-07 | 2010-07-22 | Toshiba Mobile Display Co Ltd | Liquid crystal display device |
| US20100315317A1 (en) * | 2009-06-12 | 2010-12-16 | Chung-Lung Li | Display device |
| CN102385199A (en) * | 2010-09-03 | 2012-03-21 | 东莞万士达液晶显示器有限公司 | Liquid crystal display panel and production method thereof |
| CN102981330A (en) * | 2012-09-10 | 2013-03-20 | 友达光电股份有限公司 | Display panel |
| TWI393946B (en) * | 2009-05-21 | 2013-04-21 | Au Optronics Corp | Display device |
| TWI397756B (en) * | 2009-05-22 | 2013-06-01 | Au Optronics Corp | Active array substrate, liquid crystal display panel and method for manufacturing the same |
| US20130229400A1 (en) * | 2012-03-05 | 2013-09-05 | Samsung Display Co., Ltd. | Thin film transistor display panel and manufacturing method thereof |
| JP2013210666A (en) * | 2013-05-31 | 2013-10-10 | Japan Display Inc | Liquid crystal display device |
| WO2013161685A1 (en) * | 2012-04-27 | 2013-10-31 | シャープ株式会社 | Display device |
| KR20140047321A (en) * | 2012-10-12 | 2014-04-22 | 엘지디스플레이 주식회사 | Display device |
| CN103869564A (en) * | 2012-12-13 | 2014-06-18 | 乐金显示有限公司 | Liquid crystal display device |
| CN103869568A (en) * | 2012-12-14 | 2014-06-18 | 乐金显示有限公司 | Array substrate for narrow bezel type liquid crystal display device and method of manufacturing the same |
| WO2015015925A1 (en) * | 2013-07-30 | 2015-02-05 | シャープ株式会社 | Display device |
| WO2015052187A1 (en) * | 2013-10-08 | 2015-04-16 | Plastic Logic Limited | Transistor array routing |
| WO2015092945A1 (en) * | 2013-12-20 | 2015-06-25 | パナソニック液晶ディスプレイ株式会社 | Display device |
| KR20150078593A (en) * | 2013-12-31 | 2015-07-08 | 엘지디스플레이 주식회사 | Thin film transistor substrate and Liquid crystal display device using the same |
| JP5940679B2 (en) * | 2012-11-16 | 2016-06-29 | シャープ株式会社 | Drive module, display device, and multi-display device |
| TWI560506B (en) * | 2015-09-25 | 2016-12-01 | Au Optronics Corp | Display panel |
| CN106504689A (en) * | 2016-11-08 | 2017-03-15 | 深圳市华星光电技术有限公司 | Display driver circuit and display floater |
| WO2017119338A1 (en) * | 2016-01-04 | 2017-07-13 | シャープ株式会社 | Display device |
| JP2017531816A (en) * | 2014-10-01 | 2017-10-26 | アップル インコーポレイテッド | Display with vertical gate line extension and minimized frame |
| JP2018022116A (en) * | 2016-08-05 | 2018-02-08 | Ｔｉａｎｍａ Ｊａｐａｎ株式会社 | Display device |
| CN108563081A (en) * | 2018-02-09 | 2018-09-21 | 友达光电股份有限公司 | Display panel |
| CN109387965A (en) * | 2017-08-03 | 2019-02-26 | 中华映管股份有限公司 | Image element array substrates |
| CN111752059A (en) * | 2019-08-20 | 2020-10-09 | 友达光电股份有限公司 | Display panel |
| EP3761111A1 (en) * | 2019-07-03 | 2021-01-06 | Samsung Display Co., Ltd. | Display device |
| WO2021031857A1 (en) * | 2019-08-20 | 2021-02-25 | 友达光电股份有限公司 | Display device |
| WO2021031836A1 (en) * | 2019-08-20 | 2021-02-25 | 友达光电股份有限公司 | Pixel array substrate |
| TWI722890B (en) * | 2019-09-18 | 2021-03-21 | 友達光電股份有限公司 | Pixel arraay substrate |
| US11150525B2 (en) | 2017-03-17 | 2021-10-19 | Sharp Kabushiki Kaisha | Active matrix substrate and display panel |
| US11500237B2 (en) | 2020-11-09 | 2022-11-15 | Sharp Kabushiki Kaisha | Array substrate and display device |
-
1998
- 1998-04-17 JP JP10122727A patent/JPH11305681A/en not_active Abandoned
Cited By (76)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1194810A1 (en) * | 2000-01-21 | 2002-04-10 | Rainbow Displays, Inc. | Construction of large, robust, monolithic and monolithic-like, amlcd displays with wide view angle |
| EP1194810A4 (en) * | 2000-01-21 | 2008-07-30 | Rainbow Displays Inc | Construction of large, robust, monolithic and monolithic-like, amlcd displays with wide view angle |
| JP2001356359A (en) * | 2000-06-13 | 2001-12-26 | Citizen Watch Co Ltd | Liquid crystal display device |
| KR100449437B1 (en) * | 2000-07-28 | 2004-09-21 | 샤프 가부시키가이샤 | Image display device |
| EP1242848A4 (en) * | 2000-08-28 | 2005-03-30 | Rainbow Displays Inc | Construction of large, robust, monolithic and monolithic-like, amlcd displays with wide view angle |
| EP1242848A1 (en) * | 2000-08-28 | 2002-09-25 | Rainbow Displays, Inc. | Construction of large, robust, monolithic and monolithic-like, amlcd displays with wide view angle |
| JP2004507795A (en) * | 2000-08-28 | 2004-03-11 | レインボー ディスプレイズ，インコーポレイティド | Large, rugged monolithic and monolithic-like AMLCD display with wide viewing angle |
| WO2002061723A3 (en) * | 2001-02-02 | 2004-02-05 | Koninkl Philips Electronics Nv | Display device |
| WO2002063387A1 (en) * | 2001-02-08 | 2002-08-15 | Koninklijke Philips Electronics N.V. | Display device |
| WO2002063385A1 (en) * | 2001-02-08 | 2002-08-15 | Koninklijke Philips Electronics N.V. | Method of manufacturing display cells |
| KR100534673B1 (en) * | 2001-04-19 | 2005-12-07 | 세이코 엡슨 가부시키가이샤 | Electrode driving apparatus and electronic equipment |
| KR100473614B1 (en) * | 2001-04-19 | 2005-03-08 | 세이코 엡슨 가부시키가이샤 | Electrode driving apparatus and electronic equipment |
| JP2003058075A (en) * | 2001-08-08 | 2003-02-28 | Semiconductor Energy Lab Co Ltd | Display device |
| US9972670B2 (en) | 2001-08-08 | 2018-05-15 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US9105594B2 (en) | 2001-08-08 | 2015-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| KR100604299B1 (en) * | 2001-10-02 | 2006-07-28 | 가부시키가이샤 히타치세이사쿠쇼 | Liquid crystal display device |
| KR100469505B1 (en) * | 2001-12-29 | 2005-02-02 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display device and method for reparing thereof |
| KR100914782B1 (en) * | 2002-12-20 | 2009-08-31 | 엘지디스플레이 주식회사 | Substrate of thin film transistor and liquid crystal display using the same |
| WO2004063803A1 (en) * | 2003-01-15 | 2004-07-29 | Philips Intellectual Property & Standards Gmbh | Device comprising an array of electronic elements, based on diagonal line routing |
| JP2005276029A (en) * | 2004-03-26 | 2005-10-06 | Casio Comput Co Ltd | Reader |
| JP2008502023A (en) * | 2004-06-09 | 2008-01-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Non-rectangular display device |
| WO2005121881A1 (en) * | 2004-06-09 | 2005-12-22 | Koninklijke Philips Electronics N.V. | Non-rectangular display device |
| JP2010160279A (en) * | 2009-01-07 | 2010-07-22 | Toshiba Mobile Display Co Ltd | Liquid crystal display device |
| US20100171687A1 (en) * | 2009-01-08 | 2010-07-08 | Yi-Chen Chiang | Display device having slim border-area architecture and driving method thereof |
| TWI392943B (en) * | 2009-01-08 | 2013-04-11 | Au Optronics Corp | Display device having slim border-area architecture and driving method thereof |
| US8570480B2 (en) | 2009-01-08 | 2013-10-29 | Au Optronics Corp. | Display device having slim border-area architecture and driving method thereof |
| TWI393946B (en) * | 2009-05-21 | 2013-04-21 | Au Optronics Corp | Display device |
| US8427412B2 (en) | 2009-05-21 | 2013-04-23 | Au Optronics Corp. | Display device |
| TWI397756B (en) * | 2009-05-22 | 2013-06-01 | Au Optronics Corp | Active array substrate, liquid crystal display panel and method for manufacturing the same |
| US20100315317A1 (en) * | 2009-06-12 | 2010-12-16 | Chung-Lung Li | Display device |
| TWI393947B (en) * | 2009-06-12 | 2013-04-21 | Au Optronics Corp | Display device |
| US8723758B2 (en) * | 2009-06-12 | 2014-05-13 | Au Optronics Corp. | Display device having signal internal links |
| CN102385199A (en) * | 2010-09-03 | 2012-03-21 | 东莞万士达液晶显示器有限公司 | Liquid crystal display panel and production method thereof |
| US20130229400A1 (en) * | 2012-03-05 | 2013-09-05 | Samsung Display Co., Ltd. | Thin film transistor display panel and manufacturing method thereof |
| US9122324B2 (en) * | 2012-03-05 | 2015-09-01 | Samsung Display Co., Ltd. | Thin film transistor display panel and manufacturing method thereof |
| US9217888B2 (en) | 2012-04-27 | 2015-12-22 | Sharp Kabushiki Kaisha | Display device |
| WO2013161685A1 (en) * | 2012-04-27 | 2013-10-31 | シャープ株式会社 | Display device |
| CN102981330B (en) * | 2012-09-10 | 2015-06-17 | 友达光电股份有限公司 | Display panel |
| CN102981330A (en) * | 2012-09-10 | 2013-03-20 | 友达光电股份有限公司 | Display panel |
| KR20140047321A (en) * | 2012-10-12 | 2014-04-22 | 엘지디스플레이 주식회사 | Display device |
| JPWO2014077175A1 (en) * | 2012-11-16 | 2017-01-05 | シャープ株式会社 | Drive module, display device, and multi-display device |
| JP5940679B2 (en) * | 2012-11-16 | 2016-06-29 | シャープ株式会社 | Drive module, display device, and multi-display device |
| CN103869564B (en) * | 2012-12-13 | 2017-05-03 | 乐金显示有限公司 | Liquid crystal display device |
| CN103869564A (en) * | 2012-12-13 | 2014-06-18 | 乐金显示有限公司 | Liquid crystal display device |
| US9429780B2 (en) | 2012-12-13 | 2016-08-30 | Lg Display Co., Ltd. | Liquid crystal display device comprising a plurality of vertical and horizontal gate lines that directly contact a same upper surface of a same layer |
| CN103869568A (en) * | 2012-12-14 | 2014-06-18 | 乐金显示有限公司 | Array substrate for narrow bezel type liquid crystal display device and method of manufacturing the same |
| JP2013210666A (en) * | 2013-05-31 | 2013-10-10 | Japan Display Inc | Liquid crystal display device |
| WO2015015925A1 (en) * | 2013-07-30 | 2015-02-05 | シャープ株式会社 | Display device |
| RU2660318C2 (en) * | 2013-10-08 | 2018-07-05 | Флексенэбл Лимитед | Transistors matrix distribution |
| CN105659384A (en) * | 2013-10-08 | 2016-06-08 | 弗莱克因艾伯勒有限公司 | Transistor array routing |
| CN105659384B (en) * | 2013-10-08 | 2019-04-05 | 弗莱克因艾伯勒有限公司 | Transistor array column wiring |
| US9876034B2 (en) * | 2013-10-08 | 2018-01-23 | Flexenable Limited | Transistor array routing |
| US20160233237A1 (en) * | 2013-10-08 | 2016-08-11 | Flexenable Limited | Transistor array routing |
| WO2015052187A1 (en) * | 2013-10-08 | 2015-04-16 | Plastic Logic Limited | Transistor array routing |
| WO2015092945A1 (en) * | 2013-12-20 | 2015-06-25 | パナソニック液晶ディスプレイ株式会社 | Display device |
| KR20150078593A (en) * | 2013-12-31 | 2015-07-08 | 엘지디스플레이 주식회사 | Thin film transistor substrate and Liquid crystal display device using the same |
| US10210830B2 (en) | 2014-10-01 | 2019-02-19 | Apple Inc. | Display having vertical gate line extensions and minimized borders |
| JP2017531816A (en) * | 2014-10-01 | 2017-10-26 | アップル インコーポレイテッド | Display with vertical gate line extension and minimized frame |
| TWI560506B (en) * | 2015-09-25 | 2016-12-01 | Au Optronics Corp | Display panel |
| WO2017119338A1 (en) * | 2016-01-04 | 2017-07-13 | シャープ株式会社 | Display device |
| JP2018022116A (en) * | 2016-08-05 | 2018-02-08 | Ｔｉａｎｍａ Ｊａｐａｎ株式会社 | Display device |
| CN106504689A (en) * | 2016-11-08 | 2017-03-15 | 深圳市华星光电技术有限公司 | Display driver circuit and display floater |
| US11586080B2 (en) | 2017-03-17 | 2023-02-21 | Sharp Kabushiki Kaisha | Active matrix substrate and display panel |
| US11150525B2 (en) | 2017-03-17 | 2021-10-19 | Sharp Kabushiki Kaisha | Active matrix substrate and display panel |
| CN109387965A (en) * | 2017-08-03 | 2019-02-26 | 中华映管股份有限公司 | Image element array substrates |
| CN108563081B (en) * | 2018-02-09 | 2021-01-15 | 友达光电股份有限公司 | Display panel |
| US10424603B2 (en) | 2018-02-09 | 2019-09-24 | Au Optronics Corporation | Display panel |
| CN108563081A (en) * | 2018-02-09 | 2018-09-21 | 友达光电股份有限公司 | Display panel |
| EP3761111A1 (en) * | 2019-07-03 | 2021-01-06 | Samsung Display Co., Ltd. | Display device |
| US11152450B2 (en) | 2019-07-03 | 2021-10-19 | Samsung Display Co., Ltd. | Display device |
| CN111752059A (en) * | 2019-08-20 | 2020-10-09 | 友达光电股份有限公司 | Display panel |
| WO2021031857A1 (en) * | 2019-08-20 | 2021-02-25 | 友达光电股份有限公司 | Display device |
| WO2021031836A1 (en) * | 2019-08-20 | 2021-02-25 | 友达光电股份有限公司 | Pixel array substrate |
| CN111752059B (en) * | 2019-08-20 | 2022-10-28 | 友达光电股份有限公司 | Display panel |
| TWI722890B (en) * | 2019-09-18 | 2021-03-21 | 友達光電股份有限公司 | Pixel arraay substrate |
| US11500237B2 (en) | 2020-11-09 | 2022-11-15 | Sharp Kabushiki Kaisha | Array substrate and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH11305681A (en) | Display device | |
| CN111384066B (en) | Array substrate and display device | |
| JP2000171818A (en) | Liquid crystal display device | |
| KR100243914B1 (en) | The structure of tap-pad part and its manufacturing method of lcd panel | |
| JP3570165B2 (en) | Display device | |
| US5581382A (en) | Liquid crystal display device having connection pads insulated by double layered anodic oxide material | |
| JP3580207B2 (en) | Display device | |
| JP3648596B2 (en) | Semiconductor chip bonding structure and display device having the structure | |
| JP3254230B2 (en) | LCD Display Panel Wiring Structure | |
| JP3858135B2 (en) | Junction structure of semiconductor devices | |
| JP3747484B2 (en) | Film wiring board and connection structure thereof | |
| JP3649050B2 (en) | Junction structure of semiconductor devices | |
| JP3324535B2 (en) | Display panel | |
| JP3264103B2 (en) | Liquid crystal display | |
| JPH07254760A (en) | Connecting structure of substrate and ic unit | |
| JP3994637B2 (en) | Liquid crystal display | |
| JPH08338997A (en) | Liquid crystal display element | |
| JP2572134Y2 (en) | Substrate wiring structure | |
| JP2002236458A (en) | Mounting structure for display device | |
| JP2003007749A (en) | Integrated circuit and display | |
| JP2001215893A (en) | Display device | |
| JP3113669B2 (en) | Liquid crystal display | |
| JPH02259728A (en) | Liquid crystal display device | |
| JP2810571B2 (en) | Liquid crystal display | |
| JP2000310789A (en) | Display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050405 |
|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20060202 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20060222 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070629 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070821 |
|
| A762 | Written abandonment of application |
Free format text: JAPANESE INTERMEDIATE CODE: A762 Effective date: 20070920 |