JP3264103B2 - Liquid crystal display - Google Patents

Liquid crystal display

Info

Publication number
JP3264103B2
JP3264103B2 JP15821994A JP15821994A JP3264103B2 JP 3264103 B2 JP3264103 B2 JP 3264103B2 JP 15821994 A JP15821994 A JP 15821994A JP 15821994 A JP15821994 A JP 15821994A JP 3264103 B2 JP3264103 B2 JP 3264103B2
Authority
JP
Japan
Prior art keywords
input
semiconductor chip
side connection
connection
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP15821994A
Other languages
Japanese (ja)
Other versions
JPH086058A (en
Inventor
政光 岸上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP15821994A priority Critical patent/JP3264103B2/en
Publication of JPH086058A publication Critical patent/JPH086058A/en
Application granted granted Critical
Publication of JP3264103B2 publication Critical patent/JP3264103B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は液晶表示装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display.

【0002】[0002]

【従来の技術】図4(A)は従来の液晶表示装置の一例
を示したものであり、図4(B)はその配線構造を示し
たものである。この液晶表示装置では、液晶表示パネル
1、3つの半導体チップ2〜4、フレキシブル配線基板
5、図示しない制御回路用回路基板等を備えている。こ
のうち液晶表示パネル1は、相対向する面にそれぞれ図
示しない表示電極が設けられた2枚の透明基板6、7の
間に図示しない液晶が封入されたものからなっている。
下側の透明基板7の下辺および右辺は上側の透明基板6
のそれぞれ対応する下辺および右辺から突出されてい
る。下側の透明基板7の下辺側の突出部の上面には、鎖
線で示す2つの半導体チップ搭載エリア8、9が設けら
れ、半導体チップ搭載エリア8、9の各上端部にそれぞ
れ複数本の出力側接続用配線10、11が設けられ、半
導体チップ搭載エリア8、9の各下端部にそれぞれ複数
本の入力側接続用配線12、13が設けられている。出
力側接続用配線10、11の各一端部は下側の表示電極
の駆動素子に接続され、各他端部は半導体チップ搭載エ
リア8、9内に突出されている。入力側接続用配線1
2、13の各一端部は半導体チップ搭載エリア8、9内
に突出され、各他端部は下側の透明基板7の下端部に配
置されている。また、下側の透明基板7の右辺側の突出
部の上面には、鎖線で示す1つの半導体チップ搭載エリ
ア14が設けられ、半導体チップ搭載エリア14の左端
部に複数本の出力側接続用配線15が設けられ、半導体
チップ搭載エリア14の右端部に複数本の入力側接続用
配線16が設けられ、所定の箇所に1本のコモン電極側
接続用配線17が設けられている。出力側接続用配線1
5の各一端部は下側の表示電極の駆動素子に接続され、
各他端部は半導体チップ搭載エリア14内に突出されて
いる。入力側接続用配線16の各一端部は半導体チップ
搭載エリア14内に突出され、各他端部は下側の透明基
板7の右端部に配置されている。コモン電極側接続用配
線17の一端部はクロス材18を介して上側の表示電極
と接続され、他端部は下側の透明基板7の右端部に配置
されている。
2. Description of the Related Art FIG. 4A shows an example of a conventional liquid crystal display device, and FIG. 4B shows its wiring structure. This liquid crystal display device includes a liquid crystal display panel 1, three semiconductor chips 2 to 4, a flexible wiring board 5, a control circuit circuit board (not shown), and the like. The liquid crystal display panel 1 has a liquid crystal (not shown) sealed between two transparent substrates 6 and 7 provided with display electrodes (not shown) on opposing surfaces.
The lower and right sides of the lower transparent substrate 7 are the upper transparent substrate 6
Project from the corresponding lower and right sides. Two semiconductor chip mounting areas 8 and 9 indicated by chain lines are provided on the upper surface of the projecting portion on the lower side of the lower transparent substrate 7, and a plurality of output chips are provided at the upper end of each of the semiconductor chip mounting areas 8 and 9. Side connection wirings 10 and 11 are provided, and a plurality of input side connection wirings 12 and 13 are provided at the lower ends of the semiconductor chip mounting areas 8 and 9, respectively. One end of each of the output side connection wirings 10 and 11 is connected to the drive element of the lower display electrode, and the other end protrudes into the semiconductor chip mounting areas 8 and 9. Input side connection wiring 1
One end of each of 2 and 13 protrudes into the semiconductor chip mounting areas 8 and 9, and the other end is disposed at the lower end of the lower transparent substrate 7. One semiconductor chip mounting area 14 indicated by a dashed line is provided on the upper surface of the protruding portion on the right side of the lower transparent substrate 7, and a plurality of output side connection wirings are provided at the left end of the semiconductor chip mounting area 14. A plurality of input-side connection wires 16 are provided at the right end of the semiconductor chip mounting area 14, and one common electrode-side connection wire 17 is provided at a predetermined location. Output side connection wiring 1
5 is connected to the lower display electrode driving element,
Each other end protrudes into the semiconductor chip mounting area 14. One end of the input-side connection wiring 16 protrudes into the semiconductor chip mounting area 14, and the other end is disposed at the right end of the lower transparent substrate 7. One end of the common electrode side connection wiring 17 is connected to the upper display electrode via the cross member 18, and the other end is disposed on the right end of the lower transparent substrate 7.

【0003】半導体チップ2〜4の下面には、図5に示
すように、上辺のすぐ内側に複数の出力側接続電極(バ
ンプ電極)19が設けられ、下辺のすぐ内側に複数の入
力側接続電極(バンプ電極)20が設けられている。そ
して、このうち所定の2つの半導体チップ2、3は下側
の透明基板7の下辺側の突出部の上面の各半導体チップ
搭載エリア8、9にそれぞれ搭載されている。この場
合、各入力側接続電極20および各出力側接続電極19
が異方導電性接着剤等を介して各半導体チップ搭載エリ
ア8、9内の各入力側接続用配線12、13および各出
力側接続用配線10、11とそれぞれ導電接続されてい
る。また、同様にして、残りの1つの半導体チップ4は
下側の透明基板7の右辺側の突出部の上面の半導体チッ
プ搭載エリア14に搭載されている。
As shown in FIG. 5, a plurality of output-side connection electrodes (bump electrodes) 19 are provided on the lower surface of the semiconductor chips 2 to 4 immediately inside the upper side, and a plurality of input-side connection electrodes 19 are provided immediately inside the lower side. An electrode (bump electrode) 20 is provided. The predetermined two semiconductor chips 2 and 3 are mounted on the respective semiconductor chip mounting areas 8 and 9 on the upper surface of the protruding portion on the lower side of the lower transparent substrate 7. In this case, each input-side connection electrode 20 and each output-side connection electrode 19
Are electrically connected to the input side connection wirings 12 and 13 and the output side connection wirings 10 and 11 in the semiconductor chip mounting areas 8 and 9 via an anisotropic conductive adhesive or the like. Similarly, the remaining one semiconductor chip 4 is mounted on the semiconductor chip mounting area 14 on the upper surface of the protrusion on the right side of the lower transparent substrate 7.

【0004】フレキシブル配線基板5はほぼL字状であ
って、その一端側5aの下面には下側の透明基板7の下
辺側の突出部の上面に設けられた各入力側接続用配線1
2、13に対応する2組の接続用配線21、22が設け
られ、その他端側5bの下面には下側の透明基板7の右
辺側の突出部の上面に設けられた入力側接続用配線16
およびコモン電極側接続用配線17に対応する接続用配
線23、24が設けられた構造となっている。この場
合、フレキシブル配線基板5の一端側5aは、1群のス
ルーホール導通部25を介して接続用配線21が両面配
線され、別の1群のスルーホール導通部26を介して2
組の接続用配線21、22が共通配線として導電接続さ
れている。そして、フレキシブル配線基板5の一端側5
aの各接続用配線21、22および他端側5bの各接続
用配線23、24が異方導電性接着剤等の接続部材を介
して対応する各接続用配線12、13および各接続用配
線16、17と導電接続され、フレキシブル配線基板5
の所定の箇所が制御回路用回路基板の所定の箇所と導電
接続されている。
The flexible wiring board 5 is substantially L-shaped, and the input-side connection wiring 1 provided on the lower surface of the lower transparent substrate 7 on the upper surface of the lower transparent substrate 7 is provided on the lower surface of one end 5a.
Two sets of connection wirings 21 and 22 corresponding to 2 and 13 are provided, and an input-side connection wiring provided on the upper surface of the protruding portion on the right side of the lower transparent substrate 7 on the lower surface of the other end 5b. 16
Further, connection wirings 23 and 24 corresponding to the common electrode side connection wiring 17 are provided. In this case, on one end side 5a of the flexible wiring board 5, the connection wiring 21 is wired on both sides via a group of through-hole conducting portions 25, and is connected to another side via another group of through-hole conducting portions 26.
A pair of connection wires 21 and 22 are conductively connected as a common wire. Then, one end 5 of the flexible wiring board 5
The connection wirings 21 and 22 and the connection wirings 23 and 24 on the other end 5b correspond to the connection wirings 12 and 13 and the connection wirings via connection members such as an anisotropic conductive adhesive. 16 and 17 are conductively connected to the flexible wiring board 5
Are electrically connected to predetermined portions of the control circuit board.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
このような液晶表示装置では、接続用配線21〜24を
備えたほぼL字状のフレキシブル配線基板5を液晶表示
パネル1の各半導体チップ2〜4にそれぞれ導電接続し
ているので、フレキシブル配線基板5の占有面積が大き
くなって大型化するという問題があった。また、2つの
半導体チップ2、3に対する接続用配線21、22を共
通配線として導電接続する関係から、フレキシブル配線
基板5がスルーホール導通部25、26を介した両面配
線構造となるので、フレキシブル配線基板5の構造が複
雑でコスト高になるという問題があった。このようなこ
とは、半導体チップ2、3の数が多くなればなるほど、
顕著である。この発明の目的は、小型化することができ
るとともに、フレキシブル配線基板の構造を単純化する
ことができる液晶表示装置を提供することにある。
However, in such a conventional liquid crystal display device, a substantially L-shaped flexible wiring substrate 5 having connection wirings 21 to 24 is connected to each of the semiconductor chips 2 to 2 of the liquid crystal display panel 1. 4 are conductively connected to each other, so that the area occupied by the flexible wiring board 5 is increased, and there is a problem that the size is increased. In addition, since the connection wirings 21 and 22 for the two semiconductor chips 2 and 3 are conductively connected as a common wiring, the flexible wiring board 5 has a double-sided wiring structure via the through-hole conductive portions 25 and 26, so that the flexible wiring There is a problem that the structure of the substrate 5 is complicated and the cost is high. This is because as the number of semiconductor chips 2 and 3 increases,
Notable. An object of the present invention is to provide a liquid crystal display device that can be reduced in size and can simplify the structure of a flexible wiring board.

【0006】[0006]

【課題を解決するための手段】請求項1記載の発明は、
相対向する面に表示電極が形成された2枚の基板のうち
少なくとも一方の基板が他方の基板の少なくとも一辺か
ら突出されて突出部が形成され、この突出部の一面に前
記他方の基板の少なくとも一辺に沿って複数の半導体チ
ップ搭載エリアが設けられ、前記各半導体チップ搭載エ
リアに長方形状の半導体チップが搭載されてなる液晶表
示装置において、前記半導体チップに、該半導体チップ
の一長辺に沿って配列された複数の出力側接続電極と、
他の三辺に沿って配列された第1の入力側接続電極およ
び少なくとも相対応する一組からなる第2の入力側接続
電極と、少なくとも前記相対応する一組の第2の入力側
接続電極同士を相互に接続する配線を設け、 前記一方の
基板の突出部の一面に、前記表示電極の一つに接続され
且つ前記半導体チップの出力側接続電極に接続される出
力側接続配線と、前記各半導体チップ搭載エリアにわた
って連続して設けられ、前記第1の入力側電極を接続す
る第1の入力側接続配線および前記第2の入力側接続電
極を接続する第2の入力側接続配線を互いに交差させず
に、且つ、少なくとも前記第1の入力側接続配線は前記
半導体チップ搭載エリア内をその長手方向の全領域を通
過させて設け、前記第1の入力側接続用配線および前記
第2の入力側接続配線の各一端部を前記突出部の一面の
一箇所にまとめて配置したものである。請求項2記載の
発明は、前記第1の入力側接続電極を信号入力側電極と
し、前記第2の入力側接続電極を電源信号入力側電極と
したものである。
According to the first aspect of the present invention,
Phase protrusion least one of the substrates is projected from at least one side of the other substrate of the opposing two display electrodes formed on a surface substrate is formed, at least the other substrate on one surface of the projecting portion a plurality of semiconductor chip mounting areas provided along one side, in a liquid crystal display device rectangular semiconductor chips are mounted to the each semiconductor chip mounting area, on the semiconductor chip, the semiconductor chip
A plurality of output connection electrodes arranged along one long side of
A first input-side connection electrode arranged along the other three sides and
And at least one pair of corresponding second input connections
An electrode and at least a pair of corresponding second inputs
The wiring for connecting the connection electrodes are mutually disposed, the one
One surface of the protruding portion of the substrate is connected to one of the display electrodes.
And an output connected to an output-side connection electrode of the semiconductor chip.
Power connection wiring and the semiconductor chip mounting area
To connect the first input-side electrode.
A first input-side connection wiring and a second input-side connection
Do not cross the second input connection wires connecting the poles
And at least the first input side connection wiring is
The entire area in the longitudinal direction is passed through the semiconductor chip mounting area.
The first input-side connection wiring and the
One end of each of the second input-side connection wires is collectively arranged at one position on one surface of the protruding portion. According to a second aspect of the present invention, the first input connection electrode is defined as a signal input electrode.
And the second input connection electrode is connected to a power signal input electrode.
It was done.

【0007】[0007]

【作用】請求項1記載の発明によれば、突出部の一面
に、前記各半導体チップ搭載エリアにわたって連続して
設けられ、前記第1の入力側電極を接続する第1の入力
側接続配線および第2の入力側接続電極を接続する第2
の入力側接続配線を互いに交差させずに、且つ、少なく
とも前記第1の入力側接続配線は前記半導体チップ搭載
エリア内をその長手方向の全領域を通過させて設け、前
記第1の入力側接続用配線および前記第2の入力側接続
配線の各一端部を前記突出部の一面の一箇所にまとめて
配置したので、両面に接続用配線を備えたフレキシブル
配線基板を複数の半導体チップに導電接続する場合と比
較して、小型化することができフレキシブル配線基板
の構造を単純化することができるうえ、第1の入力側接
続配線は前記半導体チップ搭載エリア内をその長手方向
の全領域を通過させて設けたので、一方の基板の突出部
の幅を狭くすることができ、さらに、半導体チップの第
2の入力側接続電極を突出部の一面に設けた第2の入力
側接続配線と半導体チップ内の配線により接続したの
で、配線抵抗を低くすることができる。
According to the first aspect of the present invention, one surface of the protrusion is provided.
And continuously over the semiconductor chip mounting area.
A first input provided for connecting the first input-side electrode;
Connecting the second side connection wiring and the second input side connection electrode
Of the input side connection wires of
Both the first input side connection wiring is the semiconductor chip mounted
In the area, pass through the entire area in the longitudinal direction
The first input-side connection wiring and the second input-side connection
Since one end of each wiring is collectively arranged at one position on one surface of the protruding portion, the size is reduced as compared with a case where a flexible wiring board having connection wiring on both surfaces is conductively connected to a plurality of semiconductor chips. it can, after which it is possible to simplify the structure of the flexible wiring board, a first input-side contact
The connection wiring runs in the semiconductor chip mounting area in the longitudinal direction.
Is provided so as to pass through the entire area of
Of the semiconductor chip can be reduced.
A second input in which two input-side connection electrodes are provided on one surface of the protrusion;
Side connection wiring and the wiring inside the semiconductor chip.
Thus, the wiring resistance can be reduced.

【0008】[0008]

【実施例】図1はこの発明による液晶表示装置の一実施
例を示したものであり、図2(A)および(B)はその
配線構造を示したものである。これらの図において、図
4(A)および(B)と同一名称部分には同一の符号を
付し、その説明を適宜省略する。この液晶表示装置の下
側の透明基板7の下辺側の突出部の上面には、従来と同
様に半導体チップ搭載エリア8、9が設けられている。
この半導体チップ搭載エリア8、9には、従来の半導体
チップ2、3の代わりに半導体チップ31、32が搭載
される。この半導体チップ31、32の下面には、図3
(A)に示すように、上辺のすぐ内側に複数の出力側接
続電極33が設けられ、右辺のすぐ内側に4つの信号入
力側接続電極34aが設けられ、下辺のすぐ内側の2箇
所に4つの電源入力側接続電極34b、34cがそれぞ
れ設けられている。この場合、左側の電源入力側接続電
極34bと互いに対応する右側の電源入力側接続電極3
4cとがチップ内部で結線されている。また、下側の透
明基板7の右辺側の突出部の上面にも、従来と同様に半
導体チップ搭載エリア14が設けられている。この半導
体チップ搭載エリア14には、従来の半導体チップ4の
代わりに半導体チップ35が搭載される。この半導体チ
ップ35の下面には、図3(B)に示すように、上辺の
すぐ内側に複数の出力側接続電極33が設けられ、左辺
のすぐ内側に4つの信号入力側接続電極34aが設けら
れ、下辺のすぐ内側の2箇所に4つの電源入力側接続電
極34b、34cがそれぞれ設けられている。この場合
も、左側の電源入力側接続電極34bと互いに対応する
右側の電源入力側接続電極34cとがチップ内部で結線
されている。
FIG. 1 shows an embodiment of the liquid crystal display device according to the present invention, and FIGS. 2A and 2B show the wiring structure thereof. In these figures, the same reference numerals are given to the same parts as those in FIGS. 4A and 4B, and the description thereof will be omitted as appropriate. Semiconductor chip mounting areas 8 and 9 are provided on the upper surface of the projection on the lower side of the transparent substrate 7 on the lower side of the liquid crystal display device as in the conventional case.
Semiconductor chips 31 and 32 are mounted on the semiconductor chip mounting areas 8 and 9 instead of the conventional semiconductor chips 2 and 3. On the lower surfaces of the semiconductor chips 31 and 32, FIG.
As shown in (A), a plurality of output side connection electrodes 33 are provided immediately inside the upper side, four signal input side connection electrodes 34a are provided just inside the right side, and four output side connection electrodes 34a are provided just inside the lower side. Two power input side connection electrodes 34b and 34c are provided, respectively. In this case, the left power input side connection electrode 34b and the right power input side connection electrode 3 corresponding to each other.
4c are connected inside the chip. Also, a semiconductor chip mounting area 14 is provided on the upper surface of the protruding portion on the right side of the lower transparent substrate 7 as in the conventional case. In this semiconductor chip mounting area 14, a semiconductor chip 35 is mounted instead of the conventional semiconductor chip 4. On the lower surface of the semiconductor chip 35, as shown in FIG. 3B, a plurality of output-side connection electrodes 33 are provided just inside the upper side, and four signal input-side connection electrodes 34a are provided just inside the left side. In addition, four power supply input side connection electrodes 34b and 34c are respectively provided at two places just inside the lower side. Also in this case, the left power input side connection electrode 34b and the corresponding right power input side connection electrode 34c are connected inside the chip.

【0009】下側の透明基板7の下辺側の突出部の上面
には、従来の入力側接続用配線12、13の代わりに互
いに交差しない4本の信号入力側接続用配線36および
4本の電源入力側接続用配線37が設けられている。4
本の信号入力側接続用配線36は、左側の半導体チップ
搭載エリア8に搭載される半導体チップ31と右側の半
導体チップ搭載エリア9に搭載される半導体チップ32
との互いに対応する信号入力側接続電極34a、34a
同士をそれぞれ接続し、両半導体チップ搭載エリア8、
9にわたって連続して設けられ、各右端部が下側の透明
基板7の突出部の右端部にまとめて配置されている。4
本の電源入力側接続用配線37は、左側の半導体チップ
搭載エリア8に搭載される半導体チップ31と右側の半
導体チップ搭載エリア9に搭載される半導体チップ32
との互いに対応する電源入力側接続電極34c、34b
同士をそれぞれ接続するとともに、右側の半導体チップ
搭載エリア9に搭載される半導体チップ32の互いに対
応する両電源入力側接続電極34b、34c同士をそれ
ぞれ接続し、各半導体チップ搭載エリア8、9にわたっ
て連続して設けられ、各右端部が下側の透明基板7の突
出部の右端部にまとめて配置されている。また、下側の
透明基板7の右辺側の突出部の上面には、従来の入力側
接続用配線16の代わりに互いに交差しない4本の信号
入力側接続用配線38および4本の電源入力側接続用配
線39が設けられている。4本の信号入力側接続用配線
38は、各上端部が半導体チップ搭載エリア14に搭載
される半導体チップ35の信号入力側接続電極34aに
接続され、各下端部が下側の透明基板7の突出部の右端
部にまとめて配置されている。4本の電源入力側接続用
配線39は、各上端部が半導体チップ搭載エリア14に
搭載される半導体チップ35の電源入力側接続電極34
bに接続され、各下端部が下側の透明基板7の突出部の
右端部にまとめて配置されている。なお、図2(A)お
よび(B)では、半導体チップ31、32、35の各接
続電極33、34a〜34cが黒丸で示されている。
On the upper surface of the protruding portion on the lower side of the lower transparent substrate 7, instead of the conventional input side connection lines 12, 13, four signal input side connection lines 36 not intersecting with each other and four signal side connection lines 36 are provided. The power supply input side connection wiring 37 is provided. 4
The signal input side connection wiring 36 is composed of a semiconductor chip 31 mounted on the left semiconductor chip mounting area 8 and a semiconductor chip 32 mounted on the right semiconductor chip mounting area 9.
Corresponding to the signal input side connection electrodes 34a, 34a
Are connected to each other, and both semiconductor chip mounting areas 8,
9, the right end portions are collectively arranged at the right end portion of the protruding portion of the lower transparent substrate 7. 4
The power supply input side connection wiring 37 includes a semiconductor chip 31 mounted on the left semiconductor chip mounting area 8 and a semiconductor chip 32 mounted on the right semiconductor chip mounting area 9.
Input side connection electrodes 34c, 34b corresponding to each other
The two power input side connection electrodes 34b and 34c of the semiconductor chip 32 mounted on the semiconductor chip mounting area 9 on the right side are connected to each other, and are continuously connected to the semiconductor chip mounting areas 8 and 9. The right end portions are collectively arranged at the right end portion of the protruding portion of the lower transparent substrate 7. Also, instead of the conventional input-side connection wiring 16, four signal-input-side connection wirings 38 and four power-supply-input sides that do not intersect each other are provided on the upper surface of the right-side protruding portion of the lower transparent substrate 7. A connection wiring 39 is provided. The four signal input side connection wires 38 are connected at their upper ends to the signal input side connection electrodes 34 a of the semiconductor chip 35 mounted on the semiconductor chip mounting area 14, and each lower end of the lower transparent substrate 7. They are arranged together at the right end of the protrusion. The four power supply input side connection wirings 39 are provided at respective upper ends of the power supply input side connection electrodes 34 of the semiconductor chip 35 mounted on the semiconductor chip mounting area 14.
b, and each lower end is collectively arranged at the right end of the protruding portion of the lower transparent substrate 7. 2A and 2B, the connection electrodes 33, 34a to 34c of the semiconductor chips 31, 32, 35 are indicated by black circles.

【0010】そして、所定の2つの半導体チップ31、
32は下側の透明基板7の下辺側の突出部に設けられた
2つの半導体チップ搭載エリア8、9にそれぞれ搭載さ
れる。この場合、半導体チップ31、32の各信号入力
側接続電極34aは、異方導電性接着剤等の接続部材を
介して半導体チップ搭載エリア8、9の相対応する信号
入力側接続用配線36にそれぞれ導電接続され、各電源
入力側接続電極34b、34cは、異方導電性接着剤等
の接続部材を介して半導体チップ搭載エリア8、9の相
対応する電源入力側接続用配線37にそれぞれ導電接続
され、各出力側接続電極33は、従来と同様に、異方導
電性接着剤等の接続部材を介して半導体チップ搭載エリ
ア8、9の相対応する出力側接続用配線10、11にそ
れぞれ導電接続される。また、残りの1つの半導体チッ
プ4も同様にして所定の1つの半導体チップ搭載エリア
14に搭載される。
Then, two predetermined semiconductor chips 31,
Reference numeral 32 is mounted on two semiconductor chip mounting areas 8 and 9 provided on the lower side protruding portion of the lower transparent substrate 7, respectively. In this case, the signal input side connection electrodes 34a of the semiconductor chips 31 and 32 are connected to the corresponding signal input side connection wirings 36 of the semiconductor chip mounting areas 8 and 9 via connection members such as an anisotropic conductive adhesive. Each of the power supply input side connection electrodes 34b and 34c is conductively connected to the corresponding power supply input side connection wiring 37 of the semiconductor chip mounting area 8 and 9 via a connection member such as an anisotropic conductive adhesive. The respective output side connection electrodes 33 are connected to the corresponding output side connection wirings 10 and 11 of the semiconductor chip mounting areas 8 and 9 via connection members such as an anisotropic conductive adhesive in the same manner as in the related art. Conductively connected. The remaining one semiconductor chip 4 is similarly mounted on one predetermined semiconductor chip mounting area 14.

【0011】このように、この液晶表示装置では、各半
導体チップ搭載エリア8、9に搭載される各半導体チッ
プ31、32の相対応する入力側接続電極34a〜34
c同士を導電接続する互いに交差しない複数本の接続用
配線36、37を各半導体チップ搭載エリア8、9にわ
たって連続して設け、接続用配線36、37の各一端部
を下側の透明基板7の突出部の一面の右端部にまとめて
配置したので、図4に示すような従来の両面に接続用配
線21を備えたフレキシブル配線基板5を複数の半導体
チップ2、3に導電接続する場合と比較して、小型化す
ることができるとともに、フレキシブル配線基板5の構
造を単純化することができる。また、複数の信号入力側
接続用配線36が右側の半導体チップ搭載エリア9内を
通過するので、その分下側の透明基板7の下辺側の突出
部の幅を狭くすることができ、この結果小型化すること
ができる。また、半導体チップ31、32の互いに対応
する2組の電源入力側接続電極34b、34cがそれぞ
れ対応する電源入力側接続用配線37に導電接続される
ので、電源入力側接続電極34b、34cが2組あって
も配線数を増やすことなく導電接続することができる。
さらに、半導体チップ31、32の互いに対応する2組
の電源入力側接続電極34b、34cがチップ内部で結
線されているので、半導体チップ31、32の互いに対
応する2組の電源入力側接続電極34b、34c間にお
いて、半導体チップ32の結線と電源入力側接続用配線
37とが並列することになり、この結果フレキシブル配
線基板5から遠い左側の半導体チップ搭載エリア8に搭
載される半導体チップ31に対して配線抵抗を低くする
ことができ、また左側の半導体チップ搭載エリア8に搭
載される半導体チップ31の両電源入力側接続電極34
b、34c間を接続する電源入力側接続用配線37を省
略することができる。
As described above, in this liquid crystal display device, the input side connection electrodes 34a to 34 corresponding to the respective semiconductor chips 31, 32 mounted on the semiconductor chip mounting areas 8, 9 respectively.
A plurality of non-intersecting connection wirings 36 and 37 for conductively connecting the wirings c are provided continuously over the semiconductor chip mounting areas 8 and 9, and one end of each of the connection wirings 36 and 37 is connected to the lower transparent substrate 7. 4 are collectively arranged on the right end of one surface of the projecting portion, so that the conventional flexible wiring board 5 having connection wirings 21 on both sides as shown in FIG. In comparison, the size can be reduced and the structure of the flexible wiring board 5 can be simplified. Further, since the plurality of signal input side connection wirings 36 pass through the inside of the semiconductor chip mounting area 9 on the right side, the width of the protruding portion on the lower side of the lower transparent substrate 7 can be reduced accordingly. The size can be reduced. Further, two sets of the power input side connection electrodes 34b and 34c corresponding to each other of the semiconductor chips 31 and 32 are conductively connected to the corresponding power input side connection wiring 37, so that the power input side connection electrodes 34b and 34c are Even if there is a set, conductive connection can be made without increasing the number of wirings.
Further, since two sets of the corresponding power input side connection electrodes 34b and 34c of the semiconductor chips 31 and 32 are connected inside the chip, two sets of the corresponding power input side connection electrodes 34b of the semiconductor chips 31 and 32 correspond to each other. , 34c, the connection of the semiconductor chip 32 and the power supply input side connection wiring 37 are arranged in parallel. As a result, the semiconductor chip 31 mounted on the semiconductor chip mounting area 8 on the left side far from the flexible wiring board 5 In addition, both power input side connection electrodes 34 of the semiconductor chip 31 mounted on the semiconductor chip mounting area 8 on the left side can be reduced.
It is possible to omit the power supply input side connection wiring 37 for connecting between b and 34c.

【0012】なお、上記実施例では、下側の透明基板7
の下辺側の突出部の上面に2つの半導体チップ31、3
2を搭載し、これら2つの半導体チップ31、32のそ
れぞれ対応する入力側接続電極34a〜34c同士を入
力側接続用配線36、37を介して導電接続する場合に
ついて説明したが、これに限定されるものではなく、例
えば、下側の透明基板7の下辺側の突出部の上面に3つ
の半導体チップ31、32を搭載し、これら3つの半導
体チップ31、32のそれぞれ対応する入力側接続電極
34a〜34c同士を入力側接続用配線36、37を介
して導電接続するようにしてもよい。また、上記実施例
では、半導体チップ31、32、35の下面に1組の信
号入力側接続電極34aを設けた場合について説明した
が、これに限定されず、電源入力側接続電極34b、3
4cと同様に、半導体チップ31、32、35に互いに
対応する2組の信号入力側接続電極34aを設け、2組
の信号入力側接続電極34aをそれぞれ対応する信号入
力側接続用配線36に導電接続し、かつ半導体チップ3
1、32、35の対応する2組の信号入力側接続電極3
4aを互いに内部で結線するようにしてもよい。
In the above embodiment, the lower transparent substrate 7
The two semiconductor chips 31 and 3 are provided on the upper surface of the protrusion on the lower side.
2 is mounted, and the corresponding input-side connection electrodes 34a to 34c of the two semiconductor chips 31 and 32 are conductively connected to each other via the input-side connection wirings 36 and 37, but the present invention is not limited to this. For example, three semiconductor chips 31 and 32 are mounted on the upper surface of the projecting portion on the lower side of the lower transparent substrate 7, and the corresponding input-side connection electrodes 34 a of the three semiconductor chips 31 and 32 are mounted. To 34c may be conductively connected to each other via the input side connection wirings 36 and 37. Further, in the above-described embodiment, the case where one set of the signal input side connection electrodes 34a is provided on the lower surface of the semiconductor chips 31, 32, 35 is described. However, the present invention is not limited to this.
Similarly to 4c, two sets of signal input side connection electrodes 34a corresponding to each other are provided on the semiconductor chips 31, 32 and 35, and the two sets of signal input side connection electrodes 34a are electrically connected to the corresponding signal input side connection wirings 36, respectively. Connected and semiconductor chip 3
1, 32, 35 corresponding two sets of signal input side connection electrodes 3
4a may be internally connected to each other.

【0013】[0013]

【発明の効果】以上説明したように、請求項1記載の発
明によれば、突出部の一面に、前記各半導体チップ搭載
エリアにわたって連続して設けられ、前記第1の入力側
電極を接続する第1の入力側接続配線および第2の入力
側接続電極を接続する第2の入力側接続配線を互いに交
差させずに、且つ、少なくとも前記第1の入力側接続配
線は前記半導体チップ搭載エリア内をその長手方向の全
領域を通過させて設け、前記第1の入力側接続用配線お
よび前記第2の入力側接続配線の各一端部を前記突出部
の一面の一箇所にまとめて配置したので、両面に接続用
配線を備えたフレキシブル配線基板を複数の半導体チッ
プに導電接続する場合と比較して、小型化することがで
フレキシブル配線基板の構造を単純化することがで
きるうえ、第1の入力側接続配線は前記半導体チップ搭
載エリア内をその長手方向の全領域を通過させて設けた
ので、一方の基板の突出部の幅を狭くすることができ、
さらに、半導体チップの第2の入力側接続電極を突出部
の一面に設けた第2の入力側接続配線と半導体チップ内
の配線により接続したので、配線抵抗を低くすることが
できる。
As described above, according to the first aspect of the present invention, each of the semiconductor chips is mounted on one surface of the protrusion.
The first input side, which is provided continuously over the area;
First input side connection wiring for connecting electrodes and second input
The second input connection wires connecting the connection electrodes are connected to each other.
At least the first input side connection
The line extends through the entire area in the semiconductor chip mounting area in the longitudinal direction.
The first input-side connection wiring and the
And one end of the second input-side connection wiring is collectively arranged at one location on one surface of the protruding portion, so that a flexible wiring board having connection wiring on both surfaces is conductively connected to a plurality of semiconductor chips. compared to, it can be miniaturized, after which it is possible to simplify the structure of the flexible wiring board, a first input connection wiring the semiconductor chip tower
The mounting area is provided so as to pass through the entire area in the longitudinal direction.
Therefore, the width of the protruding portion of one substrate can be reduced,
Furthermore, the second input-side connection electrode of the semiconductor chip is projected
The second input side connection wiring provided on one surface of the semiconductor chip and
Because of the connection of the wiring of
it can.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明による液晶表示装置の一実施例の平面
図。
FIG. 1 is a plan view of one embodiment of a liquid crystal display device according to the present invention.

【図2】(A)は同液晶表示装置の配線構造の平面図、
(B)はその要部の平面図。
FIG. 2A is a plan view of a wiring structure of the liquid crystal display device,
(B) is a plan view of the main part.

【図3】(A)はこの液晶表示装置で使用される所定の
2つの半導体チップの平面図、(B)は同液晶表示装置
で使用される残りの1つの半導体チップの平面図。
3A is a plan view of two predetermined semiconductor chips used in the liquid crystal display device, and FIG. 3B is a plan view of another semiconductor chip used in the liquid crystal display device.

【図4】(A)は従来の液晶表示装置の一例の平面図、
(B)はその配線構造の平面図。
FIG. 4A is a plan view of an example of a conventional liquid crystal display device,
(B) is a plan view of the wiring structure.

【図5】同液晶表示装置で使用される半導体チップの平
面図。
FIG. 5 is a plan view of a semiconductor chip used in the liquid crystal display device.

【符号の説明】[Explanation of symbols]

1 液晶表示パネル 5 フレキシブル配線基板 6、7 透明基板 8、9、14 半導体チップ搭載エリア 31、32、35 半導体チップ 34a 信号入力側接続電極 34b、34c 電源入力側接続電極 36、38 信号入力側接続用配線 37、39 電源入力側接続用配線 DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 5 Flexible wiring board 6, 7 Transparent board 8, 9, 14 Semiconductor chip mounting area 31, 32, 35 Semiconductor chip 34a Signal input side connection electrode 34b, 34c Power input side connection electrode 36, 38 Signal input side connection Wiring 37, 39 Wiring for power input side connection

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 相対向する面に表示電極が形成された
2枚の基板のうち少なくとも一方の基板が他方の基板の
少なくとも一辺から突出されて突出部が形成され、この
突出部の一面に前記他方の基板の少なくとも一辺に沿っ
て複数の半導体チップ搭載エリアが設けられ、前記各半
導体チップ搭載エリアに長方形状の半導体チップが搭載
されてなる液晶表示装置において、前記半導体チップに、該半導体チップの一長辺に沿って
配列された複数の出力側接続電極と、他の三辺に沿って
配列された第1の入力側接続電極および少なくとも相対
応する一組からなる第2の入力側接続電極と、少なくと
も前記相対応する一組の第2の入力側接続電極同士を相
互に接続する配線を設け、 前記一方の基板の突出部の一面に、前記表示電極の一つ
に接続され且つ前記半導体チップの出力側接続電極に接
続される出力側接続配線と、前記各半導体チップ搭載エ
リアにわたって連続して設けられ、前記第1の入力側電
極を接続する第1の入力側接続配線および前記第2の入
力側接続電極を接続する第2の入力側接続配線を互いに
交差させずに、且つ、少なくとも前記第1の入力側接続
配線は前記半導体チップ搭載エリア内をその長手方向の
全領域を通過させて設け、前記第1の入力側接続用配線
および前記第2の入力側接続配線 の各一端部を前記突出
部の一面の一箇所にまとめて配置したことを特徴とする
液晶表示装置。
At least one of two substrates having display electrodes formed on opposing surfaces is protruded from at least one side of the other substrate to form a protruding portion, and the protruding portion is formed on one surface of the protruding portion. In a liquid crystal display device in which a plurality of semiconductor chip mounting areas are provided along at least one side of the other substrate and a rectangular semiconductor chip is mounted in each of the semiconductor chip mounting areas, the semiconductor chip includes Along one long side
Along the multiple output connection electrodes arranged along the other three sides
A first input connection electrode arranged and at least a relative
A corresponding pair of second input connection electrodes and at least
The pair of second input-side connection electrodes corresponding to the phases are also connected to each other.
Wiring for connection to each other is provided, and one of the display electrodes is provided on one surface of the protruding portion of the one substrate.
Connected to the output connection electrode of the semiconductor chip.
Connected to the output side and the semiconductor chip mounting
The first input side power supply is provided continuously over the rear.
A first input-side connection wiring for connecting a pole and the second input-side connection wiring;
The second input-side connection wires that connect the power-side connection electrodes
Non-intersecting and at least the first input connection
The wiring runs in the semiconductor chip mounting area in the longitudinal direction.
The first input-side connection wiring, which is provided so as to pass through the entire area;
And one end of each of the second input-side connection wirings is collectively arranged at one position on one surface of the protruding portion.
【請求項2】 前記第1の入力側接続電極は、信号入力
側電極であり、前記第2の入力側接続電極は、電源信号
入力側電極であることを特徴とする液晶表示装置。
2. The first input-side connection electrode is connected to a signal input terminal.
Side electrode, and the second input side connection electrode is connected to a power signal
A liquid crystal display device, which is an input electrode .
JP15821994A 1994-06-17 1994-06-17 Liquid crystal display Expired - Fee Related JP3264103B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15821994A JP3264103B2 (en) 1994-06-17 1994-06-17 Liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15821994A JP3264103B2 (en) 1994-06-17 1994-06-17 Liquid crystal display

Publications (2)

Publication Number Publication Date
JPH086058A JPH086058A (en) 1996-01-12
JP3264103B2 true JP3264103B2 (en) 2002-03-11

Family

ID=15666890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15821994A Expired - Fee Related JP3264103B2 (en) 1994-06-17 1994-06-17 Liquid crystal display

Country Status (1)

Country Link
JP (1) JP3264103B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3054135B1 (en) 1999-02-05 2000-06-19 シャープ株式会社 Liquid crystal display
DE60027342T2 (en) 1999-03-26 2007-01-04 Seiko Epson Corp. Flexible printed circuit board, electro-optical device, and electronic device
JP3845551B2 (en) 2001-04-19 2006-11-15 セイコーエプソン株式会社 ELECTRODE DRIVE DEVICE AND ELECTRONIC DEVICE
JP4255683B2 (en) 2002-03-25 2009-04-15 シャープ株式会社 Glass wiring board connection structure and display device

Also Published As

Publication number Publication date
JPH086058A (en) 1996-01-12

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