CN102385199A - Liquid crystal display panel and production method thereof - Google Patents
Liquid crystal display panel and production method thereof Download PDFInfo
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- CN102385199A CN102385199A CN2010102716268A CN201010271626A CN102385199A CN 102385199 A CN102385199 A CN 102385199A CN 2010102716268 A CN2010102716268 A CN 2010102716268A CN 201010271626 A CN201010271626 A CN 201010271626A CN 102385199 A CN102385199 A CN 102385199A
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Abstract
The invention discloses a liquid crystal display panel and a production method thereof. The liquid crystal display panel comprises a pixel array. The pixel array comprises a plurality of data lines, a first insulating layer, a plurality of scanning lines, a plurality of active elements, a plurality of capacitive electrodes, a second insulating layer and a plurality of pixel electrodes. The first insulating layer covers the data lines and is provided with a plurality of grid holes and a plurality of source holes. The scanning lines are formed on the first insulating layer. Each active element comprises a grid, a source and a drain. The sources, the grids and the capacitive electrodes are formed on the first insulating layer. The second insulating layer covers the capacitive electrodes, the sources and the drains. The pixel elements correspond to the capacitive electrodes and are formed on the second insulating layer. The scanning lines are electrically connected with the corresponding grids via the corresponding grid holes, and the data lines are electrically connected with the corresponding sources via the corresponding source holes.
Description
Technical field
The present invention relates to a kind of display panels and manufacturing approach thereof, and particularly relate to a kind of data line and grid is located at display panels and manufacturing approach thereof with one deck.
Background technology
At present; Existing several can be reached the technology that wide viewing angle requires in the manufacturing technology of LCD; For example stable twisted nematic liquid crystal (TN) adds view film (Wide Viewing Film), copline suitching type (In-plane Switching, IPS) modes such as LCD, limit suitching type (Fringe Field Switching) LCD and multi-domain vertical alignment liquid crystal displays.
In order to make the pel array in the liquid crystal mesogens display panel be connected to driving circuit, the part circuit that transmission signals is used in design meeting in the past is disposed at the periphery of viewing area to avoid showing that aperture opening ratio is further limited.But, when product on the market constantly when the design of the little frame of large scale strides forward, such design can't be satisfied market demands.
In addition, the overlapping part of the capacitance electrode of available liquid crystal display panel and pixel electrode forms MM CAP.Generally speaking, mostly across the structure more than two layers, for example be insulation course between capacitance electrode and the pixel electrode.So cause the capacity effect between capacitance electrode and the pixel electrode not good, storage capacitance value descends.
Summary of the invention
The object of the present invention is to provide a kind of display panels and manufacturing approach thereof, in one embodiment, only across monolayer insulating layer, can promote capacity effect between capacitance electrode and the pixel electrode, improve storage capacitance value.
According to an aspect of the present invention, a kind of display panels is proposed.Display panels comprises one first substrate, a pel array, one second substrate and a liquid crystal layer.Pel array is formed at first substrate.Pel array comprises several data lines, one first insulation course, several sweep traces, several active components, several capacitance electrodes, one second insulation course and several pixel electrodes.Data line is formed at first substrate.The first insulation course cover data line also has several grid perforates and several source electrode perforates.Sweep trace is formed at first insulation course.Each active component comprises a grid, one source pole and a drain electrode.Grid is formed at first substrate, and source electrode, drain electrode and capacitance electrode are formed on first insulation course.Second insulation course covers capacitance electrode, source electrode and drain electrode.The corresponding capacitance electrode of pixel electrode is formed on second insulation course.Liquid crystal layer is disposed between first substrate and second substrate.Wherein, sweep trace is electrically connected corresponding grid through corresponding grid perforate, and data line is electrically connected corresponding source electrode through corresponding source electrode perforate.
A kind of manufacturing approach of display panels is proposed according to a further aspect in the invention.Manufacturing approach may further comprise the steps.One first substrate and one second substrate are provided; Form several data lines and several grids in one first substrate; Form one first insulation course cover data line and grid, wherein, first insulation course has several grid perforates and several source electrode perforates; Form several source electrodes, several drain electrodes, several capacitance electrodes and several sweep traces in first insulation course, wherein, sweep trace is electrically connected corresponding grid through corresponding grid perforate, and data line is electrically connected corresponding source electrode through corresponding source electrode perforate; Form one second insulation course and cover source electrode, drain electrode and capacitance electrode; Form several pixel electrodes on second insulation course, the corresponding capacitance electrode in the position of pixel electrode; To organizing first substrate and second substrate; And, form a liquid crystal layer between first substrate and second substrate.
For letting the foregoing of the present invention can be more obviously understandable, hereinafter is special lifts preferred embodiment, and cooperates appended accompanying drawing, elaborates as follows:
Description of drawings
Fig. 1 is the partial schematic diagram of the display panels of the present invention the 1st embodiment;
Fig. 2 is the enlarged diagram of part 2 ' among Fig. 1;
Fig. 3 is the cut-open view of direction 3-3 ' among Fig. 2;
Fig. 4 is the cut-open view of direction 4-4 ' among Fig. 2;
Fig. 5 is the manufacturing approach process flow diagram of the display panels of first embodiment of the invention;
Fig. 6 A-Fig. 6 C is the manufacturing synoptic diagram of the pel array of Fig. 2;
Fig. 7 is the partial schematic diagram of the display panels of second embodiment of the invention;
Fig. 8 is the cut-open view of direction 8-8 ' among Fig. 7.
The main element symbol description
100,200: display panels
102: the first substrates
104,204: pel array
106: the second substrates
108: liquid crystal layer
110,210: data line
112,212: the first insulation courses
114,114a, 214: sweep trace
116,216: active component
116c, 216c: channel layer
116g, 216g: grid
116s, 216s: source electrode
116d, 216d: drain electrode
118,218: capacitance electrode
120,220: the second insulation courses
122,222: pixel electrode
124,224: the grid perforate
126,226: the source electrode perforate
128,128a: gate line
130,130a: sweep trace perforate
134,234: the drain electrode perforate
140: driving circuit
236: metal electrode
238: transparency electrode
2 ': the part
Embodiment
First embodiment
Please referring to figs. 1 through Fig. 3, Fig. 1 illustrates the partial schematic diagram according to the display panels of first embodiment of the invention, and Fig. 2 illustrates the enlarged diagram of part 2 ' among Fig. 1, and Fig. 3 illustrates the cut-open view of direction 3-3 ' among Fig. 2.Like Fig. 1, display panels 100 comprises first substrate 102, pel array 104, second substrate 106 (being illustrated in Fig. 3), liquid crystal layer 108 (being illustrated in Fig. 3) and driving circuit 140.Liquid crystal layer 108 is disposed between first substrate 102 and second substrate 106.
Please be simultaneously with reference to Fig. 2 and Fig. 3, pel array 104 is formed on first substrate 102 and comprises several data lines 110, several sweep traces 114, several active components 116, several capacitance electrodes 118, several pixel electrodes 122 and several gate lines 128.Wherein, adjacent capacitance electrode 118 is connected.
As shown in Figure 2, parallel haply those data lines 110 of those gate lines 128 are formed on first substrate 102, and gate line 128 is between adjacent two data lines 110.Gate line 128 can extend to along identical haply direction with driving circuit 140 with data line 110 and be electrically connected, and so can save the hem width size of display panels 100, meets the design requirement of narrow hem width product.
As shown in Figure 3, active component 116 comprises grid 116g, source electrode 116s, channel layer 116c and drain electrode 116d.Pel array 104 more comprises first insulation course 112 and second insulation course 120.Grid 116g is formed on first substrate 102, and source electrode 116s and drain electrode 116d then are formed on first insulation course 112.
Please continue with reference to Fig. 3, pixel electrode 122 is formed on second insulation course 120, and it is electrically connected on drain electrode 116d through drain electrode perforate 134.
As shown in Figure 3, the material of capacitance electrode 118 for example is that (Indium Tin Oxide, ITO), it is formed on first insulation course 112 for metal or indium tin oxide.At least a portion is overlapping with gate line 128 across first insulation course 112 in the capacitance electrode 118, can cover the electric field that comes from gate line 128, avoids the motion of the liquid crystal of gate line 128 influence correspondence positions.Preferable but non-exclusively, capacitance electrode 118 can not be electrically connected with community electrode (illustrating), makes above-mentioned storage capacitor construction become the form of Cs on Common.
Please with reference to Fig. 4, it illustrates the cut-open view of direction 4-4 ' among Fig. 2.Gate line 128a is formed on first substrate 102, and sweep trace 114 is formed on first insulation course 112.First insulation course 112 has more several grid perforates 124 and several sweep trace perforates 130.One scan line perforate 130a with wherein is the example explanation, and the position of sweep trace perforate 130a is corresponding to sweep trace 114a.The position of those grid perforates 124 is corresponding to those grids 116g, and sweep trace 114a can be electrically connected on grid 116g through grid perforate 124.Please be simultaneously with reference to Fig. 1; Because the location overlap of sweep trace perforate 130a, gate line 128a and sweep trace 114a; Make drive signal transfer to whole piece sweep trace 114a, drive signal is transferred to each active component 116 that is connected in sweep trace 114a through grid perforate 124 (grid perforate 124 is illustrated in Fig. 2) then through sweep trace perforate 130a through gate line 128a.Similarly, 114 signals that can transmit corresponding gate line 128 of other sweep trace through corresponding scanning line perforate 130.
The display panels 100 of present embodiment is that example is explained with penetration (transmission) display panels; So this is non-in order to restriction the present invention; Implement in the aspect at another, display panels 100 also can be transflective liquid crystal display panel (tranflective liquid display panel).Say that further pel array 104 more can comprise several transparent organic films and several reflection configurations.The position of corresponding those pixel regions of those transparent organic films is located at second insulation course, 120 second insulation courses 120 and is illustrated in Fig. 3) go up to define the echo area.Preferable but non-exclusively, transparent organic film covers non-penetrating region, for example be the scope that covers active component 116.Those reflection configurations are formed on those transparent organic films, with reflection environment light accordingly.
Below be the manufacturing approach of the display panels of example explanation first embodiment of the invention with display panels 100.Please be simultaneously with reference to Fig. 5 and 6A-6C figure, Fig. 5 illustrates the manufacturing approach process flow diagram according to the display panels of first embodiment of the invention, and 6A-6C figure illustrates the manufacturing synoptic diagram of the pel array of Fig. 2.6A-6C figure only shows single pixel region.
In step S102, first substrate 102 and second substrate 106 as shown in Figure 3 is provided.
Then, in step S104, shown in Fig. 6 A, form data line 110, grid 116g and gate line 128 on first substrate 102 (not being illustrated in Fig. 6 A).Every gate line 128 is adjacent between the two in those data lines 110.
Then, in step S106, form the first transparent insulation course 112 shown in Fig. 6 B.First insulation course, 112 cover data lines 110, grid 116g and gate line 128.Wherein, first insulation course 112 has grid perforate 124, source electrode perforate 126 and sweep trace perforate 130.The position of source electrode perforate 126 is corresponding to data line 110, and the position of grid perforate 124 is corresponding to grid 116g.
Then, in step S108, shown in Fig. 6 C, form source electrode 116s, drain electrode 116d, channel layer 116c, capacitance electrode 118 and sweep trace 114 on first insulation course 112.Wherein, every sweep trace 114 is electrically connected corresponding grid 116g through corresponding grid perforate 124, and every data line 110 is electrically connected corresponding source electrode 116s through corresponding source electrode perforate 126, and the capacitance electrode 118 of part is overlapping with gate line 128 at least.
Then, in step S110, form the second transparent insulation course 120 as shown in Figure 3.Second insulation course 120 covers source electrode 116s, drain electrode 116d, channel layer 116c and capacitance electrode 118.
After step S112, can form drain electrode perforate 134 as shown in Figure 2 in second insulation course 120.The position of drain electrode perforate 134 is corresponding to drain electrode 116d.
Then, in step S112, form pixel electrode 122 as shown in Figure 2 on second insulation course 120, the corresponding capacitance electrode 118 in the position of pixel electrode 122.Pixel electrode 122 can be electrically connected drain electrode 116d through drain electrode perforate 134.
Then, in step S114, to organizing first substrate 102 and second substrate 106.
Then, in step S116, form liquid crystal layer 108 between first substrate 102 and second substrate 106.So far, accomplish the display panels 100 of the penetration of present embodiment.
In addition, though diagram does not illustrate, so implement to continue to form transparent organic film on pixel electrode 122 behind the step S112 in the aspect at another.And, form the reflection horizon on transparent organic film, to form transflective liquid crystal display panel.Above-mentioned reflection horizon for example is a metallic reflector.
Second embodiment
Please with reference to Fig. 7, it illustrates the partial schematic diagram according to the display panels of second embodiment of the invention.Continue to use same numeral with the first embodiment something in common among second embodiment, repeat no more at this.Display panels 100 differences of the display panels 200 of second embodiment and first embodiment are that display panels 200 does not comprise gate line 128 and sweep trace perforate 130.
Please with reference to Fig. 8, it illustrates the cut-open view of direction 8-8 ' among Fig. 7.Display panels 200 comprises first substrate 102, pel array 204, second substrate 106 and liquid crystal layer 108.
Those data lines 210 and those sweep traces 214 intersect and define several pixel regions jointly.
As shown in Figure 8, first insulation course 212 covers those data lines 210 and has several grid perforates 224 (grid perforate 224 is illustrated in Fig. 7) and several source electrode perforates 226.As shown in Figure 7, sweep trace 214 is formed on first insulation course 212.Wherein, every sweep trace 214 can be electrically connected corresponding grid 216g through corresponding grid perforate 224, and every data line 210 can be electrically connected corresponding source electrode 216s through corresponding source electrode perforate 226.
As shown in Figure 7, capacitance electrode 218 can be electrically connected community electrode and comprise metal electrode 236 and transparency electrode 238.Adjacent metal electrode 236 is connected, and each metal electrode 236 is formed on first insulation course 212 and its position along contiguous data line forms the ㄇ font, and the part of transparency electrode 238 is formed on the metal electrode 236, and is as shown in Figure 8.At least a portion at least a portion in second insulation course 220 and pixel electrode 222 is overlapping in the capacitance electrode 218, and overlapping part forms MM CAP.
Because the capacitance electrode 218 of present embodiment comprises metal electrode 236, so capacitance electrode 218 has low-impedance characteristic.And transparency electrode 238 does not influence the aperture opening ratio of pixel region, so capacitance electrode 218 possesses Low ESR simultaneously and makes the maximized characteristic of pixel aperture ratio.Certainly; The common knowledge the knowledgeable in present technique field should understand, and implements in the aspect one, and capacitance electrode 218 one of also can omit in metal electrode 236 and the transparency electrode 238 person; So, capacitance electrode 218 still can form MM CAP with pixel electrode 222 overlapping parts.
The position of pixel electrode 222 corresponding capacitance electrodes 218 is formed on second insulation course 220, makes pixel electrode 222 and capacitance electrode 218 overlapping parts form MM CAP.Owing to only at a distance from single layer structure (i.e. second insulation course 220),, can improve storage capacitance value between pixel electrode 222 and the capacitance electrode 218 so capacity effect is preferable.
Below with the manufacturing approach of the process step of Fig. 5 explanation display panels 200.
In step S102, first substrate 102 and second substrate 106 as shown in Figure 8 is provided.
Then, in step S104, form data line 210 as shown in Figure 7 and grid 216g on first substrate 102.
Then, in step S106, form first insulation course 212 as shown in Figure 8.First insulation course, 212 cover data lines 210 and grid 216g.Wherein, like Fig. 7 and shown in Figure 8, first insulation course 212 has grid perforate 224 and source electrode perforate 226, and the position of source electrode perforate 226 is corresponding to data line 210, and the position of grid perforate 224 is corresponding to grid 216g.
Then, in step S108, form source electrode 216s as shown in Figure 8, drain electrode 216d, channel layer 216c, capacitance electrode 218 and sweep trace 214 (being illustrated in Fig. 7) on first insulation course 212.
Then, in step S110, form second insulation course 220 as shown in Figure 8.Second insulation course 220 covers source electrode 116s, drain electrode 116d, channel layer 216c and capacitance electrode 218.
After step S112, form drain electrode perforate 234 as shown in Figure 8 in second insulation course 220.The position of drain electrode perforate 234 is corresponding to drain electrode 216d.
Then, in step S112, form pixel electrode 222 as shown in Figure 7 on second insulation course 220, the corresponding capacitance electrode 218 in the position of pixel electrode 222.Pixel electrode 222 can be electrically connected on drain electrode 216d through drain electrode perforate 234.
Subsequent step S114 and S116 repeat no more at this similar in appearance to the explanation of first embodiment.After step S116 accomplishes, form the display panels 200 of the penetration of present embodiment.
In addition, do not illustrate though illustrate, so after step S112, can continue to form transparent organic film on pixel electrode 222.And, form the reflection horizon on transparent organic film, to form transflective liquid crystal display panel.Above-mentioned reflection horizon for example is a metallic reflector.
In addition, implement can be formed with a channel patterns (not illustrating) on the pixel electrode in the aspect one, the marginal field effect that this channel patterns caused can influence the toppling direction of liquid crystal molecule, makes liquid crystal molecule present multiple domain orientation (multi-domain).
Implement in the aspect one; On pixel electrode, can be formed with the channel patterns; The position in respective pixel zone more can be provided with at least one orientation projection (protusion) on second substrate of display panels, can make liquid crystal molecule present the effect of multiple domain orientation equally.
In addition, above-mentioned display panels 100 and 200 can be TN type liquid crystal, IPS LCD, FFS type LCD and multiple domain alignment type liquid crystal display device.
In sum, though combine to have disclosed the present invention with preferred embodiment, it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking the claim person of defining who encloses.
Claims (12)
1. display panels comprises:
First substrate;
Pel array is formed at this first substrate, and this pel array comprises:
Many data lines are formed at this first substrate;
First insulation course covers those data lines and has a plurality of grid perforates and a plurality of source electrode perforate;
The multi-strip scanning line is formed at this first insulation course;
A plurality of active components, each those active component comprises a grid, one source pole and a drain electrode, and this grid is formed at this first substrate, and this source electrode and this drain electrode of each those active component are formed on this first insulation course;
A plurality of capacitance electrodes are formed on this first insulation course;
Second insulation course, those source electrodes and those drain electrodes that cover those capacitance electrodes, those active components; And
A plurality of pixel electrodes, corresponding those capacitance electrodes are formed on this second insulation course;
Second substrate; And
Liquid crystal layer is disposed between this first substrate and this second substrate;
Wherein, each those sweep trace is electrically connected on this corresponding grid through this grid perforate of correspondence, and each those data line is electrically connected on this corresponding source electrode through this source electrode perforate of correspondence.
2. display panels as claimed in claim 1 also comprises:
It is adjacent between the two in those data lines that many gate lines, parallel in fact those data lines are formed at one of this first substrate and those gate lines person;
Wherein, this first insulation course also has a plurality of sweep trace perforates, and those sweep trace perforates, those gate lines are corresponding with the position of those sweep traces, each those gate line this sweep trace perforate through correspondence this corresponding sweep trace that electrically conducts.
3. display panels as claimed in claim 2, the wherein location overlap of at least a portion and corresponding this gate line in each those capacitance electrode.
4. display panels as claimed in claim 1, wherein each those capacitance electrode comprises:
Metal electrode; And
Transparency electrode is connected in this metal electrode.
5. display panels as claimed in claim 1 also comprises:
A plurality of organic films are formed on this second insulation course; And
A plurality of reflection configurations are formed on those organic films accordingly.
6. display panels as claimed in claim 1, wherein this second insulation course has a plurality of drain electrode perforates, and those pixel electrodes are electrically connected on those drain electrodes through those drain electrode perforates.
7. display panels as claimed in claim 1, wherein the material of each those capacitance electrode be metal or indium tin oxide (Indium Tin Oxide, ITO).
8. the manufacturing approach of a display panels comprises:
One first substrate and one second substrate are provided;
Form many data lines and a plurality of grid on this first substrate;
Form one first insulation course and cover those data lines and those grids, wherein, this first insulation course has a plurality of grid perforates and a plurality of source electrode perforate;
Form a plurality of source electrodes, a plurality of drain electrode, a plurality of capacitance electrode and multi-strip scanning line on this first insulation course; Wherein, Each those sweep trace is electrically connected this corresponding grid through this corresponding grid perforate, and each those data line is electrically connected this corresponding source electrode through this corresponding source electrode perforate;
Form one second insulation course and cover those source electrodes, those drain electrodes and those capacitance electrodes;
Form a plurality of pixel electrodes on this second insulation course, corresponding those capacitance electrodes in the position of those pixel electrodes;
To organizing this first substrate and this second substrate; And
Form a liquid crystal layer between this first substrate and this second substrate.
9. manufacturing approach as claimed in claim 8 also comprises:
Form many gate lines on this first substrate, it is adjacent between the two in those data lines that those gate lines are parallel to one of those data lines and those gate lines person in fact;
Wherein in this step that forms this first insulation course; This first insulation course also has a plurality of sweep trace perforates; Those sweep trace perforates, those gate lines are corresponding with the position of those sweep traces, each those gate line this sweep trace perforate through correspondence this corresponding sweep trace that electrically conducts.
10. manufacturing approach as claimed in claim 8 wherein also comprises in this step that forms those capacitance electrodes:
Form a metal electrode; And
Form a transparency electrode and be connected in this metal electrode.
11. manufacturing approach as claimed in claim 8 also comprises:
Form a plurality of organic films on this second insulation course; And
Form a plurality of reflection horizon on those organic films.
12. manufacturing approach as claimed in claim 8 also comprises:
Form a plurality of drain electrode perforates in this second insulation course;
Forming those pixel electrodes in this step of this second insulation course, those pixel electrodes are electrically connected on those drain electrodes through those drain electrode perforates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201010271626.8A CN102385199B (en) | 2010-09-03 | 2010-09-03 | Liquid crystal display panel and production method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010271626.8A CN102385199B (en) | 2010-09-03 | 2010-09-03 | Liquid crystal display panel and production method thereof |
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| CN102385199A true CN102385199A (en) | 2012-03-21 |
| CN102385199B CN102385199B (en) | 2014-03-12 |
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| CN201010271626.8A Expired - Fee Related CN102385199B (en) | 2010-09-03 | 2010-09-03 | Liquid crystal display panel and production method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102436087A (en) * | 2011-12-14 | 2012-05-02 | 深圳市华星光电技术有限公司 | Liquid crystal display (LCD) device and method for reducing parasitic capacitance of same |
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| CN101123257A (en) * | 2007-09-12 | 2008-02-13 | 上海广电光电子有限公司 | Thin film transistor array base plate and its making method |
| CN101256985A (en) * | 2008-02-26 | 2008-09-03 | 上海广电光电子有限公司 | Thin-film transistor array substrate and manufacturing method thereof |
| CN101487962A (en) * | 2009-01-20 | 2009-07-22 | 友达光电股份有限公司 | Display equipment with narrow frame structure and its driving method |
| CN101510529A (en) * | 2009-02-17 | 2009-08-19 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
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2010
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| JPH11305681A (en) * | 1998-04-17 | 1999-11-05 | Casio Comput Co Ltd | Display device |
| CN101123257A (en) * | 2007-09-12 | 2008-02-13 | 上海广电光电子有限公司 | Thin film transistor array base plate and its making method |
| CN101256985A (en) * | 2008-02-26 | 2008-09-03 | 上海广电光电子有限公司 | Thin-film transistor array substrate and manufacturing method thereof |
| CN101487962A (en) * | 2009-01-20 | 2009-07-22 | 友达光电股份有限公司 | Display equipment with narrow frame structure and its driving method |
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| CN102436087A (en) * | 2011-12-14 | 2012-05-02 | 深圳市华星光电技术有限公司 | Liquid crystal display (LCD) device and method for reducing parasitic capacitance of same |
| CN102436087B (en) * | 2011-12-14 | 2014-02-26 | 深圳市华星光电技术有限公司 | Liquid crystal display (LCD) device and method for reducing parasitic capacitance of same |
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| CN102385199B (en) | 2014-03-12 |
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