WO2021072781A1 - 显示面板 - Google Patents

显示面板 Download PDF

Info

Publication number
WO2021072781A1
WO2021072781A1 PCT/CN2019/112158 CN2019112158W WO2021072781A1 WO 2021072781 A1 WO2021072781 A1 WO 2021072781A1 CN 2019112158 W CN2019112158 W CN 2019112158W WO 2021072781 A1 WO2021072781 A1 WO 2021072781A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
layer
disposed
substrate
bonding pad
Prior art date
Application number
PCT/CN2019/112158
Other languages
English (en)
French (fr)
Inventor
刘晋铨
林富良
Original Assignee
友达光电（昆山）有限公司
友达光电股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 友达光电（昆山）有限公司, 友达光电股份有限公司 filed Critical 友达光电（昆山）有限公司
Priority to US17/312,654 priority Critical patent/US11973086B2/en
Publication of WO2021072781A1 publication Critical patent/WO2021072781A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs

Definitions

  • the present invention relates to a display panel, and particularly relates to a display panel with a narrow frame design.
  • FIG. 1 is a schematic diagram of the structure of an existing display panel.
  • the display panel 10 has a display area AA and a peripheral area BA.
  • a pixel structure and pixel circuits are formed in the display area AA.
  • a control circuit 11, a fan-out wiring 12 and a bonding pad 13 are formed in the peripheral area BA, and In the area where the bonding pad 13 is formed, the flat layer 14 is removed.
  • the existing method is that the control circuit 11 and the fan-out wiring 12 are at least partially overlapped.
  • the present invention provides a display panel that can better meet the needs of narrow frame design, avoid short-circuits between control circuits and fan-out lines and interference with data lines, and improve display effects and display panel yields.
  • a display panel includes a first substrate including a display area and a peripheral area adjacent to each other; a plurality of pixel units arranged on the first substrate and located in the display area; and a control circuit , Disposed on the first substrate and located in the peripheral area, the control circuit is electrically connected to the pixel unit; a flat layer, disposed on the first substrate, extending from the display area to the A peripheral area, covering the pixel unit and the control circuit; a bonding pad, disposed on the first substrate, and located above the flat layer; wherein, the projection area of the bonding pad on the first substrate There is an overlap area with the projection area of the control circuit on the first substrate.
  • a display panel includes a first substrate including a display area and a peripheral area adjacent to each other; a plurality of pixel units arranged on the first substrate and located in the display area; and a wiring Structure, arranged on the first substrate and located in the peripheral area, the wiring structure is electrically connected to the pixel unit; a flat layer, arranged on the first substrate, extending from the display area to the The peripheral area covers the pixel unit and the wiring structure; a bonding pad is disposed on the first substrate, is located above the flat layer and is electrically connected to the wiring structure; wherein, the bonding pad There is an overlap area between the projected area of the first substrate and the projected area of the wiring structure on the first substrate.
  • FIG. 1 is a schematic diagram of the structure of an existing display panel.
  • FIG. 2 is a schematic diagram of the structure of a display panel according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a display panel according to another embodiment of the invention.
  • FIG. 2 is a schematic diagram of the structure of a display panel according to an embodiment of the present invention.
  • the display panel 100 includes a first substrate 101 and a control circuit 102 provided on the first substrate 101, a flat layer 103 and a bonding pad 104.
  • the first substrate 101 has a display area AA and a peripheral area BA arranged adjacently, and a plurality of pixel units (not shown in the figure) arranged in a matrix are arranged in the display area AA.
  • the control circuit 102 is disposed in the peripheral area BA and is electrically connected to the pixel unit in the display area AA, so as to drive the pixel unit for display.
  • the flat layer 102 is disposed in the display area AA and the peripheral area BA, and covers the pixel units in the display area AA and the control circuit 102 in the peripheral area.
  • the bonding pad 104 is disposed above the flat layer 103, and the projection area of the bonding pad 104 and the control circuit 102 on the first substrate 101 has an overlapping area.
  • the display panel 100 further includes a buffer layer 107 formed on the first substrate 101, and the invention is not limited to this.
  • the control circuit 102 includes a first semiconductor layer 1021, the first semiconductor layer is disposed on the first substrate 101, and the first semiconductor layer 1021 has a first doped region 1022, a second doped region 1023 and the first channel region CH1.
  • the first channel region CH1 is located between the first doped region 1022 and the second doped region 1023.
  • a shallow doped region 10211 is formed between the first channel region CH1 and the first doped region 1022 and the second doped region 1023, respectively, and the present invention is not limited to this.
  • the gate insulating layer 1024 is formed on the first semiconductor layer 1021 and covers the first semiconductor layer 1021, the first metal layer 1025 is disposed on the gate insulating layer 1024, and the position of the first metal layer 1025 is the same as the first channel region CH1 Corresponding to the location.
  • the first insulating layer 1026 is formed on the first metal layer 1025 and covers the first metal layer 1025, a second metal layer 1027 is formed on the first insulating layer 1026, and the second metal layer 1027 passes in the first insulating layer 1026
  • the formed through hole is connected to the first doped region 1022 or the second doped region 1023.
  • the bonding pad 104 is formed on the flat layer 103.
  • the specific structure of the bonding pad 104 is that a third metal layer 1041 is provided on the flat layer 103, the second insulating layer 1042 is formed on the third metal layer 1041 and covers the third metal layer 1041, and is in the second insulating layer 1042 A bonding pad opening 1043 is formed. Further, a fourth metal layer 1044 is formed in the bonding pad opening 1043, and the fourth metal layer 1044 is electrically connected to the third metal layer 1041.
  • the second insulating layer 1042 has a multi-layer structure.
  • the second insulating layer 142 can also be a single layer or other multi-layer structures, and the present invention is not limited to this.
  • the pixel unit includes a plurality of thin film transistors 105.
  • the thin film transistors 105 include a second semiconductor layer 1051 formed on the first substrate 101.
  • the second semiconductor layer 1051 has a third dopant.
  • the second channel region CH2 is located between the third doped region 1052 and the fourth doped region 1053.
  • a shallow doped region 10511 is formed between the second channel region CH2, the third doped region 1052 and the fourth doped region 1053, respectively, and the present invention is not limited to this.
  • the gate insulating layer 1024 is formed on the second semiconductor layer 1051 and covers the second semiconductor layer 1051.
  • a gate metal layer 1054 is formed on the gate insulating layer 1024, and the position of the gate metal layer 1054 corresponds to the position of the second channel region CH2. Wherein, in this embodiment, the gate metal layer 1054 can be made of the same film layer as the first metal layer 1025.
  • the first insulating layer 1026 is formed on the gate metal layer 1054 and covers the gate metal layer 1054.
  • a source/drain metal layer 1055 is formed on the first insulating layer 1026, and the source/drain metal layer 1055 is connected to the third doped region 1052 or the fourth doped region 1052 through a through hole formed in the first insulating layer 1026. Doped region 1053.
  • the source/drain metal layer 1055 can be made of the same film layer as the second metal layer 1027.
  • the flat layer 103 covers the source/drain metal layer 1055 and the first insulating layer 1026, and a second insulating layer 1042 is formed on the flat layer 103.
  • a shared electrode 108 is formed between the flat layer 103 and the second insulating layer 1042, and the shared electrode 108 is electrically connected to the pixel unit in the display area AA and the control circuit 102 in the peripheral area BA.
  • a pixel electrode 109 is also provided on the second insulating layer 1042, and the pixel electrode 109 is electrically connected to the source/drain metal layer 1055 through the through holes formed in the second insulating layer 1042 and the flat layer 103.
  • the shared electrode 108 and the pixel electrode 109 are usually made of transparent conductive layers (ITO1, ITO2), and the transparent conductive layers (ITO1, ITO2) can be, for example, indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc
  • the present invention is not limited to the transparent conductive layer such as oxide or indium germanium zinc oxide.
  • the fourth metal layer 1044 in the bonding pad 104 is made of the same film layer as the pixel electrode 109, and may also be a transparent conductive layer as described above.
  • FIG. 3 is a schematic structural diagram of a display panel according to another embodiment of the present invention. As shown in FIG. 3, the difference between the embodiment shown in FIG. 3 and the embodiment shown in FIG. 2 is that in the peripheral area BA of the display panel 100, not only the control circuit 102 is formed, but also the wiring structure 106 may be formed.
  • the wiring structure 106 is electrically connected to the pixel unit in the display area AA to transmit control and data signals.
  • the bonding pad 104 is formed above the wiring structure 106, and the projection area of the bonding pad 104 and the wiring structure 106 on the first substrate 101 has an overlapping area.
  • the wiring structure 106 includes a gate insulating layer 1024 disposed on the first substrate 101, a first wiring metal layer 1061 is formed on the gate insulating layer 1024, and a first insulating layer 1026 is formed On the first wiring metal layer 1061 and covering the first wiring metal layer 1061, the second wiring metal layer 1062 is formed on the first insulating layer 1026 and passes through the through holes in the first insulating layer 1026 and the first wiring metal layer 1061 Realize electrical connection.
  • a fifth metal layer 1063 is also formed on the flat layer 103, and the fifth metal layer 1063 is electrically connected to the third metal layer 1041 in the bonding pad 104 and the second wiring metal layer 1062 in the wiring structure 106, respectively.
  • the wiring structure 106 and the bonding pad 104 are electrically connected through the fifth metal layer 1063.
  • the first wiring metal layer 1061 can be made of the same film layer as the first metal layer 1025
  • the second wiring metal layer 1062 can be made of the same film layer as the second metal layer 1027.
  • the fifth metal layer 1063 can be made of the same film layer as the shared electrode 108, and the fifth metal layer 1063 can be a transparent conductive layer as described above.
  • control circuit 102 or the wiring structure 106 is formed in the area below the bonding pad 104 perpendicular to the first substrate 101, but generally in the display panel 100, the bonding pad 104 may also be formed at the same time.
  • the control circuit and/or wiring structure 106 will not be repeated here.
  • a circuit board is also formed in the display panel 100, and an electrical connection is realized between the circuit board and the bonding pad 104, so as to realize signal transmission between the bonding pad 104 and the display panel 100.
  • the bonding pad is formed above the control circuit and/or the wiring structure, that is, an overlapping area is formed between the bonding pad and the control circuit and/or the wiring structure, the vertical space in the peripheral area is fully utilized, The bonding pad and the control circuit and/or the wiring structure share a horizontal space. Therefore, the width of the peripheral area of the display panel is further reduced, and the narrow frame design can be better adapted.
  • the flat layer extends from the display area of the display panel to the peripheral area, which can effectively prevent moisture from invading the display area; moreover, no overlapping area is formed between the control circuit and the wiring structure, which avoids short circuits and signal interference between the two .
  • the bonding pad is formed above the control circuit and/or wiring structure, that is, an overlapping area is formed between the bonding pad and the control circuit and/or wiring structure, the vertical space of the peripheral area is fully utilized, and the bonding pad and the control circuit and/or wiring structure are fully utilized. There is a shared horizontal space, therefore, the width of the peripheral area of the display panel is further reduced, and the narrow frame design can be better adapted.
  • the flat layer extends from the display area of the display panel to the peripheral area, which can effectively prevent moisture from invading the display area; moreover, no overlapping area is formed between the control circuit and the wiring structure, which avoids short circuits and signal interference between the two .

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（100），包括：一第一基板（101），包含相邻的一显示区（AA）与一周边区（BA）；多个像素单元，设置于第一基板（101），且位于显示区（AA）；一控制电路（102），设置于第一基板（101），且位于周边区（BA），控制电路（102）与像素单元电性连接；一平坦层（103），设置于第一基板（101），从显示区（AA）延伸至周边区（BA），且覆盖像素单元及控制电路（102）；一接合垫（104），设置于第一基板（101），且位于平坦层（103）上方。接合垫（104）于第一基板（101）的投影与控制电路（102）于第一基板（101）的投影有重叠区域。

Description

显示面板 技术领域
本发明是有关于一种显示面板，且特别是有关于一种窄边框设计的的显示面板。
背景技术
随着科技的发展，显示装置被广泛应用在许多电子产品上，如手机、平板电脑、手表等。同时，为了满足更多的需求，电子产品上大多都安装了具有光学感应功能的元件，例如摄像头。
近年来，为缩小非显示区域的占比，显示面板逐渐朝窄边框设计方向发展。图1为现有显示面板的结构示意图。如图1所示，显示面板10具有显示区AA及周边区BA，显示区AA中形成有像素结构及像素电路，周边区BA中形成有控制电路11、扇出布线12以及接合垫13，且形成接合垫13的区域中，平坦层14进行了去除。为了更充分利用周边区的面积，现有的做法为控制电路11以及扇出布线12采用至少部分重叠的方式。现有的显示面板中，由于平坦层14在形成接合垫13的区域中进行了去除，且控制电路11与扇出布线12之间的重叠，容易导致控制电路11与扇出布线12之间的短路、数据线受到噪声干扰以及水气由周边区BA入侵显示区AA，造成显示面板的显示错误甚至失效。
因此，如何能更好地减小非显示区域的面积，避免控制电路与扇出线路的短路以及数据线受到干扰，实为需要解决的问题之一。
发明公开
为解决上述问题，本发明提供一种显示面板，可以更好地满足窄边框设计的需求，避免控制电路与扇出线路的短路以及数据线受到干扰，提升显示效果及显示面板的成品率。
本发明一实施例的显示面板，包括一第一基板，包含相邻的一显示区与一周边区；多个像素单元，设置于所述第一基板，且位于所述显示区；一控制电路，设置于所述第一基板，且位于所述周边区，所述控制电路与所述像素单元 电性连接；一平坦层，设置于所述第一基板，从所述显示区延伸至所述周边区，且覆盖所述像素单元及所述控制电路；一接合垫，设置于所述第一基板，且位于所述平坦层上方；其中，所述接合垫于所述第一基板的投影面积与所述控制电路于所述第一基板的投影面积有重叠区域。
本发明另一实施例的显示面板，包括一第一基板，包含相邻的一显示区与一周边区；多个像素单元，设置于所述第一基板，且位于所述显示区；一布线结构，设置于所述第一基板，且位于所述周边区，所述布线结构与所述像素单元电性连接；一平坦层，设置于所述第一基板，从所述显示区延伸至所述周边区，且覆盖所述像素单元及所述布线结构；一接合垫，设置于所述第一基板，位于所述平坦层上方且与所述布线结构电性连接；其中，所述接合垫于所述第一基板的投影面积与所述布线结构于所述第一基板的投影面积有重叠区域。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图简要说明
图1为现有显示面板的结构示意图。
图2为本发明一实施例显示面板的结构示意图。
图3为本发明另一实施例显示面板的结构示意图。
其中，附图标记：
10、100：显示面板
AA：显示区
BA：周边区
11：控制电路
12：扇出布线
13：接合垫
14：平坦层
101：第一基板
102：控制电路
103：平坦层
104：接合垫
105：薄膜晶体管
106：布线结构
107：缓冲层
108：共享电极
109：像素电极
1021：第一半导体层
1022：第一掺杂区
1023：第二掺杂区
10211：浅掺杂区
1024：栅极绝缘层
1025：第一金属层
1026：第一绝缘层
1041：第三金属层
1042：第二绝缘层
1043：接合垫开口
1044：第四金属层
1051：第二半导体层
10511：浅掺杂区
1052：第三掺杂区
1053：第四掺杂区
1054：栅极金属层
1055：源极/漏极金属层
1061：第一布线金属层
1062：第二布线金属层
1063：第五金属层
CH1：第一沟道区
CH2：第二沟道区
实现本发明的最佳方式
下面结合附图对本发明的结构原理和工作原理作具体的描述：
图2是本发明一实施例显示面板的结构示意图。如图2所示，显示面板100包括第一基板101以及设置于第一基板101上的控制电路102、平坦层103以及接合垫104。其中，第一基板101具有相邻设置的显示区AA以及周边区BA，显示区AA中设置有呈矩阵排列的多个像素单元(图中未示出)。控制电路102设置于周边区BA中且与显示区AA中的像素单元电性连接，以便驱动像素单元进行显示。平坦层102设置于显示区AA以及周边区BA，且覆盖显示区AA中的像素单元以及周边区的控制电路102。接合垫104设置于平坦层103的上方，且接合垫104以及控制电路102在第一基板101上的投影面积有重叠区域。于本实施例中，显示面板100还包括形成于第一基板101上的缓冲层107，本发明并不以此为限。
具体的，如图2所示，控制电路102包括第一半导体层1021，第一半导体层设置于第一基板101上，且第一半导体层1021具有第一掺杂区1022、第二掺杂区1023以及第一沟道区CH1，第一沟道区CH1位于第一掺杂区1022与第二掺杂区1023之间。当然，于本实施例中，第一沟道区CH1与第一掺杂区1022以及第二掺杂区1023之间还分别形成有浅掺杂区10211，本发明并不以此为限。栅极绝缘层1024形成于第一半导体层1021上并覆盖第一半导体层1021，第一金属层1025设置于栅极绝缘层1024上，且第一金属层1025的位置与第一沟道区CH1的位置相对应。第一绝缘层1026形成于第一金属层1025上并覆盖第一金属层1025，在第一绝缘层1026上形成有第二金属层1027，且第二金属层1027通过在第一绝缘层1026中形成的通孔连接于第一掺杂区1022或第二掺杂区1023。
再如图2所示，接合垫104形成在平坦层103上。接合垫104的具体结构为，在平坦层103上设置有第三金属层1041，第二绝缘层1042形成于第三金属层1041上并覆盖第三金属层1041，且在第二绝缘层1042中形成有接合垫开口1043。进一步，在接合垫开口1043中形成第四金属层1044，且第四金属层1044电性连接于第三金属层1041。于本实施例中，第二绝缘层1042为多层结构，当然，第二绝缘层142也可为单层或其他多层结构，本发明并不以此为限。
同时，如图2所示，在显示区AA中，像素单元包括多个薄膜晶体管105，薄膜晶体管105包括形成于第一基板101上的第二半导体层1051，第二半导 体层1051具有第三掺杂区1052、第四掺杂区1053以及第二沟道区CH2，第二沟道区CH2位于第三掺杂区1052与第四掺杂区1053之间。当然，第二沟道区CH2与第三掺杂区1052以及第四掺杂区1053之间还分别形成有浅掺杂区10511，本发明并不以此为限。栅极绝缘层1024形成于第二半导体层1051上并覆盖第二半导体层1051。在栅极绝缘层1024上形成栅极金属层1054，且栅极金属层1054的位置与第二沟道区CH2的位置相对应。其中，于本实施例中，栅极金属层1054可以采用与第一金属层1025相同的膜层制成。第一绝缘层1026形成于栅极金属层1054上并覆盖栅极金属层1054。在第一绝缘层1026上形成有源极/漏极金属层1055，且源极/漏极金属层1055通过在第一绝缘层1026中形成的通孔连接于第三掺杂区1052或第四掺杂区1053。其中，于本实施例中，源极/漏极金属层1055可以采用与第二金属层1027相同的膜层制成。平坦层103覆盖源极/漏极金属层1055以及第一绝缘层1026，再在平坦层103上形成有第二绝缘层1042。其中，在平坦层103与第二绝缘层1042之间形成有共享电极108，共享电极108电性连接于显示区AA中的像素单元以及周边区BA中的控制电路102。在第二绝缘层1042上还设置有像素电极109，像素电极109通过在第二绝缘层1042以及平坦层103中形成的通孔电性连接至源极/漏极金属层1055。其中，共享电极108以及像素电极109通常采用透明导电层(ITO1、ITO2)制成，透明导电层(ITO1、ITO2)可以是如铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物或铟锗锌氧化物等的透明导电层，本发明并不以此为限。另外，接合垫104中的第四金属层1044采用与像素电极109相同的膜层制成，同样也可以是如上所述的透明导电层。
图3是本发明另一实施例显示面板的结构示意图。如图3所示，图3所示实施例与图2所示实施例的区别在于，在显示面板100的周边区BA中，并不仅仅形成有控制电路102，也可能会形成布线结构106，布线结构106与显示区AA中的像素单元电性连接，以传送控制和数据信号。接合垫104形成在布线结构106的上方，且接合垫104以及布线结构106在第一基板101上的投影面积有重叠区域。
具体的，如图3所示，布线结构106包括设置于所述第一基板101上的栅极绝缘层1024，在栅极绝缘层1024上形成第一布线金属层1061，第一绝缘层1026形成于第一布线金属层1061上并覆盖第一布线金属层1061，第二布线金 属层1062形成于第一绝缘层1026上，并通过第一绝缘层1026中的通孔与第一布线金属层1061实现电性连接。另外，在平坦层103上还形成有第五金属层1063，且第五金属层1063分别电性连接于接合垫104中的第三金属层1041以及布线结构106中的第二布线金属层1062，即布线结构106与接合垫104之间通过第五金属层1063实现电性连接。其中，于本实施例中，第一布线金属层1061可以采用与第一金属层1025相同的膜层制成，第二布线金属层1062可以采用与第二金属层1027相同的膜层制成，第五金属层1063可以采用与共享电极108相同的膜层制成，且第五金属层1063可以是如上所述的透明导电层。
上述两个实施例分别具体介绍了在接合垫104相对于第一基板101垂直下方区域形成控制电路102或布线结构106的情形，但通常在显示面板100中，接合垫104下方也可能会同时形成控制电路和/或布线结构106，在此不再进行赘述。另外，在显示面板100中还会形成电路板，电路板与接合垫104之间实现电性连接，以便通过接合垫104与显示面板100之间实现信号传输。
综上，依照本发明的实施例，由于接合垫形成在控制电路和/或布线结构的上方，即接合垫与控制电路和/或布线结构之间形成重叠区域，充分利用周边区域的垂直空间，接合垫与控制电路和/或布线结构存在共用的水平空间，因而，进一步缩小了显示面板周边区的宽度，能够更好地适应窄边框设计。同时，平坦层从显示面板的显示区延伸至周边区中，可以有效防止水气入侵显示区；而且，控制电路和布线结构之间不形成重叠区域，避免了两者之间的短路和信号干扰。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
工业应用性
采用本发明的显示面板，具有以下有益效果：
由于接合垫形成在控制电路和/或布线结构的上方，即接合垫与控制电路和/或布线结构之间形成重叠区域，充分利用周边区域的垂直空间，接合垫与控制电路和/或布线结构存在共用的水平空间，因而，进一步缩小了显示面板 周边区的宽度，能够更好地适应窄边框设计。同时，平坦层从显示面板的显示区延伸至周边区中，可以有效防止水气入侵显示区；而且，控制电路和布线结构之间不形成重叠区域，避免了两者之间的短路和信号干扰。

Claims (14)

  1. 一种显示面板，其特征在于，包括：
    一第一基板，包含相邻的一显示区与一周边区；
    多个像素单元，设置于所述第一基板，且位于所述显示区；
    一控制电路，设置于所述第一基板，且位于所述周边区，所述控制电路与所述像素单元电性连接；
    一平坦层，设置于所述第一基板，从所述显示区延伸至所述周边区，且覆盖所述像素单元及所述控制电路；
    一接合垫，设置于所述第一基板，且位于所述平坦层上方；
    其中，所述接合垫于所述第一基板的投影面积与所述控制电路于所述第一基板的投影面积有重叠区域。
  2. 根据权利要求1所述的显示面板，其特征在于，所述控制电路包含：
    一第一半导体层，设置于所述第一基板，且所述第一半导体层具有一第一掺杂区、一第二掺杂区与一第一沟道区，所述第一沟道区位于所述第一掺杂区与所述第二掺杂区之间；
    一栅极绝缘层，覆盖于所述第一半导体层；
    一第一金属层，设置于所述栅极绝缘层，且位置对应于所述第一沟道区；
    一第一绝缘层，覆盖于所述第一金属层；以及
    一第二金属层，设置于所述第一绝缘层，且连接于所述第一掺杂区或所述第二掺杂区；
    其中，所述平坦层覆盖于所述第一金属层、所述第二金属层与所述第一绝缘层。
  3. 根据权利要求2所述的显示面板，其特征在于，所述接合垫包含：
    一第三金属层，设置于所述平坦层上；
    一第二绝缘层，覆盖于所述第三金属层，且所述第二绝缘层中形成有一接合垫开口；以及
    一第四金属层，设置于所述接合垫开口，且连接于所述第三金属层。
  4. 根据权利要求3所述的显示面板，其特征在于，所述像素单元中包括多个薄膜晶体管，每一所述薄膜晶体管包含：
    一第二半导体层，设置于所述第一基板，且所述第二半导体层具有一第三掺杂区、一第四掺杂区与一第二沟道区，所述第二沟道区位于所述第三掺杂区与所述第四掺杂区之间，其中所述栅极绝缘层覆盖于所述第二半导体层；
    一栅极金属层，设置于所述栅极绝缘层，且位置对应于所述第二沟道区，且所述第一绝缘层覆盖于所述栅极金属层，其中所述栅极金属层与所述第一金属层的材料相同；
    一源极/漏极金属层，设置于所述第一绝缘层，且连接于所述第三掺杂区或所述第四掺杂区，且所述平坦层分别覆盖于所述源极/漏极金属层与所述第一绝缘层，所述第二绝缘层覆盖于所述平坦层，其中所述源极/漏极金属层与所述第二金属层的材料相同；
    一共享电极，设置于所述平坦层上；以及
    一像素电极，设置于所述第二绝缘层上，且电性连于所述源极/漏极金属层，其中所述像素电极与所述第四金属层的材料相同。
  5. 根据权利要求4所述的显示面板，其特征在于，更包括一布线结构，设置于所述周边区，所述布线结构包含：
    一第一布线金属层，设置于所述栅极绝缘层，其中所述第一布线金属层与所述第一金属层的材料相同，且所述第一绝缘层覆盖于部分所述第一布线金属层；以及
    一第二布线金属层，连接于所述第一布线金属层，其中所述第二布线金属层与所述第二金属层的材料相同；
    其中，所述显示面板更包括一第五金属层，设置于所述平坦层上方，且分别电性连接于所述第二布线金属层与所述接合垫，其中所述第五金属层与所述共享电极的材料相同。
  6. 根据权利要求5所述的显示面板，其特征在于，所述第四金属层、所述共享电极、所述像素电极或所述第五金属层可以是透明导电层。
  7. 根据权利要求6所述的显示面板，其特征在于，所述透明导电层可以是金属氧化物导电材料。
  8. 根据权利要求7所述的显示面板，其特征在于，所述金属氧化物导电材料可以是铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物。
  9. 根据权利要求1所述的显示面板，其特征在于，更包含一电路板，设置 于所述接合垫，且所述电路板电性连接于所述接合垫。
  10. 一种显示面板，其特征在于，包括：
    一第一基板，包含相邻的一显示区与一周边区；
    多个像素单元，设置于所述第一基板，且位于所述显示区；
    一布线结构，设置于所述第一基板，且位于所述周边区，所述布线结构与所述像素单元电性连接；
    一平坦层，设置于所述第一基板，从所述显示区延伸至所述周边区，且覆盖所述像素单元及所述布线结构；
    一接合垫，设置于所述第一基板，位于所述平坦层上方且与所述布线结构电性连接；
    其中，所述接合垫于所述第一基板的投影面积与所述布线结构于所述第一基板的投影面积有重叠区域。
  11. 根据权利要求10所述的显示面板，其特征在于，所述布线结构包含：
    一栅极绝缘层，设置于所述第一基板；
    一第一布线金属层，设置于所述栅极绝缘层；
    一第一绝缘层，覆盖于所述第一布线金属层；以及
    一第二布线金属层，设置于所述第一绝缘层，且连接于所述第一布线金属层。
  12. 根据权利要求10所述的显示面板，其特征在于，所述接合垫包含：
    一第三金属层，设置于所述平坦层上；
    一第二绝缘层，覆盖于所述第三金属层，且所述第二绝缘层中形成有一接合垫开口；
    一第四金属层，设置于所述接合垫开口，且连接于所述第三金属层。
  13. 根据权利要求12所述的显示面板，其特征在于，还包括一第五金属层，所述接合垫与所述布线结构通过所述第五金属层实现电性连接。
  14. 根据权利要求10所述的显示面板，其特征在于，更包含一电路板，设置于所述接合垫，且所述电路板电性连接于所述接合垫。
PCT/CN2019/112158 2019-10-16 2019-10-21 显示面板 WO2021072781A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/312,654 US11973086B2 (en) 2019-10-16 2019-10-21 Display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910981509.1 2019-10-16
CN201910981509.1A CN110707100B (zh) 2019-10-16 2019-10-16 显示面板

Publications (1)

Publication Number Publication Date
WO2021072781A1 true WO2021072781A1 (zh) 2021-04-22

Family

ID=69199752

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/112158 WO2021072781A1 (zh) 2019-10-16 2019-10-21 显示面板

Country Status (4)

Country Link
US (1) US11973086B2 (zh)
CN (1) CN110707100B (zh)
TW (1) TWI717925B (zh)
WO (1) WO2021072781A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220140048A1 (en) * 2020-03-31 2022-05-05 Boe Technology Group Co., Ltd. Display panel, method for preparing the same, and display device
CN113380863B (zh) * 2021-06-03 2022-10-25 云谷（固安）科技有限公司 显示面板及电子设备

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1773334A (zh) * 2004-11-12 2006-05-17 精工爱普生株式会社 电光装置和电子设备
CN101442060A (zh) * 2008-12-25 2009-05-27 友达光电股份有限公司 像素阵列及其制造方法
CN101971235A (zh) * 2008-03-04 2011-02-09 夏普株式会社 显示装置用基板、其制造方法、显示装置、多层配线的形成方法以及多层配线基板
US20120319144A1 (en) * 2010-02-23 2012-12-20 Sharp Kabushiki Kaisha Display panel and display device
CN107664883A (zh) * 2016-07-29 2018-02-06 株式会社日本显示器 显示装置
CN107819014A (zh) * 2017-10-25 2018-03-20 武汉华星光电技术有限公司 柔性显示面板及其制备方法
KR20190079227A (ko) * 2017-12-27 2019-07-05 엘지디스플레이 주식회사 표시 장치

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3699237B2 (ja) * 1996-03-13 2005-09-28 セイコーインスツル株式会社 半導体集積回路
JP3647650B2 (ja) 1998-08-06 2005-05-18 松下電器産業株式会社 Ｒｇｂカラーモニター装置
JP4708148B2 (ja) * 2005-10-07 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置
US8058137B1 (en) * 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8362482B2 (en) * 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
TWI718565B (zh) * 2009-09-10 2021-02-11 日商半導體能源研究所股份有限公司 半導體裝置和顯示裝置
US8148728B2 (en) * 2009-10-12 2012-04-03 Monolithic 3D, Inc. Method for fabrication of a semiconductor device and structure
WO2011071559A1 (en) * 2009-12-09 2011-06-16 Nano And Advanced Materials Institute Limited Method for manufacturing a monolithic led micro-display on an active matrix panel using flip-chip technology and display apparatus having the monolithic led micro-display
US8273610B2 (en) * 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US11107721B2 (en) * 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11443971B2 (en) * 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11211279B2 (en) * 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
KR101829313B1 (ko) * 2011-11-03 2018-02-20 삼성디스플레이 주식회사 플렉서블 디스플레이 장치
JP2014045175A (ja) * 2012-08-02 2014-03-13 Semiconductor Energy Lab Co Ltd 半導体装置
TWI525378B (zh) 2013-12-06 2016-03-11 友達光電股份有限公司 主動元件陣列基板和顯示面板
US10032757B2 (en) * 2015-09-04 2018-07-24 Hong Kong Beida Jade Bird Display Limited Projection display system
WO2017090477A1 (ja) * 2015-11-24 2017-06-01 シャープ株式会社 半導体装置および半導体装置の製造方法
KR20180062293A (ko) * 2016-11-30 2018-06-08 엘지디스플레이 주식회사 유기 발광 표시 장치
CN107039467B (zh) 2017-05-15 2020-03-06 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN107300793A (zh) 2017-06-30 2017-10-27 厦门天马微电子有限公司 显示面板及显示装置
TWI694294B (zh) 2017-07-25 2020-05-21 友達光電股份有限公司 陣列基板
KR102126553B1 (ko) * 2017-12-19 2020-06-24 엘지디스플레이 주식회사 표시 장치
KR102173434B1 (ko) * 2017-12-19 2020-11-03 엘지디스플레이 주식회사 표시 장치
DE112020000567A5 (de) * 2019-01-29 2021-12-02 Osram Opto Semiconductors Gmbh μ-LED, μ-LED ANORDNUNG, DISPLAY UND VERFAHREN ZU SELBEN
KR20210032614A (ko) * 2019-09-16 2021-03-25 삼성디스플레이 주식회사 표시 장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1773334A (zh) * 2004-11-12 2006-05-17 精工爱普生株式会社 电光装置和电子设备
CN101971235A (zh) * 2008-03-04 2011-02-09 夏普株式会社 显示装置用基板、其制造方法、显示装置、多层配线的形成方法以及多层配线基板
CN101442060A (zh) * 2008-12-25 2009-05-27 友达光电股份有限公司 像素阵列及其制造方法
US20120319144A1 (en) * 2010-02-23 2012-12-20 Sharp Kabushiki Kaisha Display panel and display device
CN107664883A (zh) * 2016-07-29 2018-02-06 株式会社日本显示器 显示装置
CN107819014A (zh) * 2017-10-25 2018-03-20 武汉华星光电技术有限公司 柔性显示面板及其制备方法
KR20190079227A (ko) * 2017-12-27 2019-07-05 엘지디스플레이 주식회사 표시 장치

Also Published As

Publication number Publication date
CN110707100B (zh) 2021-12-31
US20220052077A1 (en) 2022-02-17
TWI717925B (zh) 2021-02-01
US11973086B2 (en) 2024-04-30
CN110707100A (zh) 2020-01-17
TW202117693A (zh) 2021-05-01

Similar Documents

Publication Publication Date Title
US10481717B2 (en) Display device
WO2019227806A1 (zh) Tft阵列基板及液晶显示面板
KR102313366B1 (ko) 플렉서블 디스플레이 장치와, 이의 제조 방법
WO2020133714A1 (zh) 显示面板及显示模组、电子装置
WO2020118823A1 (zh) 显示面板及具有该显示面板的显示装置
WO2016110036A1 (zh) 阵列基板及显示装置
US20220028933A1 (en) Array substrate and display device
CN109991788B (zh) 显示面板及显示装置
US11287709B2 (en) Active matrix substrate and liquid crystal display device
US20230367160A1 (en) Display panel and preparing method thereof
US20190146291A1 (en) Array substrate, repair method thereof, and display device
WO2021184506A1 (zh) 液晶显示面板
TWI628498B (zh) 顯示裝置及其顯示面板
CN112735262A (zh) 显示基板及其制作方法、和显示装置
WO2021072781A1 (zh) 显示面板
US20220223627A1 (en) Display panel
WO2019184070A1 (zh) 显示装置及其阵列基板
JP3196528U (ja) 表示パネル
WO2021248453A1 (zh) 显示面板及其制作方法和显示装置
WO2024124840A1 (zh) 显示面板
JP7397556B2 (ja) ディスプレイパネル及び表示装置
US11126290B2 (en) Pixel array substrate and method of driving the same
TWI707262B (zh) 觸控顯示面板
US11437546B2 (en) Display panel and display module
WO2023029004A1 (zh) 触控显示面板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19949131

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19949131

Country of ref document: EP

Kind code of ref document: A1