WO2019227806A1 - Tft阵列基板及液晶显示面板 - Google Patents

Tft阵列基板及液晶显示面板 Download PDF

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Publication number
WO2019227806A1
WO2019227806A1 PCT/CN2018/108019 CN2018108019W WO2019227806A1 WO 2019227806 A1 WO2019227806 A1 WO 2019227806A1 CN 2018108019 W CN2018108019 W CN 2018108019W WO 2019227806 A1 WO2019227806 A1 WO 2019227806A1
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fan
lines
layer
metal layer
line
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PCT/CN2018/108019
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English (en)
French (fr)
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李亚锋
邬金芳
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武汉华星光电技术有限公司
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Priority to US16/308,483 priority Critical patent/US20210124206A1/en
Publication of WO2019227806A1 publication Critical patent/WO2019227806A1/zh

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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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Definitions

  • the present invention relates to the field of display technology, and in particular, to a TFT array substrate and a liquid crystal display panel.
  • liquid crystal display LCD
  • organic light-emitting diode OLED
  • CRT cathode-ray tube
  • a liquid crystal display panel includes a color filter (CF) substrate, a thin film transistor (TFT) array substrate, a liquid crystal (LC) and a sealant sandwiched between the color film substrate and the thin film transistor array substrate.
  • Frame (Sealant) composition The working principle of a liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many small vertical and horizontal wires in the middle of the two glass substrates. The liquid crystal molecules are controlled to change direction by turning on or off, and the light of the backlight module is changed. Refracted to produce a picture.
  • FIG. 1 is a schematic cross-sectional structure view of a conventional TFT array substrate.
  • the TFT array substrate includes a substrate 31, a light shielding layer 32 provided on the substrate 31, a bottom insulating layer 33 covering the light shielding layer 32, An active layer 34 provided on the bottom insulating layer 33, a gate insulating layer 35 covering the active layer 34, a first metal layer provided on the gate insulating layer 35, and an interlayer insulating layer 37 covering the first metal layer A second metal layer provided on the interlayer insulating layer 37, a planarization layer 39 covering the second metal layer, a third metal layer provided on the planarization layer 39, a top insulating layer 311 covering the third metal layer,
  • the gate 36, the second metal layer includes source and drain 38, and a plurality of data
  • the fan-out area of the TFT array substrate shown in FIG. 1 includes a plurality of first fan-out lines 301, a second fan-out line 302, and a third fan-out line 303.
  • the plurality of first fan-out lines 301 are all located in the first metal layer.
  • the second fan-out lines 302 are all located in the second metal layer, the multiple first fan-out lines 301 and the multiple second fan-out lines 302 are respectively electrically connected to multiple data lines, and the multiple third fan-out lines 303 are all located in the third metal layer.
  • the plurality of third fan-out lines 303 are electrically connected to the plurality of touch traces 310, respectively.
  • the output line 302 and the third fan-out line 303 can be overlapped, which can reduce the size of the fan-out area to a certain extent to achieve a narrow frame.
  • the TFT array substrate needs to use 12 masks during production. The production process is complicated and costly.
  • the TFT array substrate includes a substrate 81 and a substrate 81 disposed on the substrate 81.
  • the data lines are used to transmit data signals, and the touch traces 882 are used to transmit touch signals.
  • the common electrode 810 passes through vias in the planarization layer 89. Connected to touch trace 882.
  • the number of masks required to make the TFT array substrate shown in FIG. 3 is 10, which can reduce the number of masks.
  • the fan-out area of the TFT array substrate shown in FIG. 3 includes a plurality of masks.
  • the first fan-out line 801 is located on the first metal layer
  • the second fan-out line 802 is located on the second metal layer.
  • Multiple first fan-out lines 801 are electrically connected to multiple data lines and Multiple second fan-out lines 802 are electrically connected to multiple touch traces 872, respectively, or multiple second fan-out lines 802 are electrically connected to multiple data lines and multiple first fan-out lines 801 are respectively electrically connected to multiple contacts Control the routing 882.
  • the fan-out lines connecting multiple data lines are located on the same metal layer and cannot overlap each other, making it impossible to compress the size of the fan-out routing area, and the larger the pixel density (PPI The more obvious the problem that the size of the fan-out routing area cannot be compressed, restricts the development of the display panel toward the narrow border.
  • An object of the present invention is to provide a TFT array substrate with a small size of a fan-out wiring area, which is beneficial to realize a narrow frame.
  • Another object of the present invention is to provide a liquid crystal display panel.
  • the size of the fan-out routing area is small, which is beneficial to realize a narrow frame.
  • the present invention first provides a TFT array substrate including a substrate, a first metal layer provided above the substrate, a first interlayer insulating layer covering the first metal layer, and a first interlayer insulation provided. A second metal layer on the layer, a second interlayer insulating layer covering the second metal layer, and a third metal layer provided on the second interlayer insulating layer;
  • the substrate includes an effective display area and a fan-out routing area which are sequentially arranged;
  • the first metal layer includes a plurality of first fan-out lines located in the fan-out routing area; and the second metal layer includes the active display area Multiple touch traces and multiple second fan-out traces in a fan-out trace area;
  • the third metal layer includes multiple data lines in an effective display area and multiple first-out traces in a fan-out trace area Three fan-out lines
  • Multiple first fan-out lines and multiple second fan-out lines are respectively electrically connected to multiple data lines, and multiple third fan-out lines are respectively electrically connected to multiple touch traces; or,
  • Multiple first fan-out lines and multiple third fan-out lines are respectively electrically connected to multiple data lines, and multiple second fan-out lines are respectively electrically connected to multiple touch traces; or,
  • the plurality of second fan-out lines and the plurality of third fan-out lines are respectively electrically connected to a plurality of data lines, and the plurality of first fan-out lines are respectively electrically connected to a plurality of touch lines.
  • Multiple first fan-out lines and multiple second fan-out lines are respectively electrically connected to multiple data lines, and multiple third fan-out lines are respectively electrically connected to multiple touch traces;
  • Each first fan-out line corresponds to a data line.
  • the first interlayer insulation layer and the second interlayer insulation layer are provided with a plurality of first vias above the plurality of first fan-out lines.
  • the fan-out line and its corresponding data line are connected through a first via;
  • Each second fan-out line corresponds to a data line
  • the second interlayer insulation layer is provided with a plurality of second vias above the plurality of second fan-out lines, and the second fan-out line and its corresponding data line Connected via a second via;
  • Each third fan-out line corresponds to a touch trace
  • the third interlayer insulation layer is provided with a plurality of third vias over the plurality of touch traces
  • the third fan-out line corresponds to The touch traces are connected via a third via.
  • the plurality of first fan-out lines and the plurality of second fan-out lines are used to access data signals, and the plurality of third fan-out lines are used to access touch signals.
  • Multiple first fan-out lines and multiple third fan-out lines are electrically connected to multiple data lines, respectively, and multiple second fan-out lines are electrically connected to multiple touch traces;
  • Each first fan-out line corresponds to a data line.
  • the first interlayer insulation layer and the second interlayer insulation layer are provided with a plurality of first vias above the plurality of first fan-out lines.
  • the fan-out line and its corresponding data line are connected through a first via;
  • Each third fan-out line is correspondingly connected to a data line
  • Each second fan-out line is correspondingly connected to a touch trace.
  • the plurality of first fan-out lines and the plurality of third fan-out lines are used to access data signals, and the plurality of second fan-out lines are used to access touch signals.
  • Multiple second fan-out lines and multiple third fan-out lines are respectively electrically connected to multiple data lines, and multiple first fan-out lines are respectively electrically connected to multiple touch traces;
  • Each second fan-out line corresponds to a data line
  • the second interlayer insulation layer is provided with a plurality of second vias above the plurality of second fan-out lines, and the second fan-out line and its corresponding data line Connected via a second via;
  • Each third fan-out line is correspondingly connected to a data line
  • Each first fan-out line corresponds to one touch trace
  • the second interlayer insulation layer is provided with a plurality of fourth vias above the plurality of touch traces.
  • the first interlayer insulation layer and The second interlayer insulating layer is provided with a plurality of fifth vias located above the plurality of first fan-out lines;
  • the third metal layer further includes a plurality of connection traces corresponding to the plurality of touch traces respectively; each A connection trace connects the corresponding touch trace and the first fan-out line corresponding to the touch trace via the fourth via and the fifth via.
  • the plurality of second fan-out lines and the plurality of third fan-out lines are used to access data signals, and the plurality of first fan-out lines are used to access touch signals.
  • the TFT array substrate further includes an active layer over the substrate and a gate insulating layer covering the active layer; the first metal layer is disposed on the gate insulating layer;
  • the TFT array substrate further includes a planarization layer covering the third metal layer, a common electrode layer disposed on the planarization layer, a passivation layer covering the common electrode layer, and a pixel electrode layer disposed on the passivation layer;
  • the active layer includes a plurality of semiconductor patterns located in an effective display area
  • the first metal layer further includes a plurality of gates located in the effective display area and correspondingly located over the plurality of semiconductor patterns;
  • the third metal layer further includes a plurality of source electrodes and a plurality of drain electrodes respectively located in the effective display area and corresponding to the plurality of gate electrodes, and a plurality of connection electrodes located in the effective display area;
  • the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer are provided with sixth via holes above both ends of the plurality of semiconductor patterns; the source and drain electrodes corresponding to a peninsula pattern are respectively Connected to both ends of the semiconductor pattern through sixth vias above both ends of the semiconductor pattern;
  • the second interlayer insulating layer is provided with a plurality of seventh vias above the plurality of touch traces, and each connection electrode is connected to a touch trace via the seventh vias;
  • the planarization layer is provided with a plurality of eighth via holes above the plurality of connection electrodes;
  • the common electrode layer includes a plurality of spaced common electrodes, and each common electrode is connected to a connection electrode via the eighth via hole;
  • the planarization layer and the passivation layer are provided with a plurality of ninth vias located above the plurality of drain electrodes; the pixel electrode layer includes a plurality of spaced pixel electrodes, and each pixel electrode passes through the ninth via and a pixel electrode. Drain connection
  • a material of the first interlayer insulating layer is silicon nitride
  • a material of the second interlayer insulating layer is silicon oxide
  • a material of the gate insulating layer is silicon oxide
  • a material of the common electrode layer is indium tin oxide
  • a material of the pixel electrode layer is indium tin oxide
  • the material of the second metal layer is titanium or molybdenum.
  • the TFT array substrate further includes a light shielding layer provided on the substrate and a bottom insulating layer covering the light shielding layer; the active layer is provided on the bottom insulating layer.
  • the present invention also provides a liquid crystal display panel including the above-mentioned TFT array substrate.
  • a TFT array substrate provided by the present invention includes a first metal layer, a first interlayer insulating layer, a second metal layer, a second interlayer insulating layer, and a third metal disposed in this order on the substrate.
  • the first metal layer includes a plurality of first fan-out lines in a fan-out routing area
  • the second metal layer includes a plurality of second fan-out lines in a fan-out routing area
  • the third metal layer includes a fan-out routing area
  • two groups of the first fan-out line, the second fan-out line, and the third fan-out line are connected to the data line, and the other group is connected to the touch line.
  • a first interlayer insulation layer is provided between the fanout lines, and a second interlayer insulation layer is provided between the third fanout line and the second fanout line, so that the first fanout line, the second fanout line, and the third fanout line can be intersected.
  • the stacked arrangement can effectively reduce the area of the fan-out routing area and help achieve a narrow border.
  • the size of the fan-out routing area of a liquid crystal display panel provided by the present invention is small, which is beneficial to realize a narrow frame.
  • 1 is a partial cross-sectional view of a conventional TFT array substrate
  • FIG. 2 is a top view of a first fan-out line, a second fan-out line, and a third fan-out line of the TFT array substrate shown in FIG. 1;
  • FIG. 3 is a partial cross-sectional view of another conventional TFT array substrate
  • FIG. 4 is a top view of a first fan-out line and a second fan-out line of the TFT array substrate shown in FIG. 2;
  • FIG. 5 is a schematic top view of a substrate, a first metal layer, a second metal layer, and a third metal layer of a first embodiment of a TFT array substrate according to the present invention
  • FIG. 6 is a partial cross-sectional view of a TFT array substrate of the present invention in an effective display area
  • FIG. 7 is a schematic cross-sectional view of a first embodiment and a second embodiment of a TFT array substrate of the present invention at a connection between a first fan-out line and a corresponding data line;
  • FIG. 8 is a schematic cross-sectional view of a first embodiment and a third embodiment of a TFT array substrate of the present invention at a connection between a second fan-out line and its corresponding data line;
  • FIG. 9 is a schematic cross-sectional view of a first embodiment of a TFT array substrate of the present invention at a connection point between a third fan-out line and a corresponding touch line;
  • FIG. 10 is a schematic top view of a substrate, a first metal layer, a second metal layer, and a third metal layer of a second embodiment of a TFT array substrate according to the present invention
  • FIG. 11 is a schematic top view of a substrate, a first metal layer, a second metal layer, and a third metal layer of a third embodiment of a TFT array substrate according to the present invention
  • FIG. 12 is a schematic cross-sectional view of a third embodiment of a TFT array substrate of the present invention at a connection between a first fan-out line and a corresponding touch line.
  • a first embodiment of a TFT array substrate of the present invention includes a substrate 100, a first metal layer 200 provided above the substrate 100, and a first interlayer insulating layer covering the first metal layer 200. 300.
  • the substrate 100 includes an effective display area 110 and a fan-out routing area 120 which are sequentially arranged.
  • the first metal layer 200 includes a plurality of first fan-out lines 220 located in the fan-out routing area 120.
  • the second metal layer 400 includes a plurality of touch lines 410 located in the effective display area 110 and a plurality of second fan-out lines 420 located in the fan-out line area 120.
  • the third metal layer 600 includes a plurality of data lines 610 located in the effective display area 110 and a plurality of third fan-out lines 620 located in the fan-out routing area 120.
  • the plurality of first fan-out lines 220 and the plurality of second fan-out lines 420 are respectively electrically connected to the plurality of data lines 610, and the plurality of third fan-out lines 620 are respectively electrically connected to the plurality of touch lines 410.
  • each first fan-out line 220 corresponds to a data line 610.
  • the first interlayer insulating layer 300 and the second interlayer insulating layer 500 are provided on a plurality of The plurality of first vias 510 above the first fan-out line 220 are connected to the corresponding data line 610 via the first vias 510.
  • each second fan-out line 420 corresponds to a data line 610, and the second interlayer insulation layer 500 is provided with a plurality of second overlying second fan-out lines 420. Via hole 520, the second fan-out line 420 and its corresponding data line 610 are connected through the second via hole 520.
  • each third fan-out line 620 corresponds to one touch line 410.
  • the second interlayer insulation layer 500 is provided with a plurality of above the plurality of touch lines 410.
  • the third via 530, the third fan-out line 620 and its corresponding touch trace 410 are connected via the third via 530.
  • the plurality of first fan-out lines 220 and the plurality of second fan-out lines 420 are used to access data signals, and the plurality of third fan-out lines 620 are used to access Touch signal.
  • the TFT array substrate of the present invention further includes an active layer 700 over the substrate 100 and a gate insulating layer 800 covering the active layer 700.
  • the first metal layer 200 is disposed on the gate insulating layer 800.
  • the TFT array substrate further includes a planarization layer 900 covering the third metal layer 600, a common electrode layer 1000 provided on the planarization layer 900, a passivation layer 1100 covering the common electrode layer 1000, and a passivation layer 1100.
  • a planarization layer 900 covering the third metal layer 600
  • a common electrode layer 1000 provided on the planarization layer 900
  • a passivation layer 1100 covering the common electrode layer 1000
  • a passivation layer 1100 covering the common electrode layer 1000
  • a passivation layer 1100 covering the common electrode layer 1000
  • a passivation layer 1100 covering the common electrode layer 1000
  • a passivation layer 1100 covering the pixel electrode layer 1200.
  • the active layer 700 includes a plurality of semiconductor patterns 710 located in the effective display area 110.
  • the first metal layer 200 further includes a plurality of gates 230 located in the effective display area 110 and correspondingly located over the plurality of semiconductor patterns 710.
  • the third metal layer 600 further includes a plurality of source electrodes 630 and a plurality of drain electrodes 640 located in the effective display area 110 and corresponding to the plurality of gate electrodes 230, respectively, and a plurality of connection electrodes 650 located in the effective display area 110.
  • the gate insulating layer 800, the first interlayer insulating layer 300, and the second interlayer insulating layer 500 are provided with sixth via holes 560 located above both ends of the plurality of semiconductor patterns 710.
  • a source electrode 630 and a drain electrode 640 corresponding to a peninsula body pattern 710 are respectively connected to both ends of the semiconductor pattern 710 through sixth via holes 560 above both ends of the semiconductor pattern 710.
  • the second interlayer insulating layer 500 is provided with a plurality of seventh vias 570 located above the plurality of touch traces 410.
  • Each connection electrode 650 is connected to a touch trace 410 via the seventh vias 570.
  • the planarization layer 900 is provided with a plurality of eighth via holes 910 above the plurality of connection electrodes 650.
  • the common electrode layer 1000 includes a plurality of spaced common electrodes 1010, and each common electrode 1010 is connected to a connection electrode 650 via an eighth via 910.
  • the planarization layer 900 and the passivation layer 1100 are provided with a plurality of ninth via holes 920 above the plurality of drain electrodes 640.
  • the pixel electrode layer 1200 includes a plurality of spaced pixel electrodes 1210, and each pixel electrode 1210 is connected to a drain electrode 640 through a ninth via 920.
  • a material of the first interlayer insulating layer 300 is silicon nitride (SiNx).
  • the material of the second interlayer insulating layer 500 is silicon oxide (SiOx).
  • a material of the gate insulating layer 800 is silicon oxide.
  • a material of the common electrode layer 1000 is indium tin oxide (ITO).
  • a material of the pixel electrode layer 1200 is indium tin oxide.
  • a material of the second metal layer 400 is titanium (Ti) or molybdenum (Mo).
  • the TFT array substrate further includes a light shielding layer 1300 provided on the substrate 100 and a bottom insulating layer 1400 covering the light shielding layer 1300.
  • the active layer 700 is disposed on the bottom insulating layer 1400.
  • the bottom insulating layer 1400 is formed by laminating a silicon nitride layer and a silicon oxide layer.
  • the second embodiment of the TFT array substrate of the present invention is different from the first embodiment described above in that a plurality of first fan-out lines 220 and a plurality of third fan-out lines 620 are respectively.
  • the plurality of data lines 610 are electrically connected, and the plurality of second fan-out lines 420 are electrically connected to the plurality of touch lines 410, respectively.
  • each first fan-out line 220 corresponds to a data line 610.
  • the first interlayer insulation layer 300 and the second interlayer insulation layer 500 are provided on a plurality of lines.
  • the plurality of first vias 510 above the first fan-out line 220 are connected to the corresponding data line 610 via the first vias 510.
  • each third fan-out line 620 is correspondingly connected to a data line 610.
  • each second fan-out line 420 is correspondingly connected to a touch line 410.
  • the plurality of first fan-out lines 220 and the plurality of third fan-out lines 620 are used for accessing data signals, and the plurality of second fan-out lines 420 are used for access Touch signal.
  • the third embodiment of the TFT array substrate of the present invention is different from the first embodiment described above in that a plurality of second fan-out lines 420 and a plurality of third fans
  • the outgoing lines 620 are electrically connected to a plurality of data lines 610
  • the first fan-out lines 220 are electrically connected to a plurality of touch lines 410, respectively.
  • each second fan-out line 420 corresponds to a data line 610, and a plurality of second fan-out lines 420 are provided on the second interlayer insulation layer 500. Second vias 520, the second fan-out lines 420 and their corresponding data lines 610 are connected via the second vias 520.
  • each third fan-out line 620 is correspondingly connected to a data line 610.
  • Each first fan-out line 220 corresponds to a touch line 410.
  • the second interlayer insulation layer 500 is provided with a plurality of fourth lines above the plurality of touch lines 410. Vias 540.
  • the first interlayer insulation layer 300 and the second interlayer insulation layer 500 are provided with a plurality of fifth vias 550 located above the plurality of first fan-out lines 220.
  • the third metal layer 600 further includes a plurality of connection traces 630 respectively corresponding to the plurality of touch traces 410. Each connection trace 630 connects the corresponding touch trace 410 and the first fan-out line 220 corresponding to the touch trace 410 through the fourth via 540 and the fifth via 550.
  • the plurality of second fan-out lines 420 and the plurality of third fan-out lines 620 are used to access data signals, and the plurality of first fan-out lines 220 are used to access Touch signal.
  • a plurality of first fan-out lines 220 located in the fan-out routing area 120 are provided in the first metal layer 200, and a fan-out routing area 120 is provided in the second metal layer 400.
  • a plurality of third fan-out lines 620 located in the fan-out routing area 120 are arranged in the third metal layer 600, and the first fan-out line 220, the second fan-out line 420, and the third Two groups of the fan-out line 620 are connected to the data line 610, and the other group is connected to the touch trace 410.
  • the third A second interlayer insulating layer 500 is provided between the fan-out line 620 and the second fan-out line 420, so that the first fan-out line 220, the second fan-out line 420, and the third fan-out line 620 can be overlapped, that is, the data line
  • the 610-connected fan-out lines can be located in different metal layers. Compared with the prior art, where the fan-out lines connected to the data lines are set in the same metal layer, the present invention can effectively reduce the area of the fan-out routing area. Helps achieve narrow borders.
  • the second metal layer 400 where the second fan-out line 420 and the touch trace 410 are located in the present invention is disposed between the first metal layer 200 and the third metal layer 600 where the data line 610 is located, compared with In the prior art, the metal layer where the touch trace is located is disposed above the metal layer where the data line is located, and a top interlayer insulating layer is provided above the touch trace and patterned.
  • the present invention can reduce one light during fabrication. The hood process can simplify the manufacturing process and reduce costs.
  • the present invention also provides a liquid crystal display panel including the above-mentioned TFT array substrate, and the structure of the array substrate will not be described repeatedly here.
  • a plurality of first fan-out lines 220 located in the fan-out routing area 120 are provided in the first metal layer 200 and provided in the second metal layer 400.
  • a plurality of second fan-out lines 420 are located in the fan-out routing area 120.
  • a plurality of third fan-out lines 620 are located in the fan-out routing area 120 in the third metal layer 600, and the first fan-out lines 220 and the second Two groups of the fan-out line 420 and the third fan-out line 620 are connected to the data line 610, and the other group is connected to the touch line 410.
  • a second interlayer insulating layer 500 is provided between the insulating layer 300, the third fan-out line 620 and the second fan-out line 420, so that the first fan-out line 220, the second fan-out line 420, and the third fan-out line 620 can be overlapped. That is, the fan-out lines connected to the data line 610 can be located in different metal layers. Compared with the prior art, where the fan-out lines connected to the data line are set in the same metal layer, the present invention can effectively reduce the fan-out. The area of the line area helps to achieve a narrow border.
  • the second metal layer 400 where the second fan-out line 420 and the touch trace 410 are located in the present invention is disposed between the first metal layer 200 and the third metal layer 600 where the data line 610 is located, compared with In the prior art, the metal layer where the touch trace is located is disposed above the metal layer where the data line is located, and a top interlayer insulating layer is provided above the touch trace and patterned.
  • the present invention can reduce a light during production
  • the hood process can simplify the manufacturing process and reduce costs.
  • the TFT array substrate of the present invention includes a first metal layer, a first interlayer insulating layer, a second metal layer, a second interlayer insulating layer, and a third metal layer, which are sequentially disposed above the substrate.
  • the metal layer includes a plurality of first fan-out lines located in the fan-out routing area
  • the second metal layer includes a plurality of second fan-out lines located in the fan-out routing area
  • the third metal layer includes a plurality of fan-out lines located in the fan-out routing area.
  • the third fan-out line, two groups of the first fan-out line, the second fan-out line, and the third fan-out line are connected to the data line, and the other group is connected to the touch line, because the first fan-out line and the second fan-out line
  • a first interlayer insulation layer is provided, and a second interlayer insulation layer is provided between the third fan-out line and the second fan-out line, so that the first fan-out line, the second fan-out line, and the third fan-out line can be overlapped and can be arranged. Effectively reducing the area of the fan-out routing area helps to achieve a narrow border.
  • the size of the fan-out routing area of a liquid crystal display panel provided by the present invention is small, which is beneficial to realize a narrow frame.

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Abstract

本发明提供一种TFT阵列基板及液晶显示面板。该TFT阵列基板包括于衬底上方依次设置的第一金属层、第一层间绝缘层、第二金属层、第二层间绝缘层及第三金属层，第一金属层包括位于扇出走线区内的多条第一扇出线，第二金属层包括位于扇出走线区内的多条第二扇出线，第三金属层包括位于扇出走线区内的多条第三扇出线，第一扇出线、第二扇出线、第三扇出线中的两组与数据线连接，另一组与触控走线连接，由于第一扇出线与第二扇出线之间设有第一层间绝缘层，第三扇出线与第二扇出线之间设有第二层间绝缘层，从而第一扇出线、第二扇出线、第三扇出线可以交叠设置，能够有效地减小扇出走线区的面积，有助于实现窄边框。

Description

TFT阵列基板及液晶显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及液晶显示面板。
背景技术
在显示技术领域，液晶显示装置(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube，CRT)显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组(backlight module)。通常液晶显示面板由彩膜(Color Filter，CF)基板、薄膜晶体管(Thin Film Transistor，TFT)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(Liquid Crystal，LC)及密封胶框(Sealant)组成。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
请参阅图1，为现有的一种TFT阵列基板的剖视结构示意图，该TFT阵列基板包括衬底31、设于衬底31上的遮光层32、覆盖遮光层32的底层绝缘层33、设于底层绝缘层33上的有源层34、覆盖有源层34的栅极绝缘层35、设于栅极绝缘层35上的第一金属层、覆盖第一金属层的层间绝缘层37、设于层间绝缘层37上的第二金属层、覆盖第二金属层的平坦化层39、设于平坦化层39上的第三金属层、覆盖第三金属层的顶层绝缘层311、设于顶层绝缘层311上的公共电极312、设于公共电极312上的钝化层313以及设于钝化层313上的像素电极314，其中，第一金属层包括位于有源层34上方的栅极36，第二金属层包括源漏极38及多条数据线，数据线用于传输数据信号，第三金属层包括触控走线310，触控走线310用于传输触控信号，公共电极312经顶层绝缘层311上的过孔与触控走线319连接，请参阅图2，图1所示的TFT阵列基板的扇出区域内，包括多条第一扇出线301、第二扇出线302及第三扇出线303，多条第一扇出线301均位于第一金属层，多条第二扇出线302均位于第二金属层，多条第一扇出线301及 多条第二扇出线302分别电性连接多条数据线，多条第三扇出线303均位于第三金属层，多条第三扇出线303分别电性连接多条触控走线310，由于第一金属层、第二金属层及第三金属层相互之间均绝缘，因此第一扇出线301、第二扇出线302及第三扇出线303之间可以交叠，能在一定程度上减小扇出区域的尺寸而实现窄边框，然而，该TFT阵列基板在制作时需要利用到12道光罩(mask)，制作过程较为复杂，成本较高。
为了减少光罩数目及制程的复杂程度以降低产品成本，如图3所示，现有技术提出了另一种TFT阵列基板，包括该TFT阵列基板包括衬底81、设于衬底81上的遮光层82、覆盖遮光层82的底层绝缘层83、设于底层绝缘层83上的有源层84、覆盖有源层84的栅极绝缘层85、设于栅极绝缘层85上的第一金属层、覆盖第一金属层85的层间绝缘层87、设于层间绝缘层87上的第二金属层、覆盖第二金属层的平坦化层89、设于平坦化层89上的公共电极810、设于公共电极810上的钝化层811以及设于钝化层811上的像素电极812，其中，第一金属层包括位于有源层84上方的栅极86，第二金属层包括源漏极881、多条数据线及多条触控走线882，数据线用于传输数据信号，触控走线882用于传输触控信号，公共电极810经平坦化层89上的过孔与触控走线882连接。制作图3所示的TFT阵列基板需要的光罩(mask)数目为10道，能够减少光罩数目，然而请参阅图4，图3所示的TFT阵列基板的扇出区域内，包括多条第一扇出线801、第二扇出线802，第一扇出线801位于第一金属层，第二扇出线802位于第二金属层，多条第一扇出线801分别电性连接多条数据线且多条第二扇出线802分别电性连接多条触控走线872，或者多条第二扇出线802分别电性连接多条数据线且多条第一扇出线801分别电性连接多条触控走线882，无论哪种方式，连接多条数据线的扇出线都位于同一金属层，互相之间无法交叠，使得无法对扇出走线区的尺寸进行压缩，且像素密度越大(PPI)无法压缩扇出走线区尺寸的问题越明显，限制了显示面板朝窄边框的方向发展。
发明内容
本发明的目的在于提供一种TFT阵列基板，扇出走线区的尺寸小，有利于实现窄边框。
本发明的另一目的在于提供一种液晶显示面板，扇出走线区的尺寸小，有利于实现窄边框。
为实现上述目的，本发明首先提供一种TFT阵列基板，包括衬底、设于衬底上方的第一金属层、覆盖第一金属层的第一层间绝缘层、设于第一 层间绝缘层上的第二金属层、覆盖第二金属层的第二层间绝缘层以及设于第二层间绝缘层上的第三金属层；
所述衬底包括依次设置的有效显示区及扇出走线区；所述第一金属层包括位于扇出走线区内的多条第一扇出线；所述第二金属层包括位于有效显示区内的多条触控走线以及位于扇出走线区内的多条第二扇出线；所述第三金属层包括位于有效显示区内的多条数据线以及位于扇出走线区内的多条第三扇出线；
多条第一扇出线及多条第二扇出线分别电性连接多条数据线，多条第三扇出线分别电性连接多条触控走线；或者，
多条第一扇出线及多条第三扇出线分别电性连接多条数据线，多条第二扇出线分别电性连接多条触控走线；或者，
多条第二扇出线及多条第三扇出线分别电性连接多条数据线，多条第一扇出线分别电性连接多条触控走线。
多条第一扇出线及多条第二扇出线分别电性连接多条数据线，多条第三扇出线分别电性连接多条触控走线；
每一条第一扇出线与一条数据线对应，所述第一层间绝缘层及第二层间绝缘层上设有位于多条第一扇出线上方的多个第一过孔，所述第一扇出线与其对应的数据线经第一过孔连接；
每一条第二扇出线与一条数据线对应，所述第二层间绝缘层上设有位于多条第二扇出线上方的多个第二过孔，所述第二扇出线与其对应的数据线经第二过孔连接；
每一第三扇出线与一条触控走线对应，所述第二层间绝缘层上设有位于多条触控走线上方的多个第三过孔，所述第三扇出线与其对应的触控走线经第三过孔连接。
所述多条第一扇出线及多条第二扇出线用于接入数据信号，所述多条第三扇出线用于接入触控信号。
多条第一扇出线及多条第三扇出线分别电性连接多条数据线，多条第二扇出线分别电性连接多条触控走线；
每一条第一扇出线与一条数据线对应，所述第一层间绝缘层及第二层间绝缘层上设有位于多条第一扇出线上方的多个第一过孔，所述第一扇出线与其对应的数据线经第一过孔连接；
每一条第三扇出线与一条数据线对应连接；
每一条第二扇出线与一条触控走线对应连接。
所述多条第一扇出线及多条第三扇出线用于接入数据信号，所述多条 第二扇出线用于接入触控信号。
多条第二扇出线及多条第三扇出线分别电性连接多条数据线，多条第一扇出线分别电性连接多条触控走线；
每一条第二扇出线与一条数据线对应，所述第二层间绝缘层上设有位于多条第二扇出线上方的多个第二过孔，所述第二扇出线与其对应的数据线经第二过孔连接；
每一条第三扇出线与一条数据线对应连接；
每一条第一扇出线与一条触控走线对应，所述第二层间绝缘层上设有位于多条触控走线上方的多个第四过孔，所述第一层间绝缘层及第二层间绝缘层上设有位于多条第一扇出线上方的多个第五过孔；所述第三金属层还包括分别与多条触控走线对应的多条连接走线；每一连接走线经第四过孔及第五过孔将对应的触控走线及该触控走线对应的第一扇出线连接。
所述多条第二扇出线及多条第三扇出线用于接入数据信号，所述多条第一扇出线用于接入触控信号。
所述TFT阵列基板还包括于衬底上方的有源层及覆盖有源层的栅极绝缘层；所述第一金属层设于栅极绝缘层上；
所述TFT阵列基板还包括覆盖第三金属层的平坦化层、设于平坦化层上的公共电极层、覆盖公共电极层的钝化层以及设于钝化层上的像素电极层；
所述有源层包括位于有效显示区内的多个半导体图案；
所述第一金属层还包括位于有效显示区内且对应位于多个半导体图案上方的多个栅极；
所述第三金属层还包括位于有效显示区内且分别与多个栅极对应的多个源极及多个漏极以及位于有效显示区内的多个连接电极；
所述栅极绝缘层、第一层间绝缘层及第二层间绝缘层上设有位于多个半导体图案两端上方的第六过孔；与一半岛体图案对应的源极及漏极分别经该半导体图案两端上方的第六过孔与该半导体图案的两端连接；
所述第二层间绝缘层上设有位于多条触控走线上方的多个第七过孔，每一连接电极经第七过孔与一触控走线连接；
所述平坦化层上设有位于多个连接电极上方的多个第八过孔；所述公共电极层包括多个间隔的公共电极，每一公共电极经第八过孔与一连接电极连接；
所述平坦化层及钝化层上设有位于多个漏极上方的多个第九过孔；所述像素电极层包括多个间隔的像素电极，每一像素电极经第九过孔与一漏 极连接；
所述第一层间绝缘层的材料为氮化硅；
所述第二层间绝缘层的材料为氧化硅；
所述栅极绝缘层的材料为氧化硅；
所述公共电极层的材料为氧化铟锡；
所述像素电极层的材料为氧化铟锡；
所述第二金属层的材料为钛或钼。
所述TFT阵列基板还包括设于衬底上的遮光层及覆盖遮光层的底层绝缘层；所述有源层设于底层绝缘层上。
本发明还提供一种液晶显示面板，包括上述的TFT阵列基板。
本发明的有益效果：本发明提供的一种TFT阵列基板包括于衬底上方依次设置的第一金属层、第一层间绝缘层、第二金属层、第二层间绝缘层及第三金属层，第一金属层包括位于扇出走线区内的多条第一扇出线，第二金属层包括位于扇出走线区内的多条第二扇出线，第三金属层包括位于扇出走线区内的多条第三扇出线，第一扇出线、第二扇出线、第三扇出线中的两组与数据线连接，另一组与触控走线连接，由于第一扇出线与第二扇出线之间设有第一层间绝缘层，第三扇出线与第二扇出线之间设有第二层间绝缘层，从而第一扇出线、第二扇出线、第三扇出线可以交叠设置，能够有效地减小扇出走线区的面积，有助于实现窄边框。本发明提供的一种液晶显示面板的扇出走线区的尺寸小，有利于实现窄边框。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的一种TFT阵列基板的局部剖视图；
图2为图1所示的TFT阵列基板的第一扇出线、第二扇出线及第三扇出线的俯视图；
图3为现有的另一种TFT阵列基板的局部剖视图；
图4为图2所示的TFT阵列基板的第一扇出线及第二扇出线俯视图；
图5为本发明的TFT阵列基板的第一实施例的衬底、第一金属层、第二金属层及第三金属层的俯视示意图；
图6为本发明的TFT阵列基板在有效显示区内的局部剖视图；
图7为本发明的TFT阵列基板的第一实施例及第二实施例在第一扇出线与其对应的数据线的连接处的剖视示意图；
图8为本发明的TFT阵列基板的第一实施例及第三实施例在第二扇出线与其对应的数据线的连接处的剖视示意图；
图9为本发明的TFT阵列基板的第一实施例在第三扇出线与其对应的触控走线的连接处的剖视示意图；
图10为本发明的TFT阵列基板的第二实施例的衬底、第一金属层、第二金属层及第三金属层的俯视示意图；
图11为本发明的TFT阵列基板的第三实施例的衬底、第一金属层、第二金属层及第三金属层的俯视示意图；
图12为本发明的TFT阵列基板的第三实施例在第一扇出线与其对应的触控走线的连接处的剖视示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图5及图6，本发明的TFT阵列基板的第一实施例包括衬底100、设于衬底100上方的第一金属层200、覆盖第一金属层200的第一层间绝缘层300、设于第一层间绝缘层300上的第二金属层400、覆盖第二金属层400的第二层间绝缘层500以及设于第二层间绝缘层500上的第三金属层600。
所述衬底100包括依次设置的有效显示区110及扇出走线区120。所述第一金属层200包括位于扇出走线区120内的多条第一扇出线220。所述第二金属层400包括位于有效显示区110内的多条触控走线410以及位于扇出走线区120内的多条第二扇出线420。所述第三金属层600包括位于有效显示区110内的多条数据线610以及位于扇出走线区120内的多条第三扇出线620。
重点需要注意的是，多条第一扇出线220及多条第二扇出线420分别电性连接多条数据线610，多条第三扇出线620分别电性连接多条触控走线410。
具体地，请参阅图6，并结合图7，每一条第一扇出线220与一条数据线610对应，所述第一层间绝缘层300及第二层间绝缘层500上设有位于多条第一扇出线220上方的多个第一过孔510，所述第一扇出线220与其对应的数据线610经第一过孔510连接。
请参阅图6，并结合图8，每一条第二扇出线420与一条数据线610对应，所述第二层间绝缘层500上设有位于多条第二扇出线420上方的多个第二过孔520，所述第二扇出线420与其对应的数据线610经第二过孔520连接。
请参阅图6，并结合图9，每一第三扇出线620与一条触控走线410对应，所述第二层间绝缘层500上设有位于多条触控走线410上方的多个第三过孔530，所述第三扇出线620与其对应的触控走线410经第三过孔530连接。
进一步地，在本发明的第一实施例中，所述多条第一扇出线220及多条第二扇出线420用于接入数据信号，所述多条第三扇出线620用于接入触控信号。
具体地，请参阅图6，本发明的TFT阵列基板还包括于衬底100上方的有源层700及覆盖有源层700的栅极绝缘层800。所述第一金属层200设于栅极绝缘层800上。
所述TFT阵列基板还包括覆盖第三金属层600的平坦化层900、设于平坦化层900上的公共电极层1000、覆盖公共电极层1000的钝化层1100以及设于钝化层1100上的像素电极层1200。
所述有源层700包括位于有效显示区110内的多个半导体图案710。
所述第一金属层200还包括位于有效显示区110内且对应位于多个半导体图案710上方的多个栅极230。
所述第三金属层600还包括位于有效显示区110内且分别与多个栅极230对应的多个源极630及多个漏极640以及位于有效显示区110内的多个连接电极650。
所述栅极绝缘层800、第一层间绝缘层300及第二层间绝缘层500上设有位于多个半导体图案710两端上方的第六过孔560。与一半岛体图案710对应的源极630及漏极640分别经该半导体图案710两端上方的第六过孔560与该半导体图案710的两端连接。
所述第二层间绝缘层500上设有位于多条触控走线410上方的多个第七过孔570，每一连接电极650经第七过孔570与一触控走线410连接。
所述平坦化层900上设有位于多个连接电极650上方的多个第八过孔910。所述公共电极层1000包括多个间隔的公共电极1010，每一公共电极1010经第八过孔910与一连接电极650连接。
所述平坦化层900及钝化层1100上设有位于多个漏极640上方的多个第九过孔920。所述像素电极层1200包括多个间隔的像素电极1210，每一 像素电极1210经第九过孔920与一漏极640连接。
具体地，所述第一层间绝缘层300的材料为氮化硅(SiNx)。所述第二层间绝缘层500的材料为氧化硅(SiOx)。
具体地，所述栅极绝缘层800的材料为氧化硅。
具体地，所述公共电极层1000的材料为氧化铟锡(ITO)。
具体地，所述像素电极层1200的材料为氧化铟锡。
具体地，所述第二金属层400的材料为钛(Ti)或钼(Mo)。
进一步地，请参阅图6，所述TFT阵列基板还包括设于衬底100上的遮光层1300及覆盖遮光层1300的底层绝缘层1400。所述有源层700设于底层绝缘层1400上。所述底层绝缘层1400由一层氮化硅层及一层氧化硅层层叠形成。
请参阅图10，并结合图6及图7，本发明的TFT阵列基板的第二实施例与上述第一实施例的区别在于，多条第一扇出线220及多条第三扇出线620分别电性连接多条数据线610，多条第二扇出线420分别电性连接多条触控走线410。
具体地，请参阅图10，并结合图7，每一条第一扇出线220与一条数据线610对应，所述第一层间绝缘层300及第二层间绝缘层500上设有位于多条第一扇出线220上方的多个第一过孔510，所述第一扇出线220与其对应的数据线610经第一过孔510连接。
请参阅图10，每一条第三扇出线620与一条数据线610对应连接。
请参阅图10，每一条第二扇出线420与一条触控走线410对应连接。
进一步地，在本发明的第二实施例中，所述多条第一扇出线220及多条第三扇出线620用于接入数据信号，所述多条第二扇出线420用于接入触控信号。
其余均与上述第一实施例相同，在此不再进行赘述。
请参阅图11及图12，并结合图6及图8，本发明的TFT阵列基板的第三实施例与上述第一实施例的区别在于，多条第二扇出线420及多条第三扇出线620分别电性连接多条数据线610，多条第一扇出线220分别电性连接多条触控走线410。
具体地，请参阅图11，并结合图8，每一条第二扇出线420与一条数据线610对应，所述第二层间绝缘层500上设有位于多条第二扇出线420上方的多个第二过孔520，所述第二扇出线420与其对应的数据线610经第二过孔520连接。
请参阅图11，每一条第三扇出线620与一条数据线610对应连接。
请参阅图11及图12，每一条第一扇出线220与一条触控走线410对应，所述第二层间绝缘层500上设有位于多条触控走线410上方的多个第四过孔540，所述第一层间绝缘层300及第二层间绝缘层500上设有位于多条第一扇出线220上方的多个第五过孔550。所述第三金属层600还包括分别与多条触控走线410对应的多条连接走线630。每一连接走线630经第四过孔540及第五过孔550将对应的触控走线410及该触控走线410对应的第一扇出线220连接。
进一步地，在本发明的第三实施例中，所述多条第二扇出线420及多条第三扇出线620用于接入数据信号，所述多条第一扇出线220用于接入触控信号。
其余均与上述第一实施例相同，在此不再赘述。
需要说明的是，本发明的TFT阵列基板通过在第一金属层200中设置位于扇出走线区120内的多条第一扇出线220，在第二金属层400中设置位于扇出走线区120内的多条第二扇出线420，在第三金属层600内设置位于扇出走线区内120的多条第三扇出线620，并使第一扇出线220、第二扇出线420、第三扇出线620中的两组与数据线610连接，另一组与触控走线410连接，由于第一扇出线220与第二扇出线420之间设有第一层间绝缘层300，第三扇出线620与第二扇出线420之间设有第二层间绝缘层500，从而第一扇出线220、第二扇出线420、第三扇出线620可以交叠设置，也即使得与数据线610连接的扇出线能够位于不同的金属层之中，相较于现有技术将与数据线连接的扇出线设置在同一金属层中，本发明能够有效地减小扇出走线区的面积，有助于实现窄边框。进一步地，由于本发明中将第二扇出线420及触控走线410所在的第二金属层400设置在第一金属层200及数据线610所在的第三金属层600之间，相较于现有技术中将触控走线所在的金属层设于数据线所在的金属层的上方并在触控走线上方设置顶层层间绝缘层并进行图案化，本发明在制作时能够减少一道光罩制程，因此能够简化制作过程，降低成本。
基于同一发明构思，本发明还提供一种液晶显示面板，包括上述的TFT阵列基板，在此不再对阵列基板的结构进行重复性描述。
需要说明的是，本发明的液晶显示面板的TFT阵列基板中，通过在第一金属层200中设置位于扇出走线区120内的多条第一扇出线220，在第二金属层400中设置位于扇出走线区120内的多条第二扇出线420，在第三金属层600内设置位于扇出走线区内120的多条第三扇出线620，并使第一扇出线220、第二扇出线420、第三扇出线620中的两组与数据线610连接， 另一组与触控走线410连接，由于第一扇出线220与第二扇出线420之间设有第一层间绝缘层300，第三扇出线620与第二扇出线420之间设有第二层间绝缘层500，从而第一扇出线220、第二扇出线420、第三扇出线620可以交叠设置，也即使得与数据线610连接的扇出线能够位于不同的金属层之中，相较于现有技术将与数据线连接的扇出线设置在同一金属层中，本发明能够有效地减小扇出走线区的面积，有助于实现窄边框。进一步地，由于本发明中将第二扇出线420及触控走线410所在的第二金属层400设置在第一金属层200及数据线610所在的第三金属层600之间，相较于现有技术中将触控走线所在的金属层设于数据线所在的金属层的上方并在触控走线上方设置顶层层间绝缘层并进行图案化，本发明在制作时能够减少一道光罩制程，因此能够简化制作过程，降低成本。
综上所述，本发明的TFT阵列基板包括于衬底上方依次设置的第一金属层、第一层间绝缘层、第二金属层、第二层间绝缘层及第三金属层，第一金属层包括位于扇出走线区内的多条第一扇出线，第二金属层包括位于扇出走线区内的多条第二扇出线，第三金属层包括位于扇出走线区内的多条第三扇出线，第一扇出线、第二扇出线、第三扇出线中的两组与数据线连接，另一组与触控走线连接，由于第一扇出线与第二扇出线之间设有第一层间绝缘层，第三扇出线与第二扇出线之间设有第二层间绝缘层，从而第一扇出线、第二扇出线、第三扇出线可以交叠设置，能够有效地减小扇出走线区的面积，有助于实现窄边框。本发明提供的一种液晶显示面板的扇出走线区的尺寸小，有利于实现窄边框。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板，包括衬底、设于衬底上方的第一金属层、覆盖第一金属层的第一层间绝缘层、设于第一层间绝缘层上的第二金属层、覆盖第二金属层的第二层间绝缘层以及设于第二层间绝缘层上的第三金属层；
    所述衬底包括依次设置的有效显示区及扇出走线区；所述第一金属层包括位于扇出走线区内的多条第一扇出线；所述第二金属层包括位于有效显示区内的多条触控走线以及位于扇出走线区内的多条第二扇出线；所述第三金属层包括位于有效显示区内的多条数据线以及位于扇出走线区内的多条第三扇出线；
    多条第一扇出线及多条第二扇出线分别电性连接多条数据线，多条第三扇出线分别电性连接多条触控走线；或者，
    多条第一扇出线及多条第三扇出线分别电性连接多条数据线，多条第二扇出线分别电性连接多条触控走线；或者，
    多条第二扇出线及多条第三扇出线分别电性连接多条数据线，多条第一扇出线分别电性连接多条触控走线。
  2. 如权利要求1所述的TFT阵列基板，其中，多条第一扇出线及多条第二扇出线分别电性连接多条数据线，多条第三扇出线分别电性连接多条触控走线；
    每一条第一扇出线与一条数据线对应，所述第一层间绝缘层及第二层间绝缘层上设有位于多条第一扇出线上方的多个第一过孔，所述第一扇出线与其对应的数据线经第一过孔连接；
    每一条第二扇出线与一条数据线对应，所述第二层间绝缘层上设有位于多条第二扇出线上方的多个第二过孔，所述第二扇出线与其对应的数据线经第二过孔连接；
    每一第三扇出线与一条触控走线对应，所述第二层间绝缘层上设有位于多条触控走线上方的多个第三过孔，所述第三扇出线与其对应的触控走线经第三过孔连接。
  3. 如权利要求2所述的TFT阵列基板，其中，所述多条第一扇出线及多条第二扇出线用于接入数据信号，所述多条第三扇出线用于接入触控信号。
  4. 如权利要求1所述的TFT阵列基板，其中，多条第一扇出线及多条第三扇出线分别电性连接多条数据线，多条第二扇出线分别电性连接多条 触控走线；
    每一条第一扇出线与一条数据线对应，所述第一层间绝缘层及第二层间绝缘层上设有位于多条第一扇出线上方的多个第一过孔，所述第一扇出线与其对应的数据线经第一过孔连接；
    每一条第三扇出线与一条数据线对应连接；
    每一条第二扇出线与一条触控走线对应连接。
  5. 如权利要求4所述的TFT阵列基板，其中，所述多条第一扇出线及多条第三扇出线用于接入数据信号，所述多条第二扇出线用于接入触控信号。
  6. 如权利要求1所述的TFT阵列基板，其中，多条第二扇出线及多条第三扇出线分别电性连接多条数据线，多条第一扇出线分别电性连接多条触控走线；
    每一条第二扇出线与一条数据线对应，所述第二层间绝缘层上设有位于多条第二扇出线上方的多个第二过孔，所述第二扇出线与其对应的数据线经第二过孔连接；
    每一条第三扇出线与一条数据线对应连接；
    每一条第一扇出线与一条触控走线对应，所述第二层间绝缘层上设有位于多条触控走线上方的多个第四过孔，所述第一层间绝缘层及第二层间绝缘层上设有位于多条第一扇出线上方的多个第五过孔；所述第三金属层还包括分别与多条触控走线对应的多条连接走线；每一连接走线经第四过孔及第五过孔将对应的触控走线及该触控走线对应的第一扇出线连接。
  7. 如权利要求6所述的TFT阵列基板，其中，所述多条第二扇出线及多条第三扇出线用于接入数据信号，所述多条第一扇出线用于接入触控信号。
  8. 如权利要求1所述的TFT阵列基板，还包括于衬底上方的有源层及覆盖有源层的栅极绝缘层；所述第一金属层设于栅极绝缘层上；
    所述TFT阵列基板还包括覆盖第三金属层的平坦化层、设于平坦化层上的公共电极层、覆盖公共电极层的钝化层以及设于钝化层上的像素电极层；
    所述有源层包括位于有效显示区内的多个半导体图案；
    所述第一金属层还包括位于有效显示区内且对应位于多个半导体图案上方的多个栅极；
    所述第三金属层还包括位于有效显示区内且分别与多个栅极对应的多个源极及多个漏极以及位于有效显示区内的多个连接电极；
    所述栅极绝缘层、第一层间绝缘层及第二层间绝缘层上设有位于多个半导体图案两端上方的第六过孔；与一半岛体图案对应的源极及漏极分别经该半导体图案两端上方的第六过孔与该半导体图案的两端连接；
    所述第二层间绝缘层上设有位于多条触控走线上方的多个第七过孔，每一连接电极经第七过孔与一触控走线连接；
    所述平坦化层上设有位于多个连接电极上方的多个第八过孔；所述公共电极层包括多个间隔的公共电极，每一公共电极经第八过孔与一连接电极连接；
    所述平坦化层及钝化层上设有位于多个漏极上方的多个第九过孔；所述像素电极层包括多个间隔的像素电极，每一像素电极经第九过孔与一漏极连接；
    所述第一层间绝缘层的材料为氮化硅；
    所述第二层间绝缘层的材料为氧化硅；
    所述栅极绝缘层的材料为氧化硅；
    所述公共电极层的材料为氧化铟锡；
    所述像素电极层的材料为氧化铟锡；
    所述第二金属层的材料为钛或钼。
  9. 如权利要求8所述的TFT阵列基板，还包括设于衬底上的遮光层及覆盖遮光层的底层绝缘层；所述有源层设于底层绝缘层上。
  10. 一种液晶显示面板，包括如权利要求1所述的TFT阵列基板。
PCT/CN2018/108019 2018-05-29 2018-09-27 Tft阵列基板及液晶显示面板 WO2019227806A1 (zh)

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