WO2019184070A1 - 显示装置及其阵列基板 - Google Patents

显示装置及其阵列基板 Download PDF

Info

Publication number
WO2019184070A1
WO2019184070A1 PCT/CN2018/087787 CN2018087787W WO2019184070A1 WO 2019184070 A1 WO2019184070 A1 WO 2019184070A1 CN 2018087787 W CN2018087787 W CN 2018087787W WO 2019184070 A1 WO2019184070 A1 WO 2019184070A1
Authority
WO
WIPO (PCT)
Prior art keywords
touch signal
layer
light shielding
line
array substrate
Prior art date
Application number
PCT/CN2018/087787
Other languages
English (en)
French (fr)
Inventor
韩约白
张嘉伟
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/071,525 priority Critical patent/US11099440B2/en
Publication of WO2019184070A1 publication Critical patent/WO2019184070A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to the field of display devices, and in particular, to a display device and an array substrate thereof.
  • Low-temperature polysilicon panels have become the star products in flat panel display products due to their high resolution, high mobility, low power consumption, etc., and are widely used in major mobile phones such as Apple, Samsung, Huawei, Huawei and Meizu.
  • On the tablet computer due to the complicated process of the low-temperature polysilicon device array process, multiple masks are required. Therefore, if the number of times the mask is used can be reduced in the low-temperature polysilicon process, the production cost can be effectively reduced.
  • In-Cell Touch Panel process it is generally required to perform Masks 13 times.
  • M2 is usually used in the industry to transmit touch signals, which can realize 9 Masks, but due to the excessive density of M2, Causes problems such as a decrease in aperture ratio.
  • the present invention provides a display device and an array substrate thereof, which can improve the aperture ratio of the entire display device and reduce power consumption.
  • the specific technical solution provided by the present invention is to provide an array substrate, wherein the array substrate includes a plurality of pixel units arranged in an array, each of the pixel units including a light shielding layer, a thin film transistor, a touch electrode, a scan line, and data.
  • a line the scan line is disposed along a first direction
  • the data line is disposed along a second direction
  • the scan line intersects the data line
  • the pixel unit further includes a touch signal line, the touch signal line
  • the two adjacent touch signal lines in the first direction are connected by the light shielding layer, and the touch signal lines pass through the first via and the light shielding layer.
  • the touch signal line is connected to the touch electrode through the second via.
  • the data line covers a portion of the touch signal line in a first direction.
  • the touch signal line includes a vertical portion extending in the first direction and a horizontal portion extending from both ends of the vertical portion toward the second direction, the data line covering the vertical portion,
  • the horizontal portion is connected to the light shielding layer through a first via hole, and the horizontal portion is connected to the touch electrode through a second via hole.
  • the horizontal portion is parallel to the scan line.
  • the vertical portion is perpendicular to the scan line.
  • the touch signal line is located between two adjacent scan lines.
  • the light shielding layer includes a light shielding portion corresponding to the thin film transistor, the light shielding portion corresponding to the horizontal portion, and the bridge portion passes through the first via hole and the horizontal portion connection.
  • the thin film transistor is of a top gate type.
  • the pixel unit includes a substrate, a light shielding layer, a buffer layer, a polysilicon layer, a first interlayer dielectric layer, a gate insulating layer, a first metal layer, a second interlayer dielectric layer, a second metal layer, and a third An interlayer dielectric layer and a touch electrode, the first metal layer is used to form the scan line and the touch signal line, and the second metal layer is used to form the data line.
  • the present invention also provides a display device comprising the array substrate of any of the above.
  • the pixel unit of the array substrate of the present invention further includes a touch signal line, wherein the touch signal line is located in the same layer as the scan line, between two adjacent touch signal lines in the first direction.
  • the touch signal line is connected to the light shielding layer through the first via hole, and the touch signal line is connected to the touch electrode through the second via hole, and the light shielding layer is adjacent
  • the bridge between the two touch signal lines transmits the touch signal through the touch signal line, so as to prevent the transmission line of the touch signal from being directly disposed on the metal layer where the data line is located, resulting in the density of the metal layer where the data line is located. Too large to limit the size of the pixel, thereby increasing the aperture ratio and reducing power consumption.
  • 1 is a schematic structural view of an array substrate
  • FIG. 2 is a schematic structural view of an array substrate not including a second metal layer in FIG. 1;
  • FIG. 3 is a schematic structural view of an array substrate not including a first metal layer in FIG. 2;
  • Figure 4 is a cross-sectional view of A in Figure 1 in a first direction
  • Fig. 5 is a schematic structural view of a display device.
  • FIG. 1 is a schematic structural view of an array substrate in which a non-conductive film layer and a touch electrode are omitted
  • FIG. 2 is a schematic structural view of the array substrate not including the second metal layer
  • FIG. 3 is a schematic structural view of the array substrate not including the first metal layer in FIG. 2
  • FIG. 4 is a cross-sectional view of A in FIG. 1 in the first direction.
  • the array substrate 1 provided in this embodiment includes a plurality of pixel units 10 arranged in an array.
  • Each of the pixel units 10 includes a light shielding layer 11 , a thin film transistor 12 , a touch electrode 13 , a scan line 14 , and a data line 15 .
  • the first direction is set, the data line 15 is disposed in the second direction, and the scan line 14 intersects the data line 15.
  • the pixel unit 10 further includes a touch signal line 16 .
  • the touch signal line 16 is located on the same layer as the scan line 14 , and the adjacent two touch signal lines 16 in the first direction are connected through the light shielding layer 11 .
  • the line 16 is connected to the light shielding layer 11 through the first via hole 20, and the touch signal line 16 is connected to the touch electrode 13 through the second via hole 21.
  • the pixel unit 10 further includes a pixel electrode (not shown) formed in the upper metal layer of the touch electrode 13.
  • the pixel electrode is connected to the scanning line 14 and the data line 15 through the thin film transistor 12.
  • the first direction in this embodiment is the x-axis direction in FIG. 1, and the second direction is the y-axis direction in FIG. 1.
  • the first direction is perpendicular to the second direction, and the plurality of scan lines 14 arranged in the first direction are A plurality of data lines 15 arranged in the second direction intersect and form a plurality of pixel units 10 arranged in an array in a grid shape, and a pixel unit 10 is formed in a region where each grid is located.
  • the array substrate 1 includes a display area and a non-display area, wherein the area where the thin film transistor 12 is located is a non-display area of the array substrate 1.
  • the pixel electrode and the touch electrode 13 in this embodiment are both transparent electrodes.
  • the touch electrode 13 is configured to receive the touch signal and transmit the touch signal to the touch signal line 16 through the second via 21 , and the touch signal line 16 transmits the touch signal to the light shielding layer 11 through the first via 20 .
  • the light shielding layer 11 transmits the touch signal to the other touch signal line 16 adjacent to the touch signal line 16 in the first direction through the first via 20, and the light shielding layer 11 serves as two adjacent touch signals.
  • the bridge between the signal lines 16 transmits the touch signal through the touch signal line 16 to prevent the transmission line of the touch signal from being directly disposed on the metal layer where the data line 15 is located, resulting in the density of the metal layer where the data line 15 is located. Too large to limit the size of the pixel, thereby increasing the aperture ratio and reducing power consumption.
  • the data line 15 covers the portion of the touch signal line 16 in the first direction, that is, the projection of the data line 15 in the plane of the touch signal line 16 coincides with the portion of the touch signal line 16 on the x-axis.
  • the touch signal line 16 does not affect the size of the pixels of the array substrate 1, thereby further increasing the aperture ratio and reducing power consumption.
  • the touch signal line 16 includes a vertical portion 16a extending in the first direction and a horizontal portion 16b bent from both ends of the vertical portion 16a toward the second direction, and the data line 15 covers the vertical portion 16a, that is, the data line
  • the projection in the plane in which the touch signal line 16 is located coincides with the vertical portion 16a.
  • the horizontal portion 16b is connected to the light shielding layer 11 through the first via hole 20, and the horizontal portion 16b is connected to the touch electrode 13 through the second via hole 21.
  • the light shielding layer 11 is respectively connected to the adjacent two touch signal lines 16 in the first direction through the first via holes 20, thereby bridging the touch signal lines 16 in the first direction.
  • the light shielding layer 11 includes a light shielding portion 11a corresponding to the thin film transistor 12, a bridge portion 11b corresponding to the horizontal portion 16b, and a bridge portion 11b connected to the horizontal portion 16b via the first via hole 20.
  • the horizontal portion 16b is parallel to the scanning line 14, and the vertical portion 16b is perpendicular to the scanning line 14, that is, the horizontal portion 16b is perpendicular to the vertical portion 16a.
  • the touch signal line 16 is located between the adjacent two scan lines 14.
  • the thin film transistor 12 in this embodiment is of a top gate type.
  • the pixel unit 10 includes a substrate 22, a light shielding layer 11, a buffer layer 23, a polysilicon layer 24, a first interlayer dielectric layer 25, a gate insulating layer 26, and a first a metal layer 27, a second interlayer dielectric layer, a second metal layer, a third interlayer dielectric layer 28, a touch electrode 13, a fourth interlayer dielectric layer, and a pixel electrode.
  • the light shielding layer 11 is disposed on the substrate 22, and the buffer layer 23 is disposed on the substrate 22 and covers the light shielding layer 11.
  • the polysilicon layer 24 is disposed on the buffer layer 23, and the first interlayer dielectric layer 25 is disposed on the buffer layer 23 and covers the polysilicon layer 24.
  • the gate insulating layer 26 is disposed on the first interlayer dielectric layer 25.
  • the first metal layer 27 is disposed on the gate insulating layer 26 for forming the touch signal line 16 and the scan line 14.
  • the scan line 14 serves as the thin film transistor 12.
  • the gate, the second interlayer dielectric layer covers the first metal layer 27, the second metal layer is disposed on the second interlayer dielectric layer, and the second metal layer is used to form the data line 15.
  • the third interlayer dielectric layer 28 covers the second metal layer, the touch electrode 13 is disposed on the third interlayer dielectric layer 28, the fourth interlayer dielectric layer covers the touch electrode 13, and the pixel electrode is disposed between the fourth layers.
  • the source of the thin film transistor 12 is connected to the data line, and the drain of the thin film transistor 12 is connected to the pixel electrode.
  • This embodiment further provides a display device, which may be an LCD or an OLED. There is no limit here.
  • the display device is an LCD, and the display device includes an array substrate 1 , a CF substrate 2 , and a liquid crystal layer 3 .
  • the array substrate 1 and the CF substrate 2 are disposed on the cell, and the liquid crystal layer 3 is disposed on the array substrate 1 and the CF substrate.
  • the display device can increase the aperture ratio of the entire display device and reduce the power consumption of the display device by using the array substrate 1 described above.

Abstract

一种显示装置及其阵列基板（1），阵列基板（1）包括呈阵列设置的多个像素单元（10），每一个像素单元（10）包括遮光层（11）、薄膜晶体管（12）、触控电极（13）、扫描线（14）及数据线（15），扫描线（14）沿第一方向设置，数据线（15）沿第二方向设置，扫描线（14）与数据线（15）交叉，像素单元（10）还包括触控信号线（16），触控信号线（16）与扫描线（14）位于同一层，在第一方向上的相邻两个触控信号线（16）之间通过遮光层（11）连接，触控信号线（16）通过第一过孔（20）与遮光层（11）连接，触控信号线（16）通过第二过孔（21）与触控电极（13）连接。将遮光层（11）作为相邻两个触控信号线（16）之间的桥接线，通过触控信号线（16）来传递触控信号，避免将触控信号的传输线直接设置在数据线（15）所在的金属层上，造成数据线（15）所在的金属层的密度过大而限制像素的大小，从而提升了开口率、降低功耗。

Description

显示装置及其阵列基板 技术领域
本发明涉及显示装置技术领域，尤其涉及一种显示装置及其阵列基板。
背景技术
低温多晶硅面板借着其高分辨率、高迁移率、低功耗等诸多优点已成为了目前平板显示产品中的明星产品，被广泛应用在例如苹果、三星、华为、小米、魅族等各大手机及平板电脑上，由于低温多晶硅器件阵列工艺制程复杂，需要多次光罩(Mask)，因此，在低温多晶硅制程中如果能够降低光罩使用次数将会有效的降低生产成本。在目前生产的In-Cell Touch Panel工艺过程中，一般需要13次Mask，而为了节约成本，目前行业内通常使用M2传递触控信号，可实现9次Mask，但由于M2密度过大，将会造成开口率降低等问题。
发明内容
为了解决上述问题，本发明提供一种显示装置及其阵列基板，能够提升整个显示装置的开口率、降低功耗。
本发明提出的具体技术方案为：提供一种阵列基板，所述阵列基板包括呈阵列设置的多个像素单元，每一个所述像素单元包括遮光层、薄膜晶体管、触控电极、扫描线及数据线，所述扫描线沿第一方向设置，所述数据线沿第二方向设置，所述扫描线与所述数据线交叉，所述像素单元还包括触控信号线，所述触控信号线与所述扫描线位于同一层，在第一方向上的相邻两个所述触控信号线之间通过所述遮光层连接，所述触控信号线通过第一过孔与所述遮光层连接，所述触控信号线通过第二过孔与所述触控电极连接。
进一步地，所述数据线覆盖所述触控信号线位于第一方向上的部分。
进一步地，所述触控信号线包括沿第一方向延伸的垂直部以及由所述垂直部的两端朝向第二方向弯折延伸出的水平部，所述数据线覆盖所述垂直部，所 述水平部通过第一过孔与所述遮光层连接，所述水平部通过第二过孔与所述触控电极连接。
进一步地，所述水平部与所述扫描线平行。
进一步地，所述垂直部与所述扫描线垂直。
进一步地，所述触控信号线位于相邻两条扫描线之间。
进一步地，所述遮光层包括遮光部和桥接部，所述遮光部与所述薄膜晶体管对应，所述桥接部与所述水平部对应，所述桥接部通过第一过孔与所述水平部连接。
进一步地，所述薄膜晶体管为顶栅型。
进一步地，所述像素单元包括衬底、遮光层、缓冲层、多晶硅层、第一层间介质层、栅绝缘层、第一金属层、第二层间介质层、第二金属层、第三层间介质层及触控电极，所述第一金属层用于形成所述扫描线和所述触控信号线，所述第二金属层用于形成所述数据线。
本发明还提供了一种显示装置，所述显示装置包括如上任一所述的阵列基板。
本发明提出的阵列基板的像素单元包括还包括触控信号线，所述触控信号线与所述扫描线位于同一层，在第一方向上的相邻两个所述触控信号线之间通过所述遮光层连接，所述触控信号线通过第一过孔与所述遮光层连接，所述触控信号线通过第二过孔与所述触控电极连接，将遮光层作为相邻两个触控信号线之间的桥接线，通过触控信号线来传递触控信号，避免将触控信号的传输线直接设置在数据线所在的金属层上，造成数据线所在的金属层的密度过大而限制像素的大小，从而提升了开口率、降低功耗。
附图说明
图1为阵列基板的结构示意图；
图2为图1中不包括第二金属层的阵列基板的结构示意图；
图3为图2中不包括第一金属层的阵列基板的结构示意图；
图4为图1中的A处在第一方向上的截面图；
图5为显示装置的结构示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。在附图中，相同的标号将始终被用于表示相同的元件。
参照图1～4，本实施例的图1为省略了不导电膜层和触控电极的阵列基板的结构示意图，图2为图1中不包括第二金属层的阵列基板的结构示意图，图3为图2中不包括第一金属层的阵列基板的结构示意图，图4为图1中的A处在第一方向上的截面图。下面参照图1-3对本实施例的阵列基板的结构进行详细的描述。
本实施例提供的阵列基板1包括呈阵列设置的多个像素单元10，每一个像素单元10包括遮光层11、薄膜晶体管12、触控电极13、扫描线14及数据线15，扫描线14沿第一方向设置，数据线15沿第二方向设置，扫描线14与数据线15交叉。像素单元10还包括触控信号线16，触控信号线16与扫描线14位于同一层，在第一方向上的相邻两个触控信号线16之间通过遮光层11连接，触控信号线16通过第一过孔20与遮光层11连接，触控信号线16通过第二过孔21与触控电极13连接。
像素单元10还包括像素电极(图未示)，像素电极在触控电极13的上层金属层中形成。像素电极通过薄膜晶体管12与扫描线14、数据线15连接。
本实施例中的第一方向为图1中的x轴方向，第二方向为图1中的y轴方向，第一方向与第二方向垂直，沿第一方向排列的多个扫描线14与沿第二方向排列的多个数据线15交叉并呈网格状形成阵列排布的多个像素单元10，每一个网格所在区域形成一个像素单元10。阵列基板1包括显示区域和非显示区域，其中，薄膜晶体管12所在的区域为阵列基板1的非显示区域。本实施例中的像素电极和触控电极13都为透明电极。
触控电极13用于接收触控信号并通过第二过孔21将触控信号传递给触控信号线16，触控信号线16再通过第一过孔20将触控信号传递给遮光层11，遮光层11再通过第一过孔20将触控信号传递至在第一方向上与该触控信号线16相邻的另一触控信号线16，遮光层11作为相邻两个触控信号线16之间的桥接线，通过触控信号线16来传递触控信号，避免将触控信号的传输线直接设置在数据线15所在的金属层上，造成数据线15所在的金属层的密度过大而限制像素的大小，从而提升了开口率、降低功耗。
较佳地，数据线15覆盖触控信号线16位于第一方向上的部分，即数据线15在触控信号线16所在的平面内的投影与触控信号线16位于x轴上的部分重合。这样，触控信号线16不会影响阵列基板1的像素的大小，从而进一步地提升了开口率、降低功耗。
具体地，触控信号线16包括沿第一方向延伸的垂直部16a以及由垂直部16a的两端朝向第二方向弯折延伸出的水平部16b，数据线15覆盖垂直部16a，即数据线15在触控信号线16所在的平面内的投影与垂直部16a重合。水平部16b通过第一过孔20与遮光层11连接，水平部16b通过第二过孔21与触控电极13连接。遮光层11通过第一过孔20分别与在第一方向上的相邻两个触控信号线16连接，从而实现将第一方向上的触控信号线16进行桥接。
遮光层11包括遮光部11a和桥接部11b，遮光部11a与薄膜晶体管12对应，桥接部11b与水平部16b对应，桥接部11b通过第一过孔20与水平部16b连接。
水平部16b与扫描线14平行，垂直部16b与扫描线14垂直，即水平部16b与垂直部16a垂直。触控信号线16位于相邻两条扫描线14之间。
本实施例中的薄膜晶体管12为顶栅型，具体地，像素单元10包括衬底22、遮光层11、缓冲层23、多晶硅层24、第一层间介质层25、栅绝缘层26、第一金属层27、第二层间介质层、第二金属层、第三层间介质层28、触控电极13、第四层间介质层及像素电极。
遮光层11设置于衬底22上，缓冲层23设置于衬底22上并覆盖遮光层11。多晶硅层24设置于缓冲层23上，第一层间介质层25设置于缓冲层23上并覆盖多晶硅层24。栅绝缘层26设置于第一层间介质层25上，第一金属层27设置于栅绝缘层26上，其用于形成触控信号线16和扫描线14，扫描线14作为薄膜晶体管12的 栅极，第二层间介质层覆盖第一金属层27，第二金属层设置于第二层间介质层上，第二金属层用于形成数据线15。第三层间介质层28覆盖于第二金属层上，触控电极13设置于第三层间介质层28上，第四层间介质层覆盖触控电极13，像素电极设置于第四层间介质层上。薄膜晶体管12的源极与数据线连接，薄膜晶体管12的漏极与像素电极连接。
本实施例还提供了一种显示装置，该显示装置可以是LCD，也可以是OLED。这里不做限定。
参照图5，以显示装置为LCD为例，显示装置包括阵列基板1、CF基板2及液晶层3，阵列基板1与CF基板2对盒设置，液晶层3夹设于阵列基板1与CF基板2之间，显示装置通过采用上述阵列基板1可以提升整个显示装置的开口率、降低显示装置的功耗。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (18)

  1. 一种阵列基板，其中，包括呈阵列设置的多个像素单元，每一个所述像素单元包括遮光层、薄膜晶体管、触控电极、扫描线及数据线，所述扫描线沿第一方向设置，所述数据线沿第二方向设置，所述扫描线与所述数据线交叉，所述像素单元还包括触控信号线，所述触控信号线与所述扫描线位于同一层，在第一方向上的相邻两个所述触控信号线之间通过所述遮光层连接，触控信号线通过第一过孔与遮光层连接，所述触控信号线通过第二过孔与所述触控电极连接。
  2. 根据权利要求1所述的阵列基板，其中，所述数据线覆盖所述触控信号线位于第一方向上的部分。
  3. 根据权利要求2所述的阵列基板，其中，所述触控信号线包括沿第一方向延伸的垂直部以及由所述垂直部的两端朝向第二方向弯折延伸出的水平部，所述数据线覆盖所述垂直部，所述水平部通过第一过孔与所述遮光层连接，所述水平部通过第二过孔与所述触控电极连接。
  4. 根据权利要求3所述的阵列基板，其中，所述水平部与所述扫描线平行。
  5. 根据权利要求1所述的阵列基板，其中，所述垂直部与所述扫描线垂直。
  6. 根据权利要求1所述的阵列基板，其中，所述触控信号线位于相邻两条扫描线之间。
  7. 根据权利要求3所述的阵列基板，其中，所述遮光层包括遮光部和桥接部，所述遮光部与所述薄膜晶体管对应，所述桥接部与所述水平部对应，所述桥接部通过第一过孔与所述水平部连接。
  8. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管为顶栅型。
  9. 根据权利要求7所述的阵列基板，其中，所述像素单元包括衬底、遮光层、缓冲层、多晶硅层、第一层间介质层、栅绝缘层、第一金属层、第二层间介质层、第二金属层、第三层间介质层及触控电极，所述第一金属层用于形成所述扫描线和所述触控信号线，所述第二金属层用于形成所述数据线。
  10. 一种显示装置，其中，包括阵列基板，所述阵列基板包括呈阵列设置的多个像素单元，每一个所述像素单元包括遮光层、薄膜晶体管、触控电极、扫描线及数据线，所述扫描线沿第一方向设置，所述数据线沿第二方向设置，所述扫描线与所述数据线交叉，所述像素单元还包括触控信号线，所述触控信号线与所述扫描线位于同一层，在第一方向上的相邻两个所述触控信号线之间通过所述遮光层连接，触控信号线通过第一过孔与遮光层连接，所述触控信号线通过第二过孔与所述触控电极连接。
  11. 根据权利要求10所述的显示装置，其中，所述数据线覆盖所述触控信号线位于第一方向上的部分。
  12. 根据权利要求11所述的显示装置，其中，所述触控信号线包括沿第一方向延伸的垂直部以及由所述垂直部的两端朝向第二方向弯折延伸出的水平部，所述数据线覆盖所述垂直部，所述水平部通过第一过孔与所述遮光层连接，所述水平部通过第二过孔与所述触控电极连接。
  13. 根据权利要求12所述的显示装置，其中，所述水平部与所述扫描线平行。
  14. 根据权利要求10所述的显示装置，其中，所述垂直部与所述扫描线垂直。
  15. 根据权利要求10所述的显示装置，其中，所述触控信号线位于相邻两条扫描线之间。
  16. 根据权利要求12所述的显示装置，其中，所述遮光层包括遮光部和桥接部，所述遮光部与所述薄膜晶体管对应，所述桥接部与所述水平部对应，所述桥接部通过第一过孔与所述水平部连接。
  17. 根据权利要求10所述的显示装置，其中，所述薄膜晶体管为顶栅型。
  18. 根据权利要求16所述的显示装置，其中，所述像素单元包括衬底、遮光层、缓冲层、多晶硅层、第一层间介质层、栅绝缘层、第一金属层、第二层间介质层、第二金属层、第三层间介质层及触控电极，所述第一金属层用于形成所述扫描线和所述触控信号线，所述第二金属层用于形成所述数据线。
PCT/CN2018/087787 2018-03-30 2018-05-22 显示装置及其阵列基板 WO2019184070A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/071,525 US11099440B2 (en) 2018-03-30 2018-05-22 Display device and array substrate thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810275956.0 2018-03-30
CN201810275956.0A CN108490666B (zh) 2018-03-30 2018-03-30 显示装置及其阵列基板

Publications (1)

Publication Number Publication Date
WO2019184070A1 true WO2019184070A1 (zh) 2019-10-03

Family

ID=63317680

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/087787 WO2019184070A1 (zh) 2018-03-30 2018-05-22 显示装置及其阵列基板

Country Status (3)

Country Link
US (1) US11099440B2 (zh)
CN (1) CN108490666B (zh)
WO (1) WO2019184070A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110580113A (zh) 2019-08-09 2019-12-17 武汉华星光电半导体显示技术有限公司 一种oled显示面板
CN112035006A (zh) * 2020-08-06 2020-12-04 武汉华星光电技术有限公司 显示面板
CN114755863A (zh) * 2022-04-19 2022-07-15 武汉华星光电技术有限公司 阵列基板、显示面板以及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN204440372U (zh) * 2015-03-13 2015-07-01 京东方科技集团股份有限公司 一种内嵌式触摸屏及显示装置
US20160109998A1 (en) * 2014-10-15 2016-04-21 Semiconductor Energy Laboratory Co., Ltd. Touch Panel and Electronic Device
CN106292036A (zh) * 2016-09-28 2017-01-04 厦门天马微电子有限公司 一种阵列基板、显示装置及其制作方法
CN107422560A (zh) * 2017-09-04 2017-12-01 京东方科技集团股份有限公司 一种阵列基板、其检测方法及显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101334564A (zh) * 2007-06-28 2008-12-31 上海广电Nec液晶显示器有限公司 一种液晶显示装置及其制造方法
TWI417766B (zh) * 2008-05-23 2013-12-01 Innolux Corp 觸控液晶顯示裝置及其驅動方法
KR101290709B1 (ko) * 2009-12-28 2013-07-29 엘지디스플레이 주식회사 터치센서 인셀 타입 액정표시장치용 어레이 기판 및 이의 제조방법
CN103092446B (zh) * 2013-01-17 2015-09-09 北京京东方光电科技有限公司 一种触摸屏及制备方法、显示装置
KR102071204B1 (ko) * 2013-09-30 2020-01-30 엘지디스플레이 주식회사 터치 표시장치 및 그 구동방법
CN104731412B (zh) * 2015-04-01 2018-03-13 上海天马微电子有限公司 阵列基板、显示面板及显示装置
CN104900658B (zh) * 2015-06-15 2018-07-27 京东方科技集团股份有限公司 触控面板及其制备方法、触控显示装置
TWI581149B (zh) * 2015-11-02 2017-05-01 友達光電股份有限公司 觸控顯示面板
CN106168865B (zh) * 2016-06-28 2019-11-26 京东方科技集团股份有限公司 内嵌式触摸屏及其制作方法、显示装置
CN106908980B (zh) * 2017-05-09 2020-10-16 上海中航光电子有限公司 阵列基板、触控显示面板及显示装置
CN108227326A (zh) * 2018-02-01 2018-06-29 京东方科技集团股份有限公司 阵列基板及其制造方法、触控显示面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160109998A1 (en) * 2014-10-15 2016-04-21 Semiconductor Energy Laboratory Co., Ltd. Touch Panel and Electronic Device
CN204440372U (zh) * 2015-03-13 2015-07-01 京东方科技集团股份有限公司 一种内嵌式触摸屏及显示装置
CN106292036A (zh) * 2016-09-28 2017-01-04 厦门天马微电子有限公司 一种阵列基板、显示装置及其制作方法
CN107422560A (zh) * 2017-09-04 2017-12-01 京东方科技集团股份有限公司 一种阵列基板、其检测方法及显示装置

Also Published As

Publication number Publication date
CN108490666B (zh) 2020-06-16
US11099440B2 (en) 2021-08-24
CN108490666A (zh) 2018-09-04
US20210080790A1 (en) 2021-03-18

Similar Documents

Publication Publication Date Title
US10067613B2 (en) Touch display device
WO2019227806A1 (zh) Tft阵列基板及液晶显示面板
US20190157311A1 (en) Flexible array substrate and preparation method thereof, display substrate and display device
WO2018036179A1 (zh) 触控结构、阵列基板和显示装置
US10168593B2 (en) Liquid crystal display panel having dual capacitors connected in parallel to shift register unit and array substrate thereof
WO2016110036A1 (zh) 阵列基板及显示装置
WO2016179972A1 (zh) 阵列基板、液晶显示面板及显示装置
WO2017012304A1 (zh) 一种阵列基板、显示装置及制作方法
CN107015410B (zh) 一种阵列基板、显示面板和显示装置
US20180294288A1 (en) Array substrate and display device
US10042494B2 (en) Array substrate, touch display panel and touch display device
WO2019184070A1 (zh) 显示装置及其阵列基板
CN103926760A (zh) 像素结构及像素阵列基板
WO2017092485A1 (zh) 阵列基板及显示装置
JP2020529642A (ja) タッチ表示基板および表示装置
TW202044330A (zh) 顯示裝置及顯示裝置之薄膜電晶體的製造方法
WO2014176876A1 (zh) 显示面板及其制作方法、液晶显示器
US9841639B2 (en) Touch display panel and fabrication method thereof, and display device
WO2019184071A1 (zh) 显示装置及其阵列基板
WO2018219345A1 (zh) 阵列基板、显示面板及显示装置
WO2016110039A1 (zh) 像素结构、阵列基板、显示面板和显示装置
US20140306227A1 (en) Display apparatus, array substrate, and method for producing the array substrate
WO2021072781A1 (zh) 显示面板
WO2019051971A1 (zh) 阵列基板及显示面板
US9915846B2 (en) Array substrate and display device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18912741

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 18912741

Country of ref document: EP

Kind code of ref document: A1