WO2017092485A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

Info

Publication number
WO2017092485A1
WO2017092485A1 PCT/CN2016/099721 CN2016099721W WO2017092485A1 WO 2017092485 A1 WO2017092485 A1 WO 2017092485A1 CN 2016099721 W CN2016099721 W CN 2016099721W WO 2017092485 A1 WO2017092485 A1 WO 2017092485A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
line
branch electrode
array substrate
lines
Prior art date
Application number
PCT/CN2016/099721
Other languages
English (en)
French (fr)
Inventor
程鸿飞
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/539,770 priority Critical patent/US10204929B2/en
Publication of WO2017092485A1 publication Critical patent/WO2017092485A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode

Definitions

  • the present disclosure relates to an array substrate and a display device.
  • the common electrode line becomes longer and longer, which makes the resistance of the common electrode line also become larger, causing the delay phenomenon of the common electrode signal to become more serious, thereby affecting the picture. Display quality.
  • At least one embodiment of the present invention provides an array substrate, including: a substrate substrate, a gate line, a data line disposed on the substrate substrate, and a display unit defined by the intersection of the data line and the gate line, a thin film transistor, a sub-pixel electrode, and a common electrode line are disposed in the display unit, wherein the common electrode line includes a main electrode line extending in the same direction as the extension direction of the gate line, and is connected to the main electrode line Branch electrode line.
  • the branch electrode line includes: at least two first branch electrode lines extending in the same direction as the extending direction of the data line; at least one extending direction and the gate The second branch electrode lines of the same extending direction of the line, the second branch electrode lines connecting all of the first branch electrode lines.
  • the first branch electrode lines are three, and the two first branch electrode lines are respectively disposed at two end regions of the display unit, one of the The first branch electrode line is disposed in an intermediate portion of the display unit.
  • one of the second branch electrode lines is disposed in a region of the sub-pixel electrode.
  • the sub-pixel electrodes are not less than two, the sub-pixel electrodes are connected to each other, and one of the at least one of the sub-pixel electrodes is disposed in the region.
  • Second branch electrode line is
  • the sub-pixel electrode and the drain of the thin film transistor are disposed in different layers, and are connected to the drain of the thin film transistor through a via hole. And the via is at least partially overlapped with one of the second branch electrode lines.
  • two of the sub-pixel electrodes are disposed in each of the display units, and the two sub-pixel electrodes are spaced apart from each other, and each of the sub-pixel electrodes corresponds to One of the thin film transistors is connected to a drain of the corresponding thin film crystal through its corresponding via hole, and each of the via holes is at least partially overlapped with a different one of the second branch electrode lines .
  • the sub-pixel electrodes are two, the two sub-pixel electrodes are spaced apart from each other, and the extending direction of the gap between two adjacent sub-pixel electrodes is
  • the gate lines extend in the same direction, and one of the second branch electrode lines at least partially overlaps the gap.
  • the sub-pixel electrode is a slit electrode
  • the sub-pixel electrode includes a first root stem portion, a second root stem portion, a branch electrode, and a slit, and the slit The adjacent branch electrodes are separated.
  • the first branch electrode line and the second root stem are at least partially overlapped; the second branch electrode line at least partially overlaps with the first root stem .
  • the common electrode line is disposed in the same layer as the gate line.
  • the common electrode line further includes: a connection line connecting the respective branch electrode lines of adjacent display units of the same peer.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • FIG. 1 and 2 are schematic structural views of an array substrate of the present disclosure in Embodiment 1;
  • Embodiment 3 is a schematic structural view of an array substrate of the present disclosure in Embodiment 2;
  • FIG. 5 is a schematic structural view of an array substrate of the present disclosure in Embodiment 4.
  • FIG. 6 is a schematic structural view of an array substrate of the present disclosure in Embodiment 5;
  • FIG. 7 is a schematic structural view of an array substrate of the present disclosure in Embodiment 6;
  • Embodiment 8 is a schematic structural view of an array substrate of the present disclosure in Embodiment 7;
  • Embodiment 9 is a schematic structural view of an array substrate of the present disclosure in Embodiment 8.
  • FIG. 10 is a schematic structural view of an array substrate of the present disclosure in Embodiment 9.
  • the present disclosure provides an array substrate, the array substrate includes: a substrate substrate, a gate line, a data line disposed on the substrate, a display unit defined by the intersection of the data line and the gate line, and the thin film transistor is disposed in the display unit a sub-pixel electrode and a common electrode line including a main electrode line extending in the same direction as the extension direction of the gate line, and a branch electrode line connected to the main electrode line.
  • the present disclosure reduces the resistance of the common electrode signal by setting the branch electrode line connected to the main electrode line to reduce the resistance of the common electrode line, thereby improving the display quality of the display panel.
  • the array substrate of the present embodiment includes a gate line 10 and a data line 30 formed on the base substrate 1, and a display unit defined by the intersection of the data line 30 and the gate line 10, and is displayed in the display unit.
  • a thin film transistor, a sub-pixel electrode 50, and a common electrode line 20 are also included.
  • the common electrode line 20 includes a main electrode line 21 and a branch electrode line connected to the main electrode line 21.
  • the branch electrode lines include first branch electrode lines 22a, 22b extending in the same direction as the extending direction of the data lines 30, and second branch electrode lines 23 extending in the same direction as the extending direction of the gate lines 10, the second branch electrode lines 23
  • the first branch electrode lines 22a, 22b are connected such that the branch electrode lines composed of the first branch electrode lines 22a, 22b and the second branch electrode lines 23 can be connected to the main electrode line 21.
  • the display unit includes a sub-pixel electrode 50 (the sub-pixel electrode in FIG. 1 is embodied in a bold line frame), and the sub-pixel electrode 50 is connected to the data line 30 through a thin film transistor.
  • the thin film transistor includes a gate 10a, an active layer 25, a source 31, and a drain 33.
  • the gate 10a is connected or integrally formed with the gate line 10
  • the gate insulating layer 15 is on the gate 10a
  • the active layer 25 is on the gate insulating layer 15
  • the source 31 and the drain 33 are on the active layer 25, blunt
  • the layer 35 is located on the source 31 and the drain 33.
  • the sub-pixel electrode 50 is connected to the drain 33 through a via 40 on the passivation layer 35
  • the source 31 is connected to the data line 30.
  • the gate insulating layer 15 may be silicon nitride or silicon oxide; the gate insulating layer may be a single layer structure or a multilayer structure such as silicon oxide/silicon nitride.
  • the active layer 25 may be amorphous silicon, polycrystalline silicon, microcrystalline silicon or an oxide semiconductor.
  • the passivation layer 35 may be made of an inorganic material such as silicon nitride or an organic insulating layer such as an organic resin material.
  • the sub-pixel electrode 50 is made of indium tin oxide (ITO), indium zinc oxide (IZO) or other transparent metal oxide conductive material.
  • the second branch electrode line 23 and the via hole 40 at least partially overlap. It should be noted that the position at which the second branch electrode line 23 is connected to the first branch electrode lines 22a and 22b is not limited herein.
  • the common electrode line 20 includes a main electrode line 21, first branch electrode lines 22a, 22b, and second branch electrode lines 23a, 23b.
  • the extending direction of the first branch electrode lines 22a, 22b is the same as the extending direction of the data line 30, the extending direction of the second branch electrode lines 23a, 23b is the same as the extending direction of the gate line 10, and the second branch electrode lines 23a, 23b are respectively connected.
  • the second branch electrode line 23a and the via hole 40 are at least partially overlapped.
  • the sub-pixel electrode 50 (the sub-pixel electrode in FIG. 3 is embodied in a bold line frame) is connected to the drain 33 of the thin film transistor through the via 40.
  • connection position of the second branch electrode line 23b and the first branch electrode lines 22a and 22b is not limited.
  • the second branch electrode line 23b may be connected to the end points of the first branch electrode lines 22a, 22b, respectively.
  • the second branch electrode line 23b is connected to the end of the shorter one of the first branch electrode lines 22a, 22b, and to the first branch electrode line The non-end point portions of the longer lengths of 22a, 22b are connected.
  • the common electrode line 20 includes a main electrode line 21, first branch electrode lines 22a, 22b, 22c, and second branch electrode lines 23a, 23b.
  • the extending direction of the first branch electrode lines 22a, 22b, 22c is the same as the extending direction of the data line 30, and the second branch electrode
  • the extending direction of the lines 23a, 23b is the same as the extending direction of the gate line 10
  • the second branch electrode lines 23a, 23b are connected to the first branch electrode lines 22a, 22b, 22c, respectively.
  • the gate line 10 and the data line 30 intersect to define a display unit.
  • the first branch electrode lines 22a, 22b are respectively disposed at two end regions of the display unit, the first The branch electrode line 22c is disposed in an intermediate portion of the display unit.
  • a sub-pixel electrode 50 (the sub-pixel electrode in FIG. 4 is represented by a bold wire frame) is further disposed in the display unit of the embodiment, and the sub-pixel electrode 50 passes through the via 40 and the drain of the thin film transistor. 33 connections.
  • the embodiment includes two second branch electrode lines, and the second branch electrode lines are not at least partially overlapped with the via holes 40.
  • the common electrode line 20 includes a main electrode line 21, first branch electrode lines 22a and 22b, and second branch electrode lines 23a, 23b, and 23c.
  • the extending direction of the first branch electrode lines 22a, 22b is the same as the extending direction of the data line 30
  • the extending direction of the second branch electrode lines 23a, 23b, 23c is the same as the extending direction of the gate line 10
  • the second branch electrode lines 23a, 23b And 23c are connected to the first branch electrode lines 22a and 22b, respectively.
  • the display unit defined by the intersection of the data line 30 and the gate line 10 includes sub-pixel electrodes 51, 52, 53 (the sub-pixels in FIG. 5 are embodied in bold line frames).
  • the sub-pixel electrode 51 is connected to the sub-pixel electrode 52 via the connection portion 54
  • the sub-pixel electrode 52 is connected to the sub-pixel electrode 53 via the connection portion 55.
  • the sub-pixel electrodes 51, 52, and 53 are integrally formed with the connecting portions 54, 55.
  • a corresponding one of the second branch electrode lines is respectively disposed in a region of the sub-pixel electrodes 51, 52, 53 in the present embodiment.
  • the sub-pixel electrode 51 is provided with a second branch electrode line 23a
  • the sub-pixel electrode 52 is provided with a second branch electrode line 23b
  • the sub-pixel electrode 53 is provided with a second branch electrode line 23c.
  • a second branch electrode line may be disposed on only a portion of the sub-pixel electrode, such as a second branch electrode line disposed under the sub-pixel electrode 51 and the sub-pixel electrode 52; Or a second branch electrode line is disposed under each of the sub-pixel electrode 51 and the sub-pixel electrode 53; or a second branch electrode line is disposed under each of the sub-pixel electrode 52 and the sub-pixel electrode 53.
  • the sub-pixel electrode 51 is connected to the drain 33 of the thin film transistor through the via 40, so that the sub-pixel electrodes 51, 52, 53 are commonly loaded with the data line from the drain 33. signal.
  • the second branch electrode line 23a corresponding to the sub-pixel electrode 51 and the via hole 40 are at least partially overlapped.
  • the main body of the sub-pixel electrodes 51, 52, 53 (the sub-pixel electrodes in FIG. 6 are indicated by bold lines) in the present embodiment may be a plate electrode.
  • the edge of the plate electrode is formed with a strip electrode 56.
  • sub-pixel electrodes disclosed in the embodiments of the present invention are not limited to the shapes shown in FIGS. 1 to 6 .
  • the array substrate in this embodiment includes: gate lines 10i, 10i+1, and data lines 30j, 30j+1, and 30j+2.
  • the gate lines 10i, 10i+1 and the data lines 30j, 30j+1 enclose a first display unit, and the sub-pixel electrodes 50i+1, j are disposed in the first display unit.
  • the gate lines 10i, 10i+1 and the data lines 30j+1, 30j+2 enclose a second display unit that is adjacent to the first display unit, and the sub-pixel electrode 50i+1 is disposed in the second display unit. j+1.
  • a common electrode line 20 is further disposed on the array substrate provided in this embodiment, and the common electrode line 20 includes a main electrode line 21 and branch electrode lines respectively corresponding to the first display unit and the second display unit.
  • the branch electrode line of the first display unit includes: a first branch electrode line 22a extending in the same direction as the extending direction of the data lines 30j, 30j+1, 30j+2 And 22b, and second branch electrode lines 23a and 23b extending in the same direction as the extending directions of the gate lines 10i and 10i+1.
  • the sub-pixel electrode 50i+1,j is connected to the drain 33 of the thin film transistor through the via 40.
  • the second branch electrode line 23a and the via hole 40 are at least partially overlapped.
  • the branch electrode lines of the first display unit and the second display unit are connected through a connection electrode 24, and the connection electrode 24 and the common electrode are connected.
  • the wire 20 is integrally formed.
  • the array substrate provided in this embodiment includes: gate lines 10i-1, 10i, 10i+1, data lines 30j, 30j+1, 30j+2, 30j+3 and common electrode lines 20i, 20i+1.
  • the gate lines 10i-1, 10i, 10i+1 and the data lines 30j, 30j+1, 30j+2, and 30j+3 are surrounded by four displays.
  • Each of the display units is correspondingly provided with two sub-pixel electrodes adjacent to each other (the sub-pixel electrodes in FIG. 8 are represented by a bold line frame), and the main electrode lines 21 of the common electrode line 20i are on the upper left and upper right sides.
  • the regions of the two display units respectively extend with branch electrode lines, and the main electrode lines 21 of the common electrode lines 20i+1 respectively extend the branch electrode lines for the regions of the lower left and lower right display units.
  • the branch electrode lines of the common electrode line 20i+1 include:
  • the first branch electrode lines 22a and 22b extending in the same direction as the extending direction of the data lines 30j and 30j+1, and the second branch electrode lines 23a and 23b extending in the same direction as the extending directions of the gate lines 10i and 10i+1 are formed.
  • the display unit in the lower left corner includes pixel electrodes 50i, j, 50i+1, j which are vertically adjacent but spaced apart from each other.
  • the sub-pixel electrode 50i+1,j is connected to the drain 33 of the lower thin film transistor T1 via the via 40a, and the sub-pixel electrode 50i,j is connected to the drain 33 of the upper thin film transistor T2 via the via 40b.
  • the second branch electrode line 23a is disposed in the region of the sub-pixel electrode 50i+1,j, and the second branch electrode line 23a and the via hole 40a are at least partially overlapped.
  • the second branch electrode line 22b is disposed in the region of the sub-pixel electrode 50i,j, and the second branch electrode line 22b and the via hole 40b are at least partially overlapped.
  • the sub-pixel electrode in this embodiment may be a plate-shaped electrode whose edge is a strip electrode 60c, and a slit 60d is formed between each strip electrode 60c.
  • the array substrate provided in this embodiment includes: gate lines 10i-1, 10i, 10i+1, data lines 30j, 30j+1, 30j+2, 30j+3 and common electrode lines 20i, 20i+1.
  • the gate lines 10i-1, 10i, 10i+1 and the data lines 30j, 30j+1, 30j+2, and 30j+3 are divided into four display units, and each display unit is correspondingly provided with two sub-pixels adjacent to each other.
  • An electrode, and a region of the main electrode line 21 of the common electrode line 20i for the upper left and upper right display units respectively has a branch electrode line, and the main electrode line 21 of the common electrode line 20i+1 is for the lower left and lower right display units The regions are respectively extended with branch electrode lines.
  • the branch electrode lines of the common electrode line 20i+1 include: first branch electrode lines 22a, 22b extending in the same direction as the extending direction of the data lines 30j, 30j+1, and extending directions and gates
  • the second branch electrode lines 23a and 23b having the same extending direction of the lines 10i and 10i+1.
  • the display unit in the lower left corner includes sub-pixel electrodes 50i, j, 50i+1, j which are vertically adjacent but spaced apart from each other.
  • Sub-pixel electrode 50i+1,j passes through via 40a and underlying thin film transistor T1
  • the drain electrodes 33 are connected, and the sub-pixel electrodes 50i, j are connected to the drain 33 of the upper thin film transistor T2 through the via holes 40b.
  • the second branch electrode line 23a is disposed in the region of the sub-pixel electrode 50i+1,j, for example, the second branch electrode line 23a overlaps at least a portion of the via hole 40a.
  • the second branch electrode line 22b is disposed in the region of the sub-pixel electrode 50i,j, for example, the second branch electrode line 22b and the via hole 40b at least partially overlap.
  • the first branch electrode lines 22a, 22b are respectively disposed on the left and right sides of the sub-pixel electrodes 50i, j, 50i+1, j, and the gap between the adjacent two sub-pixel electrodes 50i, j, 50i+1, j
  • the extending direction is the same as the direction in which the gate lines extend, wherein one of the second branch electrode lines 23a is at least partially overlapped with the gap; and the other second branch electrode line 23b is connected to the end points of the first branch electrode lines 22a, 22b.
  • the sub-pixel electrode in the present embodiment is, for example, a fine slit electrode including a first root portion 71a, a second root portion 71b, a branch electrode 71c, and a slit 71d.
  • the slit 71d separates the adjacent branch electrodes 71c.
  • the array substrate in this embodiment further includes a connection electrode 24 integrally formed with the common electrode line 20, and the connection electrode 24 is used to connect branch electrode lines of different display regions.
  • the array substrate provided in this embodiment includes: gate lines 10i-1, 10i, 10i+1, data lines 30j, 30j+1, 30j+2, 30j+3, and common electrode lines 20i, 20i+1 ( The common electrode line is shown in bold line frame in Fig. 10).
  • the gate lines 10i-1, 10i, 10i+1 and the data lines 30j, 30j+1, 30j+2, and 30j+3 are divided into four display units, and each display unit is correspondingly provided with two sub-pixel electrodes adjacent to each other.
  • a region on the main electrode line 21 of the common electrode line 20i for the upper left and upper right display units respectively has a branch electrode line
  • the main electrode line 21 of the common electrode line 20i+1 is for the lower left and lower right display units
  • the regions respectively have branch electrode lines extending.
  • the branch electrode lines of the common electrode line 20i+1 include: first branch electrode lines 22a, 22b, 22c extending in the same direction as the extending direction of the data lines 30j, 30j+1, and the extending direction Second branch electrode lines 23a, 23b, 23C having the same extension direction as the gate lines 10i, 10i+1.
  • the display unit in the lower left corner includes sub-pixel electrodes 50i, j, 50i+1, j that are vertically adjacent but spaced apart from each other.
  • the sub-pixel electrode 50i+1,j is connected to the drain 33 of the lower thin film transistor T1 via the via 40a
  • the sub-pixel electrode 50i,j is connected to the drain 33 of the upper thin film transistor T2 via the via 40b.
  • the sub-pixel electrode (for example, the sub-pixel electrode 50i, j, 50i+1, j,) in this embodiment is a fine slit electrode including a first root portion 71a and a second root stem. Portion 71b, branch electrode 71c, and slit 71d. This slit 71d separates the adjacent branch electrodes 71c.
  • the first branch electrode lines 22a, 22b are respectively disposed on the sub-pixel electrodes 50i, j, 50i+! The left and right sides of j, and the first branch electrode line 22c and the second root stem portion 71b are at least partially overlapped.
  • the extending direction of the gap between the adjacent two sub-pixel electrodes 50i, j, 50i+1, j is the same as the extending direction of the gate line, wherein one of the second branch electrode lines 23a and the gap At least partially overlapped.
  • the second branch electrode line 23b is connected to the end points of the first branch electrode lines 22a, 22b, and the second branch electrode line 23c is at least partially overlapped with the first root portion 71a of the sub-pixels 50i+1, j.
  • the common electrode line in this embodiment may further include more first branch electrode lines and second branch electrode lines, and between each of the first branch electrode lines or between the respective second branch electrode lines. It is not necessary to have the same length or width.
  • the embodiment of the present invention further provides a display device including the array substrate of any one of Embodiments 1 to 9, in which the overall resistance of the common electrode line is reduced, and thus the display device of the present embodiment
  • the common electrode signal has a small delay phenomenon and has a higher display quality than current display devices.
  • the display device in this embodiment may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • An embodiment of the present invention provides an array substrate and a display device.
  • the branch electrode line connected to the main electrode line is provided to reduce the resistance value of the entire common electrode line, thereby effectively reducing the delay phenomenon of the common electrode signal, thereby improving the delay.
  • the display quality of the display panel is provided.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及显示装置，阵列基板包括衬底基板（1），设置在衬底基板（1）上的栅线（10）、数据线（30），以及由数据线（30）和栅线（10）交叉限定的显示单元，显示单元内设置有薄膜晶体管、子像素电极（50）以及公共电极线（20）。其中，公共电极线（20）包括：延伸方向与栅线（10）延伸方向相同的主电极线（21），以及与主电极线（21）连接的分支电极线。通过设置与主电极线（21）连接的分支电极线以降低公共电极线（20）整体的阻值，从而有效降低公共电极信号的延迟现象，进而提高显示面板的显示质量。

Description

阵列基板及显示装置 技术领域
本公开涉及一种阵列基板及显示装置。
背景技术
随着目前的显示屏越做越大，公共电极线也越来越长，这使得公共电极线的电阻也变得较大，导致公共电极信号的延迟现象变得更加严重，从而影响了画面的显示质量。
发明内容
本发明至少一个实施例提供一种阵列基板，包括：衬底基板，设置在所述衬底基板上的栅线、数据线，由所述数据线和所述栅线交叉限定的显示单元，所述显示单元内设置有薄膜晶体管、子像素电极以及公共电极线，其中，所述公共电极线包括延伸方向与所述栅线的延伸方向相同的主电极线，以及与所述主电极线连接的分支电极线。
例如，在本发明的实施例提供的阵列基板中，所述分支电极线包括：至少两条延伸方向与所述数据线的延伸方向相同的第一分支电极线；至少一条延伸方向与所述栅线的延伸方向相同的第二分支电极线，所述第二分支电极线连接所有所述第一分支电极线。
例如，在本发明的实施例提供的阵列基板中，所述第一分支电极线为三条，其中两条所述第一分支电极线分别设置于所述显示单元的两端区域，其中一条所述第一分支电极线设置于所述显示单元的中间区域。
例如，在本发明的实施例提供的阵列基板中，所述子像素电极的区域中设置有一条所述第二分支电极线。
例如，在本发明的实施例提供的阵列基板中，所述子像素电极不少于两个，所述子像素电极相互连接，且在至少一个所述子像素电极的区域中设置有一条所述第二分支电极线。
例如，在本发明的实施例提供的阵列基板中，所述子像素电极与所述薄膜晶体管的漏极设置在不同层，并通过过孔与所述薄膜晶体管的漏极连 接，且所述过孔与其中一条所述第二分支电极线至少部分重叠设置。
例如，在本发明的实施例提供的阵列基板中，每个所述显示单元中设置有两个所述子像素电极，所述两个子像素电极相互间隔，且每个所述子像素电极均对应一个所述薄膜晶体管，并分别通过其对应的所述过孔与其对应的所述薄膜晶体的漏极连接，且每个所述过孔分别与不同的所述第二分支电极线至少部分重叠设置。
例如，在本发明的实施例提供的阵列基板中，所述子像素电极为两个，所述两个子像素电极相互间隔，相邻两个所述子像素电极之间的间隙的延伸方向与所述栅线的延伸方向相同，其中一条所述第二分支电极线与所述间隙至少部分重叠。
例如，在本发明的实施例提供的阵列基板中，所述子像素电极为狭缝电极，所述子像素电极包括第一根茎部、第二根茎部、分支电极、狭缝，所述狭缝将相邻的所述分支电极分隔开。
例如，在本发明的实施例提供的阵列基板中，所述第一分支电极线与所述第二根茎部至少部分重叠设置；所述第二分支电极线与所述第一根茎部至少部分重叠。
例如，在本发明的实施例提供的阵列基板中，所述公共电极线与所述栅线同层设置。
例如，在本发明的实施例提供的阵列基板中，所述公共电极线还包括：连接同行的相邻所述显示单元的各个所述分支电极线的连接线。
本发明的实施例还提供一种显示装置，包括上述的阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1、图2为本公开的阵列基板在实施例一中的结构示意图；
图3为本公开的阵列基板在实施例二中的结构示意图；
图4为本公开的阵列基板在实施例三中的结构示意图；
图5为本公开的阵列基板在实施例四中的结构示意图；
图6为本公开的阵列基板在实施例五中的结构示意图；
图7为本公开的阵列基板在实施例六中的结构示意图；
图8为本公开的阵列基板在实施例七中的结构示意图；
图9为本公开的阵列基板在实施例八中的结构示意图；
图10为本公开的阵列基板在实施例九中的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本公开提供一种阵列基板，该阵列基板包括：衬底基板，设置在衬底基板上的栅线、数据线，由数据线和栅线交叉限定的显示单元，该显示单元内设置有薄膜晶体管、子像素电极以及公共电极线，该公共电极线包括延伸方向与栅线的延伸方向相同的主电极线，以及与主电极线连接的分支电极线。
本公开通过设置与主电极线连接的分支电极线，以降低公共电极线整体的阻值，从而解决公共电极信号延迟的问题，进而提高显示面板的显示质量。
下面结合几种实施例，对本公开的阵列基板进行介绍。
实施例一
如图1和图2所示，本实施例的阵列基板包括形成在衬底基板1上的栅线10、数据线30，由数据线30和栅线10交叉限定的显示单元，且显示单元内还包括薄膜晶体管、子像素电极50以及公共电极线20。公共电极线20包括主电极线21和与该主电极线21连接的分支电极线。分支电极线包括延伸方向与数据线30的延伸方向相同的第一分支电极线22a、22b，以及延伸方向与栅线10的延伸方向相同的第二分支电极线23，该第二分支电极线23连接第一分支电极线22a、22b，使得由第一分支电极线22a、22b和第二分支电极线23组成的分支电极线能够与主电极线21连接。
在本实施例中，显示单元包括子像素电极50(图1中的子像素电极以粗体线框体现)，该子像素电极50通过薄膜晶体管与数据线30连接。
例如，该薄膜晶体管包括：栅极10a、有源层25、源极31和漏极33。栅极10a与栅线10连接或一体形成，栅极绝缘层15位于栅极10a上，有源层25位于栅极绝缘层15上，源极31和漏极33位于有源层25上，钝化层35位于源极31和漏极33上，子像素电极50通过钝化层35上的过孔40连接漏极33，且源极31与数据线30连接。
例如，栅极绝缘层15可以采用氮化硅或氧化硅；栅极绝缘层可以是单层结构或者多层结构，例如氧化硅\氮化硅。有源层25可以采用非晶硅，多晶硅，微晶硅或氧化物半导体。钝化层35可以采用无机物如氮化硅，或者采用有机绝缘层，如采用有机树脂材料。子像素电极50采用氧化铟锡(ITO)，氧化铟锌(IZO)或其他透明金属氧化物导电材料制备。
在本实施例中，第二分支电极线23与过孔40至少部分重叠。需要说明的是第二分支电极线23与第一分支电极线22a、22b的连接的位置在此不做限定。
实施例二
参考图3，在本实施例中，公共电极线20包括：主电极线21、第一分支电极线22a、22b和第二分支电极线23a、23b。第一分支电极线22a、22b的延伸方向与数据线30的延伸方向相同，第二分支电极线23a、23b的延伸方向与栅线10的延伸方向相同，第二分支电极线23a、23b分别连接第一分支电极线22a、22b。第二分支电极线23a与过孔40至少部分重叠设置。子像素电极50(图3中的子像素电极以粗体线框体现)通过过孔40与薄膜晶体管的漏极33连接。
需要说明的是，在本实施例中，对第二分支电极线23b与第一分支电极线22a、22b的连接位置不作限定。例如在第一分支电极线22a、22b的长度相等的情况下，第二分支电极线23b可以与第一分支电极线22a、22b的端点分别连接。或者在第一分支电极线22a、22b的长度不等的情况下，第二分支电极线23b与第一分支电极线22a、22b中的长度较短者的端点连接，并与第一分支电极线22a、22b中的长度较长者的非端点部位连接。
实施例三
参考图4，在本实施例中，公共电极线20包括：主电极线21、第一分支电极线22a、22b、22c以及第二分支电极线23a、23b。第一分支电极线22a、22b、22c的延伸方向与数据线30的延伸方向相同，第二分支电极 线23a、23b的延伸方向与栅线10的延伸方向相同，第二分支电极线23a、23b分别连接第一分支电极线22a、22b、22c。
例如，在本实施例中，栅线10和数据线30交叉限定显示单元，例如，如图4所示，上述第一分支电极线22a、22b分别设置在显示单元的两端区域，上述第一分支电极线22c设置于显示单元的中间区域。
此外，本实施例的显示单元内还设置有一个子像素电极50((图4中的子像素电极以粗体线框体现))，该子像素电极50通过过孔40与薄膜晶体管的漏极33连接。
与实施例二不同的是，本实施例包括两个第二分支电极线，且第二分支电极线并不与过孔40至少部分重叠设置。
实施例四
参考图5，在本实施例提供的阵列基板中，公共电极线20包括：主电极线21、第一分支电极线22a、22b以及第二分支电极线23a、23b、23c。第一分支电极线22a、22b的延伸方向与数据线30的延伸方向相同，第二分支电极线23a、23b、23c的延伸方向与栅线10的延伸方向相同，第二分支电极线23a、23b、23c分别连接第一分支电极线22a、22b。
例如，由数据线30和栅线10交叉所限定的显示单元包括子像素电极51、52、53(图5中的子像素以粗体线框体现)。该子像素电极51通过连接部54与子像素电极52连接，子像素电极52通过连接部55与子像素电极53连接。子像素电极51、52、53与连接部54、55一体成形。
示例性地，在本实施例中的子像素电极51、52、53的区域中分别设置有对应的一条第二分支电极线。如图5所示，子像素电极51对应设置有第二分支电极线23a,子像素电极52对应设置有第二分支电极线23b，子像素电极53对应设置有第二分支电极线23c。当然，作为其它可行的方案，在本实施例中也可以只有一部分子像素电极的区域上设置第二分支电极线，比如在子像素电极51和子像素电极52下方各设置一条第二分支电极线；或者在子像素电极51和子像素电极53下方各设置一条第二分支电极线；又或者在子像素电极52和子像素电极53下方各设置一条第二分支电极线，本文不再一一举例赘述。
在本实施例中，子像素电极51通过过孔40与薄膜晶体管的漏极33连接，从而使得子像素电极51、52、53共同加载来自漏极33上的数据线 信号。
例如，如图5所示，子像素电极51对应的第二分支电极线23a与过孔40至少部分重叠设置。
实施例五
参考图6，与实施例四不同的是，本实施例中的子像素电极51、52、53(图6中的子像素电极以粗体线框表示)的主体可以为板状电极(plate electrode)，板状电极的边缘形成有条状电极56。
需要说明的是，本发明的实施例公开的子像素电极不限于图1至图6所示的几种的形状。
实施例六
参考图7，本实施例中的阵列基板包括：栅线10i、10i+1，数据线30j、30j+1、30j+2。其中，栅线10i、10i+1与数据线30j、30j+1围成第一显示单元，在该第一显示单元内设置有子像素电极50i+1，j。同理，栅线10i、10i+1与数据线30j+1、30j+2围成与第一显示单元同行的第二显示单元，在该第二显示单元内设置有子像素电极50i+1，j+1。
例如，在本实施例提供的阵列基板上还设置公共电极线20，该公共电极线20包括主电极线21、以及分别对应第一显示单元和第二显示单元的分支电极线。
以第一显示单元的分支电极线为例进行介绍，该第一显示单元的分支电极线包括：延伸方向与数据线30j、30j+1、30j+2的延伸方向相同的第一分支电极线22a、22b，以及延伸方向与栅线10i、10i+1的延伸方向相同的第二分支电极线23a、23b。子像素电极50i+1，j通过过孔40与薄膜晶体管的漏极33连接。例如，第二分支电极线23a与过孔40至少部分重叠设置。
此外，如图7所示，本实施例为进一步降低公共电极线20的阻值，还通过一连接电极24连接第一显示单元和第二显示单元的分支电极线，该连接电极24与公共电极线20一体成形。
实施例七
参考图8，本实施例提供的阵列基板包括：栅线10i-1、10i、10i+1，数据线30j、30j+1、30j+2、30j+3以及公共电极线20i、20i+1。其中，栅线10i-1、10i、10i+1与数据线30j、30j+1、30j+2、30j+3围成四个显 示单元，每个显示单元均对应设置有上下相邻的两个子像素电极(图8中的子像素电极以粗体线框体现)，且公共电极线20i的主电极线21上针对左上和右上两个显示单元的区域分别延伸有分支电极线，公共电极线20i+1的主电极线21针对左下和右下两个显示单元的区域分别延伸有分支电极线。
以左下角的显示单元为例，公共电极线20i+1的分支电极线包括：
延伸方向与数据线30j、30j+1的延伸方向相同的第一分支电极线22a、22b，以及延伸方向与栅线10i、10i+1的延伸方向相同的第二分支电极线23a、23b。例如，左下角的显示单元包括：上下相邻子但相互间隔的像素电极50i，j、50i+1，j。其中，子像素电极50i+1，j通过过孔40a与下方的薄膜晶体管T1的漏极33连接，子像素电极50i，j通过过孔40b与上方的薄膜晶体管T2的漏极33连接。
对应地，第二分支电极线23a设置在子像素电极50i+1，j的区域内，且该第二分支电极线23a与过孔40a至少部分重叠设置。同理，第二分支电极线22b设置在子像素电极50i，j的区域内，且该第二分支电极线22b与过孔40b至少部分重叠设置。
例如，本实施例中的子像素电极可以是边缘为条状电极60c的板状电极，每个条状电极60c之间形成有狭缝60d。
实施例八
参考图9，本实施例提供的阵列基板包括：栅线10i-1、10i、10i+1，数据线30j、30j+1、30j+2、30j+3以及公共电极线20i、20i+1。该栅线10i-1、10i、10i+1与数据线30j、30j+1、30j+2、30j+3围成四个显示单元，每个显示单元均对应设置有上下相邻的两个子像素电极，且公共电极线20i的主电极线21上针对左上和右上两个显示单元的区域分别延伸有分支电极线，公共电极线20i+1的主电极线21针对左下和右下两个显示单元的区域分别延伸有分支电极线。
以左下角的显示单元为例，公共电极线20i+1的分支电极线包括：延伸方向与数据线30j、30j+1的延伸方向相同的第一分支电极线22a、22b，以及延伸方向与栅线10i、10i+1的延伸方向相同的第二分支电极线23a、23b。左下角的显示单元包括：上下相邻但相互间隔的子像素电极50i，j、50i+1，j。子像素电极50i+1，j通过过孔40a与下方的薄膜晶体管T1的 漏极33连接，子像素电极50i，j通过过孔40b与上方的薄膜晶体管T2的漏极33连接。
对应地，第二分支电极线23a设置在子像素电极50i+1，j的区域内，例如，该第二分支电极线23a与过孔40a至少一部分重叠。同理，第二分支电极线22b设置在子像素电极50i，j的区域内，例如，该第二分支电极线22b与过孔40b至少部分重叠。
例如，第一分支电极线22a、22b分别设置在子像素电极50i，j、50i+1，j的左右两侧，相邻两个子像素电极50i，j、50i+1，j之间的间隙的延伸方向与栅线延伸方向相同，其中一个第二分支电极线23a与该间隙至少部分重叠设置；另一第二分支电极线23b连接第一分支电极线22a、22b的端点。
如图9所示，示例性地，本实施例中的子像素电极例如为精细狭缝电极，该子像素电极包括第一根茎部71a、第二根茎部71b、分支电极71c、狭缝71d。其中，狭缝71d将相邻的分支电极71c分隔开。
此外，本实施例中的阵列基板还包括与公共电极线20一体成形的连接电极24，该连接电极24用于连接不同显示区域的分支电极线。
实施例九
参考图10，本实施例提供的阵列基板包括：栅线10i-1、10i、10i+1，数据线30j、30j+1、30j+2、30j+3以及公共电极线20i、20i+1(公共电极线在图10以粗体线框体现)。栅线10i-1、10i、10i+1与数据线30j、30j+1、30j+2、30j+3围成四个显示单元，每个显示单元均对应设置有上下相邻的两个子像素电极，且公共电极线20i的主电极线21上针对左上和右上两个显示单元的区域分别延伸有分支电极线，公共电极线20i+1的主电极线21针对左下和右下两个显示单元的区域分别延伸有分支电极线。
以左下角的显示单元为例，公共电极线20i+1的分支电极线包括：延伸方向与数据线30j、30j+1的延伸方向相同的第一分支电极线22a、22b、22c，以及延伸方向与栅线10i、10i+1的延伸方向相同的第二分支电极线23a、23b、23C。例如，左下角的显示单元包括：上下相邻但相互间隔的子像素电极50i，j、50i+1，j。例如，子像素电极50i+1，j通过过孔40a与下方的薄膜晶体管T1的漏极33连接，子像素电极50i，j通过过孔40b与上方的薄膜晶体管T2的漏极33连接。
如图10所示，本实施例中的子像素电极(例如子像素电极50i，j、50i+1，j,)为精细狭缝电极，该子像素电极包括第一根茎部71a、第二根茎部71b、分支电极71c、狭缝71d。该狭缝71d将相邻的分支电极71c分隔开。
例如，第一分支电极线22a、22b分别设置在子像素电极50i，j、50i+！，j的左右两侧，而第一分支电极线22c与第二根茎部71b至少部分重叠设置。此外，在本实施例中，相邻两个子像素电极50i，j、50i+1，j之间的间隙的延伸方向与栅线的延伸方向相同，其中一个第二分支电极线23a与所述间隙至少部分重叠设置。第二分支电极线23b连接第一分支电极线22a、22b的端点，第二分支电极线23c与子像素50i+1，j的第一根茎部71a至少部分重叠设置。
需要说明的是，本实施例中的公共电极线还可以包括更多的第一分支电极线以及第二分支电极线，且各个第一分支电极线之间或者各个第二分支电极线之间并不一定要长度或者宽度相等。
实施例十
本发明的实施例还提供一种包括实施例一至实施例九中任一阵列基板的显示装置，在该显示装置中，公共电极线的整体阻值得到了降低，因此本实施例中显示装置的公共电极信号的延迟现象较小，比当前的显示装置具有更高的显示质量。
例如，本实施例中的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明的实施例提供了一种阵列基板及显示装置，通过设置与主电极线连接的分支电极线以降低公共电极线整体的阻值，从而有效降低了公共电极信号的延迟现象，进而提高了显示面板的显示质量。
显然，本领域的技术人员可以对本发明进行各种改动或变型而不脱离本发明的精神和范围。如果这些修改或变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动或变型在内。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年12月1日递交的中国专利申请第201520977392.7号的优先权，在此全文引用上述中国专利申请公开的 内容以作为本申请的一部分。

Claims (13)

  1. 一种阵列基板，包括：
    衬底基板，
    设置在所述衬底基板上的栅线、数据线，以及
    由所述数据线和所述栅线交叉限定的显示单元，所述显示单元内设置有薄膜晶体管、子像素电极以及公共电极线，其中，
    所述公共电极线包括延伸方向与所述栅线的延伸方向相同的主电极线，以及与所述主电极线连接的分支电极线。
  2. 根据权利要求1所述的阵列基板，其中，
    所述分支电极线包括：
    至少两条延伸方向与所述数据线的延伸方向相同的第一分支电极线；
    至少一条延伸方向与所述栅线的延伸方向相同的第二分支电极线，所述第二分支电极线连接所有所述第一分支电极线。
  3. 根据权利要求2所述的阵列基板，其中，
    所述第一分支电极线为三条，其中两条所述第一分支电极线分别设置于所述显示单元的两端区域，其中一条所述第一分支电极线设置于所述显示单元的中间区域。
  4. 根据权利要求2或3所述的阵列基板，其中，
    所述子像素电极的区域中设置有一条所述第二分支电极线。
  5. 根据权利要求2所述的阵列基板，其中，
    所述子像素电极不少于两个，所述子像素电极相互连接，且在至少一个所述子像素电极的区域中设置有一条所述第二分支电极线。
  6. 根据权利要求2所述的阵列基板，其中，
    所述子像素电极与所述薄膜晶体管的漏极设置在不同层，并通过过孔与所述薄膜晶体管的漏极连接，且所述过孔与其中一条所述第二分支电极线至少部分重叠设置。
  7. 根据权利要求6所述的阵列基板，其中，
    每个所述显示单元中设置有两个所述子像素电极，所述两个子像素电极相互间隔，且每个所述子像素电极均对应一个所述薄膜晶体管，并分别通过其对应的所述过孔与其对应的所述薄膜晶体的漏极连接，且每个所述 过孔分别与不同的所述第二分支电极线至少部分重叠设置。
  8. 根据权利要求2所述的阵列基板，其中，
    所述子像素电极为两个，所述两个子像素电极相互间隔，相邻两个所述子像素电极之间的间隙的延伸方向与所述栅线的延伸方向相同，其中一条所述第二分支电极线与所述间隙至少部分重叠。
  9. 根据权利要求2-8中任一项所述的阵列基板，其中，
    所述子像素电极为狭缝电极，所述子像素电极包括第一根茎部、第二根茎部、分支电极、狭缝，所述狭缝将相邻的所述分支电极分隔开。
  10. 根据权利要求9所述的阵列基板，其中，所述第一分支电极线与所述第二根茎部至少部分重叠设置；所述第二分支电极线与所述第一根茎部至少部分重叠。
  11. 根据权利要求1-10中任一项所述的阵列基板，其中，
    所述公共电极线与所述栅线同层设置。
  12. 根据权利要求11所述的阵列基板，其中，
    所述公共电极线还包括：
    连接同行的相邻所述显示单元的各个所述分支电极线的连接线。
  13. 一种显示装置，包括权利要求1-12中任一项所述的阵列基板。
PCT/CN2016/099721 2015-12-01 2016-09-22 阵列基板及显示装置 WO2017092485A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/539,770 US10204929B2 (en) 2015-12-01 2016-09-22 Array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201520977392.7 2015-12-01
CN201520977392.7U CN205139543U (zh) 2015-12-01 2015-12-01 一种阵列基板及显示装置

Publications (1)

Publication Number Publication Date
WO2017092485A1 true WO2017092485A1 (zh) 2017-06-08

Family

ID=55625319

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/099721 WO2017092485A1 (zh) 2015-12-01 2016-09-22 阵列基板及显示装置

Country Status (3)

Country Link
US (1) US10204929B2 (zh)
CN (1) CN205139543U (zh)
WO (1) WO2017092485A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN205139543U (zh) * 2015-12-01 2016-04-06 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN106371256A (zh) * 2016-11-30 2017-02-01 京东方科技集团股份有限公司 像素结构、显示面板及显示装置
CN106773423B (zh) * 2017-02-23 2020-05-19 深圳市华星光电技术有限公司 像素结构、阵列基板和液晶显示面板
CN108628045B (zh) * 2017-03-21 2022-01-25 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN110764329A (zh) * 2019-10-31 2020-02-07 京东方科技集团股份有限公司 阵列基板及其制备方法、液晶显示面板、显示装置
WO2021196089A1 (zh) * 2020-04-01 2021-10-07 京东方科技集团股份有限公司 阵列基板和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101424804A (zh) * 2007-11-02 2009-05-06 上海广电Nec液晶显示器有限公司 液晶显示装置
US20110199550A1 (en) * 2011-01-26 2011-08-18 Fan Shih-Hung Liquid crystal display device
CN104360549A (zh) * 2014-11-17 2015-02-18 深圳市华星光电技术有限公司 一种阵列基板、显示装置
US20150261052A1 (en) * 2011-04-25 2015-09-17 Japan Display Inc. Liquid crystal display device
CN205139543U (zh) * 2015-12-01 2016-04-06 京东方科技集团股份有限公司 一种阵列基板及显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101133761B1 (ko) * 2005-01-26 2012-04-09 삼성전자주식회사 액정 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101424804A (zh) * 2007-11-02 2009-05-06 上海广电Nec液晶显示器有限公司 液晶显示装置
US20110199550A1 (en) * 2011-01-26 2011-08-18 Fan Shih-Hung Liquid crystal display device
US20150261052A1 (en) * 2011-04-25 2015-09-17 Japan Display Inc. Liquid crystal display device
CN104360549A (zh) * 2014-11-17 2015-02-18 深圳市华星光电技术有限公司 一种阵列基板、显示装置
CN205139543U (zh) * 2015-12-01 2016-04-06 京东方科技集团股份有限公司 一种阵列基板及显示装置

Also Published As

Publication number Publication date
US20180012907A1 (en) 2018-01-11
US10204929B2 (en) 2019-02-12
CN205139543U (zh) 2016-04-06

Similar Documents

Publication Publication Date Title
WO2017092485A1 (zh) 阵列基板及显示装置
US20190157311A1 (en) Flexible array substrate and preparation method thereof, display substrate and display device
US9496288B2 (en) Array substrate, display panel and display apparatus
WO2018036179A1 (zh) 触控结构、阵列基板和显示装置
US10197870B2 (en) Array substrate and display device
US10317758B2 (en) Array substrate and display device
US9461074B2 (en) Motherboard, array substrate and fabrication method thereof, and display device
US9869914B2 (en) Array substrate and display device
WO2016110036A1 (zh) 阵列基板及显示装置
WO2016119344A1 (zh) 阵列基板及其制造方法和显示面板
WO2019242438A1 (zh) 阵列基板及其制作方法、显示装置
US10147744B2 (en) Array substrate, method of manufacturing the same, and display device
JP7362488B2 (ja) タッチ表示基板および表示装置
US20230017104A1 (en) Array substrate and display device
KR101689462B1 (ko) 디스플레이 장치
WO2016141705A1 (zh) 阵列基板及其制造方法和显示装置
WO2016011716A1 (zh) 阵列基板和显示装置
WO2016106893A1 (zh) 阵列基板及显示面板
WO2016023303A1 (zh) 阵列基板及其制造方法、显示装置
US9841639B2 (en) Touch display panel and fabrication method thereof, and display device
WO2016110039A1 (zh) 像素结构、阵列基板、显示面板和显示装置
WO2019184070A1 (zh) 显示装置及其阵列基板
WO2015143837A1 (zh) 薄膜晶体管及其制备方法、阵列基板及显示装置
US9401374B2 (en) Pixel structure, dual gate pixel structure and display device
WO2019051971A1 (zh) 阵列基板及显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15539770

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16869796

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16869796

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16869796

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 18/01/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 16869796

Country of ref document: EP

Kind code of ref document: A1