WO2015143837A1 - 薄膜晶体管及其制备方法、阵列基板及显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板及显示装置 Download PDF

Info

Publication number
WO2015143837A1
WO2015143837A1 PCT/CN2014/085499 CN2014085499W WO2015143837A1 WO 2015143837 A1 WO2015143837 A1 WO 2015143837A1 CN 2014085499 W CN2014085499 W CN 2014085499W WO 2015143837 A1 WO2015143837 A1 WO 2015143837A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
active layer
thin film
film transistor
cover
Prior art date
Application number
PCT/CN2014/085499
Other languages
English (en)
French (fr)
Inventor
吴俊纬
李禹奉
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/436,373 priority Critical patent/US9590055B2/en
Publication of WO2015143837A1 publication Critical patent/WO2015143837A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor, a method for fabricating the same, an array substrate, and a display device.
  • the source and drain electrodes are directly disposed above the active layer, and there is no setting between the source/drain electrodes and the active layer.
  • Etch barrier ESL Due to the lack of protection of the etch barrier layer, subsequent fabrication processes and the environment after fabrication are more or less affected by portions of the active layer that are not covered by the source/drain electrodes, thereby affecting the oxide thin film transistor. performance.
  • the present disclosure provides a thin film transistor, an array substrate, and a display device, which can ensure effective protection of an active layer of a BCE type oxide thin film transistor.
  • an embodiment of the present disclosure provides a thin film transistor including: a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode, wherein the source electrode and the drain electrode are formed in the Above the source layer, and respectively located at opposite first and second ends of the active layer; the drain electrode completely covers the second end of the active layer.
  • the drain electrode is rectangular.
  • drain electrode comprises:
  • the cover electrode completely covers the second end of the active layer, and the longitudinal width of the cover electrode is greater than or equal to the longitudinal width of the active layer;
  • the contact electrode is for contacting with a pixel electrode, wherein a longitudinal width of the contact electrode is greater than a longitudinal width of the cover electrode, and the longitudinal direction is connected to the first end and the second end of the active layer The direction in which the line is perpendicular.
  • drain electrode comprises:
  • the connecting electrode being located between the covering electrode and the contact electrode, respectively connected to the covering electrode and the contact electrode;
  • the cover electrode completely covers the second end of the active layer
  • connection electrode is at least partially overlapped with the gate electrode, the longitudinal width of the connection electrode is smaller than a longitudinal width of the cover electrode, and the longitudinal direction is opposite to the first end and the second end of the active layer The direction in which the line is perpendicular;
  • the contact electrode is for contacting the pixel electrode.
  • the cover electrode and the connection electrode are connected in a T-shape or an L-shape.
  • the cover electrode is rectangular.
  • the cover electrode has a concave shape, and an opening of the groove covering the electrode faces the source electrode.
  • the longitudinal width of the contact electrode is greater than or equal to the longitudinal width of the connection electrode.
  • the source electrode completely covers the first end of the active layer.
  • the source electrode includes: a first electrode, a second electrode, and a third electrode, the second electrode being located between the first electrode and the third electrode, respectively, with the first electrode and the The third electrode is connected;
  • first electrode and the second electrode are connected in a T-shape or an L-shape.
  • the first electrode has a rectangular shape.
  • the present disclosure also provides an array substrate including the above thin film transistor.
  • the present disclosure also provides a display device including the above array substrate.
  • the drain electrode of the thin film transistor can completely cover one end portion of the active layer, thereby enabling the active layer to be protected as much as possible, and reducing the influence of the subsequent fabrication process and the environment after the fabrication on the active layer.
  • FIG. 1 is a schematic structural view of a thin film transistor according to Embodiment 1 of the present disclosure.
  • FIG. 2 is a schematic structural view of a thin film transistor according to Embodiment 2 of the present disclosure.
  • FIG. 3 is a schematic structural view of a thin film transistor according to Embodiment 3 of the present disclosure.
  • FIG. 4 is a schematic structural view of a thin film transistor according to Embodiment 4 of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a thin film transistor according to Embodiment 5 of the present disclosure.
  • FIG. 6 is a schematic structural view of a thin film transistor according to Embodiment 6 of the present disclosure.
  • the present disclosure provides a BCE type thin film transistor that does not include an etch barrier layer, the thin film transistor including: a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode, the source An electrode and the drain electrode are formed above the active layer and respectively located at opposite first and second ends of the active layer, the drain electrode completely covering the active layer Two ends.
  • the longitudinal width of the partial electrode of the drain electrode for covering the second end of the active layer must be greater than or equal to The longitudinal width of the second end of the active layer.
  • the longitudinal direction is the first end of the active layer and The direction of the line connecting the second end is perpendicular to the direction.
  • the drain electrode of the thin film transistor can completely cover one end portion of the active layer, thereby enabling the active layer to be protected as much as possible, reducing the subsequent manufacturing process and the environment after the completion of the fabrication. The effect of the generation of the active layer.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to Embodiment 1 of the present disclosure.
  • the thin film transistor includes a gate electrode 201, a gate insulating layer (not shown), an active layer 202, a source electrode 203, and a drain electrode 204, the source electrode 203 and the drain electrode 204 are formed above the active layer 203, and are respectively located at opposite first and second ends of the active layer 203, The drain electrode 204 completely covers the second end of the active layer 202, and the drain electrode 204 is rectangular.
  • FIG. 2 is a schematic structural diagram of a thin film transistor according to Embodiment 2 of the present disclosure.
  • the thin film transistor includes a gate electrode 201, a gate insulating layer (not shown), an active layer 202, a source electrode 203, and a drain electrode 204, the source electrode 203 and the drain electrode 204 are formed above the active layer 203, and are respectively located at opposite first and second ends of the active layer 203, The drain electrode 204 completely covers the second end of the active layer 202.
  • the area in which the source electrode 203 overlaps the gate electrode 201 becomes smaller, thereby reducing the capacitance between the source electrode 203 and the gate electrode 201 and improving the performance of the thin film transistor.
  • first electrode 2031 and the second electrode 2042 are connected in a T-type.
  • first electrode 2031 and the second electrode 2042 may also be Other connections, such as an L-shaped connection.
  • the first electrode 2031 has a rectangular shape.
  • the first electrode 2031 may have other shapes, for example, a concave shape, and an opening of the groove faces the drain electrode.
  • the source electrode partially covers both ends in the longitudinal direction of the active layer in addition to the first end portion of the active layer The active layer is further protected.
  • the longitudinal width of the contact electrode 2042 is greater than the longitudinal width of the connecting electrode 2043.
  • the contact electrode The longitudinal width of 2042 may also be equal to the longitudinal width of the connecting electrode 2043, and in addition, the possibility that the longitudinal width of the contact electrode 2042 is smaller than the longitudinal width of the connecting electrode 2043 is not excluded.
  • An embodiment of the present disclosure further provides an array substrate, including the thin film transistor described in any of the above embodiments.
  • the embodiment of the present disclosure further provides a method for fabricating a thin film transistor, which is used to prepare the thin film transistor in the above embodiment, the method comprising: forming a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode a step of forming the source electrode and the drain electrode over the active layer and respectively located at opposite first and second ends of the active layer, the drain electrode being completely Covering the second end of the active layer.
  • the longitudinal width of the partial electrode of the drain electrode for covering the second end of the active layer must be greater than or equal to The longitudinal width of the second end of the active layer.
  • the longitudinal direction is a direction perpendicular to a direction in which the first end portion and the second end portion of the active layer are connected.
  • the drain electrode of the thin film transistor can completely cover one end portion of the active layer, thereby enabling the active layer to be protected as much as possible, reducing the subsequent manufacturing process and the environment after the completion of the fabrication. The effect of the generation of the active layer.

Abstract

一种薄膜晶体管及其制作方法、阵列基板及显示装置，该薄膜晶体管包括：栅电极、栅绝缘层、有源层、源电极和漏电极，所述源电极和所述漏电极形成于所述有源层的上方，且分别位于所述有源层的相对的第一端部和第二端部；所述漏电极完全覆盖住所述有源层的第二端部。能够保证背沟道刻蚀类型的氧化物薄膜晶体管的有源层得到有效的保护。

Description

薄膜晶体管及其制备方法、阵列基板及显示装置
相关申请的交叉引用
本申请主张在2014年3月25日在中国提交的中国专利申请号No.201410113582.4的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、阵列基板及显示装置。
背景技术
在现有技术中的背沟道刻蚀(BCE)类型的氧化物薄膜晶体管(TFT)中，源电极和漏电极直接设置于有源层上方，源/漏电极和有源层之间没有设置刻蚀阻挡层(ESL)。由于缺少了刻蚀阻挡层的保护，后续制作工艺以及制作完成后的环境等，或多或少会对有源层的未被源/漏电极覆盖的部分产生影响，从而影响氧化物薄膜晶体管的性能。
发明内容
有鉴于此，本公开提供一种薄膜晶体管、阵列基板及显示装置，能够保证BCE类型的氧化物薄膜晶体管的有源层得到有效的保护。
为解决上述技术问题，本公开的实施例提供一种薄膜晶体管，包括：栅电极、栅绝缘层、有源层、源电极和漏电极，所述源电极和所述漏电极形成于所述有源层的上方，且分别位于所述有源层的相对的第一端部和第二端部；所述漏电极完全覆盖住所述有源层的第二端部。
其中，所述漏电极为矩形。
其中，所述漏电极包括：
彼此相连的覆盖电极和接触电极；其中，
所述覆盖电极，完全覆盖住所述有源层的第二端部，所述覆盖电极的纵向宽度大于或等于所述有源层的纵向宽度；
所述接触电极，用于与像素电极接触，所述接触电极的纵向宽度大于所述覆盖电极的纵向宽度，所述纵向是与所述有源层的第一端部和第二端部的连线所在方向垂直的方向。
其中，所述漏电极包括：
覆盖电极、连接电极和接触电极，所述连接电极位于所述覆盖电极和所述接触电极之间，分别与所述覆盖电极和所述接触电极相连；
所述覆盖电极，完全覆盖住所述有源层的第二端部；
所述连接电极，至少部分与所述栅电极重叠，所述连接电极的纵向宽度小于所述覆盖电极的纵向宽度，所述纵向是与所述有源层的第一端部和第二端部的连线所在方向垂直的方向；
所述接触电极，用于与像素电极接触。
其中，所述覆盖电极和所述连接电极呈T型或L型连接。
其中，所述覆盖电极为矩形。
其中，所述覆盖电极呈凹字型，所述覆盖电极的凹槽的开口朝向所述源电极。
其中，所述接触电极的纵向宽度大于或等于所述连接电极的纵向宽度。
其中，所述源电极完全覆盖住所述有源层的第一端部。
其中，所述源电极包括：第一电极、第二电极和第三电极，所述第二电极位于所述第一电极和所述第三电极之间，分别与所述第一电极和所述第三电极相连；
所述第一电极，完全覆盖住所述有源层的第一端部；
所述第二电极，至少部分与所述栅电极重叠，所述第二电极的纵向宽度小于所述第一电极和所述第三电极的纵向宽度，所述纵向是与所述有源层的第一端部和第二端部的连线所在方向垂直的方向。
其中，所述第一电极和所述第二电极呈T型或L型连接。
其中，所述第一电极呈矩形。
其中，所述第一电极呈凹字型，其凹槽的开口朝向所述漏电极。
本公开还提供一种阵列基板，包括上述薄膜晶体管。
本公开还提供一种显示装置，包括上述阵列基板。
本公开还提供了一种薄膜晶体管的制备方法，包括：
形成栅电极、栅绝缘层、有源层、源电极和漏电极的步骤，
其中，所述源电极和所述漏电极形成于所述有源层的上方，且分别位于所述有源层的相对的第一端部和第二端部，所述漏电极完全覆盖住所述有源层的第二端部。
本公开的上述技术方案的有益效果如下：
薄膜晶体管的漏电极能够完全覆盖住有源层的一端部，因而使得有源层能够尽可能地得到保护，减小后续制作工艺以及制作完成后的环境等对有源层的产生的影响。
附图说明
图1为本公开实施例一的薄膜晶体管的结构示意图。
图2为本公开实施例二的薄膜晶体管的结构示意图。
图3为本公开实施例三的薄膜晶体管的结构示意图。
图4为本公开实施例四的薄膜晶体管的结构示意图。
图5为本公开实施例五的薄膜晶体管的结构示意图。
图6为本公开实施例六的薄膜晶体管的结构示意图。
具体实施方式
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本公开提供一种BCE类型的薄膜晶体管，该种类型的薄膜晶体管不包括刻蚀阻挡层，所述薄膜晶体管包括：栅电极、栅绝缘层、有源层、源电极和漏电极，所述源电极和所述漏电极形成于所述有源层的上方，且分别位于所述有源层的相对的第一端部和第二端部，所述漏电极完全覆盖住所述有源层的第二端部。
由于所述漏电极能够完全覆盖住所述有源层的第二端部，因此所述漏电极的用于覆盖所述有源层的第二端部的部分电极的纵向宽度必然大于或等于所述有源层的第二端部的纵向宽度。所述纵向是与所述有源层的第一端部和 第二端部的连线所在方向垂直的方向。
通过本公开实施例提供的方案，薄膜晶体管的漏电极能够完全覆盖住有源层的一端部，因而使得有源层能够尽可能地得到保护，减小后续制作工艺以及制作完成后的环境等对有源层的产生的影响。
下面结合具体实施例，对本公开的薄膜晶体管的结构进行详细说明。
实施例一
请参考图1，图1为本公开的实施例一的薄膜晶体管的结构示意图，所述薄膜晶体管包括：栅电极201、栅绝缘层(图未示出)、有源层202、源电极203和漏电极204，所述源电极203和所述漏电极204形成于所述有源层203的上方，且分别位于所述有源层203的相对的第一端部和第二端部，所述漏电极204完全覆盖住所述有源层202的第二端部，所述漏电极204为矩形。
实施例二
请参考图2，图2为本公开的实施例二的薄膜晶体管的结构示意图，所述薄膜晶体管包括：栅电极201、栅绝缘层(图未示出)、有源层202、源电极203和漏电极204，所述源电极203和所述漏电极204形成于所述有源层203的上方，且分别位于所述有源层203的相对的第一端部和第二端部，所述漏电极204完全覆盖住所述有源层202的第二端部。
所述漏电极204包括：彼此相连的覆盖电极2041和接触电极2042；其中，所述覆盖电极2041完全覆盖住所述有源层202的第二端部；所述接触电极2042用于与像素电极接触，所述接触电极2042的纵向宽度大于所述覆盖电极2041的纵向宽度，如图所示，所述纵向(Y方向)是与所述有源层202的第一端部和第二端部的连线所在方向(X方向)垂直的方向。
该实施例与实施例一相比，漏电极204与栅电极201重叠的面积变小，从而减小漏电极204与栅电极201之间的栅漏电容(Cgd)，提高薄膜晶体管的性能。
实施例三
请参考图3，图3为本公开的实施例三的薄膜晶体管的结构示意图，所述薄膜晶体管包括：栅电极201、栅绝缘层(图未示出)、有源层202、源电 极203和漏电极204，所述源电极203和所述漏电极204形成于所述有源层203的上方，且分别位于所述有源层203的相对的第一端部和第二端部，所述漏电极204完全覆盖住所述有源层202的第二端部。
所述漏电极204包括：
覆盖电极2041、连接电极2043和接触电极2042，所述连接电极2043位于所述覆盖电极2041和所述接触电极2042之间，分别与所述覆盖电极2041和所述接触电极2042相连；其中，所述覆盖电极2041完全覆盖住所述有源层202的第二端部；所述连接电极2043至少部分与所述栅电极201重叠，所述连接电极2043的纵向宽度小于所述覆盖电极2041的纵向宽度，如图所示，所述纵向(Y方向)是与所述有源层202的第一端部和第二端部的连线所在方向(X方向)垂直的方向。所述接触电极2042用于与像素电极接触。
该实施例与实施例二相比，所述漏电极204的覆盖电极2041和连接电极2043呈T型连接，漏电极204与栅电极201重叠的面积变得更小，从而进一步减小了漏电极204与栅电极201之间的栅漏电容(Cgd)，提高薄膜晶体管的性能。
实施例四
请参考图4，图4为本公开的实施例四的薄膜晶体管的结构示意图，该实施例与实施例三的区别仅在于，实施例三中，所述覆盖电极2041和所述连接电极2043呈T型连接，本公开实施例中，所述覆盖电极2041和所述连接电极2043呈L型连接。
当然，在本公开的其他实施例中，所述覆盖电极2041和所述连接电极2043也不排除采用其他方式连接。
上述实施例二至实施例四中的所述覆盖电极均为矩形，当然，在本公开的其他实施例中，所述覆盖电极也可以为其他形状，下面举例进行说明。
实施例五
请参考图5，图5为本公开的实施例五的薄膜晶体管的结构示意图，该实施例与实施例三的区别仅在于，所述覆盖电极2041呈凹字型，所述覆盖电极2041的凹槽的开口朝向所述源电极203。
该种结构的薄膜晶体管中，所述漏电极204除了覆盖住所述有源层202 的第二端部之外，还部分覆盖所述有源层202的纵向方向上的两个端部，使得有源层202进一步得到保护。
上述各实施例中，所述源电极203同时完全覆盖住所述有源层202的第一端部，以使得有源层202进一步得到保护。
上述实施例一至实施例五中，所述源电极203均呈矩形，呈矩形的源电极203与位于其下层的栅电极201之间的重叠面积较大，使得所述源电极203与栅电极201之间的电容较大，影响薄膜晶体管的性能。
实施例六
请参考图6，图6为本公开的实施例六的薄膜晶体管的结构示意图，该实施例与实施例三的区别仅在于，所述源电极203包括：
第一电极2031、第二电极2032和第三电极2033，所述第二电极2032位于所述第一电极2031和所述第三电极2033之间，分别与所述第一电极2031和所述第三电极2033相连；
所述第一电极2031，完全覆盖住所述有源层202的第一端部；
所述第二电极2032，至少部分与所述栅电极201重叠，所述第二电极2032的纵向宽度小于所述第一电极2031和所述第三电极2032的纵向宽度，所述纵向是与所述有源层202的第一端部和第二端部的连线所在方向垂直的方向。
该实施例与上述各实施例相比，源电极203与栅电极201重叠的面积变小，从而减小源电极203与栅电极201之间的电容，提高薄膜晶体管的性能。
本实施例中，所述第一电极2031和所述第二电极2042呈T型连接，当然，在本公开的其他实施例中，所述第一电极2031和所述第二电极2042还可以为其他连接方式，如呈L型连接。
本实施例中，所述第一电极2031呈矩形，当然，所述第一电极2031也可以为其他形状，例如，呈凹字型，其凹槽的开口朝向所述漏电极。当薄膜晶体管包括呈凹字型的第一电极时，所述源电极除了覆盖住所述有源层的第一端部之外，还部分覆盖所述有源层的纵向方向上的两个端部，使得有源层进一步得到保护。
上述实施例三至实施例六中，所述接触电极2042的纵向宽度均大于所述连接电极2043的纵向宽度，当然，在本公开的其他实施例中，所述接触电极 2042的纵向宽度也可以等于所述连接电极2043的纵向宽度，另外，也不排除接触电极2042的纵向宽度小于所述连接电极2043的纵向宽度的可能。
上述实施例三至实施例六的附图中的虚线表示漏电极204各个部分的分割线。
本公开实施例还提供一种阵列基板，包括上述任一实施例所述的薄膜晶体管。
本公开实施例还提供一种显示装置，包括上述阵列基板。所述显示装置可以为：液晶显示面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供一种薄膜晶体管的制备方法，所述方法用于制备上述实施例中的薄膜晶体管，所述方法包括：形成栅电极、栅绝缘层、有源层、源电极和漏电极的步骤，其中，所述源电极和所述漏电极形成于所述有源层的上方，且分别位于所述有源层的相对的第一端部和第二端部，所述漏电极完全覆盖住所述有源层的第二端部。
由于所述漏电极能够完全覆盖住所述有源层的第二端部，因此所述漏电极的用于覆盖所述有源层的第二端部的部分电极的纵向宽度必然大于或等于所述有源层的第二端部的纵向宽度。所述纵向是与所述有源层的第一端部和第二端部的连线所在方向垂直的方向。
通过本公开实施例提供的方案，薄膜晶体管的漏电极能够完全覆盖住有源层的一端部，因而使得有源层能够尽可能地得到保护，减小后续制作工艺以及制作完成后的环境等对有源层的产生的影响。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (16)

  1. 一种薄膜晶体管，包括：栅电极、栅绝缘层、有源层、源电极和漏电极，所述源电极和所述漏电极形成于所述有源层的上方，且分别位于所述有源层的相对的第一端部和第二端部；其中，所述漏电极完全覆盖住所述有源层的第二端部。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述漏电极为矩形。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述漏电极包括：
    彼此相连的覆盖电极和接触电极；其中，
    所述覆盖电极，完全覆盖住所述有源层的第二端部，所述覆盖电极的纵向宽度大于或等于所述有源层的纵向宽度；
    所述接触电极，用于与像素电极接触，所述接触电极的纵向宽度大于所述覆盖电极的纵向宽度，所述纵向是与所述有源层的第一端部和第二端部的连线所在方向垂直的方向。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述漏电极包括：
    覆盖电极、连接电极和接触电极，所述连接电极位于所述覆盖电极和所述接触电极之间，分别与所述覆盖电极和所述接触电极相连；
    所述覆盖电极，完全覆盖住所述有源层的第二端部；
    所述连接电极，至少部分与所述栅电极重叠，所述连接电极的纵向宽度小于所述覆盖电极的纵向宽度，所述纵向是与所述有源层的第一端部和第二端部的连线所在方向垂直的方向；
    所述接触电极，用于与像素电极接触。
  5. 根据权利要求4所述的薄膜晶体管，其中，所述覆盖电极和所述连接电极呈T型或L型连接。
  6. 根据权利要求3-5中任一项所述的薄膜晶体管，其中，所述覆盖电极为矩形。
  7. 根据权利要求3-5中任一项所述的薄膜晶体管，其中，所述覆盖电极呈凹字型，所述覆盖电极的凹槽的开口朝向所述源电极。
  8. 根据权利要求4所述的薄膜晶体管，其中，所述接触电极的纵向宽度 大于或等于所述连接电极的纵向宽度。
  9. 根据权利要求1-8中任一项所述的薄膜晶体管，其中，所述源电极完全覆盖住所述有源层的第一端部。
  10. 根据权利要求1所述的薄膜晶体管，其中，所述源电极包括：第一电极、第二电极和第三电极，所述第二电极位于所述第一电极和所述第三电极之间，分别与所述第一电极和所述第三电极相连；
    所述第一电极，完全覆盖住所述有源层的第一端部；
    所述第二电极，至少部分与所述栅电极重叠，所述第二电极的纵向宽度小于所述第一电极和所述第三电极的纵向宽度，所述纵向是与所述有源层的第一端部和第二端部的连线所在方向垂直的方向。
  11. 根据权利要求10所述的薄膜晶体管，其中，所述第一电极和所述第二电极呈T型或L型连接。
  12. 根据权利要求10或11所述的薄膜晶体管，其中，所述第一电极呈矩形。
  13. 根据权利要求10或11所述的薄膜晶体管，其中，所述第一电极呈凹字型，其凹槽的开口朝向所述漏电极。
  14. 一种阵列基板，包括权利要求1-13任一项所述的薄膜晶体管。
  15. 一种显示装置，包括权利要求14所述的阵列基板。
  16. 一种薄膜晶体管的制备方法，包括：
    形成栅电极、栅绝缘层、有源层、源电极和漏电极的步骤，
    其中，所述源电极和所述漏电极形成于所述有源层的上方，且分别位于所述有源层的相对的第一端部和第二端部，所述漏电极完全覆盖住所述有源层的第二端部。
PCT/CN2014/085499 2014-03-25 2014-08-29 薄膜晶体管及其制备方法、阵列基板及显示装置 WO2015143837A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/436,373 US9590055B2 (en) 2014-03-25 2014-08-29 Thin film transistor, method for manufacturing the same, array substrate, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410113582.4A CN103915509B (zh) 2014-03-25 2014-03-25 一种薄膜晶体管、阵列基板及显示装置
CN201410113582.4 2014-03-25

Publications (1)

Publication Number Publication Date
WO2015143837A1 true WO2015143837A1 (zh) 2015-10-01

Family

ID=51041044

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/085499 WO2015143837A1 (zh) 2014-03-25 2014-08-29 薄膜晶体管及其制备方法、阵列基板及显示装置

Country Status (3)

Country Link
US (1) US9590055B2 (zh)
CN (1) CN103915509B (zh)
WO (1) WO2015143837A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915509B (zh) 2014-03-25 2017-07-18 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
CN104576760A (zh) * 2015-02-02 2015-04-29 合肥鑫晟光电科技有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
US10417369B2 (en) 2017-05-26 2019-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, corresponding mask and method for generating layout of same
CN107968095A (zh) * 2017-11-21 2018-04-27 深圳市华星光电半导体显示技术有限公司 背沟道蚀刻型tft基板及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6479398B1 (en) * 2000-08-02 2002-11-12 Industrial Technology Research Institute Method of manufacturing an amorphous-silicon thin film transistor
US20060170048A1 (en) * 2005-01-31 2006-08-03 Quanta Display Inc. Thin film transistor array substrate and fabrication method thereof
CN102593189A (zh) * 2012-03-29 2012-07-18 浙江大学 一种薄膜晶体管
CN103545221A (zh) * 2013-11-14 2014-01-29 广州新视界光电科技有限公司 金属氧化物薄膜晶体管及其制备方法
CN103915509A (zh) * 2014-03-25 2014-07-09 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
CN203746864U (zh) * 2014-03-25 2014-07-30 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4604440B2 (ja) * 2002-02-22 2011-01-05 日本電気株式会社 チャネルエッチ型薄膜トランジスタ
JP4046267B2 (ja) 2002-03-26 2008-02-13 株式会社半導体エネルギー研究所 表示装置
CN100468749C (zh) * 2003-04-09 2009-03-11 友达光电股份有限公司 薄膜晶体管的双栅极布局结构
CN100578814C (zh) * 2006-03-03 2010-01-06 中华映管股份有限公司 薄膜晶体管与薄膜晶体管阵列基板
CN100557804C (zh) * 2006-04-11 2009-11-04 中华映管股份有限公司 像素结构、薄膜晶体管阵列基板以及液晶显示面板
CN100510918C (zh) * 2006-04-12 2009-07-08 中华映管股份有限公司 像素结构及其液晶显示面板
CN101315937A (zh) * 2007-05-29 2008-12-03 中华映管股份有限公司 像素阵列
CN101556959A (zh) * 2008-04-10 2009-10-14 北京京东方光电科技有限公司 阵列基板及液晶显示装置
CN102054832B (zh) * 2009-10-29 2012-04-18 华映视讯（吴江）有限公司 具有电容补偿的像素结构
CN101750826B (zh) * 2009-12-28 2011-09-14 深超光电（深圳）有限公司 像素结构
WO2013089115A1 (en) * 2011-12-15 2013-06-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6479398B1 (en) * 2000-08-02 2002-11-12 Industrial Technology Research Institute Method of manufacturing an amorphous-silicon thin film transistor
US20060170048A1 (en) * 2005-01-31 2006-08-03 Quanta Display Inc. Thin film transistor array substrate and fabrication method thereof
CN102593189A (zh) * 2012-03-29 2012-07-18 浙江大学 一种薄膜晶体管
CN103545221A (zh) * 2013-11-14 2014-01-29 广州新视界光电科技有限公司 金属氧化物薄膜晶体管及其制备方法
CN103915509A (zh) * 2014-03-25 2014-07-09 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
CN203746864U (zh) * 2014-03-25 2014-07-30 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置

Also Published As

Publication number Publication date
US20160293716A1 (en) 2016-10-06
CN103915509B (zh) 2017-07-18
CN103915509A (zh) 2014-07-09
US9590055B2 (en) 2017-03-07

Similar Documents

Publication Publication Date Title
US20160291750A1 (en) Array substrate and liquid crystal display panel
JP6570640B2 (ja) 配列基板と、表示パネルと、配列基板の調製方法
US11049889B2 (en) Method for preparing array substrate by stripping first photo-resist layer through wet etching before forming ohm contact layer and active layer
US9859304B2 (en) Manufacturing method of array substrate, array substrate and display device
WO2016045423A1 (en) Array substrate, fabrication method thereof and display device
US9450103B2 (en) Thin film transistor, method for manufacturing the same, display device and electronic product
US9773817B2 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
JP6359650B2 (ja) アレイ基板、表示装置及びアレイ基板の製作方法
TWI497182B (zh) 顯示裝置
EP3089214B1 (en) Array substrate and manufacturing method thereof, and display device
WO2019242438A1 (zh) 阵列基板及其制作方法、显示装置
WO2015143837A1 (zh) 薄膜晶体管及其制备方法、阵列基板及显示装置
WO2017092485A1 (zh) 阵列基板及显示装置
WO2017156885A1 (zh) 薄膜晶体管、阵列基板及其制作和驱动方法、显示装置
US20190094639A1 (en) Array substrate, manufacturing method thereof and display device
WO2015096374A1 (zh) 阵列基板及其制作方法、显示装置和薄膜晶体管
CN105140291B (zh) 薄膜晶体管及其制作方法、阵列基板以及显示装置
CN106292100B (zh) 阵列基板及具有该阵列基板的液晶显示面板
WO2015096369A1 (zh) 阵列基板及其制造方法、显示装置
US20180149934A1 (en) Array substrate and liquid crystal display panel
US10126610B2 (en) Array substrate, manufacturing method thereof and display device
WO2020062422A1 (zh) 一种阵列基板及显示面板
WO2014146362A1 (zh) 阵列基板及其制备方法和显示面板
US9685463B2 (en) Array substrate, its manufacturing method, display panel and display device
TWI588968B (zh) 顯示面板及其製造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14436373

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14887260

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 17.02.2017)

122 Ep: pct application non-entry in european phase

Ref document number: 14887260

Country of ref document: EP

Kind code of ref document: A1