WO2015096369A1 - 阵列基板及其制造方法、显示装置 - Google Patents
阵列基板及其制造方法、显示装置 Download PDFInfo
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- WO2015096369A1 WO2015096369A1 PCT/CN2014/078267 CN2014078267W WO2015096369A1 WO 2015096369 A1 WO2015096369 A1 WO 2015096369A1 CN 2014078267 W CN2014078267 W CN 2014078267W WO 2015096369 A1 WO2015096369 A1 WO 2015096369A1
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- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
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Definitions
- Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
- TFT-LCD Thin Film Transistor Liquid Crystal Display, film
- TFT-LCD Thin Film Transistor Liquid Crystal Display, film
- Transparent metal oxide materials such as indium tin oxide (ITO)
- ITO indium tin oxide
- Source drain and data line Such a cross-sectional structure of the array substrate along the data line direction can As shown in FIG. 1, the gate line 11 (including the gate of the TFT) and the gate insulating layer 12 are sequentially formed.
- a data line 13 is formed on the surface of the gate insulating layer 12, the data line 13 is made of ITO material, and the surface of the data line 13 is sequentially formed with an etch barrier layer 14 And a transparent electrode 15.
- the data line 13 and the transparent electrode 15 have a longer section of overlap, so that in the case of power up, due to the level difference, A parasitic capacitance Cdc is generated between the data line 14 and the transparent electrode 15.
- Input on data line 14 At the moment of the voltage signal, the voltage signal on the data line 14 is high due to the existence of parasitic capacitance.
- a low change causes the transparent electrode 15 to undergo a voltage change correspondingly, thereby causing application to the image
- the voltage on the liquid crystal changes in the prime causing the display to flicker and the data line is delayed. And power consumption will also increase.
- an array substrate comprises: on a transparent base A plurality of gate lines and data lines arranged horizontally and vertically on the board.
- the data line is formed in the same layer as the gate line
- the surface of the transparent substrate, the data line is disconnected in the gate line region.
- the area of the gate line a connection pattern, the connection pattern is insulated from the gate line, and the data is located on both sides of the gate line
- the wires are electrically connected by the connection pattern.
- a display device includes as described above Array substrate.
- a method of fabricating an array substrate includes: Forming gate lines and data lines on the surface of the transparent substrate in the same layer, and the data lines are disconnected in the gate line region; Forming a connection pattern corresponding to the gate line region on the substrate having the gate line and the data line, the connection The connection pattern is insulated from the gate line, and the data lines on both sides of the gate line pass through the connection pattern Electrical connection.
- FIG. 1 is a schematic structural view of an array substrate according to a technique
- FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
- FIG. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
- FIG. 4 is a partial plan view of a substrate after forming an insulating layer pattern and a cross-sectional view taken along line A-A thereof;
- FIG. 5 is a partial plan view of a substrate after forming a gate line, a data line, and a gate of a TFT; B-B cross-sectional view;
- FIG. 6 is a schematic structural view of a substrate after forming an insulating material layer
- FIG. 7 is a schematic structural view of a substrate after forming a first insulating layer
- FIG. 8 is a schematic structural view of a substrate after forming a gate insulating layer
- FIG. 9 is a partial plan view of a substrate after forming an active layer, and a cross-sectional view taken along line C-C thereof;
- FIG. 10 is a schematic structural view of a substrate after forming an etch barrier layer
- 11 is a partial plan view of a substrate after forming a via hole, and a cross-sectional view taken along line D-D thereof;
- FIG. 12 is a partial plan view of a substrate after forming a connection pattern and a source/drain of a TFT, and an E-E thereof Cross-sectional view;
- Figure 13 is a partial plan view of the substrate after forming the first transparent electrode and its F-F cross-sectional view
- FIG. 14 is a schematic structural view of a substrate after forming a passivation layer
- 15 is a partial plan view of a substrate after forming a second transparent electrode.
- the array substrate provided by the embodiment of the present invention includes: The gate line 21 and the data line 22, the data line 22 is disposed in the same layer as the gate line 21, and the data line 22 is on the gate line The 21 area is disconnected.
- the array substrate further includes a first transparent electrode 241 at least part of the data line and A first insulating layer 26, a gate insulating layer 27, and an etch barrier are disposed between the first transparent electrodes 241 Layer 23.
- the gate line 21 and the data line 22 may be formed of the same metal layer by one patterning process. It is formed on the surface of the transparent substrate 20.
- the gate line 21 region has a connection pattern 25, and the connection pattern 25 and the gate line 21 are absolutely
- the data lines 22 located on both sides of the gate line 21 are electrically connected by the connection pattern 25.
- the data lines are formed in the same layer as the gate lines, and the data lines are The gate line region is disconnected, and the disconnected data lines are electrically connected by a connection pattern disposed in the gate line region.
- the data line and the transparent can be significantly increased on the basis of ensuring the quality of the gate line and the data line.
- the spacing between the electrodes thereby effectively reducing the parasitic capacitance Cdc between the data line and the transparent electrode,
- the output jump voltage caused by excessive parasitic capacitance is prevented from being bad, and the display screen is effectively improved. Flashing, reducing data line delay and power consumption, and improving the quality of the display device.
- the first insulating layer 26 covers the gate line 21 and the data line 22 is located at the gate. Other parts than the ends on either side of the line. The ends of the data lines 22 on both sides of the gate line 21 are exposed at The surface of the first insulating layer 26. In the area of the gate line 21, the connection pattern 25 is formed on the first insulating layer The surface of 26.
- the surface of the edge layer 26 may be formed on the surface of the transparent substrate 20 by a patterning process in advance. a height of the insulating layer pattern 261, the insulating layer pattern 261 may be located on both sides of the gate line 21 to be formed According to the area of the line. Further forming gate lines 21 and numbers on the surface of the substrate on which the insulating layer pattern 261 is formed According to the line 22, the ends of the data lines 22 on both sides of the gate line 21 are covered in the insulating layer pattern 261. surface. Then, the insulating layer material is deposited to expose at least the data lines on the surface of the insulating layer pattern 261, Thereby, the first insulating layer 26 is finally formed.
- the first insulating layer 26 may be formed by other processes, which is not limited in the present invention.
- the data line 22 and the first transparent electrode The pitch D' between 241 is much larger than the pitch D between the data line 13 and the transparent electrode 15 in Fig. 1.
- the array substrate may further include a TFT, a gate of the TFT (not shown in the figure) Shown in the same layer as the gate line 21.
- the gate portion of the TFT is exposed on the surface of the first insulating layer 26.
- it may be on both sides of the gate line 21.
- the region where the data line is to be formed forms the insulating layer pattern 261, and is formed in the channel region of the TFT. There is a certain height of the insulating layer pattern 261.
- a gate electrode is formed while forming a data line and a gate line. then, Depositing an insulating layer material to form a first insulating layer 26 and exposing a gate portion of the TFT to the first insulating layer The surface of layer 26.
- the gate of the TFT can be raised to make the channel region of the TFT
- the array substrate may further include the gate electrode sequentially formed on the gate surface of the TFT The edge layer 27 and the active layer (not shown in Fig. 2).
- the active layer may be made of a transparent metal oxide material having semiconductor characteristics.
- metal The oxide material may include: IGZO (indium gallium zinc oxide), IGO (indium gallium oxide), ITZO At least one of (indium tin zinc oxide) and AlZnO (aluminum zinc oxide).
- IGZO indium gallium zinc oxide
- IGO indium gallium oxide
- ITZO At least one of (indium tin zinc oxide) and AlZnO (aluminum zinc oxide).
- the active layer of the TFT has the advantages of low preparation temperature requirement and high mobility, and the technology can be applied to High-frequency display and high-resolution display products with equipment investment costs relative to LTPS TFT technology Low, low operating support costs and so on.
- a gate insulating layer 27 is formed on the surface of the first insulating layer 26.
- An etch barrier layer 23 is formed on the surface of the gate insulating layer 27.
- a via penetrates through the etch barrier layer 23 and the gate insulating layer 27 to expose the via hole
- connection pattern 25 can be further formed by the patterning process in the region of the via hole. This can effectively define the coverage area of the connection pattern 25.
- An array substrate having such a structure Since the first line having a certain thickness is further added between the data line 22 and the first transparent electrode 241 The insulating layer 26 and the gate insulating layer 27, so that the data line 22 and the first transparent electrode can be further enlarged The spacing between 241 reduces the parasitic capacitance existing between the data line 22 and the first transparent electrode 241 Cdc.
- the structure of the array substrate provided by the embodiment of the present invention may also be as shown in FIG. 3, including:
- the first insulating layer 262 covers the gate line 21 and the data line 22.
- In the gate line 21 area a region in which the connection pattern 25 is formed on the surface of the first insulating layer 262, and the connection pattern 25 passes through
- the via holes of an insulating layer 262 are electrically connected to the ends of the data lines 22 on both sides of the gate lines 21, respectively.
- the rest of the structure can refer to the array substrate shown in FIG.
- the difference from the array substrate shown in FIG. 2 is that the array substrate shown in FIG. 3 does not need to be in advance.
- the surface of the substrate is formed with the insulating layer pattern 261, so that the array substrate can be simplified to some extent. Production process to reduce production difficulty.
- the first insulating layer 26 shown in FIG. 2 and the first insulating layer shown in FIG. 262 can be made of a material such as an organic resin material having good insulating properties, and the present invention No restrictions.
- the TFT-LCD array substrate provided by the embodiment of the present invention can be applied to FFS.
- FFS Flexible Field Switching
- AD-SDS Advanced-Super Dimensional Switching, referred to as ADS
- ADS advanced super-dimensional field switch type
- IPS In Plane
- TN Transverse electric field effect type
- TN Transverse electric field effect type
- the electric field and the longitudinal electric field generated between the pixel electrode layer and the common electrode layer form a multi-dimensional electric field, so that the liquid crystal All the aligned liquid crystal molecules between the pixel electrodes in the box and directly above the electrodes can generate a rotation conversion, thereby The planar orientation system liquid crystal working efficiency is improved and the light transmission efficiency is increased.
- the counter substrate and the array substrate which are formed into a box are included.
- the common electrode of the TN type display device is disposed on the opposite substrate, and the pixel electrode is disposed in the array.
- public power of the FFS type display device, the ADS type display device, and the IPS type display device Both the pole and the pixel electrode are disposed on the array substrate.
- the array substrate may further include: a passivation layer 28 formed on the surface of the first transparent electrode 241, The passivation layer 28 covers the connection pattern 25 located in the area of the gate line 21; and is formed on the surface of the passivation layer The second transparent electrode 242.
- the first transparent electrode 241 may be a pixel electrode, and the second transparent electrode 242 may be a common electrode.
- the first transparent electrode 241 can be a plate-like structure, and the second transparent electrode 242 can include multiple Bar electrodes arranged in a row.
- the common electrode and the pixel electrode are different Layer setting, optionally, the electrode on the upper layer contains a plurality of strip electrodes, and the electrodes on the lower layer may Contains multiple strip electrodes or is flat.
- the electrode located in the lower layer is The shape of the flat plate is taken as an example.
- the different layer settings are for at least two patterns, at least two patterns
- the heterogeneous layer setting means that at least two layers of the film are respectively formed into at least two patterns by a patterning process. Correct The arrangement of the two patterns in different layers means that a pattern is formed by each of the two films by a patterning process.
- the lower electrode is formed by the second layer of the transparent conductive film
- the upper electrode is formed by a patterning process, wherein
- the lower electrode is a common electrode (or a pixel electrode), and the upper electrode is a pixel electrode (or a common electrode).
- the array substrate provided by the embodiment of the invention can also be applied to an IPS type display device, and FFS
- the type display device is different in that the common electrode and the pixel electrode are disposed in the same layer, and the public power
- the pole includes a plurality of first strip electrodes, the pixel electrodes including a plurality of second strip electrodes, the first The strip electrode and the second strip electrode are spaced apart.
- the same layer setting is for at least two patterns
- At least two patterns in the same layer arrangement mean that at least two patterns are formed by the same film through a patterning process case.
- the same layer arrangement of the common electrode and the pixel electrode means: by the same transparent conductive film
- the pattern process forms a pixel electrode and a common electrode.
- the pixel electrode refers to a switch unit (for example, Is a thin film transistor) electrically connected to the data line, the common electrode is electrically connected to the common electrode line Electrode.
- Embodiments of the present invention also provide a display device including the array base as described above. board.
- the array substrate includes a plurality of gate lines 21 and data lines 22 disposed transversely and vertically, and the data lines 22 and The gate lines 21 are disposed in the same layer, and the data lines 22 are disconnected in the area of the gate lines 21.
- the array substrate further includes a transparent electrode 241, disposed between at least a portion of the data line and the first transparent electrode 241
- An insulating layer 26 (or first insulating layer 262), a gate insulating layer 27, and an etch stop layer 23.
- the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, or a liquid Any product or component with display function, such as crystal display, digital photo frame, mobile phone, tablet computer, etc.
- a display device provided by an embodiment of the invention includes an array substrate by using a data line and a gate line
- the layer is fabricated, and the data line is disconnected in the gate line region, and the connection pattern disposed in the gate line region is broken.
- the data lines are electrically connected. In this way, it can be significant on the basis of ensuring the quality of the grid lines and data lines.
- the parasitic capacitance Cdc between them prevents the output jump voltage from being excessive due to excessive parasitic capacitance. Effectively improve display screen flicker, reduce data line delay and power consumption, and improve the quality of display devices.
- the embodiment of the invention further provides a method for manufacturing an array substrate, the method comprising:
- the gate line and the data line can be formed of the same layer of metal material by a patterning process.
- connection pattern Form a connection pattern on the corresponding gate line region on the substrate on which the gate line and the data line are formed.
- the connection pattern is insulated from the gate lines, and the data lines on both sides of the gate lines are electrically connected by a connection pattern.
- the method for manufacturing an array substrate provided by the embodiment of the present invention is to make a data line and a gate line in the same layer. And the data line is disconnected in the gate line region, and the disconnected data line is formed by the connection pattern disposed in the gate line region Electrical connection.
- the data can be significantly increased on the basis of ensuring the quality of the gate line and the data line.
- the spacing between the line and the transparent electrode which can effectively reduce the parasitic between the data line and the transparent electrode Capacitor Cdc, in order to avoid the output jump voltage caused by excessive parasitic capacitance, effectively change Good display flickering, reducing data line delay and power consumption, and improving the quality of the display device.
- the method for manufacturing an array substrate provided by the embodiment of the present invention includes:
- the insulating layer pattern 261 is formed in The area on both sides of the gate line where the data line is to be formed.
- the insulating layer pattern 261 may be further formed at The channel region of the TFT.
- the transparent substrate may be made of a transparent material such as glass or a transparent resin having a certain firmness. to make.
- an insulating layer pattern is formed by one patterning process. For example, you can first The surface of the transparent substrate is coated with a layer of organic resin material having a certain thickness, by having a specific pattern The mask is subjected to exposure development to finally form an insulating layer pattern 261 as shown in FIG.
- plasma enhanced chemical vapor deposition can be used on a substrate on which an insulating layer pattern is formed.
- PECVD plasma enhanced chemical vapor deposition
- the metal layer can A single layer film formed of a metal such as molybdenum, aluminum, aluminum bismuth alloy, tungsten, chromium, or copper, or the like A multilayer film formed of metal. Patterning the metal layer to form a gate 71 and a gate line of the TFT 21 and the data line 22 are as shown in the top view of the array substrate in FIG.
- the gate 71 of the TFT is located in the trench
- the insulating layer pattern 261 of the track region is used to form a metal layer.
- a surface of the substrate on which the gate lines and the data lines are formed may be coated with a certain thickness
- the organic resin material is as shown in FIG. 6 to form a layer 260 of insulating material.
- the insulating material layer 260 The gate and data lines will be completely covered.
- the insulating material layer 260 is processed by an ashing process, and its thickness is reduced overall. Low until the surface of the data line is exposed, a patterned first insulating layer 26 is finally formed.
- an ashing process is taken as an example, and it should be understood that in order to expose the position In the data lines on the surface of the insulating layer pattern, various other patterning processes can also be used, and the present invention No restrictions.
- the ends of the data lines on both sides of the gate lines are exposed on the surface of the first insulating layer, and the number A first insulating layer is formed on the surface of the portion other than the end portions on both sides of the gate line.
- a uniform thickness is formed on the surface of the substrate on which the first insulating layer 26 is formed.
- Gate insulating layer 27 is formed on the surface of the substrate on which the first insulating layer 26 is formed.
- a semiconductor layer may be formed on the surface of the substrate on which the above structure is formed, and exposed through a mask The active layer 111 as shown in the top view of the array substrate in FIG. 9 is formed.
- the active layer 111 may adopt semiconductor characteristics.
- the metal oxide material may include: IGZO, IGO, At least one of ITZO and AlZnO.
- Transparent metal is used relative to a-Si TFT or LTPS TFT
- An oxide material to form an active layer of the TFT which has low preparation temperature requirements and high mobility Advantages, the technology can be applied to high frequency display and high resolution display products, and compared to LTPS TFT Technology has the advantages of low equipment investment cost and low operating guarantee cost.
- the pattern 23 of the etch stop layer can be as shown in FIG.
- it can be formed by An etch stop layer is coated or deposited on the substrate of the structure.
- the substrate structure can be as shown in FIG.
- connection pattern 25 can be further formed by the patterning process in the region of the via hole. This can effectively define the coverage area of the connection pattern 25.
- An array substrate having such a structure Since the first line having a certain thickness is further added between the data line 22 and the first transparent electrode 241 The insulating layer 26 and the gate insulating layer 27, so that the data line 22 and the first transparent electrode can be further enlarged The spacing between 241 reduces the parasitic capacitance existing between the data line 22 and the first transparent electrode 241 Cdc.
- connection pattern 25 The substrate structure in which the connection pattern 25 is formed may be as shown in FIG. Data line on both sides of the grid line The connection patterns 25 are electrically connected to each other.
- the substrate on which the first transparent electrode 241 is formed may be as shown in FIG.
- the substrate on which the passivation layer 28 is formed may be as shown in FIG.
- a top view of the substrate on which the second transparent electrode 242 is formed may be as shown in FIG. 15 along the G-G
- a schematic cross-sectional view of the direction is a schematic structural view of the array substrate shown in FIG.
- the first transparent electrode 241 may be a pixel electrode, and the second transparent electrode 242 may be a common electrode, and The first transparent electrode 241 may be a plate-like structure, and the second transparent electrode 242 may include a plurality of spaces. Arranged strip electrodes.
- the array substrate provided by the embodiment of the invention can also be applied to an ADS type display device and an IPS type.
- Production of various display device array substrates such as display devices or TN type display devices. I can think of it when When the position or shape structure of the pixel electrode or the common electrode is changed, by changing the above process Related steps, the production of various structural array substrates can also be realized, which is in the embodiment of the present invention. Not enumerated one by one.
- the space between the data line and the transparent electrode can be significantly increased. Distance, so that the capacitance between the two electrodes of the parallel plate capacitor is increased, so that the capacitance value is significantly reduced. It can effectively reduce the parasitic capacitance Cdc between the data line and the transparent electrode, thereby avoiding parasitic If the capacitor is too large, the output jump voltage is poor, which can effectively improve the display screen flicker and lower the data line. Delay and power consumption improve the quality of the display device.
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Abstract
Description
Claims (20)
- 一种阵列基板,包括:在透明基板上横纵交叉设置的多条栅线和数据 线,其中所述数据线与所述栅线同层形成在所述透明基板的表面,所述数据线在 所述栅线区域断开;并且所述栅线的区域具有连接图案,所述连接图案与所述栅线绝缘,位于所 述栅线两侧的所述数据线通过所述连接图案电连接。
- 根据权利要求1所述的阵列基板,其中所述阵列基板还包括第一透明 电极,在至少部分数据线与所述第一透明电极之间设置有第一绝缘层、栅绝 缘层和刻蚀阻挡层。
- 根据权利要求2所述的阵列基板,其中所述第一绝缘层覆盖栅线以及数据线的除位于栅线两侧的端部之外的其 他部分,数据线的位于栅线两侧的端部露出在该第一绝缘层的表面。
- 根据权利要求3所述的阵列基板,其中所述阵列基板还包括TFT,所述TFT的栅极与所述栅线同层制成;并且所述TFT的栅极部分露出在所述第一绝缘层的表面。
- 根据权利要求3所述的阵列基板,其中所述栅绝缘层形成在所述第一绝缘层表面;所述刻蚀阻挡层形成在所述栅绝缘层的表面;在所述栅线区域,过孔贯穿所述刻蚀阻挡层和所述栅绝缘层,以暴露出 过孔底部的所述第一绝缘层以及所述数据线的位于所述栅线两侧的端部。
- 根据权利要求5所述的阵列基板,其中所述连接图案形成在所述过孔中,并电连接所述数据线的位于所述栅线 两侧的端部。
- 根据权利要求2所述的阵列基板,其中所述第一绝缘层覆盖所述栅线与所述数据线;在所述栅线区域,所述连接图案形成在所述第一绝缘层的表面,且所述 连接图案通过贯穿所述第一绝缘层的过孔分别与位于所述栅线两侧的所述数 据线电连接。
- 根据权利要求7所述的阵列基板,其中所述栅绝缘层形成在所述第一绝缘层表面;并且所述刻蚀阻挡层形成在所述栅绝缘层的表面。
- 根据权利要求1-8任一所述的阵列基板,其中所述阵列基板还包括:形成在所述第一透明电极表面的钝化层,所述钝化层还覆盖位于所述栅 线区域的连接图案;以及形成在所述钝化层表面的第二透明电极。
- 根据权利要求9所述的阵列基板,其中所述第一透明电极为像素电 极,所述第二透明电极为公共电极;并且所述第一透明电极为板状结构,所述第二透明电极包括多个间隔排列的 条状电极。
- 一种显示装置,包括如权利要求1-10任一所述的阵列基板。
- 一种阵列基板制造方法,包括:在透明基板的表面同层形成栅线和数据线,数据线在栅线区域断开;在形成有所述栅线和所述数据线的基板上对应所述栅线区域形成连接图 案,所述连接图案与所述栅线绝缘,位于所述栅线两侧的所述数据线通过所 述连接图案电连接。
- 根据权利要求12所述的制造方法,还包括:形成第一透明电极,并且在至少部分数据线与所述第一透明电极之间形 成第一绝缘层、栅绝缘层和刻蚀阻挡层。
- 根据权利要求13所述的制造方法,包括:在透明基板的表面通过构图工艺形成绝缘层图案,该绝缘层图案形成在 栅线两侧的待形成数据线的区域;在形成有绝缘层图案的基板的表面通过构图工艺形成栅线和数据线,数 据线位于栅线两侧的端部覆盖在绝缘层图案的表面;在栅线和数据线的表面形成绝缘材料层;采用灰化工艺处理绝缘材料层,以至少暴露出位于绝缘层图案表面的数 据线,以形成所述第一绝缘层。
- 根据权利要求14所述的制造方法,还包括在形成有所述第一绝缘层的基板的表面形成所述栅绝缘层;在所述栅绝缘层对应TFT的栅极区域的表面通过构图工艺形成有源层;在形成有所述有源层的基板的表面形成所述刻蚀阻挡层;在刻蚀阻挡层的表面通过构图工艺形成贯穿刻蚀阻挡层和栅绝缘层的过 孔,以暴露出过孔底部的第一绝缘层以及数据线的位于栅线两侧的端部;以 及在第一绝缘层的表面,对应栅线区域通过构图工艺形成所述连接图案。
- 根据权利要求14所述的方法,其中所述绝缘层图案还位于TFT的 沟道区域,所述TFT的栅极部分覆盖在所述绝缘层图案的表面。
- 根据权利要求13所述的制造方法,包括:在透明基板的表面同层形成栅线和数据线;形成所述第一绝缘层以覆盖所述栅线和所述数据线;并且形成贯穿所述第一绝缘层的过孔,该过孔对应于数据线的位于栅线两侧 的端部;以及在所述第一绝缘层的表面,对应栅线区域通过构图工艺形成连接图案。
- 根据权利要求17所述的方法,还包括:在所述第一绝缘层的表面形成所述栅绝缘层;在所述栅绝缘层对应TFT的栅极区域的表面通过构图工艺形成有源层;在形成有所述有源层的基板的表面形成所述刻蚀阻挡层。
- 根据权利要求13-18任一所述的阵列基板制造方法,还包括:在形成有刻蚀阻挡层的基板的表面通过构图工艺形成所述第一透明电 极;在所述第一透明电极的表面通过构图工艺形成钝化层,所述钝化层还覆 盖位于所述栅线区域的连接图案;在所述钝化层的表面通过构图工艺处理形成第二透明电极。
- 根据权利要求19所述的阵列基板制造方法,其中所述第一透明电极 为像素电极,所述第二透明电极为公共电极;并且所述第一透明电极为板状结构,所述第二透明电极包括多个间隔排列的 条状电极。
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CN109887885A (zh) * | 2019-03-01 | 2019-06-14 | 武汉华星光电技术有限公司 | 阵列基板的制作方法及阵列基板 |
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CN102645801A (zh) * | 2011-04-07 | 2012-08-22 | 京东方科技集团股份有限公司 | 薄膜晶体管阵列基板、彩膜基板、制作方法和显示设备 |
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CN103730474A (zh) * | 2013-12-26 | 2014-04-16 | 京东方科技集团股份有限公司 | 一种阵列基板及其制造方法、显示装置 |
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