WO2017012304A1 - 一种阵列基板、显示装置及制作方法 - Google Patents

一种阵列基板、显示装置及制作方法 Download PDF

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Publication number
WO2017012304A1
WO2017012304A1 PCT/CN2016/070741 CN2016070741W WO2017012304A1 WO 2017012304 A1 WO2017012304 A1 WO 2017012304A1 CN 2016070741 W CN2016070741 W CN 2016070741W WO 2017012304 A1 WO2017012304 A1 WO 2017012304A1
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Prior art keywords
common electrode
line
electrode line
array substrate
pixel
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PCT/CN2016/070741
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English (en)
French (fr)
Inventor
李少茹
金熙哲
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京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US15/301,972 priority Critical patent/US10031393B2/en
Publication of WO2017012304A1 publication Critical patent/WO2017012304A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of liquid crystal display, and more particularly to an array substrate, a display device, and a method of fabricating the same.
  • liquid crystal display devices have replaced traditional cathode ray tube displays in many electronic products because of their advantages of thinness, power saving, and no radiation.
  • the gate can be driven by the single side of the Gate IC, that is, the array substrate can have a common electrode (common electrode) trace on one side, and the common electrode trace can be reduced by designing a wider common electrode. Small common electrode resistance, which reduces the probability of Greenish occurrence.
  • the Gate IC needs to be designed to be driven on both sides of the array substrate, so that the entire display device has no wiring space for the common electrode, and the current solution is to increase the cost.
  • the Gate IC sets the voltage compensation circuit to eliminate the Greenish phenomenon.
  • the present disclosure is to solve the problem of signal interference caused by excessive resistance of the common electrode line in current high-resolution, large-sized display devices.
  • an embodiment of the present disclosure provides an array substrate, including: a substrate substrate; and a plurality of gate lines, data lines, a first common electrode, and a second common electrode disposed on the substrate;
  • the first common electrode line is the same as the extending direction of the gate line; the second common electrode line The extending direction of the data line is the same; the first common electrode line is different from the second common electrode line, and the first common electrode line is bridged with the second common electrode line.
  • the gate line is disposed in the same layer as the first common electrode line.
  • the second common electrode line is disposed in the same layer as the data line; the array substrate further includes: a gate insulating layer disposed between the gate line and the data line; the gate insulating layer is disposed a via hole; the second common electrode line spanning the first common electrode line through a via of the gate insulating layer.
  • the via hole of the gate insulating layer is located at a overlapping area of the first common electrode line and the second common electrode line.
  • the array substrate includes: a plurality of rows and columns of sub-pixels, wherein the plurality of rows and columns of sub-pixels are divided into a plurality of pixel groups, each pixel group is composed of two sub-pixels adjacent to each other, and one sub-pixel There is only one pixel group corresponding to each; wherein each row of pixel groups is respectively provided with a gate line belonging to the row pixel group above and below; in each pixel group, one sub-pixel is driven by a corresponding gate line above it; The other sub-pixel is driven by a corresponding gate line below it, and the two sub-pixels are connected to the same data line; the second common electrode line is disposed between the control groups.
  • the array substrate further includes: a common electrode formed on the base substrate; the first common electrode line directly overlaps the common electrode.
  • the array substrate further includes: a common electrode formed above the data line layer, the common electrode and the second common electrode line being bridged.
  • the gate line and the first common electrode line are formed by a first metal material layer, and the data line and the second common electrode line are formed by a second metal material layer;
  • the second common electrode line is specifically disposed in a non-display area between adjacent data lines.
  • the array substrate further includes: a pixel electrode; and the second common electrode line is disposed in the same layer as the pixel electrode.
  • the array substrate further includes: a common electrode disposed above the pixel electrode layer; a passivation layer disposed between the common electrode and the pixel electrode, the passivation layer is provided with a via; the common An electrode bridges the second common electrode line through a via of the passivation layer.
  • Another embodiment of the present disclosure also provides a display device including the above array substrate.
  • another embodiment of the present disclosure further provides a method for fabricating the above array substrate, including the steps of forming gate lines and data lines on a substrate;
  • the manufacturing method further includes: forming a first one obtained from the first material layer by a first patterning process a common electrode line, the first common electrode line extending in the same direction as the gate line; forming a second common electrode line obtained from the second material layer by a second patterning process; the second common electrode line and the The data lines extend in the same direction;
  • the first common electrode line and the second common electrode line are different layers, and the first common electrode line and the second common electrode line are bridged.
  • the manufacturing method further includes: forming, by the first patterning process, a gate line obtained from the first material layer;
  • a data line or a pixel electrode obtained from the second material layer is formed by the second patterning process.
  • the common electrode lines are respectively disposed on the two conductive layers of the original grid line and the data line of the array substrate, and the two common electrode lines are connected in parallel to reduce the common
  • the resistance of the electrode line reduces the influence of the voltage fluctuation of the common electrode signal, and can effectively avoid the green screen phenomenon.
  • FIG. 1 is a schematic structural view of an array substrate of the present disclosure
  • FIG. 2 is a schematic structural view of an array substrate of a single gate driving method in the related art
  • FIG. 3 is a schematic structural view of an array substrate of a dual gate driving method in the related art
  • FIG. 4 is a schematic structural view of an array substrate in at least some embodiments of the present disclosure.
  • Figure 5 is a cross-sectional view of the array substrate of Figure 4.
  • FIG. 6 is a schematic structural view of an array substrate in at least some embodiments of the present disclosure.
  • FIG. 7 is a schematic structural view of an array substrate in at least some embodiments of the present disclosure.
  • 8A-8F are schematic diagrams showing the process of fabricating the structure of the array substrate shown in FIG. 6.
  • the present disclosure provides a new structure of an array substrate on which a small resistance common electrode line can be disposed, thereby reducing voltage interference of a common electrode signal.
  • the array substrate of this embodiment includes:
  • a gate line 2, a data line 4, and a common electrode line are formed on the base substrate 1.
  • the common electrode line is composed of two parts, that is, a first common electrode line a that is the same as the direction in which the gate line 2 extends, and is disposed in the same layer, and a second common electrode line b that is the same as the direction in which the data lines extend.
  • the first common electrode line a and the second common electrode line b are bridged, that is, another functional layer (such as a gate insulating layer) is formed between the two.
  • the resistance value of the entire common electrode line can be effectively reduced, thereby reducing the voltage fluctuation of the common electrode signal, and the green screen phenomenon can be effectively avoided.
  • the first common electrode line and the gate line extend in the same direction, then the first common electrode line and the gate line are in the first patterning process, and the same layer or even the same material is the easiest to implement.
  • the second common electrode line and the data line can also be formed in the same layer or even the same material in one patterning process.
  • the distance between the signal lines is too close, and interference occurs.
  • the gate line is loaded with a scan signal, and the scan signal only needs to open the corresponding thin film transistor with a fixed potential, so when the first common electrode line is disposed between the gate lines, there is no need to worry about the first common electrode line.
  • the signal will interfere with the scan signal.
  • the data signal on the data line needs to constantly change the potential to change the polarity of the pixel. Therefore, if the second common electrode line is too close to the data line, the display quality will be affected. Therefore, as an alternative, it is necessary to reasonably select whether to set the second common electrode line on the data line layer according to the distance between the data lines.
  • the distance between the data lines is determined by the driving manner of the pixels.
  • pixel driving methods namely “single gate drive” and “double gate drive”.
  • Each sub-pixel of the single-gate drive that is, the row up, is loaded with a data signal by a respective one of the data lines.
  • the pixel units in the row up include red R, green G, and blue B3 seed pixels (white pixel is additionally added to the pixel unit of the 4K display).
  • the sub-pixels R, G, and B in the same row respectively correspond to the thin film transistors T1, T2, and T3.
  • the thin film transistors T1, T2, and T3 are driven by the same gate line.
  • the sub-pixel R loads the data signal on the data line 41
  • the sub-pixel G loads the data signal on the data line 42
  • the sub-pixel B loads the data signal on the data line 43.
  • it is a single gate driven structure.
  • the sub-pixel is divided into a plurality of pixel groups, each pixel group is composed of two sub-pixels adjacent to each other, and one sub-pixel corresponds to only one pixel group; wherein, each row of pixel groups is above and below Each of the pixel groups is respectively provided with a gate line belonging to the pixel group of the row; in each pixel group, one sub-pixel is driven by a corresponding gate line above the other, and the other sub-pixel is driven by a corresponding gate line below, and the two sub-pixels
  • the pixels are connected to the same data line.
  • the sub-pixels R, G, and B of the same row respectively correspond to the thin film transistors T1, T2, and T3.
  • the thin film transistors T1, T3 are driven by the gate lines 21, and after the gate lines 21 open the thin film transistors T1, T3, the sub-pixels R, G load the data signals on the data lines 41.
  • the thin film transistor T2 is driven by the gate line 22, and after the gate line 22 turns on the thin film transistor T2, the sub-pixel B loads the data signal on the data line 42.
  • the distance L2 between the two data lines in Fig. 3 is much larger than the distance L1 between the two data lines in Fig. 2. That is, in the structure of the double gate driving, the second common electrode line is disposed in the same layer as the data line, and the distance between them is far from each other, and the phenomenon of mutual signal interference can be effectively suppressed. In the single-gate driving structure, the spacing between the data lines is relatively close. To avoid affecting the display quality, the second common electrode line may be disposed on other conductive layers (such as the pattern layer of the pixel electrode).
  • the array substrate in at least some embodiments of the present disclosure is a dual gate driving structure in which a second common electrode line is formed in a data line layer. As shown in FIG. 4 and FIG. 5, the array substrate includes:
  • a gate line 2 is extended at a position of the gate Ta, and a first common electrode line a is formed also in the same layer as the gate line.
  • a data line 4 extends at a position of the source Tb, and a second common electrode line b is formed in the same layer as the data line, and the second common electrode line b is bridged through the via 31 of the gate insulating layer 3 to the first common
  • the electrode line a, the via 31 of the gate insulating layer is located at a region of overlap of the first common electrode line and the second common electrode line.
  • the second common electrode line b may be located on the non-display area between the pixel areas 9 (ie, between the groups of pixels described above) to avoid obscuring the underlying light source.
  • a flat layer 5 is formed over the second common electrode line b and the data line.
  • the pixel layer 6 is provided on the flat layer 5, and the pixel electrode 6 is connected to the drain Tc through a via hole on the flat layer 5.
  • a passivation layer 7 is formed over the pixel electrode 6, and a common electrode 8 is formed on the passivation layer 7, and the common electrode 8 is connected to the second common electrode line b through the passivation layer 7 and via holes on the flat layer 5, that is, The common electrode is bridged with the second common electrode line, wherein the common electrode 8 has a slit shape, and the pixel electrode 6 has a plate shape.
  • the second common electrode line b may also be disposed in the same layer as the pixel electrode 6.
  • the common electrode 8 formed over the pixel electrode 6 bridges the second common electrode line b through the via of the passivation layer 7.
  • the pixel electrode is in the display region, and thus is made of a transparent conductive ITO material, and the data line of the non-display region can be formed of a metal material that is opaque but has better conductivity (such as copper, aluminum, molybdenum).
  • the second common electrode line is arranged in the data line layer, and it is apparent that the effect of reducing the resistance is better than the arrangement of the common electrode line in the pixel electrode layer.
  • the second common electrode lines are disposed between the data lines. It can be seen that the gate line layer and the data line layer are relatively close two conductive layers in the entire array substrate, although the common electrode line of the via portion has a small cross-sectional area but a short length, so This will make the resistance of the entire common electrode line too large.
  • the array substrate shown in FIG. 6 also adopts a double gate driving structure in which the second common electrode line b is formed in the same layer as the data line.
  • the common electrode 8 is formed between the gate line layer and the base substrate 1. Wherein, at least a portion of the first common electrode line a in the same layer as the gate line is directly formed on the common electrode 8, that is, the first common electrode line a overlaps with the common electrode 8, while the first common electrode line a and the second common
  • the electrode line b is bridged by a via hole of the gate insulating layer 3, wherein the common electrode 8 has a plate shape, and the pixel electrode 6 has a slit shape.
  • the array substrate structure in FIG. 6 is simplified to the array base in FIG.
  • the board has obvious advantages in production cost and production efficiency.
  • the array substrate in at least some embodiments of the present disclosure is a single gate driving structure.
  • the distance between the data lines of the single gate driving structure is short, so in order to ensure display quality, the second layer is not disposed on the data line layer.
  • the common electrode 8 of the array substrate in at least some embodiments of the present disclosure is still formed between the gate line layer and the substrate substrate 1.
  • the second common electrode line b and the pixel electrode 6 are formed of the same material in the same layer, and pass through the via holes on the flat layer 5 and the gate insulating layer 3 to bridge the first common electrode line. a.
  • the common electrode line b is disposed on the pixel electrode layer to avoid signal interference.
  • the common electrode and the pixel electrode are not unique in position, the first common electrode line and the second common electrode line are connected in a plurality of ways. However, these connection methods are not limited to the scope of protection of the present disclosure.
  • another embodiment of the present disclosure also provides a display device including the above array substrate. Since the common electrode line is reduced in resistance on the array substrate, the common electrode line is not required to occupy the outer space of the array substrate as compared with the related art, and is particularly suitable for a display device that requires driving on both sides of the array substrate.
  • another embodiment of the present disclosure further provides a method for fabricating an array substrate, including the steps of forming a gate line and a data line on a substrate;
  • the first common electrode line obtained by the first material layer is formed by the first patterning process, and the first common electrode line and the gate line are extended in the same direction; Forming, by a second patterning process, a second common electrode line obtained from the second material layer, the second common electrode line extending in the same direction as the data line; wherein the first common electrode line and the second common electrode line Different layers, and the first common electrode line is bridged with the second common electrode line.
  • the first common electrode line and the second common electrode line extending in a direction perpendicular to each other are connected across the layer so that the two form a parallel relationship and increase the overall common electrode line.
  • the gate line obtained by the first material layer is formed in the first patterning process, that is, the gate line is formed of the same material as the first common electrode line.
  • the second patterning process also forms a data line or a pixel electrode obtained from the second material layer, that is, the second common electrode line is formed of the same material as the data line or the pixel electrode.
  • Step 801 referring to FIG. 8A, on the base substrate 1, a common electrode 8 made of a layer of ITO material is formed.
  • Step 802 referring to FIG. 8B, on the base substrate 1 on which the common electrode 8 is formed, a gate Ta obtained by a metal layer, a gate line (not shown), and a first common electrode a are formed by one patterning process.
  • Step 803 referring to FIG. 8C, on the base substrate 1, a gate insulating layer 3 is formed, which covers the gate Ta, the gate line (not shown), and the first common electrode a.
  • Step 804 referring to FIG. 8D, via holes are formed on the gate insulating layer 3, and are formed by one patterning process: an active layer Td, a source Tb, a drain Tc, and a second common electrode line b.
  • the second common electrode line b and the source Tb and the drain Tc may be made of the same metal material layer, and the second common electrode line b is bridged to the first common electrode line a through the via of the gate insulating layer 3.
  • Step 805 referring to FIG. 8E, a flat layer 5 covering the second common electrode line b, the source Tb, and the drain Tc is formed.
  • the above is a method for fabricating the array substrate shown in FIG. 6. It should be noted that the manufacturing method of the present disclosure can also be used to fabricate the array substrate structure as shown in FIG. 7, and the second common electrode line is placed on the pixel electrode. Formed in the patterning process, that is, the second common electrode line and the pixel electrode are formed in the same material in one patterning process.

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Abstract

一种阵列基板、显示装置及制作方法。阵列基板包括：衬底基板（1）以及设置在所述衬底基板（1）上的多条栅线（2）、数据线（4）、与所述栅线（2）的延伸方向相同的第一公共电极线（a），以及与所述数据线（4）的延伸方向相同的第二公共电极线（b）。所述第一公共电极线（a）与所述第二公共电极线（b）不同层，且所述第一公共电极线（a）与所述第二公共电极线（b）跨接。

Description

一种阵列基板、显示装置及制作方法
相关申请的交叉引用
本申请主张在2015年7月21日在中国提交的中国专利申请号No.201510431650.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及液晶显示领域，特别是一种阵列基板、显示装置及制作方法。
背景技术
近年来，液晶显示装置因其轻薄、省电、无辐射等优点，已经取代了传统阴极射线管显示器广泛应用于诸多电子产品中。
相关技术中的大多数液晶显示装置，由于发光需要，其内部设有大量的线路，而线路之间的信号相互影响会造成电压波动，容易使液晶显示装置的画面发绿，也就是我们常说的Greenish现象。为了解决这种现象，针对大尺寸高清产品，栅极可通过Gate IC单边驱动，即阵列基板有一侧可以布置公共电极(公共电极)走线，通过设计较大宽的公共电极走线以减小公共电极电阻，从而降低Greenish的发生概率。但针对大尺寸的全高清/超高清产品，Gate IC需要设计在阵列基板的两侧进行驱动，这样一来整个显示装置就没有公共电极的布线空间，而当前解决的办法是再增加成本，为Gate IC设置电压的补偿电路以消除Greenish现象发生。
发明内容
本公开要解决目前高分辨率、大尺寸的显示设备中因公共电极线电阻过大所造成的信号干扰问题。
为解决上述技术问题，本公开的实施例提供一种阵列基板，包括：衬底基板以及设置在所述衬底基板上的多条栅线、数据线、第一公共电极和第二公共电极；
所述第一公共电极线与所述栅线的延伸方向相同；所述第二公共电极线 与所述数据线的延伸方向相同；所述第一公共电极线与所述第二公共电极线不同层，且所述第一公共电极线与所述第二公共电极线跨接。
其中，所述栅线与所述第一公共电极线同层设置。
其中，所述第二公共电极线与所述数据线同层设置；所述阵列基板还包括：设置在所述栅线与所述数据线之间的栅绝缘层；所述栅绝缘层设置有过孔；所述第二公共电极线通过所述栅绝缘层的过孔跨接所述第一公共电极线。所述栅绝缘层的过孔位于所述第一公共电极线与所述第二公共电极线的重合区域。
其中，所述阵列基板包括：多行多列的子像素，所述多行多列的子像素划分为多个像素组，每个像素组由同行相邻的两个子像素构成，且一个子像素只对应有一个像素组；其中，每一行像素组的上方和下方分别设置有一条只属于该行像素组的栅线；在每个像素组中，一个子像素由其上方对应的栅线驱动，另一子像素由其下方对应的栅线驱动，且这两个子像素与同一条数据线连接；所述第二公共电极线设置于控制组之间。
其中，阵列基板还包括：形成在所述衬底基板上的公共电极；所述第一公共电极线直接与所述公共电极搭接。
其中，所述阵列基板还包括：形成在所述数据线图层上方的公共电极，所述公共电极与所述第二公共电极线跨接。
其中，所述栅线与所述第一公共电极线由第一金属材料层形成，所述数据线与所述第二公共电极线由第二金属材料层形成；
所述第二公共电极线具体设置在相邻数据线之间的非显示区域内。其中，阵列基板还包括：像素电极；所述第二公共电极线与所述像素电极同层设置。
其中，阵列基板还包括：设置在所述像素电极图层上方的公共电极；设置在所述公共电极与所述像素电极中间的钝化层，所述钝化层设置有过孔；所述公共电极通过所述钝化层的过孔跨接所述第二公共电极线。
此外，本公开的另一实施例还提供一种包括上述阵列基板的显示装置。
此外，本公开的另一实施例还提供一种针对上述阵列基板的制作方法，包括在衬底基板上形成栅线、数据线的步骤；
所述制作方法还包括：通过第一构图工艺形成由第一材料层得到的第一 公共电极线，所述第一公共电极线与所述栅线的延伸方向相同；通过第二构图工艺形成由第二材料层得到的第二公共电极线；所述第二公共电极线与所述数据线的延伸方向相同；
其中，所述第一公共电极线与所述第二公共电极线不同层，且所述第一公共电极线与所述第二公共电极线跨接。
其中，所述制作方法还包括：通过所述第一构图工艺还形成由第一材料层得到的栅线；
通过所述第二构图工艺形成由第二材料层得到的数据线或像素电极。
本公开的上述技术方案的有益效果如下：
本公开的方案中，在阵列基板结原有的栅线和数据线这两个导电图层上分别设置公共电极线，并将这两层公共电极线以并联的方式跨接，以减小公共电极线的电阻，从而降低了公共电极信号的电压波动影响，能够有效避免绿屏现象发生。
附图说明
图1为本公开的阵列基板的结构示意图；
图2为相关技术中，单栅驱动方式的阵列基板的结构示意图；
图3为相关技术中，双栅驱动方式的阵列基板的结构示意图；
图4为本公开至少一些实施例中阵列基板的结构示意图；
图5为图4中阵列基板的剖面示意图；
图6为本公开至少一些实施例中阵列基板的结构示意图；
图7为本公开至少一些实施例中阵列基板的结构示意图；
图8A-图8F为本公开图6所示阵列基板结构的制作方法的过程示意图。
具体实施方式
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
针对现有问题，本公开提供一种新结构的阵列基板，能够在该阵列基板上布置小阻值的公共电极线，从而降低了公共电极信号的电压干扰。
如图1所示，本实施例的阵列基板包括：
在衬底基板1上形成的栅线2、数据线4和公共电极线。
所述公共电极线由两部分组成，即与栅线2延伸方向相同、且同层设置的第一公共电极线a，以及与数据线延伸方向相同的第二公共电极线b。
其中，第一公共电极线a与第二公共电极线b跨接，即两者之间还形成有其它的功能图层(如栅绝缘层)。
本实施例的阵列基板结构中，延伸方向近似垂直的第一公共电极线与第二公共电极线在跨接后，一是能够增大整体走线的横截面积，二是两者形成并联关系，因此能够有效减小公共电极线整体的阻值，从而降低了公共电极信号的电压波动，能够有效避免绿屏现象发生。
当然，基于上述原理所能够理解的是，第一公共电极线与栅线的延伸方向相同，那么第一公共电极线与栅线在一次构图工艺中，同层甚至同材料形成是最容易实现的方案。同理，第二公共电极线与数据线也可在一次构图工艺中，同层甚至同材料形成。
但是，在实际应用中，各信号线之间距离过近，会产生干扰显现。栅极线加载的是扫描信号，扫描信号只需以一固定电位打开对应的薄膜晶体管即可，因此当在栅极线之间设置第一公共电极线时，并不用担心第一公共电极线上的信号会干扰到扫描信号。而数据线上的数据信号则需要不断地进行电位变化，以改变像素的极性，因此若第二公共电极线与数据线过近，会影响到显示质量。因此，作为可选方案，需要根据数据线之间的距离，来合理选择是否在数据线图层上设置第二公共电极线。
下面对第二公共电极线的设置进行详细介绍。
相关技术中，在开口率一定的前提下，数据线之间的距离由像素的驱动方式决定。目前的像素驱动方式主要有两种，即“单栅驱动”和“双栅驱动”。
单栅驱动即行向上的每个子像素均由各自的一条数据线加载数据信号。作为示例性介绍，如图2所示，假设行向上的像素单元中包括红R、绿G、蓝B3种子像素(4K显示器的像素单元上额外加入白色子像素)。其中，同一行的子像素R、G、B分别对应有薄膜晶体管T1、T2、T3。薄膜晶体管T1、T2、T3由同一条栅线驱动。当薄膜晶体管T1、T2、T3被栅线上的扫描信号 打开后，子像素R加载数据线41上的数据信号，子像素G加载数据线42上的数据信号，子像素B加载数据线43上的数据信号。通过图2可以看出，为单栅驱动的结构。
而针对双栅驱动，子像素划分为多个像素组，每个像素组由同行相邻的两个子像素构成，且一个子像素只对应有一个像素组；其中，每一行像素组的上方和下方分别设置有一条只属于该行像素组的栅线；在每个像素组中，一个子像素由其上方对应的栅线驱动，另一子像素由其下方对应的栅线驱动，且这两个子像素与同一条数据线连接。作为示例性介绍，如图3所示，同一行的子像素R、G、B分别对应有薄膜晶体管T1、T2、T3。薄膜晶体管T1、T3由栅线21驱动，当栅线21打开薄膜晶体管T1、T3后，子像素R、G加载数据线41上的数据信号。而薄膜晶体管T2则由栅线22驱动，当栅线22打开薄膜晶体管T2后，子像素B加载数据线42上的数据信号。
对比图2和图3可以发现，图3中两个数据线之间的距离L2要远大于图2中两个数据线之间的距离L1。即双栅极驱动的结构中，第二公共电极线与数据线同层设置，则彼此之间相距较远，相互产生信号干扰的现象能够得到有效抑制。而单栅极驱动的结构中，数据线之间的间距较近，为避免影响显示质量，第二公共电极线可以设置在其他导电图层上(如像素电极的图案层)。
下面结合几个实现方式，对本公开的阵列基板进行详细介绍。
本公开至少一些实施例中的阵列基板为双栅驱动结构，其中，在数据线层形成第二公共电极线。如图4、图5所示，阵列基板包括：
衬底基板1；
形成在衬底基板1上的薄膜晶体管T；薄膜晶体管T由栅极Ta、源极Tb、漏极Tc和有源层Td构成，栅极Ta上覆盖有栅绝缘层3。
在栅极Ta的位置延伸有栅线2，与栅线同层同材料还形成有第一公共电极线a。
在源极Tb的位置延伸有数据线4，与数据线同层同材料还形成有第二公共电极线b，该第二公共电极线b通过栅绝缘层3的过孔31跨接第一公共电极线a，栅绝缘层的过孔31位于所述第一公共电极线与所述第二公共电极线的重合区域。其中，若数据线4与第二公共电极线b采用电阻较低的金属材 料，则第二公共电极线b可以位于像素区域9之间的非显示区域上(即上文所述像素组之间)，以避免遮挡下方光源。
在第二公共电极线b、数据线上方形成有平坦层5。平坦层5上设置有像素电极6，像素电极6通过平坦层5上的过孔与漏极Tc连接。
在像素电极6上方形成有钝化层7，钝化层7上形成有公共电极8，该公共电极8通过钝化层7以及平坦层5上的过孔与第二公共电极线b连接，即公共电极与所述第二公共电极线跨接，其中公共电极8为狭缝状，像素电极6为板状。
需要说明的是，虽然本公开至少一些实施例中的阵列基板为双栅驱动结构，但第二公共电极线b也可以与像素电极6同层设置。当第二公共电极线b与像素电极6与同层设置时，形成在像素电极6上方的公共电极8通过钝化层7的过孔跨接第二公共电极线b。在相关技术中，像素电极在显示区域内，因此由透明导电的ITO材料制成，而非显示区域的数据线则可以由不透明、但导电性能更好的金属材料形成(如铜、铝、钼\铝\钼等)。因此，对于双栅驱动结构的阵列基板，在数据线图层布置第二公共电极线，显然在降阻效果上要好于在像素电极图层布置公共电极线。
以上是本公开至少一些实施例中阵列基板的结构，由于双栅驱动方式下，数据线之间相距较远，因此在数据线之间设置第二公共电极线。可以看出，栅线图层和数据线图层是整个阵列基板中相对较近的两个导电图层，虽然过孔部分的公共电极线的横截面积较小，但长度较短，因此不会使整个公共电极线的电阻过大。
如图6所示的阵列基板也采用双栅驱动结构，其中，第二公共电极线b与数据线同层形成。
与图5所示结构不同的是，公共电极8形成在栅线图层与衬底基板1之间。其中，与栅线同层的第一公共电极线a至少有一部分直接形成在公共电极8上，即第一公共电极线a与公共电极8搭接，同时第一公共电极线a与第二公共电极线b通过栅绝缘层3的过孔跨接，其中公共电极8为板状，像素电极6为狭缝状。
对比图5和图6可知，图6中的阵列基板结构要简化于图5中的阵列基 板，因此在制作成本以及制作效率上具有明显的优势。
本公开至少一些实施例中的阵列基板为单栅驱动结构，通过上文可知，单栅驱动结构的数据线之间的距离较短，因此为保证显示质量，不在数据线图层上设置第二公共电极线b。
如图7所示，本公开至少一些实施例中的阵列基板的公共电极8依然形成在栅线图层与衬底基板1之间。
其中，与图6所示结构不同的是，第二公共电极线b与像素电极6同层同材料形成，并通过平坦层5和栅绝缘层3上的过孔，跨接第一公共电极线a。
在图7所示的阵列基板结构中，由于单栅驱动方式下，数据线之间相距较近，因此将公共电极线b设置在像素电极图层，以避免发生信号干扰现象。
基于上述阵列基板的几个实现方式，需要说明的是，由于公共电极和像素电极位置并不唯一，因此第一公共电极线与第二公共电极线的连接方式有很多种。但这些连接方式并不限于本公开的保护范围。
此外，本公开的另一实施例还提供一种包括上述阵列基板的显示装置。由于在阵列基板上实现了公共电极线的降阻，因此相比于相关技术，不需要占用阵列基板的外侧空间来布置公共电极线，特别适用于需要在阵列基板两侧设置驱动的显示装置。
此外，本公开的另一实施例还提供一种阵列基板的制作方法，包括在衬底基板上形成有栅线、数据线步骤；
与相关技术不同的是，在本实施例的中，通过第一构图工艺形成由第一材料层得到的第一公共电极线，该第一公共电极线与栅线与的延伸方向相同；此外，通过第二构图工艺形成由第二材料层得到的第二公共电极线，该第二公共电极线与数据线的延伸方向相同；其中，所述第一公共电极线与所述第二公共电极线不同层，且所述第一公共电极线与所述第二公共电极线跨接。
在本公开至少一些实施例的制作方法中，将延伸方向近似垂直的第一公共电极线与第二公共电极线进行跨图层的连接，以使两者形成并联关系，并增加公共电极线整体的横截面积，从而降低了公共电极线的电阻，抑制其在加载信号时所产生的电压波动。
当然，作为可选方案，在第一构图工艺还形成由第一材料层得到的栅线，即栅线与第一公共电极线同层同材料形成。在第二构图工艺还形成由第二材料层得到的数据线或像素电极，即第二公共电极线与数据线或像素电极同层同材料形成。
下面结合图6所示的阵列基板结构，对本公开至少一些实施例中的制作方法进行示例性介绍。
本实施例的制作方法包括：
步骤801，参考图8A，在衬底基板1上，形成由ITO材料层制成的公共电极8。
步骤802，参考图8B，在形成公共电极8的衬底基板1上，通过一次构图工艺形成：由金属层得到的栅极Ta、栅线(未显示)以及第一公共电极a。
步骤803，参考图8C，在衬底基板1上，形成栅绝缘层3，该栅绝缘层3覆盖栅极Ta、栅线(未显示)以及第一公共电极a。
步骤804，参考图8D，在栅绝缘层3上进行过孔，并通过一次构图工艺形成：有源层Td、源极Tb、漏极Tc以及第二公共电极线b。
其中，第二公共电极线b与源极Tb、漏极Tc可以由同一金属材料层制成，且第二公共电极线b通过栅绝缘层3的过孔跨接第一公共电极线a。
步骤805，参考图8E，形成覆盖第二公共电极线b、源极Tb、漏极Tc的平坦层5。
步骤806，参考图8F，在平坦层5形成开孔，并在其上形成像素电极6，该像素电极6通过平坦层5的过孔与漏极Tc连接。
以上是对应图6所示阵列基板的制作方法，需要给予说明的是，本公开的制作方法还可以用于制作如图7所示的阵列基板结构，将第二公共电极线放在像素电极的构图工艺中形成，即第二公共电极线与像素电极在一个构图工艺中，同材料形成。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (13)

  1. 一种阵列基板，包括：衬底基板以及设置在所述衬底基板上的多条栅线、数据线，其中，所述阵列基板还包括：
    与所述栅线的延伸方向相同的第一公共电极线；
    与所述数据线的延伸方向相同的第二公共电极线；
    其中，所述第一公共电极线与所述第二公共电极线不同层，且所述第一公共电极线与所述第二公共电极线跨接。
  2. 根据权利要求1所述的阵列基板，其中，
    所述栅线与所述第一公共电极线同层设置。
  3. 根据权利要求2所述的阵列基板，其中，
    所述第二公共电极线与所述数据线同层设置；
    所述阵列基板还包括：设置在所述栅线与所述数据线之间的栅绝缘层；所述栅绝缘层设置有过孔；
    其中，所述第二公共电极线通过所述栅绝缘层的过孔跨接所述第一公共电极线。
  4. 根据权利要求3所述的阵列基板，其中，
    所述栅绝缘层的过孔位于所述第一公共电极线与所述第二公共电极线的重合区域。
  5. 根据权利要求3所述的阵列基板，还包括：
    多行多列的子像素，所述多行多列的子像素划分为多个像素组，每个像素组由同行相邻的两个子像素构成，且一个子像素只对应有一个像素组；
    其中，每一行像素组的上方和下方分别设置有一条只属于该行像素组的栅线；在每个像素组中，一个子像素由其上方对应的栅线驱动，另一子像素由其下方对应的栅线驱动，且这两个子像素与同一条数据线连接；
    所述第二公共电极线设置于相邻像素组之间。
  6. 根据权利要求3所述的阵列基板，还包括：
    形成在所述衬底基板上的公共电极；所述第一公共电极线直接与所述公共电极搭接。
  7. 根据权利要求3所述的阵列基板，还包括：
    形成在所述数据线图层上方的公共电极，所述公共电极与所述第二公共电极线跨接。
  8. 根据权利要求5所述的阵列基板，其中，
    所述栅线与所述第一公共电极线由第一金属材料层形成，所述数据线与所述第二公共电极线由第二金属材料层形成；
    所述第二公共电极线具体设置在相邻数据线之间的非显示区域内。
  9. 根据权利要求2所述的阵列基板，还包括：
    像素电极；
    所述第二公共电极线与所述像素电极同层设置。
  10. 根据权利要求9所述的阵列基板，还包括：
    设置在所述像素电极图层上方的公共电极；
    设置在所述公共电极与所述像素电极中间的钝化层，所述钝化层设置有过孔；
    其中，所述公共电极通过所述钝化层的过孔跨接所述第二公共电极线。
  11. 一种显示装置，包括如权利要求1-10任一项所述的阵列基板。
  12. 一种阵列基板的制作方法，包括在衬底基板上形成栅线、数据线的步骤，其中，在所述制作方法包括：
    通过第一构图工艺形成由第一材料层得到的第一公共电极线；所述第一公共电极线与所述栅线的延伸方向相同；
    通过第二构图工艺形成由第二材料层得到的第二公共电极线；所述第二公共电极线与所述数据线的延伸方向相同；
    其中，所述第一公共电极线与所述第二公共电极线不同层，且所述第一公共电极线与所述第二公共电极线跨接。
  13. 根据权利要求12所述的制作方法，还包括：
    通过所述第一构图工艺形成由第一材料层得到的栅线；
    通过所述第二构图工艺形成由第二材料层得到的数据线或像素电极。
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