WO2022147791A1 - 阵列基板、其驱动方法及显示装置 - Google Patents

阵列基板、其驱动方法及显示装置 Download PDF

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Publication number
WO2022147791A1
WO2022147791A1 PCT/CN2021/070955 CN2021070955W WO2022147791A1 WO 2022147791 A1 WO2022147791 A1 WO 2022147791A1 CN 2021070955 W CN2021070955 W CN 2021070955W WO 2022147791 A1 WO2022147791 A1 WO 2022147791A1
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Prior art keywords
pixel
pixels
address selection
data
sub
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PCT/CN2021/070955
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English (en)
French (fr)
Inventor
李秀玲
谷其兵
胡国锋
梅洪格
高娜娜
付宝
陈相逸
时凌云
黄文杰
Original Assignee
京东方科技集团股份有限公司
京东方晶芯科技有限公司
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Application filed by 京东方科技集团股份有限公司, 京东方晶芯科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180000026.4A priority Critical patent/CN115119521A/zh
Priority to PCT/CN2021/070955 priority patent/WO2022147791A1/zh
Priority to EP21916846.5A priority patent/EP4195190A4/en
Priority to US18/044,664 priority patent/US20230326398A1/en
Priority to TW110136839A priority patent/TWI792597B/zh
Publication of WO2022147791A1 publication Critical patent/WO2022147791A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a driving method thereof, and a display device.
  • miniature light-emitting diodes refer to shrinking the size of LEDs to less than 300 microns, and fixing thousands, tens of thousands or even more miniature light-emitting diodes on the substrate. More detailed local dimming can be performed to present a display screen with high contrast and high color expression.
  • the miniature light-emitting diode display device adopts a passive matrix (PM) driving method.
  • This driving method requires a large number of signal traces to be fabricated on a glass substrate, so that the signal traces can be bound together. It is more difficult, especially for spliced display products, it is necessary to adopt a side routing process, which further increases the difficulty of the process.
  • a multiplexer MUX
  • MUX multiplexer
  • an array substrate which includes:
  • At least one pixel includes: a sub-pixel, and a pixel driving chip for driving each of the sub-pixels in the pixel;
  • the sub-pixel includes at least one light emitting diode;
  • the pixel driving chip includes: a data signal terminal and an addressing signal terminal;
  • a plurality of data lines are located on the base substrate; the data lines are coupled to the data signal terminals of each of the pixel driving chips of a row of the pixels arranged in the second direction.
  • each of the address selection signal lines extends along the first direction and is arranged along the second direction;
  • the address selection signal line is located in a gap between two adjacent rows of the pixels arranged in the first direction.
  • it further includes: a plurality of address selection signal switching lines;
  • a plurality of the address selection signal switching lines extend along the second direction and are arranged along the first direction;
  • a plurality of the address selection signal transfer lines are in one-to-one correspondence with the plurality of the address selection signal lines;
  • the address selection signal transfer line and the address selection signal line are disposed in different layers, and the address selection signal transfer line is coupled to the corresponding address selection signal line through a first via hole; the first via hole penetrates through The insulating layer between the address selection signal transfer wire and the address selection signal wire.
  • each of the data lines extends along the second direction and is arranged along the first direction;
  • the data line is located in a gap between two adjacent rows of the pixels arranged in the first direction.
  • it further includes: a plurality of power supply signal lines, and a plurality of fixed voltage signal lines;
  • the pixel driving chip further includes: a signal channel terminal and a fixed voltage signal terminal;
  • the power signal line is coupled to the first electrodes of the light emitting diodes of a row of the pixels arranged in the second direction; the second electrodes of the light emitting diodes in the pixels are respectively connected to the each of the signal channel ends of the pixel driving chip is coupled;
  • the fixed voltage signal line is coupled to the fixed voltage signal terminal of the pixel driving chip of a row of the pixels arranged in the second direction.
  • the pixel at least includes: a red sub-pixel, a green sub-pixel, and a blue sub-pixel;
  • the plurality of power signal lines are divided into a plurality of first power signal lines and a plurality of second power signal lines;
  • the first power signal line is coupled to the first electrodes of each of the red sub-pixels of a row of the pixels arranged in the second direction;
  • the second power signal line is coupled to the first poles of each of the green sub-pixels and each of the blue sub-pixels of a row of the pixels arranged in the second direction.
  • auxiliary signal lines a plurality of auxiliary signal lines
  • Each of the auxiliary signal lines extends along the first direction and is arranged along the second direction;
  • the auxiliary signal line is located in the gap between two adjacent rows of the pixels arranged in the first direction;
  • the auxiliary signal lines and the fixed voltage signal lines are disposed in different layers, and each of the auxiliary signal lines is coupled to at least one of the fixed voltage signal lines through a second via hole; the second via hole penetrates the an insulating layer between the auxiliary signal line and the fixed voltage signal line.
  • an embodiment of the present disclosure further provides a display device, which includes: any of the above array substrates.
  • an embodiment of the present disclosure also provides a method for driving any of the above array substrates, including:
  • Each display frame includes at least: address allocation stage and data signal transmission stage; wherein,
  • the address selection information is sequentially input to each address selection signal line; the address selection information includes address information corresponding to a row of pixels arranged in the first direction;
  • data information is respectively input to each data line;
  • the data information includes a plurality of sub-data information;
  • the sub-data information includes: address information corresponding to a row of pixels arranged in the first direction, and Pixel data information of the pixel corresponding to the address information and coupled to the data line.
  • the address selection information includes: a start command, the address information, an interval command, and an end command that are set in sequence.
  • the sub-data information includes: a start instruction, the address information, a data transmission instruction, an interval instruction, the image information, and an end instruction that are set in sequence.
  • each display frame further includes: a current setting stage before the data signal transmission stage;
  • current setting information is input to each of the data lines.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a connection relationship of a pixel in an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of another connection relationship of a pixel in an embodiment of the disclosure.
  • FIG. 4 is a timing diagram corresponding to a driving method provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic time sequence diagram of address selection information in an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of encoding of a data signal.
  • Embodiments of the present disclosure provide an array substrate, a driving method thereof, and a display device.
  • FIG. 1 is a schematic plan view of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate provided by an embodiment of the present disclosure may include:
  • the plurality of pixels 11 are located on the base substrate 10; the plurality of pixels 11 are arranged in an array in the first direction F1 and the second direction F2, and the first direction F1 and the second direction F2 cross each other.
  • FIG. 2 is a schematic diagram of a connection relationship of a pixel 11 in an embodiment of the disclosure.
  • at least one pixel 11 of the plurality of pixels 11 includes: a sub-pixel 111 , and a sub-pixel for driving each sub-pixel in the pixel 11
  • the addressing signal terminal Uc of the pixel driving chip 112 is coupled;
  • N data lines D are located on the base substrate 10; each data line D j (0 ⁇ j ⁇ N, j is a positive integer) is connected to each pixel driving chip 112 of a row of pixels arranged in the second direction F2
  • the data signal terminal Da is coupled.
  • first direction may be the row direction, and the second direction may be the column direction; or, the first direction may be the column direction, and the second direction may be the row direction, which is not limited here.
  • first direction is the row direction
  • second direction is the column direction.
  • At least one pixel includes: a sub-pixel, and a pixel driving chip.
  • the pixel driving chip By using the pixel driving chip to directly drive each sub-pixel in the pixel to emit light, pixel-level fine driving can be realized.
  • the address selection information is sequentially input to each address selection signal line, and a plurality of sub-data information is respectively input to each data line, so that each pixel driving chip will The sub-data information is then provided to the corresponding sub-pixels, thereby realizing the active addressing driving mode, greatly reducing the number of signal lines on the base substrate, so that there is enough space in the array substrate for signal lines.
  • the resistance of the signal wiring can be reduced by increasing the width of the signal wiring and other wiring methods. Without increasing the thickness of the signal wiring, the brightness of the light-emitting diode can be increased, thereby reducing the power of the array substrate. At the same time, the number of signal traces can be greatly reduced, thereby reducing the width of the binding area and the binding difficulty of the binding area and the signal traces.
  • each sub-pixel includes one light-emitting diode as an example for illustration.
  • a sub-pixel may also include more light-emitting diodes.
  • the sub-pixel in FIG. 3 may include two light-emitting diodes. The number of light-emitting diodes in a sub-pixel is not limited.
  • the colors of the light-emitting diodes in the sub-pixel are the same.
  • the colors of the light-emitting diodes in the sub-pixel may not be exactly the same. limited.
  • the light-emitting diodes in the sub-pixels are connected in parallel for illustration, and the light-emitting diodes in the sub-pixels may also be connected in series, which is not limited here.
  • each address selection signal line S i extends along the first direction F1 and is arranged along the second direction F2; It is located in the gap between two adjacent rows of pixels 11 arranged along the first direction F1.
  • the address selection signal line S i can be more easily connected to the corresponding row of pixels 11 , which facilitates wiring and prevents crossover between signal wirings.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure, with continued reference to FIG. 1 , it may further include: M address selection signal transition lines Q;
  • the M address selection signal transfer lines Q extend along the second direction F2 and are arranged along the first direction F1;
  • Each address selection signal transfer line Q i (0 ⁇ i ⁇ M, i is a positive integer) corresponds to the address selection signal line S i one-to-one, for example, the address selection signal transfer line Q 1 corresponds to the address selection signal line S 1 ;
  • the address selection signal transfer line Q and the address selection signal line S are arranged in different layers, and the address selection signal transfer line Q i passes through the first via hole (as shown in the figure at the intersection of the address selection signal transfer line Q i and the address selection signal line S i )
  • the black circle of ) is coupled to the corresponding address selection signal line Si ; the first via hole penetrates the insulating layer between the address selection signal transfer line Qi and the address selection signal line Si .
  • the address selection signal transfer line Qi extended by F2 can provide the address selection signal to the corresponding address selection signal line Si through the address selection signal transfer line Qi, so that signals such as each address selection signal line Si and each data line Dj can be connected
  • the signal source of the line is arranged on the same side of the array substrate.
  • the signal source can be arranged at at least one of the two ends of the addressing signal transition line Qi, thereby reducing the area of the frame area of the array substrate.
  • the signal source may provide the address selection signal to the address selection signal transition line Qi , for example, the signal source may be a driver chip.
  • the address selection signal adapter line Qi can be arranged in the gap between two adjacent pixel columns.
  • Each address selection signal transfer line Q i is set to be evenly distributed in each gap. For example, when the number of rows and columns in the array substrate is equal, an address selection signal transfer line can be set on the same side of each pixel column. Q i .
  • the address selection signal transfer lines Qi may be provided in every gap between two adjacent pixel columns , and at least part of the gaps may be provided with two address selection signal transfer lines Qi .
  • each data line Dj extends along the second direction F2 and is arranged along the first direction F1;
  • the data line Dj is located in the gap between two adjacent rows of pixels 11 arranged in the first direction F1. In this way, the data lines D j can be more easily connected to the corresponding row of pixels 11 , which facilitates wiring and prevents crossover between signal wirings.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure, with reference to FIG. 1 and FIG. 2 , may further include: N power signal lines Va and Vb, and N fixed voltage signal lines G;
  • the pixel driving chip 112 may further include: a signal channel terminal CH (eg CH 1 , CH 2 , CH 3 ) and a fixed voltage signal terminal Gd;
  • a signal channel terminal CH eg CH 1 , CH 2 , CH 3
  • Gd fixed voltage signal terminal
  • the power signal lines Va j and Vb j are coupled to the first electrodes of the light emitting diodes of a row of pixels 11 arranged in the second direction F2;
  • the signal channel terminal CH is coupled; wherein, the first electrode can be the positive electrode of the light emitting diode, and the second electrode can be the negative electrode of the light emitting diode.
  • the fixed voltage signal line Gj (0 ⁇ j ⁇ N, j is a positive integer) is coupled to the fixed voltage signal terminal Gd of the pixel driving chip 112 of the pixel driving chip 112 of a row of pixels 11 arranged in the second direction F2.
  • the power signal line Va j (or Vb j ) (0 ⁇ j ⁇ N, j is a positive integer) is coupled to the first electrode of the light emitting diode, so the power signal line Va j (or Vb j ) can provide power to the light emitting diode , and the second electrode of the light emitting diode is coupled to the signal channel terminal CH of the pixel driving chip 112, the fixed voltage signal line G j is coupled to the fixed voltage signal terminal Gd of the pixel driving chip 112, and the fixed voltage signal line G j can be connected to The pixel driving chip 112 provides a fixed voltage signal to form a power supply loop.
  • the light-emitting diode is a current-driven element, and the pixel driving chip 112 provides a signal path to the coupled light-emitting diode through the signal channel terminal CH, so that the light-emitting diode can be controlled by current signals with different current amplitudes and/or different duty ratios.
  • each power signal line Va j (or Vb j ) and each fixed voltage signal line G j may be disposed in the gap between two adjacent pixel columns.
  • the pixel 11 at least includes: a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.
  • the red sub-pixel R may include at least one red micro-LED
  • the green sub-pixel G may include at least one green micro-LED
  • the blue sub-pixel B may include at least one blue micro-LED;
  • the plurality of power signal lines are divided into a plurality of first power signal lines Va j and a plurality of second power signal lines Vb j ;
  • the first power signal line Va j is coupled to the first electrodes of each red sub-pixel R of a row of pixels 11 arranged in the second direction F2;
  • the second power signal line Vb j is coupled to the first poles of each green sub-pixel G and each blue sub-pixel B of a row of pixels 11 arranged in the second direction F2.
  • the signal line Vbj is coupled to each green sub-pixel G and each blue sub-pixel B in a column of pixels 11.
  • the green sub-pixel G and the blue sub-pixel B share the power signal line, which can greatly reduce the number of power signal lines and simplify the array. wiring of the substrate.
  • Each auxiliary signal line Wi (0 ⁇ i ⁇ M, i is a positive integer) extends along the first direction F1, and is arranged along the second direction F2;
  • the auxiliary signal line Wi is located in the gap between two adjacent rows of pixels 11 arranged in the first direction F1 to avoid affecting the light output of each sub-pixel;
  • the auxiliary signal line Wi and the fixed voltage signal line Gj are arranged in different layers, and each auxiliary signal line Wi passes through the second via hole (as shown in the black color at the intersection of the auxiliary signal line Wi and the fixed voltage signal line Gj ). circle) is coupled to at least one fixed voltage signal line G j ; the second via hole penetrates the insulating layer between the auxiliary signal line Wi and the fixed voltage signal line G j .
  • auxiliary signal line W i By arranging an auxiliary signal line W i in a different layer from the fixed voltage signal line G j , and the auxiliary signal line W i is coupled to the fixed voltage signal line G j through the second via hole, so that the plurality of fixed voltage signal lines G and the plurality of The auxiliary signal lines W form a grid-like parallel structure to reduce the resistance of the fixed voltage signal line G to reduce the voltage drop of the fixed voltage signal line G j and reduce the signal delay on the fixed voltage signal line G j .
  • a second via hole may be provided in each area where the orthographic projections of the fixed voltage signal line G and the auxiliary signal line W on the base substrate overlap, so as to increase the number of the fixed voltage signal line G j and the auxiliary signal line.
  • the parallel region of lines Wi further reduces the signal delay on the fixed voltage signal line Gj .
  • each address selection signal line Si and each auxiliary signal line Wi can be arranged on the same film layer , and each data line D j , each address selection The signal transfer wires Qi, the power signal wires Va j and Vb j , and the fixed voltage signal wires G j are arranged on the same film layer. That is to say, the signal traces extending along the first direction F1 are arranged on the same film layer, and the signal traces extending along the second direction F2 are arranged on the same film layer, so that it can be avoided that the signal traces extending along the first direction F1 are arranged on the same film layer.
  • crossover occurs, which reduces wiring difficulty.
  • a signal source can be set at the edge of the side of the array substrate extending along the first direction F1, and the signal source can be connected with N data lines D, M address selection signal switching lines Q, N
  • the power signal lines Va, the N power signal lines Vb, and the N fixed voltage signal lines G are coupled to pass corresponding driving signals to the signal lines extending along the second direction F2.
  • the signal source may be a Field Programmable Gate Array (FPGA), or an Integrated Circuit (Integeral Cirtcuit, IC), or a Printed Circuit Board (PCB), or a Flexible Circuit Board (Flexible Printed Circuit, FPC), or chip on film (Chip On Flex, COF), etc., which are not limited here.
  • FPGA Field Programmable Gate Array
  • IC Integrated Circuit
  • PCB Printed Circuit Board
  • FPC Flexible Circuit Board
  • COF Chip On Flex, COF
  • an embodiment of the present disclosure also provides a display device including the above-mentioned array substrate.
  • the display device can be applied to any mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, etc. functional product or component. Since the principle of solving the problem of the display device is similar to that of the above-mentioned array substrate, the implementation of the display device may refer to the implementation of the above-mentioned array substrate, and the repetition will not be repeated.
  • an embodiment of the present disclosure also provides a driving method for any of the above-mentioned array substrates. Since the principle of solving the problem of the driving method is similar to that of the above-mentioned array substrate, the implementation of the driving method can refer to the implementation of the above-mentioned array substrate. , and the repetition will not be repeated.
  • FIG. 4 is a timing diagram corresponding to the driving method provided by the embodiment of the present disclosure.
  • the driving method for any of the foregoing array substrates provided by the embodiment of the present disclosure may include:
  • Each display frame T may at least include: an address allocation stage t 1 and a data signal transmission stage t 3 ; wherein,
  • FIG. 5 is a schematic time sequence diagram of address selection information in an embodiment of the present disclosure.
  • the address selection information si may include a row of pixels 11 arranged in the first direction F1 to assign a corresponding address information ID.
  • the address selection signal line S1 distributes the address selection information s1 including the address information ID of 00000001 to the first row of pixels 11 in the current row arranged in the first direction F1, and sends the address selection signal line S2 to the address selection signal line S2.
  • data information da is input to each data line Dj , respectively.
  • a plurality of sub-data information da i are sequentially input to each data line Dj, that is, each data information da includes a plurality of sub-data information da i sequentially arranged in a specific order (for example, the specific order may be the arrangement order of pixels in each column),
  • the data line Dj transmits the corresponding sub-data information da i to each pixel driving chip in the corresponding pixel column in turn.
  • the sub-data information includes: the address information ID corresponding to each pixel 11, and the pixel data information of the pixel 11 corresponding to the address information ID and coupled to the data line D j , and the pixel driving chip receives the sub-data information da i Then, according to the address information ID in the sub-data information dai , the pixel data information is transmitted to the corresponding pixel.
  • the sub-data information da i is sequentially input to the data line D j
  • the pixel driver chip coupled to the data line D j receives the sub-data information da 1 and decodes to obtain the address information ID.
  • the pixel data information carried in the sub-data information da 1 is transmitted to the pixel 11 located in the first row of the jth column.
  • the data information da includes pixel data information corresponding to the plurality of pixels 11 arranged in the first direction F1, thereby controlling different pixels 11 to achieve different light-emitting brightness.
  • address selection information is sequentially input to each address selection signal line, and the address selection information includes the address information ID of the corresponding pixel row.
  • the sub-data information in the data information includes the address information ID and pixel data information of the corresponding pixel row. Therefore, after the pixel driver chip receives the pixel data information, the pixel data information of the pixel row can be respectively It is transmitted to the corresponding sub-pixels, thereby realizing the driving mode of active addressing.
  • the address selection information si may include: a start command SoT, address information ID, an interval command DCX, and an end command EoT that are set in sequence.
  • the address information IDs in the address selection information si corresponding to each address selection signal line Si are different, so as to distinguish the address information of pixels located in different rows.
  • the length of the address selection information si can be set to 12 bits, wherein the start command SoT can be set to 1 bit, the address information ID can be set to 8 bits, the interval command DCX can be set to 1 bit, and the end command EoT can be set to 2bit.
  • the address selection function and other functions can be distinguished by distinguishing the signal amplitudes transmitted by the address selection signal lines Si.
  • the address selection function is performed when the signal amplitude level V 2 (eg, the voltage value is 3.3V)
  • the display function is performed when the signal amplitude level V 1 (eg, the voltage value is 1.8V).
  • the amplitude of the signal transmitted by the addressing signal line Si needs to be raised from the level V 0 (for example, 0V) to the level V 1 to make the components connected to the addressing signal line Si enter the working state, After the signal amplitude changes from level V1 to fluctuate with level V2 as the reference, the address selection signal line Si performs the address selection function, and transmits the fluctuation law of the signal by modulating the address selection signal line Si .
  • the signal varies between the first amplitude V 2H and the second amplitude V 2L , V 1 ⁇ V 2L ⁇ V 2 ⁇ V 2H , by modulating the change of the first amplitude V 1 and the second amplitude V 2
  • the address selection information si can be modulated into the signal, so that the corresponding address information is transmitted while the power is transmitted.
  • the address selection information si starts with the start command SoT, then transmits the address information ID and the interval command DCX, and finally ends the address assignment of the pixel row with the end command EoT.
  • the address selection signal line Si can be used to realize other functions, such as multiplexing s to do
  • the sensing signal lines and the like are not limited here, and of course, the addressing signal lines Si may not have any function in this case.
  • the above-mentioned sub-data information may include: start command SoT, address information ID, data transmission command DCX, interval command IoT, and pixel data information Rda , Gda, Bda and the end instruction EoT.
  • the data transmission command DCX is the set value, it means data transmission.
  • the pixel driver chip recognizes that the value of DCX is 1, it transmits the pixel data information in the sub-data information. to the corresponding LED.
  • the pixel data information Rda represents the image data information required to drive the red sub-pixel to emit light
  • the pixel data information Gda represents the image data information required to drive the green sub-pixel to emit light
  • the pixel data information Bda represents the image data required to drive the blue sub-pixel to emit light.
  • the length of the sub-data information can be set to 63 bits, wherein the start command SoT occupies 1 bit, the address information ID occupies 8 bits, the data transmission command DCX occupies 1 bit, the interval command IoT occupies 1 bit, and the image information Rda, Gda or Bda They occupy 16 bits respectively, and the end command EoT occupies 2 bits.
  • the interval command IoT can also be set between adjacent pixel data information.
  • FIG. 6 is a schematic diagram of encoding of data signals.
  • the timing sequence of sub-data information da 1 is used as an example for illustration.
  • each bit in the data information da can be represented by designing the duty cycle in the pulse sequence. meaning. For example, when the duty cycle of a pulse in the pulse sequence is 25%, it means that the bit represents 0; when the duty cycle of a pulse is 75%, it means that the bit represents 1; the duty cycle of a pulse is When it is 50%, it means that the bit is the start command SoT; when the duty ratio of two consecutive pulses is 50%, there are 2 consecutive SoTs, and the meaning of the 2bits bit is the end command EoT.
  • each display frame T may further include: a current setting phase t 2 before the data signal transmission phase t 3 , for example, a current setting phase t 2 may be located between the address assignment phase t 1 and the data signal transmission phase t 3 .
  • current setting information Co is input to each data line D j .
  • the size of the driving current of the pixel driving chip can be controlled, thereby further accurately controlling the display brightness of the corresponding pixel.
  • the driving currents provided by different pixel driving chips can be set to be different.
  • address information ID may also be set in the current setting information Co, so that the current setting information Co is input to the corresponding pixel row.
  • the length of the current setting information Co may be 63 bits, which may specifically include: a 1-bit start command SoT, an 8-bit address information ID, a 1-bit current setting command DCX, a 1-bit interval command IoT, and a start from the frame. 16bits data, 1bit interval command IoT, 16bits reserved control command bits P2+P3, 1bit Interval command IoT, 16bits reserved control command bits P4+P5, and 2bits end command EoT.
  • the current setting command DCX is a set value, it indicates that the current setting is performed. For example, when DCX is 0, it indicates that the current setting is performed.
  • each address selection signal line Si is controlled to be enabled row by row, and the address information ID is written to the pixel driver chips in each row in turn, that is, the address information ID of the pixel driver chips in the same row can be the same, so that the data signal can have the same ID.
  • the transmission stage t3 when the pixel driving chip receives and analyzes the data signal, it can obtain data information matching its own address.
  • the current setting information Co is simultaneously input to all the data lines Dj, and each data line Dj writes correction data to the buffers of the pixel driving chips in the same pixel column.
  • the photoelectric characteristics of light-emitting diodes in different pixels are inevitably different, which makes the brightness of different pixels different when the display device displays a pure color picture.
  • the display brightness of the light emitting diodes in each pixel can be adjusted.
  • the data information da is simultaneously input to all the data lines Dj, and each data information da transmits its own required data information to the pixel driving chips in the same pixel row in turn, and the pixel driving chips receive and analyze the data information.
  • the sub-data information da j matching its own address can be acquired, and the light-emitting diode is driven to emit light according to the sub-data information da j .
  • the above-mentioned array substrate, driving method and display device provided by the embodiments of the present disclosure adopt a pixel-level constant current driving chip, which can directly drive each sub-pixel in the pixel to emit light, thereby realizing pixel-level driving display.
  • the address selection information is sequentially input to each address selection signal line, and a plurality of sub-data information is respectively input to each data line, so as to control each pixel driving chip to
  • the pixel data information is provided to each sub-pixel, thereby realizing the driving mode of active addressing and greatly reducing the number of signal lines on the base substrate.

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Abstract

一种阵列基板及其驱动方法和显示装置，该阵列基板包括：衬底基板（10）；多个像素（11），位于衬底基板（10）之上；多个像素（11）在第一方向（F1）和第二方向（F2）呈阵列排布，第一方向（F1）与第二方向（F2）相互交叉；多个像素（11）中的至少一个像素（11）包括：子像素（111），以及用于驱动该像素（11）内各子像素（111）的像素驱动芯片（112）；子像素（111）包括至少一个发光二极管；像素驱动芯片（112）包括：数据信号端（Da）和寻址信号端（Uc）；多条选址信号线（S），位于衬底基板（10）之上；选址信号线（S）与在第一方向（F1）上排列的一排像素（11）的各像素驱动芯片（112）的寻址信号端（Uc）耦接；多条数据线（D），位于衬底基板（10）之上；数据线（D）与在第二方向（F2）上排列的一排像素（11）的各像素驱动芯片（112）的数据信号端（Da）耦接。阵列基板可实现有源寻址的驱动方式。

Description

阵列基板、其驱动方法及显示装置 技术领域
本公开涉及显示技术领域，尤指一种阵列基板、其驱动方法及显示装置。
背景技术
随着发光二极管(Light Emitting Diode，LED)技术的不断发展，微型发光二极管是指将LED尺寸微缩为300微米以下，将数千颗、数万颗甚至更多的微型发光二极管固定在基板上，可以进行更细致的局部调光，呈现出对比度高、色彩表现度高的显示画面。
在相关技术中，微型发光二极管显示装置采用的是无源寻址(Passive Matrix，PM)的驱动方式，这种驱动方式需要在玻璃基板上制作大量的信号走线，使得信号走线的绑定难度较大，尤其对于拼接的显示产品来说，需要采用侧边走线工艺，使工艺难度进一步提高。并且，由于制作信号走线的金属层厚度不足和层数限制，需要采用多路复用器(Multiplexer，MUX)来减少信号走线的数量，但是高比例的多路复用器会导致微型发光二极管显示装置的功率过高。
发明内容
本公开实施提供的阵列基板，其中，包括：
衬底基板；
多个像素，位于所述衬底基板之上；所述多个像素在第一方向和第二方向呈阵列排布，所述第一方向与所述第二方向相互交叉；所述多个像素中的至少一个像素包括：子像素，以及用于驱动该像素内各所述子像素的像素驱动芯片；所述子像素包括至少一个发光二极管；所述像素驱动芯片包括：数据信号端和寻址信号端；
多条选址信号线，位于所述衬底基板之上；所述选址信号线与在所述第 一方向上排列的一排所述像素的各所述像素驱动芯片的所述寻址信号端耦接；
多条数据线，位于所述衬底基板之上；所述数据线与在所述第二方向上排列的一排所述像素的各所述像素驱动芯片的所述数据信号端耦接。
可选地，在本公开实施例中，各所述选址信号线沿所述第一方向延伸，并沿所述第二方向排列；
所述选址信号线位于沿所述第一方向上排列的相邻两排所述像素之间的间隙中。
可选地，在本公开实施例中，还包括：多条选址信号转接线；
多条所述选址信号转接线沿所述第二方向延伸，并沿所述第一方向排列；
多条所述选址信号转接线与多条所述选址信号线一一对应；
所述选址信号转接线与所述选址信号线异层设置，且所述选址信号转接线通过第一过孔与对应的所述选址信号线耦接；所述第一过孔贯穿所述选址信号转接线与所述选址信号线之间的绝缘层。
可选地，在本公开实施例中，各所述数据线沿所述第二方向延伸，并沿所述第一方向排列；
所述数据线位于沿所述第一方向上排列的相邻两排所述像素之间的间隙中。
可选地，在本公开实施例中，还包括：多条电源信号线，以及多条固定电压信号线；
所述像素驱动芯片还包括：信号通道端和固定电压信号端；
所述电源信号线与在所述第二方向上排列的一排所述像素的所述发光二极管的第一电极耦接；所述像素中的各所述发光二极管的第二电极分别与所述像素驱动芯片的各所述信号通道端耦接；
所述固定电压信号线与在所述第二方向上排列的一排所述像素的所述像素驱动芯片的所述固定电压信号端耦接。
可选地，在本公开实施例中，所述像素至少包括：红色子像素，绿色子像素，以及蓝色子像素；
所述多条电源信号线分为多条第一电源信号线及多条第二电源信号线；
所述第一电源信号线与在所述第二方向上排列的一排所述像素的各所述红色子像素的第一电极耦接；
所述第二电源信号线与在所述第二方向上排列的一排所述像素的各所述绿色子像素和各所述蓝色子像素的第一极耦接。
可选地，在本公开实施例中，多条辅助信号线；
各所述辅助信号线沿所述第一方向延伸，并沿所述第二方向排列；
所述辅助信号线位于在第一方向上排列的相邻两排所述像素之间的间隙中；
所述辅助信号线与所述固定电压信号线异层设置，且每一条所述辅助信号线通过第二过孔与至少一条所述固定电压信号线耦接；所述第二过孔贯穿所述辅助信号线与所述固定电压信号线之间的绝缘层。
相应地，本公开实施例还提供了一种显示装置，其中，包括：上述任一阵列基板。
相应地，本公开实施例还提供了一种上述任一阵列基板的驱动方法，其中，包括：
每一个显示帧至少包括：地址分配阶段及数据信号传输阶段；其中，
在所述地址分配阶段，依次向各选址信号线输入选址信息；所述选址信息包括在第一方向上排列的一排像素对应的地址信息；
在所述数据信号传输阶段，向各数据线分别输入数据信息；所述数据信息包括多个子数据信息；所述子数据信息包括：在第一方向上排列的一排像素对应的地址信息，以及与该地址信息对应且与该数据线耦接的所述像素的像素数据信息。
可选地，在本公开实施例中，所述选址信息包括：依次设置的起始指令、所述地址信息、间隔指令及结束指令。
可选地，在本公开实施例中，所述子数据信息包括：依次设置的起始指令、所述地址信息、数据传输指令、间隔指令、所述图像信息及结束指令。
可选地，在本公开实施例中，每一个显示帧还包括：在所述数据信号传输阶段之前的电流设定阶段；
在所述电流设定阶段，向各所述数据线输入电流设定信息。
附图说明
图1为本公开实施例提供的阵列基板的平面结构示意图；
图2为本公开实施例中一个像素的连接关系示意图；
图3为本公开实施例中一个像素的另一连接关系示意图；
图4为本公开实施例提供的驱动方法对应的时序图；
图5为本公开实施例中选址信息的时序示意图；
图6为数据信号的编码示意图。
具体实施方式
本公开实施例提供了一种阵列基板、其驱动方法及显示装置。
下面结合附图，对本公开实施例提供的阵列基板、其驱动方法及显示装置的具体实施方式进行详细地说明。附图中各结构的大小和形状不反映真实比例，目的只是示意说明本公开内容。
图1为本公开实施例提供的阵列基板的平面结构示意图，如图1所示，本公开实施例提供的阵列基板，可以包括：
衬底基板10；
多个像素11，位于衬底基板10之上；多个像素11在第一方向F1和第二方向F2呈阵列排布，第一方向F1与第二方向F2相互交叉。图2为本公开实施例中一个像素11的连接关系示意图，结合图1和图2，多个像素11中的至少一个像素11包括：子像素111，以及用于驱动该像素11内各子像素111的像素驱动芯片112；每个子像素111包括至少一个发光二极管；像素驱动芯片112包括：数据信号端Da和寻址信号端Uc；
M条选址信号线S，位于衬底基板10之上；各选址信号线S i(0＜i≤M， i为正整数)与在第一方向F1上排列的一排像素11的各像素驱动芯片112的寻址信号端Uc耦接；
N条数据线D，位于衬底基板10之上；各数据线D j(0＜j≤N，j为正整数)与在第二方向F2上排列的一排像素的各像素驱动芯片112的数据信号端Da耦接。
应该说明的是，第一方向可以为行方向，第二方向可以为列方向；或者，第一方向可以为列方向，第二方向可以为行方向，此处不做限定。为了便于说明，在本公开实施例中，第一方向为行方向，第二方向为列方向。
本公开实施例提供的阵列基板中，至少一个像素包括：子像素，以及像素驱动芯片，通过采用像素驱动芯片直接驱动该像素内的各子像素发光，能够实现像素级的精细驱动。通过设置多条选址信号线和多条数据信号线，在驱动过程中，依次向各选址信号线输入选址信息，向各数据线分别输入多个子数据信息，以使各像素驱动芯片将子数据信息再分别提供给对应的子像素，从而实现了有源寻址的驱动方式，大幅减小了衬底基板上信号走线的数量，使阵列基板中具有足够的空间进行信号走线的布线，可以通过增加信号走线的宽度等布线方式，来降低信号走线的电阻，在不增加信号走线的厚度的情况下，可以增大发光二极管的亮度，从而降低了阵列基板的功率。同时，可以大大降低信号走线的数量，进而降低了绑定区域的宽度以及绑定区域和信号走线的绑定难度。
在本公开实施例中，上述发光二极管可以为次毫米发光二极管(微型发光二极管)，也可以为微型发光二极管(Micro LED)，此处不做限定。图1和图2中以每个子像素包括一个发光二极管为例进行示意，在具体实施时，子像素中也可以包括更多个发光二极管，例如图3中子像素可以包括两个发光二极管，此处不对子像素中的发光二极管的数量进行限定。为了便于控制，子像素中包括至少两个发光二极管时，子像素中的各发光二极管的颜色相同，当然，在一些情况下子像素中的各发光二极管的颜色也可以不完全相同，此处不做限定。图3中以子像素中的各发光二极管并联连接进行示意，子像素中 的各发光二极管也可以串联连接，此处不做限定。
可选地，本公开实施例提供的上述阵列基板中，如图1所示，各选址信号线S i沿第一方向F1延伸，并沿第二方向F2排列；各选址信号线S i位于沿第一方向F1上排列的相邻两排像素11之间的间隙中。这样，可以使选址信号线S i更容易与对应的一排像素11实现连接，便于布线，防止信号走线之间出现交叉。
在具体实施时，本公开实施例提供的上述阵列基板中，继续参照图1，还可以包括：M条选址信号转接线Q；
M条选址信号转接线Q沿第二方向F2延伸，并沿第一方向F1排列；
各选址信号转接线Q i(0＜i≤M，i为正整数)与选址信号线S i一一对应，例如，选址信号转接线Q 1与选址信号线S 1对应；
选址信号转接线Q与选址信号线S异层设置，且选址信号转接线Q i通过第一过孔(如图中选址信号转接线Q i与选址信号线S i交叉位置处的黑色圆圈所示)与对应的选址信号线S i耦接；第一过孔贯穿选址信号转接线Q i与选址信号线S i之间的绝缘层。
假如不设置选址信号转接线Qi，则需要在选址信号线Si延伸方向的两端设置信号源，增大了阵列基板的边框区域的面积，本公开实施例中，通过设置沿第二方向F2延伸的选址信号转接线Qi，可以通过选址信号转接线Q i向对应的选址信号线S i提供选址信号，从而，可以将各选址信号线Si及各数据线Dj等信号线的信号源设置在阵列基板的同一侧边处，例如，可以将信号源设置在选址信号转接线Q i两端中的至少一端，从而减少阵列基板的边框区域的面积。其中，信号源可以向选址信号转接线Q i提供选址信号，例如该信号源可以为驱动芯片。
可选地，为了避免各选址信号转接线Q i影响发光二极管出射光线，可以将选址信号转接线Q i设置在相邻两个像素列之间的间隙中，在实际应用中，可以将各选址信号转接线Q i设置为较均匀的分布于各间隙中，例如，阵列基板中的行数与列数相等时，可以在每一个像素列的同一侧均设置一条选址信 号转接线Q i。当阵列基板中的行数大于列数时，可以在每相邻两个像素列的间隙中均设置选址信号转接线Q i，并且，至少部分间隙中设置两条选址信号转接线Q i。
可选地，本公开实施例提供的上述阵列基板中，如图1所示，各数据线D j沿第二方向F2延伸，并沿第一方向F1排列；
数据线D j位于沿第一方向F1上排列的相邻两排像素11之间的间隙中。这样，可以使数据线D j更容易与对应的一排像素11实现连接，便于布线，防止信号走线之间出现交叉。
此外，本公开实施例提供的上述阵列基板中，结合图1和图2，还可以包括：N条电源信号线Va及Vb，以及N条固定电压信号线G；
像素驱动芯片112还可以包括：信号通道端CH(例如CH 1、CH 2、CH 3)和固定电压信号端Gd；
电源信号线Va j、Vb j与在第二方向F2上排列的一排像素11的发光二极管的第一电极耦接；像素11中的各发光二极管的第二电极分别与像素驱动芯片112的各信号通道端CH耦接；其中，第一电极可以为发光二极管的正极，第二电极可以为发光二极管的负极。
固定电压信号线G j(0＜j≤N，j为正整数)与在第二方向F2上排列的一排像素11的像素驱动芯片112的固定电压信号端Gd耦接。
电源信号线Va j(或Vb j)(0＜j≤N，j为正整数)与发光二极管的第一电极耦接，因而，电源信号线Va j(或Vb j)可以向发光二极管提供电源，并且，发光二极管的第二电极与像素驱动芯片112的信号通道端CH耦接，固定电压信号线G j与像素驱动芯片112的固定电压信号端Gd耦接，固定电压信号线G j可以向像素驱动芯片112提供固定电压信号，以形成供电回路。发光二极管为电流驱动型元件，像素驱动芯片112通过信号通道端CH向耦接的发光二极管提供信号通路，以使发光二极管在不同电流幅值和/或不同占空比的电流信号的控制下，实现不同的出光亮度。可选地，各电源信号线Va j(或Vb j)及各固定电压信号线G j可以设置在相邻两个像素列之间的间隙中。
在具体实施时，本公开实施例提供的上述阵列基板中，结合图1和图2，像素11至少包括：红色子像素R，绿色子像素G，以及蓝色子像素B。其中，红色子像素R可以包括至少一个红色微型发光二极管，绿色子像素G可以包括至少一个绿色微型发光二极管，蓝色子像素B可以包括至少一个蓝色微型发光二极管；
多条电源信号线分为多条第一电源信号线Va j及多条第二电源信号线Vb j；
第一电源信号线Va j与在第二方向F2上排列的一排像素11的各红色子像素R的第一电极耦接；
第二电源信号线Vb j与在第二方向F2上排列的一排像素11的各绿色子像素G和各蓝色子像素B的第一极耦接。
由于不同颜色的发光二极管的特性不同，红色子像素所需电压与绿色子像素所需电压的差异较大，绿色子像素所需电压与蓝色子像素所需电压近似，因而，将第二电源信号线Vbj与一列像素11中的各绿色子像素G和各蓝色子像素B耦接，绿色子像素G与蓝色子像素B共用电源信号线，可以大幅减少电源信号线的数量，简化阵列基板的布线。
可选地，本公开实施例提供的上述阵列基板中，如图1所示，M条辅助信号线W；
各辅助信号线W i(0＜i≤M，i为正整数)沿第一方向F1延伸，并沿第二方向F2排列；
辅助信号线W i位于在第一方向F1上排列的相邻两排像素11之间的间隙中，避免影响各子像素的出光；
辅助信号线W i与固定电压信号线G j异层设置，且每一条辅助信号线W i通过第二过孔(如图中辅助信号线W i与固定电压信号线G j交叉位置处的黑色圆圈所示)与至少一条固定电压信号线G j耦接；第二过孔贯穿辅助信号线W i与固定电压信号线G j之间的绝缘层。
通过设置与固定电压信号线G j异层的辅助信号线W i，且辅助信号线W i通过第二过孔与固定电压信号线G j耦接，从而使多根固定电压信号线G和多 根辅助信号线W构成网格状的并联结构，降低固定电压信号线G的电阻，以降低固定电压信号线G j的压降，减小固定电压信号线G j上的信号延迟。可选地，可以在固定电压信号线G与辅助信号线W在衬底基板上的正投影存在交叠的每个区域均设置第二过孔，以增大固定电压信号线G j与辅助信号线W i的并联区域，进一步减小固定电压信号线G j上的信号延迟。
本公开实施例中，为了节省工艺制作流程，节约制作成本，可以将各选址信号线S i，以及各辅助信号线W i设置于同一膜层，可以将各数据线D j，各选址信号转接线Q i，各电源信号线Va j及Vb j，以及各固定电压信号线G j设置于同一膜层。也就是说，将沿第一方向F1延伸的各信号走线设置在同一膜层，将沿第二方向F2延伸的各信号走线设置在同一膜层，这样，还可以避免沿第一方向F1延伸的信号走线与沿第二方向F2延伸的信号走线位于同一膜层时出现交叉，降低布线难度。
在具体实施时，参照图1，可以在阵列基板沿第一方向F1延伸的侧边的边缘处设置信号源，该信号源可以与N条数据线D，M条选址信号转接线Q，N条电源信号线Va及N条电源信号线Vb，以及N条固定电压信号线G耦接，以向沿第二方向F2延伸的各信号走线通过相应的驱动信号。可选地，该信号源可以为现场可编程逻辑门阵列(Field Programmable Gate Array，FPGA)，或者集成电路(Integeral Cirtcuit，IC)，或者印刷电路板(Printed Circuit Board，PCB)，或者柔性电路板(Flexible Printed Circuit，FPC)，或者覆晶薄膜(Chip On Flex，COF)等，此处不做限定。本公开实施例中，通过设置一个信号源即可向各信号走线提供相应的信号，可以大幅增大阵列基板的布线空间，有利于阵列基板的窄边框化。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括上述阵列基板，该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与上述阵列基板相似，因此该显示装置的实施可以参见上述阵列基板的实施，重复之处不再赘述。
基于同一发明构思，本公开实施例还提供了一种上述任一阵列基板的驱动方法，由于该驱动方法解决问题的原理与上述阵列基板相似，因此该驱动方法的实施可以参见上述阵列基板的实施，重复之处不再赘述。
图4为本公开实施例提供的驱动方法对应的时序图，结合图1和图4，本公开实施例提供的上述任一阵列基板的驱动方法，可以包括：
每一个显示帧T至少可以包括：地址分配阶段t 1及数据信号传输阶段t 3；其中，
在地址分配阶段t 1，依次向各选址信号线S i输入选址信息s i。图5为本公开实施例中选址信息的时序示意图，如图5所示，选址信息s i可以包括在第一方向F1上排列的一排像素11分配对应的地址信息ID。举例来说，选址信号线S 1将包括地址信息ID为00000001的选址信息s 1分配至沿第一方向F1上排列的当前排中的第一行像素11，向选址信号线S 2将包括地址信息ID为00000010的选址信息s 2分配至沿第一方向F1上排列的当前排中的第二行像素11，以此类推，完成向各像素行中的像素驱动芯片的地址分配过程。
在数据信号传输阶段t 3，向各数据线D j分别输入数据信息da。具体地，向各数据线Dj依次输入多个子数据信息da i，即每个数据信息da包括按特定顺序(例如特定顺序可以为每列像素的排列顺序)依次排列的多个子数据信息da i，使得数据线Dj依次向对应的像素列中的各像素驱动芯片传输对应的子数据信息da i。其中，子数据信息包括：各像素11对应的地址信息ID，以及与该地址信息ID对应且与该数据线D j耦接的像素11的像素数据信息，像素驱动芯片接收到子数据信息da i后，根据子数据信息da i中的地址信息ID，将像素数据信息传输给对应的像素。举例来说，在数据信号传输阶段t 3，向数据线D j依次输入子数据信息da i，与数据线D j耦接的像素驱动芯片接收到子数据信息da 1后，解码得到地址信息ID为00000001，则将子数据信息da 1中携带像素数据信息传输给位于第j列第一行的像素11。数据信息da中包括了对应在第一方向F1排列的多个像素11的像素数据信息，从而控制不同的像素11实现不同的出光亮度。
本公开实施例提供的驱动方法中，在地址分配阶段，依次向各选址信号线输入选址信息，选址信息中包括对应的像素行的地址信息ID，在数据信号传输阶段，向各数据线分别输入数据信息；数据信息中的子数据信息中包括对应的像素行的地址信息ID及像素数据信息，因而，像素驱动芯片接收到像素数据信息后，可以将该像素行的像素数据信息分别传送给对应的子像素，从而实现了有源寻址的驱动方式。
可选地，本公开实施例提供的上述驱动方法中，如图5所示，选址信息s i可以包括：依次设置的起始指令SoT、地址信息ID、间隔指令DCX及结束指令EoT。在实际应用中，各选址信号线S i对应的选址信息s i中的地址信息ID不同，从而区分位于不同行像素的地址信息。在具体实施时，选址信息s i的长度可以设置为12bit，其中，起始指令SoT可以设为1bit，地址信息ID可以设为8bit、间隔指令DCX可以设为1bit，结束指令EoT可以设为2bit。
如图5所示，在具体实施时，可以通过区分选址信号线S i传输的信号幅值，来区分选址功能和其他功能。例如，信号幅值的电平V 2(例如电压值为3.3V)时执行选址功能，信号幅值的电平V 1(例如电压值为1.8V)时执行显示功能。实际工作时，首先选址信号线S i传输的信号幅值需要从电平V 0(例如0V)升高至电平V 1以使与选址信号线S i连接的元器件进入工作状态，随后信号幅值从电平V 1变化至以电平V 2为基准波动后，则选址信号线S i执行选址功能，通过调制选址信号线S i传输信号的波动变化规律。例如，信号在第一幅值V 2H和第二幅值V 2L之间变化，V 1<V 2L<V 2<V 2H，通过调制第一幅值V 1和第二幅值V 2的变化规律，可以将选址信息s i调制到该信号中，从而使在传输电能的同时传输对应的地址信息。例如，选址信息s i以起始指令SoT作为开始，然后传输地址信息ID及间隔指令DCX，最后以结束指令EoT结束该像素行的地址分配。当信号幅值从以电平V 2为基准波动再回到电平V 1后并一直保持电平V 1的情况下，选址信号线S i可以用于实现其他功能，例如复用s做感测信号线等，在此不做限定，当然选址信号线S i在此情况下也可以不具有任何功能。
可选地，本公开实施例提供的上述驱动方法中，如图4所示，上述子数据信息可以包括：起始指令SoT、地址信息ID、数据传输指令DCX、间隔指令IoT、像素数据信息Rda、Gda、Bda及结束指令EoT。其中，数据传输指令DCX为设定值时，表示进行数据传输，例如DCX＝1时，表示数据传输，当像素驱动芯片识别到DCX的值为1时，将子数据信息中的像素数据信息传输给对应的发光二极管。像素数据信息Rda表示驱动红色子像素发光所需的图像数据信息，像素数据信息Gda表示驱动绿色子像素发光所需的图像数据信息，像素数据信息Bda表示驱动蓝色子像素发光所需的图像数据信息。在具体实施时，子数据信息的长度可以设置为63bit，其中，起始指令SoT占1bit，地址信息ID占8bit，数据传输指令DCX占1bit，间隔指令IoT占1bit，图像信息Rda、Gda或Bda分别占16bit，结束指令EoT占2bit，此外，相邻的像素数据信息之间也可以设置间隔指令IoT。
图6为数据信号的编码示意图，图6中以子数据信息da 1的时序为例进行示意，如图6所示，可以通过设计脉冲序列中的占空比来表示数据信息da中各bit位的含义。例如脉冲序列中某个脉冲的占空比为25％时，表示该bit位代表0；某个脉冲的占空比为75％时，表示该bit位代表1；某个脉冲的占空比为50％时，表示该bit位为开始指令SoT；当连续两个脉冲的占空比均为50％时，即出现2个连续的SoT，则该2bits位的含义为结束指令EoT。
此外，本公开实施例提供的上述驱动方法中，如图4所示，每一个显示帧T还可以包括：在数据信号传输阶段t 3之前的电流设定阶段t 2，例如电流设定阶段t 2可以位于地址分配阶段t 1与数据信号传输阶段t 3之间。
结合图1和图4，在电流设定阶段t 2，向各数据线D j输入电流设定信息Co。通过向数据线输入电流设定信息，可以控制像素驱动芯片的驱动电流的大小，进而进一步精确控制对应像素的显示亮度。在具体实施时，不同的像素驱动芯片提供的驱动电流可以设置为不同。在具体实施时，电流设定信息Co中也可以设有地址信息ID，从而向对应的像素行输入电流设定信息Co。
可选地，电流设定信息Co的长度可以为63bit，具体可以包括：1bit的起 始指令SoT、8bits的地址信息ID、1bit的电流设定指令DCX、1bit的间隔指令IoT、由帧起始指令C和控制指令P1(例如表示信号通道端CH需要提供给发光二极管的电流幅值校正系数)共同组成的16bits数据、1bit的间隔指令IoT、16bits的预留控制指令位P2+P3、1bit的间隔指令IoT、16bits的预留控制指令位P4+P5，以及2bits的结束指令EoT。其中，电流设定指令DCX为设定值时表示进行电流设定，例如DCX为0时，表示进行电流设定。
以下结合图4所示的时序，对本公开实施例中一个显示帧T的驱动过程进行详细说明。
在地址分配阶段t 1，控制各选址信号线Si逐行使能，依次向各行的像素驱动芯片写入地址信息ID，即位于相同行的像素驱动芯片的地址信息ID可以相同，从而在数据信号传输阶段t3，像素驱动芯片接收并解析数据信号时，能够获取与自身地址匹配的数据信息。
在电流设定阶段t 2，向所有的数据线Dj同时输入电流设定信息Co，每一条数据线Dj向同一像素列中的各像素驱动芯片的缓冲器写入校正数据。例如，由于生产厂家、批次不同等原因，不同像素内的发光二极管的光电特性不可避免的存在差异，这就使得显示装置显示纯色画面时，不同像素呈现的亮度不同。本公开实施例中，在电流设定阶段t 2，通过向各像素驱动芯片写入校正数据，可以调整各像素中发光二极管的显示亮度。
在数据信号传输阶段t 3，向所有的数据线Dj同时输入数据信息da，每一个数据信息da向同一像素列的像素驱动芯片依次传输各自所需的数据信息，像素驱动芯片接收并解析数据信息da后，能够获取与自身地址匹配的子数据信息da j，根据子数据信息da j驱动发光二极管发光。
本公开实施例提供的上述阵列基板、其驱动方法及显示装置，采用像素级恒流驱动芯片，可以直接驱动该像素内的各子像素发光，实现了像素级驱动显示。通过设置多条选址信号线和多条数据信号线，在驱动过程中，依次向各选址信号线输入选址信息，向各数据线分别输入多个子数据信息，以控制各像素驱动芯片将像素数据信息提供给各子像素，从而实现了有源寻址的 驱动方式，大幅减小了衬底基板上信号走线的数量。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (12)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    多个像素，位于所述衬底基板之上；所述多个像素在第一方向和第二方向呈阵列排布，所述第一方向与所述第二方向相互交叉；所述多个像素中的至少一个像素包括：子像素，以及用于驱动该像素内各所述子像素的像素驱动芯片；所述子像素包括至少一个发光二极管；所述像素驱动芯片包括：数据信号端和寻址信号端；
    多条选址信号线，位于所述衬底基板之上；所述选址信号线与在所述第一方向上排列的一排所述像素的各所述像素驱动芯片的所述寻址信号端耦接；
    多条数据线，位于所述衬底基板之上；所述数据线与在所述第二方向上排列的一排所述像素的各所述像素驱动芯片的所述数据信号端耦接。
  2. 如权利要求1所述的阵列基板，其中，各所述选址信号线沿所述第一方向延伸，并沿所述第二方向排列；
    所述选址信号线位于沿所述第一方向上排列的相邻两排所述像素之间的间隙中。
  3. 如权利要求2所述的阵列基板，其中，还包括：多条选址信号转接线；
    多条所述选址信号转接线沿所述第二方向延伸，并沿所述第一方向排列；
    多条所述选址信号转接线与多条所述选址信号线一一对应；
    所述选址信号转接线与所述选址信号线异层设置，且所述选址信号转接线通过第一过孔与对应的所述选址信号线耦接；所述第一过孔贯穿所述选址信号转接线与所述选址信号线之间的绝缘层。
  4. 如权利要求1所述的阵列基板，其中，各所述数据线沿所述第二方向延伸，并沿所述第一方向排列；
    所述数据线位于沿所述第一方向上排列的相邻两排所述像素之间的间隙中。
  5. 如权利要求1～4任一项所述的阵列基板，其中，还包括：多条电源信号线，以及多条固定电压信号线；
    所述像素驱动芯片还包括：信号通道端和固定电压信号端；
    所述电源信号线与在所述第二方向上排列的一排所述像素的所述发光二极管的第一电极耦接；所述像素中的各所述发光二极管的第二电极分别与所述像素驱动芯片的各所述信号通道端耦接；
    所述固定电压信号线与在所述第二方向上排列的一排所述像素的所述像素驱动芯片的所述固定电压信号端耦接。
  6. 如权利要求5所述的阵列基板，其中，所述像素至少包括：红色子像素，绿色子像素，以及蓝色子像素；
    所述多条电源信号线分为多条第一电源信号线及多条第二电源信号线；
    所述第一电源信号线与在所述第二方向上排列的一排所述像素的各所述红色子像素的第一电极耦接；
    所述第二电源信号线与在所述第二方向上排列的一排所述像素的各所述绿色子像素和各所述蓝色子像素的第一极耦接。
  7. 如权利要求5所述的阵列基板，其中，多条辅助信号线；
    各所述辅助信号线沿所述第一方向延伸，并沿所述第二方向排列；
    所述辅助信号线位于在第一方向上排列的相邻两排所述像素之间的间隙中；
    所述辅助信号线与所述固定电压信号线异层设置，且每一条所述辅助信号线通过第二过孔与至少一条所述固定电压信号线耦接；所述第二过孔贯穿所述辅助信号线与所述固定电压信号线之间的绝缘层。
  8. 一种显示装置，其中，包括：如权利要求1～7任一项所述的阵列基板。
  9. 一种如权利要求1～7任一项所述的阵列基板的驱动方法，其中，包括：
    每一个显示帧至少包括：地址分配阶段及数据信号传输阶段；其中，
    在所述地址分配阶段，依次向各选址信号线输入选址信息；所述选址信息包括在第一方向上排列的一排像素对应的地址信息；
    在所述数据信号传输阶段，向各数据线分别输入数据信息；所述数据信息包括多个子数据信息；所述子数据信息包括：各像素对应的地址信息，以及与该地址信息对应且与该数据线耦接的所述像素的像素数据信息。
  10. 如权利要求9所述的驱动方法，其中，所述选址信息包括：依次设置的起始指令、所述地址信息、间隔指令及结束指令。
  11. 如权利要求9所述的驱动方法，其中，所述子数据信息包括：依次设置的起始指令、所述地址信息、数据传输指令、间隔指令、所述图像信息及结束指令。
  12. 如权利要求9～11任一项所述的驱动方法，其中，每一个显示帧还包括：在所述数据信号传输阶段之前的电流设定阶段；
    在所述电流设定阶段，向各所述数据线输入电流设定信息。
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