WO2023205935A1 - 电子设备及显示驱动方法 - Google Patents

电子设备及显示驱动方法 Download PDF

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Publication number
WO2023205935A1
WO2023205935A1 PCT/CN2022/088732 CN2022088732W WO2023205935A1 WO 2023205935 A1 WO2023205935 A1 WO 2023205935A1 CN 2022088732 W CN2022088732 W CN 2022088732W WO 2023205935 A1 WO2023205935 A1 WO 2023205935A1
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WIPO (PCT)
Prior art keywords
circuit
coupled
driving
control signal
light
Prior art date
Application number
PCT/CN2022/088732
Other languages
English (en)
French (fr)
Inventor
李秀玲
谷其兵
胡国锋
付宝
黄文杰
时凌云
Original Assignee
京东方科技集团股份有限公司
京东方晶芯科技有限公司
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Application filed by 京东方科技集团股份有限公司, 京东方晶芯科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/088732 priority Critical patent/WO2023205935A1/zh
Priority to CN202280000856.1A priority patent/CN117413312A/zh
Publication of WO2023205935A1 publication Critical patent/WO2023205935A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of light emitting technology, and in particular to electronic devices and display driving methods.
  • LED display refers to the traditional LEDs that are arrayed and miniaturized and then transferred to the circuit substrate in large quantities to form ultra-fine spacing LEDs. The length of the LEDs from the millimeter level is further reduced to the micron level. A technology that achieves ultra-high pixels and ultra-high resolution and can theoretically adapt to screens of various sizes.
  • a first end of at least one of the plurality of device groups is coupled to the positive signal line, and a second end of at least one of the plurality of device groups is coupled to any one of the plurality of driving elements.
  • the output end of the driving element is coupled, and the reference voltage end of any one of the plurality of driving elements is configured to be coupled with the reference signal line;
  • Any one of the plurality of driving elements is configured to: control the positive signal line and its reference voltage terminal to form an electrical circuit within the working time period of a light-emitting cycle; and, during the working time period of the light-emitting cycle Before that, the potential of the second end of the device group coupled thereto is adjusted.
  • any one of the plurality of driving elements is further configured to: before the working period, control the second end of the device group coupled thereto to conduct a second end with its reference voltage end. One compensation time.
  • any one of the plurality of driving elements is further configured to: at the end of the first compensation time, control the positive signal line to at least sequentially pass through the The device group, the output terminal of the driving element, and the reference voltage terminal form an electrical circuit.
  • any one of the plurality of driving elements is further configured to: control the second end of the device group coupled thereto to conduct with its reference voltage end within the operating time period. Second compensation time.
  • the first compensation time and the second compensation time are sequentially consecutive time periods.
  • the second compensation time corresponding to the device group is less than the first compensation time.
  • the second compensation time corresponding to the device group is less than half of the first compensation time.
  • the at least one device group includes a plurality of devices
  • Each device in the plurality of devices has a one-to-one correspondence with the first compensation time and the second compensation time, and the second compensation time corresponding to each device in the plurality of devices is less than the Half of the first compensation time.
  • At least two devices among the plurality of devices respectively correspond to different first compensation times; where the first compensation time is relatively larger, the corresponding second compensation time is relatively larger.
  • the second compensation time corresponding to at least some of the devices in the plurality of devices is the same.
  • any one of the plurality of driving elements is further configured to: control the second component of the device group coupled thereto according to a pre-stored potential compensation time corresponding to the device group coupled thereto.
  • the potential compensation time is connected between the terminal and its reference voltage terminal; wherein, the potential compensation time is the first compensation time; or, the potential compensation time is one of the first compensation time and the second compensation time.
  • any one of the plurality of driving elements includes: a processing control circuit and a data driving circuit; the data driving circuit is respectively connected to the processing control circuit, the output terminal and the reference voltage terminal coupling;
  • the processing control circuit is configured to generate a lighting control signal during the lighting period and send the lighting control signal to the data driving circuit; and generate a potential adjustment control signal according to the potential compensation time, and sending the potential adjustment control signal to the data driving circuit;
  • the data driving circuit is configured to control the positive signal line to sequentially pass through the device group coupled to the driving element and the output of the driving element according to the received light-emitting control signal during the light-emitting period. terminal and the reference voltage terminal to form an electrical circuit; and according to the effective level of the received potential adjustment control signal, control the second terminal of the corresponding device group to conduct with its reference voltage terminal; wherein, the corresponding second terminal of the device group
  • the effective level duration of the potential adjustment control signal is the potential compensation time.
  • the data driving circuit includes: at least one data driving sub-circuit; one of the data driving sub-circuit is coupled to one of the output terminals;
  • the data driving subcircuit is configured to receive a lighting control signal and a potential adjustment control signal corresponding to the coupled device group, and in response to the lighting control signal, control the positive signal line to pass through the driving element sequentially.
  • the coupled device group, the output end of the driving element, and the reference voltage terminal form an electrical loop; and in response to the potential adjustment control signal, control the second end of the coupled device group to conduct with its reference voltage end .
  • the lighting control signal includes a driving control signal and a current control signal
  • the data driving sub-circuit includes: a modulation circuit, a constant current source circuit and a potential adjustment circuit; wherein the constant current source circuit is coupled to the processing control circuit and the modulation circuit respectively, and the modulation circuit is connected to the corresponding The output terminal is coupled; the potential adjustment circuit is coupled to the processing control circuit and the corresponding output terminal respectively;
  • the constant current source circuit is configured to receive the current control signal of the corresponding device group, and according to the received current control signal, output a current corresponding to a constant amplitude of the current control signal;
  • the modulation circuit is configured to receive the drive control signal of the corresponding device group, and input the current generated by the constant current source circuit into the coupled output terminal according to the effective level of the received drive control signal. , to control the positive signal line to form an electrical loop at least sequentially through the device group coupled to the driving element, the output end of the driving element, and the reference voltage end during the working period;
  • the potential adjustment circuit is configured to receive the potential adjustment control signal of the corresponding device group, and control the second end of the coupled device group to be conductive with its reference voltage end according to the received potential adjustment control signal.
  • the electronic device further includes: a control circuit; the control circuit is respectively coupled to the plurality of driving elements;
  • the control circuit is configured to store the potential compensation time of the device group corresponding to each of the coupled driving elements; and, when the electronic device is turned on, set the device corresponding to each of the driving elements.
  • the potential compensation time of the group is sent to each of the driving elements;
  • the driving element is configured to receive and store the potential compensation time sent by the system circuit when the electronic device is turned on; and to clear the stored potential compensation time when the electronic device is turned off.
  • a drive signal terminal of any one of the plurality of drive elements is configured to be coupled to a drive signal line
  • the control circuit is further configured to be coupled to the drive signal line and store the address of each coupled drive element; and to transmit a drive carrying the address corresponding to the drive element to the drive signal line. data;
  • the driving element is further configured to receive the driving data when a corresponding address in the driving data is recognized, and generate the lighting control signal according to the driving data.
  • the addressing signal terminal of any one of the plurality of driving elements is configured to be coupled with the addressing signal line;
  • the control circuit is further configured to be coupled to the address selection signal line and input a supply voltage to the address selection signal line;
  • the driving element is further configured to receive the supply voltage via the addressing signal terminal.
  • the display driving method provided by the embodiment of the present disclosure is applied to electronic equipment, where the electronic equipment includes multiple device groups and multiple driving elements;
  • the display driving method includes:
  • the potential of the second end of the device group coupled thereto is adjusted.
  • Figure 1 is a schematic structural diagram of some electronic devices provided by embodiments of the present disclosure.
  • Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of some partial structures of a display panel provided by an embodiment of the present disclosure.
  • Figure 4 is another partial structural diagram of a display panel provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of some further partial structures of a display panel provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of some layout structures of a display panel provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic cross-sectional structural diagram along the direction AA’ in the layout structural diagram shown in Figure 6;
  • Figure 8 is another structural schematic diagram of an electronic device provided by an embodiment of the present disclosure.
  • Figure 9 is some signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 10 is another signal timing diagram provided by an embodiment of the present disclosure.
  • Figure 11 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 12 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 13 is a schematic structural diagram of some driving elements provided by embodiments of the present disclosure.
  • Figure 14 is a schematic diagram of some partial structures of driving elements provided by embodiments of the present disclosure.
  • Figure 15 is another partial structural diagram of a driving element provided by an embodiment of the present disclosure.
  • Figure 16 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • Figure 17 is some further signal timing diagrams provided by embodiments of the present disclosure.
  • the electronic device may be a display device, and the functional unit may be a pixel unit.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • the electronic device includes a plurality of driving elements arranged in an array, arranged in M rows and N columns.
  • FIG. 1 is only a possible illustration of the position of the driving element on the base substrate. In actual applications, the number of driving components (i.e., the specific values of N and M) can be determined according to the needs of the actual application, and is not limited here.
  • the electronic device further includes multiple device groups.
  • the first end of a device group can be coupled to the positive signal line, and the second end of the device group can be coupled to the output end of a driving element 112 .
  • a device group ZL and a driving element 112 constitute a functional unit P, and in each functional unit P, the first end of the device group ZL is coupled to the positive signal line, and the device group ZL The second* terminal is coupled to the output terminal of the driving element 112.
  • four device groups ZL_1 ⁇ ZL_4 and one driving element 112 constitute a functional unit P, and in each functional unit P, the first end of the device group 74/8 ZL_1 ⁇ ZL_4 is connected to the positive signal line Coupling, the second terminals of the device groups ZL_1 ⁇ ZL_4 are coupled to different output terminals of the 74/8 driving element 112 respectively.
  • This disclosure does not limit the number of device groups/in each functional unit.
  • a device group includes at least one device.
  • a device group includes multiple devices.
  • the device may be configured as a light-emitting device, and then a device group may include at least one light-emitting device.
  • the first end of the device group may be the positive electrode of the light-emitting device, and the second end may be the negative electrode of at least one light-emitting device.
  • each device group may include three light-emitting devices (eg, 1111 to 1113).
  • the functional types and specific quantities of the devices in the device group can be determined according to the needs of the actual application, and are not limited here. The following description takes the example that each device group can include three light-emitting devices.
  • one device group ZL includes multiple devices.
  • the number of output terminals of the driving element 112 may be the same as the number of devices in the device group ZL.
  • one device group ZL includes three light-emitting devices, then the driving element 112 may have three output terminals, and one output terminal is coupled to the negative electrode of the light-emitting device in a sub-pixel.
  • a device group ZL includes six light-emitting devices, but the six light-emitting devices are divided into three groups.
  • each group Two light-emitting devices in each group are connected in parallel, and each group is arranged in a one-to-one sub-pixel.
  • the driving element 112 can still have only three output terminals, and one output terminal is simultaneously coupled to the negative electrodes of the two light-emitting devices in a parallel relationship.
  • the number of output terminals of the driving element 112 may be related to the number of all devices in the multiple device groups ZL. For example, as shown in FIG. 5 , one driving element controls four device groups ZL_1 to ZL_4, and each device group includes three light-emitting devices. Then the driving element 112 has 12 output terminals, and one output terminal is connected to one light-emitting device. The negative coupling of the device.
  • the display panel may further include: a plurality of first positive signal lines Va1...Van...VaN (1 ⁇ n ⁇ N, n is an integer), a plurality of first positive signal lines Va1...Van...VaN (1 ⁇ n ⁇ N, n is an integer), a plurality of first positive signal lines Two positive signal lines Vb1...Vbn...VbN, multiple reference signal lines G1...Gn...GN, multiple address selection signal lines S1...Sm...SM (1 ⁇ m ⁇ M, m is an integer), Multiple address selection signal transfer lines Q1...Qm...QM, multiple drive signal lines D1...Dn...DN, and multiple auxiliary signal lines W1...Wm...WM.
  • a column of functional units P can be made to correspond to at least one first positive signal line among the plurality of first positive signal lines, at least one second positive signal line among the plurality of second positive signal lines, and at least one of the plurality of reference signal lines. At least one reference signal line and at least one driving signal line among the plurality of driving signal lines.
  • one row of functional units P can be made to correspond to at least one of the plurality of address selection signal lines, at least one of the plurality of auxiliary signal lines, and at least one of the plurality of address signal transfer lines.
  • Signal transfer cable For example, the column of functional units P can correspond to a first positive signal line, a second positive signal line, a reference signal line and a driving signal line.
  • one row of functional units P can correspond to one address selection signal line, one auxiliary signal line and one address selection signal transfer line.
  • each first positive signal line, each second positive signal line, each reference signal line, and each driving signal line may be disposed in a gap between two adjacent functional unit columns.
  • Each address selection signal line, each auxiliary signal line and each address selection signal transfer line can be arranged in the gap between two adjacent functional unit rows.
  • the corresponding manner between the functional units and the above-mentioned signal lines can be determined according to the needs of the actual application, and is not limited here.
  • each auxiliary signal line Wm can be coupled with at least one reference signal line Gn to reduce the resistance of the reference signal line Gn and reduce the voltage drop of the reference signal line Gn. Signal delay on small reference signal line Gn.
  • each address selection signal transfer line Qm can be set in one-to-one correspondence with the address selection signal line Sm.
  • each auxiliary signal line Wm can be coupled to each reference signal line Gn, the address selection signal transfer line Q1 is correspondingly coupled to the address selection signal line S1, and the address selection signal transfer line Qm is correspondingly coupled to the address selection signal line Sm.
  • the address selection signal transfer line QM and the address selection signal line SM are coupled correspondingly.
  • the first positive signal line Van can transmit the first positive voltage VLED1
  • the second positive signal line Vbn can transmit the second positive voltage VLED2
  • the reference signal line Gn can transmit the reference voltage VSS.
  • the address signal line Sm can transmit the supply voltage VCC and address selection information
  • the drive signal line Dn can transmit drive data.
  • each device group may include three different colors of light-emitting devices (such as a first color light-emitting device 1111, a second color light-emitting device 1112, a third color light-emitting device Device 1113).
  • the driving element 112 may have output terminals O1 ⁇ O3, a driving signal terminal O4, an addressing signal terminal O5 and a reference voltage terminal O6.
  • the output terminal O1 is coupled to the negative electrode R- of the first color light-emitting device 1111
  • the output terminal O2 is coupled to the negative electrode G- of the second color light-emitting device 1112
  • the output terminal O3 is coupled to the negative electrode B- of the third color light-emitting device 1113.
  • the driving signal terminal O4 is coupled to the driving signal line Dn through the first via p1
  • the addressing signal terminal O5 is coupled to the address selection signal line Sm
  • the reference voltage terminal O6 is coupled to the reference signal line Gn through the first via p2 coupled
  • the auxiliary signal line Vm is coupled to the reference signal line Gn through the first via p5.
  • the positive electrode R+ of the first color light-emitting device 1111 is coupled to the first positive signal line Van
  • the positive electrode G+ of the second color light-emitting device 1112 is coupled to the second positive signal line Vbn through the first via p4
  • the third color light-emitting device 1113 The positive electrode B+ is coupled to the second positive signal line Vbn through the first via hole p4.
  • the address selection signal line Sm is coupled to the address selection signal transfer line Qm through the first via p3.
  • FIG. 6 only illustrates the terminals (for example, O1 ⁇ O6) of the driving element 112 and the positive and negative electrodes (for example, R+, R-, G+) of the light-emitting device. , G-, B+, B-), the driving element 112 and the main part of the light-emitting device are omitted.
  • the first color light-emitting device 1111 may be a red light-emitting device
  • the second color light-emitting device 1112 may be a green light-emitting device
  • the third color light-emitting device 1113 may be a blue light-emitting device.
  • the voltage required to be applied to the positive electrode R+ of the red light-emitting device is usually greater than the voltage required to be applied to the positive electrode G+ of the green light-emitting device and the blue light-emitting device The voltage required to be applied to the positive electrode B+.
  • the positive electrodes of the red light-emitting device, the green light-emitting device and the blue light-emitting device are all coupled to the same positive signal line, the voltage that needs to be loaded on the positive signal line will be relatively large, which not only increases the power consumption, but also increases the power consumption. It will also cause the voltage loaded on the positive electrode of the green light-emitting device and the blue light-emitting device to be too large, reducing their service life.
  • the first positive signal line Van and the second positive signal line Vbn are respectively provided, the positive electrode R+ of the red light-emitting device is coupled to the second positive signal line Vbn, the positive electrode G+ of the green light-emitting device and the positive electrode B+ of the blue light-emitting device are coupled. Connect the first positive signal line Van.
  • the second positive voltage VLED2 applied on the second positive signal line Vbn can be higher than the first positive voltage VLED1 applied on the first positive signal line Van, which not only enables the red light-emitting device to achieve its luminous brightness, but also It can also reduce power consumption and improve the service life of green light-emitting devices and blue light-emitting devices.
  • the display panel may include: a base substrate 010 , a buffer layer 011 located on the base substrate 010 , and the buffer layer 011 is located away from the base substrate 010
  • the first metal layer 012 on one side, the insulating layer 013 on the side of the first metal layer 012 facing away from the base substrate 010, the second metal layer 014 on the side of the insulating layer 013 facing away from the base substrate 010, the second metal layer 014 is the flat layer 015 on the side facing away from the base substrate 010, and the passivation layer 016 is on the side of the flat layer 015 facing away from the base substrate 010.
  • the light-emitting device and the driving element 112 are disposed on the side of the passivation layer 016 away from the base substrate 010 .
  • the first metal layer 012 may include a plurality of first anode signal lines Van, a plurality of second anode signal lines Vbn, and a plurality of spaced apart from each other.
  • the plurality of first positive signal lines Va1, the plurality of second positive signal lines Vb1, the plurality of reference signal lines Gn, the plurality of address selection signal transfer lines Qm and the plurality of driving signal lines Dn can be arranged along the first direction FS1 arranged, extending along the second direction FS2. For example, as shown in FIG.
  • the second direction FS2 is arranged perpendicularly to the first direction FS1.
  • the second direction FS2 may be the column direction
  • the first direction FS1 may be the row direction.
  • the second direction FS2 may be a row direction
  • the first direction FS1 may be a column direction.
  • the second metal layer 014 may include a plurality of first electrodes 144, a plurality of signal connection portions 141, a plurality of connection pads 142, and a plurality of connection traces 143.
  • a plurality of first electrodes 144 , a signal connection portion 141 , a plurality of connection pads 142 and a plurality of connection traces 143 can be provided in one functional unit.
  • a plurality of connection pads 142 may be used to connect the light emitting device and the driving element 112 .
  • part of the first electrode 144 may be coupled to the reference signal line Gn through the first via hole p2, and part of the first electrode 144 may be coupled to the driving signal line Dn through the first via hole p1. It can be coupled with the address selection signal line Sm.
  • different types of signal lines transmit different types of signals, so the line widths of different types of signal lines are also different. If the signal line extends along the first direction FS1, the width of the signal line refers to the width of the signal line perpendicular to the extension direction of its main body (for example, the second direction FS2). For example, as shown in FIG. 6, the width of the reference signal line Gn is greater than the width of the data line Dn.
  • the flat layer 015 includes a plurality of second via holes a2 , and the plurality of second via holes a2 penetrate the flat layer 015 to expose the second metal layer 014 .
  • the passivation layer 016 may include a plurality of third via holes a3 penetrating to the flat layer 015 .
  • a third via hole a3 and a second via hole a2 are positioned correspondingly, forming a through via hole penetrating from the passivation layer 016 to the connection pad 142 of the second metal layer 014 .
  • the light emitting device may be connected to two connection pads 142 through through vias penetrating the planar layer 015 and the passivation layer 016
  • the driving element 112 may be connected to six connection pads 142 through through vias penetrating the planar layer 015 and the passivation layer 016 .
  • the disk 142 is connected, so that under the control of the signal transmitted by the signal line and the driving element 112, the light-emitting device is driven to emit light.
  • the positive and negative electrodes of the light-emitting device and the output terminal of the driving element 112 to the reference voltage terminal O6 can be connected through a soldering material S (such as solder, tin-silver-copper alloy, tin-copper alloy, etc.) coupled to the corresponding connection pad 142 .
  • a soldering material S such as solder, tin-silver-copper alloy, tin-copper alloy, etc.
  • the output terminal O3 of the driving element 112 can be coupled to a connection pad 142 through the soldering material S
  • the negative electrode B- of the third color light-emitting device 1113 can also be coupled to a connection pad 142 through the soldering material S
  • the coupling The connection pad 142 connected to the negative electrode B- can be coupled to the connection pad 142 coupled to the reference voltage terminal O6 through the connection trace 143.
  • the positive electrode B+ of the third color light-emitting device 1113 can also be coupled to a connection pad 142 through the soldering material S.
  • connection pad 142 coupled to the positive electrode B+ can be coupled through a signal connection part 141, and the signal connection part 141 can be connected through The first via p4 is coupled to the first positive signal line Va1.
  • the reference voltage terminal O6 of the driving element 112 may also be coupled to a connection pad 142 through the soldering material S.
  • the connection pad 142 coupled to the reference voltage terminal O6 is coupled to a first electrode 144.
  • the first electrode 144 It may be coupled to the reference signal line Gn through the first via p2.
  • each first positive signal line Van is not a signal line with the same width everywhere.
  • the first positive signal line Van is The width is wider, and in some locations, the width of the first positive signal line Van is narrower.
  • the width of the first positive signal line Van may be the average width of the first positive signal line Van in its extension direction (first direction FS1), and the first positive signal line Van is in the first direction.
  • the average width on FS1 refers to a weighted sum of the widths at each position of the first positive signal line Van.
  • the second positive signal line Vbn, the reference signal line Gn, the address selection signal transfer line Qn, and the drive signal line Dn all have similar characteristics.
  • the average width L3 of the reference signal line Gn can be made greater than the average width L2 of the first positive signal line Van, or the average width L1 of the second positive signal line Vbn, or the average width L5 of the address selection signal transfer line Qn, Or the average width L4 of the driving signal line Dn, which is not limited here.
  • the light-emitting device may be, for example, a mini light-emitting diode (Mini LED) or a micro light-emitting diode (Micro LED).
  • the orthographic projection of the light-emitting device on the base substrate may be in the shape of a quadrilateral, and the size of its long side or wide side may be between 80 ⁇ m and 350 ⁇ m.
  • the light-emitting device can be mounted on the substrate through surface mount technology (SMT) or mass transfer technology.
  • SMT surface mount technology
  • mass transfer technology mass transfer technology
  • the electronic device may further include a control circuit coupled to each driving element 112 of the plurality of driving elements 112 respectively.
  • the control circuit may include a logic control circuit 200 and a system circuit 300 .
  • the system circuit 300 receives an initial signal related to the display screen from a television network interface, etc., performs a series of rendering and decoding processes on the initial signal to generate an image signal, and at the same time generates a frame refresh signal FB, and sets the edge when the pulse of the frame refresh signal FB appears.
  • the image signal is output to the logic control circuit 200.
  • the logic control circuit 200 receives the image signal from the system circuit 300, and after further conversion processing, passes through each first positive signal line Va1, each second positive signal line Vb1, each reference signal line Gn, and each address selection signal in the display panel 100
  • the adapter line Qm and the drive signal line Dn output corresponding drive signals to the drive element or device group.
  • the electronic device may include multiple display panels (eg, 100_1, 100_2) and multiple logic control circuits (eg, 200_1, 200_2).
  • one display panel corresponds to one logic control circuit, and all logic control circuits (such as 200_1, 200_2) are coupled with one system circuit 300. In this way, by splicing multiple display panels, a larger size display panel can be obtained.
  • the system circuit 300 may send the image signal of a corresponding display frame to the logic control circuit.
  • the setting edge of the frame refresh signal may be a falling edge.
  • FB represents a frame refresh signal.
  • the frame refresh signal FB has multiple pulses.
  • the system circuit 300 outputs the image signal corresponding to the display frame to the logic control circuit.
  • the logic control circuit receives the image signal of the display frame F1.
  • the logic control circuit When the falling edge of the second pulse of the frame refresh signal FB occurs, the logic control circuit receives the image signal of the display frame F2. When the falling edge of the third pulse of the frame refresh signal FB occurs, the logic control circuit receives the image signal of the display frame F3.
  • the setting edge of the frame refresh signal may also be a rising edge, and the implementation may refer to the setting edge of the frame refresh signal being a falling edge, which will not be described again here.
  • each display frame includes multiple display sub-frames.
  • the logic control circuit repeatedly sends the same driving data to the driving element K times at the first frequency.
  • the first frequency is The product of the frequency of the frame refresh signal FB and K.
  • the value of K can be 32, 64, etc., and is not limited here.
  • the logic control circuit pre-stores the address of each driving element coupled thereto. Furthermore, in order to control each driving element coupled to the logic control circuit to operate as synchronously as possible, the logic control circuit can generate a horizontal synchronization signal in each display frame, and when the pulse of the generated horizontal synchronization signal appears at a set edge, Corresponding driving data is output to the coupled driving element, and the frequency of the horizontal synchronization signal is the first frequency. For example, within a display frame, the number of setting edges of the horizontal synchronization signal may be K, so that when the pulse of the horizontal synchronization signal appears at the setting edge, the driving data can be sent to the driving element.
  • the setting edge of the horizontal synchronization signal HB is a falling edge
  • the setting edge of the frame refresh signal FB is a falling edge.
  • the system circuit 300 receives an initial signal related to the picture to be displayed in the display frame Fn.
  • the system circuit 300 receives an initial signal related to the picture to be displayed in the display frame F1, and after performing a series of rendering and decoding processes on the initial signal, the system circuit 300 obtains the initial signal according to the pre-stored address ID_1 corresponding to the logic control circuit 200_1 and the corresponding address ID_1 of the logic control circuit 200_2.
  • the address ID_2 is split, and the image signal TX1 corresponding to the logic control circuit 200_1 and the image signal corresponding to the logic control circuit 200_2 are separated ( Figure 9 takes the image signal TX1 corresponding to the logic control circuit 200_1 as an example, and the image signal TX1 corresponding to the logic control circuit 200_2 is The image signal is not shown).
  • the frame refresh signal FB is generated. When the falling edge of the frame refresh signal FB occurs, the image signal TX1 corresponding to the logic control circuit 200_1 can be sent to the logic control circuit 200_1, and the image signal corresponding to the logic control circuit 200_2 can be sent to the logic control circuit 200_1.
  • the logic control circuit 200_1 after receiving the image signal TX1, the logic control circuit 200_1 generates driving data corresponding to the coupled driving element 112 according to the image signal TX1, and generates a horizontal synchronization signal HB.
  • the logic control circuit 200_1 can provide driving data to the driving element 112.
  • Each driving element 112 can decode the portion of the driving data corresponding to its corresponding address and process it twice, and then drive the coupled light-emitting device to emit light.
  • the working process of the logic control circuit 200_2 can refer to the working process of the logic control circuit 200_1, and details will not be described here. It should be noted that the setting edge of the horizontal synchronization signal can also be set as a rising edge, and the implementation method can refer to the implementation method when the setting edge of the horizontal synchronization signal is a falling edge, which will not be described again here.
  • any driving element 112 can control the positive signal line and its reference voltage terminal O6 to form an electrical loop within the working period of a light-emitting cycle. Since the positive signal line is coupled to the first end of the light-emitting device in the device group, the reference voltage terminal O6 of the driving element 112 is coupled to the second end of the light-emitting device in the device group, the positive signal line passes through the coupled device group, When an electrical loop is formed between the output terminal of the driving element 112 and the reference voltage terminal O6, the light-emitting device can be controlled to emit light under the control of current signals with different current amplitudes and/or different duty cycles.
  • each light-emitting period corresponds to a display sub-frame
  • the working period is the time stage in which the above-mentioned electrical circuit is formed.
  • the positive signal line includes a first positive signal line and a second positive signal line. Any driving element 112 can control the first positive signal line to pass through the coupled first color light-emitting device 1111, the output end of the driving element 112, and
  • the reference voltage terminal O6 forms an electrical circuit during the working period of each display subframe, which can cause the first color light-emitting device 1111 to emit light.
  • the second positive signal line is controlled to form an electrical circuit through the coupled second color light-emitting device 1112, the output terminal of the driving element 112, and its reference voltage terminal O6 in sequence during the working period of each display sub-frame, so that The second color light emitting device 1112 emits light.
  • the second positive signal line is controlled to form an electrical circuit through the coupled third color light-emitting device 1113, the output terminal of the driving element 112, and its reference voltage terminal O6 in sequence during the working period of each display sub-frame, so that The third color light emitting device 1113 emits light.
  • the working process of the electronic device may include an address allocation phase t1 and a data signal transmission phase t3.
  • the logic control circuit 200_1 and the display panel 110_1 of the electronic device as an example, the description will be made in conjunction with the signal timing diagrams shown in FIG. 10 and FIG. 11 .
  • the logic control circuit 200_1 can sequentially input address selection information sm to each address selection signal line Sm (m is a positive integer, and 1 ⁇ m ⁇ M).
  • the driving element 112 can receive the corresponding addressing information sm.
  • Figure 11 is a schematic timing diagram of address selection information in an embodiment of the present disclosure.
  • the logic control circuit 200_1 transmits the address selection information s1 including the address ID 00000001 to the address selection signal line S1, arranged along the first direction FS1 and with The plurality of driving elements 112 connected to the address selection signal line S1 receive the address selection information s1.
  • the logic control circuit 200_1 transmits the address selection information s2 including the address ID 00000010 to the address selection signal line S2, and the plurality of driving elements 112 arranged along the first direction FS1 and connected to the address selection signal line S2 receive the address selection information s2. The rest are the same and can be deduced in this way to complete the address allocation process to the driving elements 112 in each functional unit.
  • the logic control circuit 200_1 can provide driving with the address of each driving element 112 coupled thereto to each driving signal line Dn. data da.
  • the driving element 112 recognizes the corresponding address in the driving data, it can receive the driving data and generate a light-emitting control signal according to the driving data to control the positive signal line to pass through the device group coupled to the driving element 112 and the driving element 112 in sequence.
  • the output terminal and the reference voltage terminal O6 form an electrical circuit.
  • each driving data da may include a plurality of sub-data information dam (m is a positive integer, and 1 ⁇ m ⁇ M) arranged in a specific order (for example, the specific order may be the physical positions of the driving elements).
  • m is a positive integer, and 1 ⁇ m ⁇ M
  • the specific order may be the physical positions of the driving elements.
  • multiple sub-data information dam can be input to each drive signal line Dn in sequence, so that the drive signal line Dn can sequentially transmit the corresponding sub-data information dam to each drive element 112 in the corresponding functional unit column.
  • the sub-data information may include: the address ID corresponding to each functional unit P, and the pixel data information of the functional unit P corresponding to the address ID and coupled to the driving signal line Dn.
  • the driving element 112 When the driving element 112 recognizes that the address ID in the sub-data information dam is the same as the address ID received in the address allocation stage t1, it can receive the sub-data information dam and generate corresponding output terminals of the driving element 112 based on the driving data.
  • the light emission control signal is used to control the coupled positive signal line (for example, the first positive signal line and/or the second positive signal line) to pass through the device group coupled to the driving element 112, the output end of the driving element 112, and
  • the reference voltage terminal O6 forms an electrical circuit.
  • the logic control circuit 200_1 and the display panel 100_1 shown in FIG. 3 as an example, in the data signal transmission stage t3, the logic control circuit 200_1 inputs sub-data information da1 ⁇ to the driving signal line Dn.
  • the driving element 112 coupled to the driving signal line Dn respectively obtains the sub-data information matching its address ID from the data information including the sub-data information da1 to daM.
  • the driving element 112 can generate a light-emitting control signal EM1 corresponding to the first color light-emitting device 1111 coupled to the output terminal O1, a light-emitting control signal EM2 corresponding to the second color light-emitting device 1112 coupled to the output terminal O2, based on the sub-data information. and a lighting control signal EM3 corresponding to the third color light-emitting device 1113 coupled to the output terminal O3.
  • At least one positive signal line can be realized to form an electrical circuit with the first color light-emitting device 1111, the output terminal O1 of the driving element 112, and the reference voltage terminal O6 in sequence, so that the first color
  • the light-emitting device 1111 emits light
  • at least one positive signal line can be realized to form an electrical circuit in sequence with the second color light-emitting device 1112, the output terminal O2 of the driving element 112, and the reference voltage terminal O6,
  • the second color light-emitting device 1112 emits light
  • under the control of the light-emitting control signal EM3 at least one positive signal line can be realized to pass through the third color light-emitting device 1113, the output terminal O4 of the driving element 112, and the reference voltage terminal in sequence.
  • O6 forms an electrical circuit, thereby causing the third color light-emitting device 1113 to emit light.
  • each driving data da includes a set of sub-data information corresponding to M driving elements arranged in the second direction FS2, and the sub-data information includes a set of sub-data information corresponding to each driving element among the M driving elements.
  • Driver information for the connected device group includes a set of sub-data information corresponding to M driving elements arranged in the second direction FS2, and the sub-data information includes a set of sub-data information corresponding to each driving element among the M driving elements.
  • the address selection information sm may include: a start command SoT, an address ID, an interval command DCX, and an end command EoT set in sequence.
  • the address IDs in the address information sm corresponding to each address selection signal line Sm are different, thereby distinguishing the addresses of driving elements located in different rows.
  • the length of the address selection information sm can be set to 12 bits, in which the start command SoT can be set to 1 bit, the address ID can be set to 8 bits, the interval command DCX can be set to 1 bit, and the end command EoT can be set to 2 bits.
  • the logic control circuit can also input a power supply voltage to the address selection signal line Sm, and the driving element 112 can receive the power supply voltage transmitted by the address selection signal line Sm through the address signal terminal O5.
  • the addressing function (such as transmitting address information) and other functions (such as transmitting the supply voltage VCC) can be distinguished by distinguishing the signal amplitude transmitted by the addressing signal line Sm.
  • the address selection function is performed when the signal amplitude is at level V2 (for example, the voltage value is 3.3V)
  • the display function (such as transmitting the supply voltage VCC) is performed when the signal amplitude is at level V1 (for example, the voltage value is 1.8V).
  • the signal amplitude transmitted by the address selection signal line Sm needs to increase from level V0 (for example, 0V) to level V1 to make the components connected to the address selection signal line Sm enter the working state. Then the signal amplitude After the level V1 changes to fluctuating based on the level V2, the address selection signal line Sm performs the address selection function and transmits the fluctuation change pattern of the signal by modulating the address selection signal line Sm. For example, the signal changes between the first amplitude V2H and the second amplitude V2L, and V1 ⁇ V2L ⁇ V2 ⁇ V2H.
  • the address selection information can be SM is modulated into the signal, so that the corresponding address is transmitted while transmitting power.
  • the address selection information sm starts with the start command SoT, then transmits the address ID and interval command DCX, and finally ends the address allocation of the pixel row with the end command EoT.
  • the address selection signal line Sm can be used to transmit the supply voltage. In other words, the level V1 transmitted by the address selection signal line Sm can be used as the power supply voltage.
  • the above sub-data information may include: start command SoT, address ID, data transmission Command DCX, interval command IoT, pixel data information Rda, Gda, Bda and end command EoT.
  • start command SoT address ID
  • data transmission command DCX interval command IoT
  • pixel data information Rda Gda
  • Bda end command EoT
  • the driving element 112 recognizes that the value of DCX is 1, it transmits the pixel data information in the sub-data information. to the corresponding LED.
  • the pixel data information Rda represents the information required to drive the first color light-emitting device 1111 to emit light
  • the pixel data information Gda represents the information necessary to drive the second color light-emitting device 1112 to emit light
  • the pixel data information Bda represents the information required to drive the third color light-emitting device 1113
  • the length of each sub-data information can be set to 63 bits.
  • the length of sub-data information da1 can be set to 63 bits, in which the starting instruction SoT occupies 1 bit and the address ID occupies 8 bits.
  • the data transfer command DCX occupies 1 bit
  • the interval command IoT occupies 1 bit
  • the pixel data information Rda, Gda or Bda each occupies 16 bits
  • the end command EoT occupies 2 bits.
  • the interval command IoT can also be set between adjacent pixel data information.
  • the driving element 112 of the present disclosure may be in a sleep state, which is a low-power operating mode or a non-working state.
  • the supply voltage VCC is input to the addressing signal terminal O5 of the driving element 112 through the address selection signal line Sm, so that the driving element 112 is released from the sleep state, that is, the t0 stage in FIG. 10 .
  • the logic control circuit 200_1 and the display panel 100_1 shown in Figure 5 as an example, with reference to Figure 12, in the data signal transmission stage t3, the logic control circuit 200_1 sequentially inputs to the drive signal line Dn
  • the driving element 112 coupled to the drive signal line Dn respectively obtains the sub-data information matching its address ID from the driving data including the sub-data information da1 to daM.
  • the driving element 112 can generate a lighting control signal EM1_1 corresponding to the first color light-emitting device 1111 coupled to the output terminal O1_1, a lighting control signal EM1_2 corresponding to the first color light-emitting device 1111 coupled to the output terminal O1_2, based on the sub-data information.
  • At least one positive signal line can be realized to sequentially pass through the first color light-emitting device 1111, the output terminal O1 of the driving element 112 (including any one of O1_1 to O1_4), and the reference
  • the voltage terminal O6 forms an electrical circuit, thereby causing the corresponding first color light-emitting device 1111 to emit light;
  • the control of the light-emitting control signals EM2_1 to EM2_4 it is possible to realize that at least one positive signal line sequentially passes through the second color light-emitting device 1112 and the driver
  • the output terminal O2 of the element 112 (including any one of O2_1 to O2_4) and the reference voltage terminal O6 form an electrical circuit, thereby causing the corresponding second color light-emitting device 1112 to emit light; under the control of the light-emitting control signals EM3_1 to EM3_4, At least one positive signal line is realized to form an
  • the sub-data information may include: starting instruction SoT, address ID, data transmission Command DCX, interval command IoT, pixel data information Rda1 ⁇ Rda4, Gda1 ⁇ Gda4, Bda1 ⁇ Bda4 and end command EoT.
  • the driving element 112 recognizes that the value of DCX is 1, it transmits the pixel data information in the sub-data information. to the corresponding LED.
  • the pixel data information Rda1 to Rda4 represents the information required to drive the four first color light-emitting devices 1111 coupled to the driving element 112 to emit light
  • the pixel data information Gda1 to Gda4 represents the information required to drive the four first color light-emitting devices 1111 coupled to the driving element 112
  • the information required for the second color light-emitting device 1112 to emit light, and the pixel data information Bda1 to Bda4 represent the information required to drive the four third-color light-emitting devices 1113 coupled to the driving element 112 to emit light.
  • the length of each sub-data information can be set to 63 bits.
  • the starting instruction SoT occupies 1 bit
  • the address ID occupies 8 bits
  • the data transmission instruction DCX occupies 1 bit
  • the interval instruction IoT occupies 1 bit.
  • the sub-pixel data Rda1, Rda2, Rda3, and Rda4 occupy a total of 16 bits.
  • the sub-pixel data Gda1, Gda2, Gda3, and Gda4 occupy a total of 16 bits.
  • the sub-pixel data Bda1, Bda2, Bda3, and Bda4 occupy a total of 16 bits.
  • the end command EoT occupies 2 bits.
  • the interval command IoT can be set between any two adjacent sub-data information.
  • one driving element 112 drives 12 light-emitting devices
  • the serial number relationship between the four pixels 1 connected to the driving element 112 can be realized through the digital logic circuit inside the driving element 112 to convert the pixel data into The sub-pixel data corresponding to each light-emitting device in the information is accurately distributed to the corresponding output terminal.
  • each display frame may also include: a current setting stage t2 before the data signal transmission stage t3.
  • the current setting stage t2 may be located between the address allocation stage t1 and the data signal transmission stage t3.
  • the logic control circuit 200_1 inputs the current setting information Co provided with the address ID to each drive signal line Dn.
  • the driving element 112 recognizes the corresponding address in the current setting information Co, it can receive the current setting information Co, so as to control the size of the driving current of the driving element 112 according to the received current setting information Co, thereby further accurately controlling the driving element 112 .
  • the logic control circuit 200_1 inputs the current setting information Co to each drive signal line Dn.
  • the current setting information Co may be provided with an address ID.
  • the driving element 112 receives the current setting information corresponding to the address from the current setting information Co transmitted on the driving signal line Dn.
  • the length of the current setting information Co may be 63 bits, which may specifically include: a 1-bit start command SoT, an 8-bit address ID, a 1-bit current setting command DCX, a 1-bit interval command IoT, and a frame start command.
  • C and the control command P1 (for example, indicating that the current amplitude correction coefficient of the light-emitting diode coupled to a certain output terminal needs to be provided), the 16bits data, the 1bit interval command IoT, the 16bits reserved control command bits P2+P3, 1bit interval command IoT, 16bits reserved control command bits P4+P5, and 2bits end command EoT.
  • the current setting command DCX is a set value, it means that the current is set. For example, when DCX is 0, it means that the current is set.
  • the display panel may not display the picture in the first display frame entered after the electronic device is turned on (for example, the display is completely black), but perform t0 in the first display frame.
  • the electronic device can only execute the t2 phase and t3 phase.
  • each display subframe in each display frame can have a process of the t2 phase and the t3 phase respectively.
  • the processes of stage t0, stage t1 and stage t2 may also be performed in the first display frame, and in the second and subsequent display frames, the electronic device may only need to perform the process of stage t3.
  • each display subframe in each display frame can have a process of phase t3. That is to say, in the signal timing diagram shown in Figure 9, before the display frame F1, there may also be a display frame F0. In the display frame F0, the process of the t0 stage and the t1 stage or the process of the t0 stage to the t2 stage can be performed. process. Each display subframe in the display frames F1 to F3 executes the process of phase t3 respectively.
  • any one of the plurality of driving elements 112 may include: a processing control circuit 1122 and a data driving circuit 1121 .
  • the processing control circuit 1122 is coupled to the driving signal terminal O4 and the addressing signal terminal O5 respectively
  • the data driving circuit 1121 is coupled to the processing control circuit 1122, the output terminal of the driving element 112, the addressing signal terminal O5 and the reference voltage terminal O6 respectively. catch.
  • the data driving circuit 1121 is coupled to the second terminal of the light-emitting device in the corresponding device group through the output terminal.
  • the processing control circuit 1122 may receive the driving data through the driving signal terminal O4 during the light-emitting period (the light-emitting period may be a display subframe, for example) when identifying the corresponding address in the driving data, and generate a light-emitting control signal according to the driving data, And the light emission control signal is sent to the data driving circuit 1121. Furthermore, the data driving circuit 1121 controls the positive signal line (such as the first positive signal line and the second positive signal line) to pass through the device group coupled to the driving element 112 in sequence during the light-emitting period according to the received light-emitting control signal.
  • the light-emitting devices, the output terminal of the driving element 112, and the reference voltage terminal O6 form an electrical circuit to control each light-emitting device to emit light through the formed electrical circuit.
  • the data driving circuit 1121 may include at least one data driving sub-circuit (such as 11211, 11212, 11213).
  • the data driver sub-circuit (such as 11211, 11212, 11213) is coupled to the processing control circuit 1122, the addressing signal terminal O5 and the reference voltage terminal O6 respectively, and a data driver sub-circuit is coupled to an output terminal, that is, a data
  • the driving sub-circuit can be coupled to the negative electrode of the light-emitting device in a sub-pixel through a corresponding output terminal.
  • the supply voltage VCC When the supply voltage VCC is input through the addressing signal terminal O5, the supply voltage VCC can be input to the data driving subcircuit to power the data driving subcircuit.
  • the reference voltage VSS When the reference voltage VSS is input through the reference voltage terminal O6, the reference voltage VSS can be input to the data driving subcircuit to provide a low voltage for the data driving subcircuit.
  • the data driving subcircuit (such as 11211, 11212, 11213) can receive the lighting control signal corresponding to the coupled device group during the lighting period, and respond to the lighting control signal to control the positive signal line to pass through the device group coupled to the driving element 112 in sequence.
  • the output terminal of the driving element 112, and the reference voltage terminal O6 form an electrical circuit. Exemplarily, as shown in FIG. 3 , FIG. 13 and FIG.
  • the data driving sub-circuit 11211 is coupled to the output terminal O1 , the output terminal O1 is coupled to the cathode of the first color light-emitting device 1111 , and the first color light-emitting device 1111
  • the positive electrode is coupled to the first positive signal line, and the data driving sub-circuit 11211 can receive the lighting control signal EM1 of the corresponding first color light-emitting device 1111, and in response to the lighting control signal EM1, can drive the first positive signal line Van, the first positive signal line Van, and the first positive signal line Van.
  • An electrical circuit is formed between the first color light-emitting device 1111, the output terminal O1 and the reference voltage terminal O6, so that the first color light-emitting device 1111 has current flowing through it and emits light. Furthermore, the data driver sub-circuit 11212 is coupled to the output terminal O2, the output terminal O2 is coupled to the negative electrode of the second color light-emitting device 1112, and the positive electrode of the second color light-emitting device 1112 is coupled to the second positive signal line Vbn. The data driver sub-circuit 11212 is coupled to the output terminal O2.
  • the circuit 11212 can receive the lighting control signal EM2 of the corresponding second color light-emitting device 1112, and in response to the lighting control signal EM2, can drive the second positive signal line Vbn, the second color light-emitting device 1112, the output terminal O2 and the reference voltage terminal.
  • An electrical circuit is formed between O6, so that the second color light-emitting device 1112 has current flowing through it and emits light.
  • the data driver sub-circuit 11213 is coupled to the output terminal O3, the output terminal O3 is coupled to the negative electrode of the third color light-emitting device 1113, the positive electrode of the third color light-emitting device 1113 is coupled to the second positive signal line Vbn, and the data driver sub-circuit 11213 is coupled to the negative electrode of the third color light-emitting device 1113.
  • the circuit 11213 can receive the lighting control signal EM3 of the corresponding third color light-emitting device 1113, and in response to the lighting control signal EM3, can drive the second positive signal line Vbn, the third color light-emitting device 1113, the output terminal O3 and the reference voltage terminal.
  • An electrical circuit is formed between O6, so that the third color light-emitting device 1113 has current flowing through it and emits light.
  • the lighting control signal may include a driving control signal and a current control signal.
  • Each data driving subcircuit may include: a modulation circuit and a constant current source circuit; wherein the constant current source circuit is coupled to the processing control circuit 1122 and the modulation circuit respectively, and the modulation circuit is coupled to the corresponding output terminal.
  • the constant current source circuit can receive the current control signal of the corresponding device group, and according to the received current control signal, output a current with a constant amplitude corresponding to the current control signal.
  • the modulation circuit can receive the drive control signal of the corresponding device group, and according to the effective level of the received drive control signal, input the current generated by the constant current source into the coupled output end to control the positive signal line during the working period.
  • An electrical loop is formed at least sequentially through the device group coupled to the driving element, the output terminal of the driving element, and the reference voltage terminal.
  • the lighting control signal EM1 may include the driving control signal PWM1 and the current control signal DAC1 .
  • the data driving sub-circuit 11211 includes: a modulation circuit 112111 and a constant current source circuit 112112 .
  • the constant current source circuit 112112 can receive the current control signal DAC1 corresponding to the first color light-emitting device 1111, and according to the received current control signal DAC1, output a constant amplitude current IL1 corresponding to the current control signal DAC1.
  • the modulation circuit 112111 can receive the drive control signal PWM1 corresponding to the first color light-emitting device 1111, and input the current IL1 generated by the constant current source circuit 112112 into the coupling according to the effective level (for example, high level) of the received drive control signal PWM1.
  • the connected output terminal O1 is used to control the first positive signal line Van to form an electrical circuit through at least the first color light-emitting device 1111, the output terminal O1 of the driving element 112, and the reference voltage terminal O6 during the working period, so that the first color The light emitting device 1111 emits light. That is to say, within the duration of the effective level of the driving control signal PWM1, the first color light-emitting device 1111 can be regarded as being in the working period. In this way, the luminous brightness of the first color light-emitting device 1111 in each display sub-frame in each display frame can be controlled by combining the drive control signal PWM1 and the current control signal DAC1.
  • the light emission control signal EM2 may include a drive control signal PWM2 and a current control signal DAC2, and the data drive sub-circuit 11212 includes a modulation circuit 112121 and a constant current source circuit 112122.
  • the constant current source circuit 112122 may receive the current control signal DAC2 corresponding to the second color light-emitting device 1112, and according to the received current control signal DAC2, output a current IL2 of constant amplitude corresponding to the current control signal DAC2.
  • the modulation circuit 112121 can receive the drive control signal PWM2 corresponding to the second color light-emitting device 1112, and input the current IL2 generated by the constant current source circuit 112122 into the coupling according to the effective level (for example, high level) of the received drive control signal PWM2.
  • the connected output terminal O2 is used to control the second positive signal line Vbn to form an electrical circuit through at least the second color light-emitting device 1112, the output terminal O2 of the driving element 112, and the reference voltage terminal O6 during the working period, so that the second color The light emitting device 1112 emits light. That is to say, within the duration of the effective level of the driving control signal PWM2, the second color light-emitting device 1112 can be regarded as being in the working period. In this way, the luminous brightness of the second color light-emitting device 1112 in each display sub-frame in each display frame can be controlled by combining the drive control signal PWM2 and the current control signal DAC2.
  • the light emission control signal EM3 may include the drive control signal PWM3 and the current control signal DAC3
  • the data driving sub-circuit 11213 includes: a modulation circuit 112131 and a constant current source circuit 112132.
  • the constant current source circuit 112132 can receive the current control signal DAC3 corresponding to the third color light-emitting device 1113, and according to the received current control signal DAC3, output a current IL3 of a constant amplitude corresponding to the current control signal DAC3.
  • the modulation circuit 112131 can receive the drive control signal PWM3 corresponding to the third color light-emitting device 1113, and input the current IL3 generated by the constant current source circuit 112132 into the coupling according to the effective level (for example, high level) of the received drive control signal PWM3.
  • the connected output terminal O3 is used to control the second positive signal line Vbn to form an electrical circuit through at least the third color light-emitting device 1113, the output terminal O3 of the driving element 112, and the reference voltage terminal O6 during the working period, so that the third color The light emitting device 1113 emits light. That is to say, within the duration of the effective level of the driving control signal PWM3, the third color light-emitting device 1113 can be regarded as being in the working period. In this way, the luminous brightness of the third color light-emitting device 1113 in each display sub-frame in each display frame can be controlled by combining the drive control signal PWM3 and the current control signal DAC3.
  • the effective level of the drive control signal can also be low level, which is not limited here.
  • the modulation circuit when the modulation circuit is turned on, the above electrical loop is turned on and the device group emits light. When the modulation circuit is turned off, the above electrical circuit is disconnected and the device group does not emit light. Therefore, the modulation circuit can modulate the current flowing through the device group under the control of the drive control signal PWM, so that the current flowing through the device group appears as a current signal that can be modulated by the pulse width. Therefore, the drive control signal PWM can be used as a pulse width modulation signal. Moreover, the modulation circuit can modulate the current flowing through the device group according to parameters such as the duty cycle of the drive control signal PWM, thereby controlling the working state of the device group.
  • the device group contains a light-emitting device
  • the duty cycle of the drive control signal PWM by increasing the duty cycle of the drive control signal PWM, the total lighting time of the light-emitting device within a display frame (or display sub-frame) can be increased, thereby increasing the time the light-emitting device emits in the display frame (or display sub-frame). Or the total luminous brightness within the display subframe), so that the brightness of the device group where the light-emitting device is located increases.
  • the duty cycle of the control signal PWM the total lighting time of the light-emitting device in a display frame (or display sub-frame) can be reduced, thereby reducing the total lighting brightness of the light-emitting device in the display frame (or display sub-frame). , causing the brightness of the device group where the light-emitting device is located to decrease.
  • the modulation circuit may be a switching element, such as a metal-oxide semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), a thin film field-effect transistor (Thin Film Transistor, TFT), or other transistors.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • TFT Thin Film Transistor
  • the specific implementation of the modulation circuit can be determined according to the needs of the actual application, and is not limited here.
  • the constant current source circuit may be implemented in a variety of ways.
  • the constant current source circuit may be configured as a circuit composed of a constant current diode, a combination of a digital-to-analog converter and a flip-flop, a current mirror current, and so on.
  • the specific implementation of the constant current source circuit can be determined according to the needs of the actual application, and is not limited here.
  • the 16-bit pixel data information corresponding to other light-emitting devices adopts the same data type and encoding rules.
  • the current control signal DAC1 occupies 6 bits and the drive control signal PWM1 occupies 10 bits; or the current control signal DAC1 occupies 5 bits and the drive control signal PWM1 occupies 11 bits; Either the current control signal DAC1 occupies 4 bits and the drive control signal PWM1 occupies 12 bits; or the current control signal DAC1 occupies 3 bits and the drive control signal PWM1 occupies 13 bits.
  • the current control signal DAC1 can control the constant current source circuit 112112 to output 64 (2 6 ) different current amplitudes.
  • the constant current source circuit 112112 can have different current levels, such as 2uA, 3uA, 5uA, etc.
  • the maximum value of the current IL1 that the constant current source circuit 112112 can output is 128uA (2uA*64), and the minimum value is 2uA (2uA*1), so that the total amplitude of the current IL1 can be
  • the drive control signal PWM1 occupies 10 bits, so the duty cycle of the drive control signal PWM1 can have 1024 (2 10 ) different situations. The more bits the drive control signal PWM1 occupies, the more types of duty cycle conditions there are.
  • each light-emitting device Since the positive and negative electrodes of each light-emitting device are respectively connected to the connection pads on the base substrate, when the connection pads have a voltage difference, a capacitance will be formed between the connection pads, and this capacitance is the light-emitting device itself.
  • Parasitic capacitance has a capacitance ranging from a few pF to tens of pF.
  • the capacitor and the light-emitting device are connected in parallel. Since electronic equipment includes multiple device groups, each device includes at least one light-emitting device. Since each light-emitting device has different parasitic capacitance values due to manufacturing process fluctuations or different light-emitting states, different light-emitting devices are composed of The time for switching from the off state (i.e.
  • off state ZT-off to the lighting state (i.e. on state ZT-on) or the time for switching from the lighting state (i.e. on state ZT-on) to the off state (i.e. off state ZT-off)
  • Different which results in different light-emitting devices actually showing different brightness when they should display the same brightness, thus affecting the visual experience.
  • FL1 represents the theoretical value of the voltage change of the negative electrode of the first color light-emitting device 1111
  • FL2 represents the first color light-emitting device.
  • the positive electrode of the first color light-emitting device 1111 is coupled to the first positive signal line Van
  • the negative electrode of the first color light-emitting device 1111 is coupled to the reference voltage terminal O6 through the modulation circuit 112111 and the constant current source circuit 112112.
  • the existence of the parasitic capacitance of the light-emitting device 1111 causes the cathode voltage of the first color light-emitting device 1111 to be unable to be pulled down from a high level (for example, 2V) to the reference voltage VSS (for example, 1V) instantly, that is, the first color light-emitting device 1111 cannot be pulled down quickly.
  • Switching from the off state (ie, off state ZT-off) to the light emitting state (ie, on state ZT-on) shortens the time for the first color light emitting device 1111 to emit light.
  • the driving element 112 when the driving element 112 is working, it will also generate a similar parasitic capacitance.
  • This parasitic capacitance will also cause the first color light-emitting device 1111 to be unable to quickly switch from the off state (ie, off state ZT-off) to the light emitting state (ie, on state ZT-on), shortening the time for the first color light-emitting device 1111 to emit light (that is, the time of the on state ZT-on).
  • the light-emitting device when the light-emitting device is in the light-emitting state (that is, the on state ZT-on), as long as the voltage difference between the positive and negative electrodes of the light-emitting device is greater than its turn-on voltage, it can emit light. Therefore, the negative voltage of the light-emitting device does not need to be reduced to the reference voltage VSS for the light-emitting device to emit light. Instead, the voltage value of the negative voltage of the light-emitting device plus the turn-on voltage of the light-emitting device is less than the positive voltage of the light-emitting device. It can be in the light-emitting state (i.e. on state ZT-on).
  • the driving element 112 provided by the embodiment of the present disclosure can also adjust the potential of the second end of the device group coupled to it before the working period of the light emitting cycle, for example, pull down the potential of the second end of the device group.
  • the driving element 112 can also adjust the potential of the second end of the device group coupled to it before the working period of the light emitting cycle, for example, pull down the potential of the second end of the device group.
  • the device group includes a first color light-emitting device 1111 , a second color light-emitting device 1112 , and a third color light-emitting device 1113 ; the second end of the device group includes the first color light-emitting device 1111 The negative electrode of the second color light-emitting device 1112 and the negative electrode of the third color light-emitting device 1113; wherein, the negative electrode of the first color light-emitting device 1111 is connected to the output terminal O1 of the driving element 112, and the negative electrode of the second color light-emitting device 1112 is connected to the output terminal O1 of the driving element 112.
  • the output terminal O2 of the driving element 112 is connected, and the negative electrode of the third color light-emitting device 1113 is connected to the output terminal O3 of the driving element 112 .
  • FL3 represents the actual value of the voltage of the negative electrode of the first color light-emitting device 1111 after being adjusted by the potential adjustment circuit.
  • the driving element 112 can adjust the potential of the negative electrode of the first color light-emitting device 1111 before the working period of the first color light-emitting device 1111, so that the negative electrode potential of the first color light-emitting device 1111 can be reduced in advance to enable the first color to emit light.
  • the device 1111 is in a critical state of lighting, so that the first color light-emitting device 1111 can quickly switch from the off state (ie, off state ZT-off) to the light-emitting state (ie, on state ZT-on) at the beginning of the working period, and then The actual time that the first color light-emitting device 1111 is in the light-emitting state (ie, on state ZT-on) can be made as consistent as possible with the theoretical value.
  • the driving element 112 can adjust the potential of the negative electrode of the second color light-emitting device 1112 before the working period of the second color light-emitting device 1112, so that the negative electrode potential of the second color light-emitting device 1112 can be reduced in advance to enable the second color light-emitting device 1112 to operate.
  • the driving element 112 can adjust the potential of the negative electrode of the third color light-emitting device 1113 before the working period of the third color light-emitting device 1113, so that the negative electrode potential of the third color light-emitting device 1113 can be reduced in advance to enable the third color light-emitting device 1113 to operate.
  • any one of the plurality of driving elements can control the second end of the device group coupled to it to conduct with its reference voltage end for a first compensation time before the working period, so as to adopt The reference voltage loaded on the reference voltage terminal adjusts the potential of the second terminal of the device group coupled thereto within the first compensation time.
  • the driving element 112 may drive the first phase of the control signal PWM1 before the working period of the first color light-emitting device 1111 (for example, within one display subframe F1_1 ).
  • the negative electrode of the first color light-emitting device 1111 is connected to the reference voltage terminal O6 for the first compensation time ts1, so that the reference voltage VSS loaded by the reference voltage terminal O6 is used to adjust the first compensation time ts1.
  • the negative electrode of the second color light-emitting device 1112 is connected to the reference voltage terminal O6 for a first compensation time, so as to use the reference voltage loaded by the reference voltage terminal O6, in the first
  • the potential of the negative electrode of the second color light-emitting device 1112 is adjusted during the compensation time.
  • the negative electrode of the third color light-emitting device 1113 is connected to the reference voltage terminal O6 for a first compensation time, so as to use the reference voltage loaded by the reference voltage terminal O6, in the first
  • the potential of the negative electrode of the third color light-emitting device 1113 is adjusted within the compensation time.
  • any one of the plurality of driving elements can control the positive signal line at least in sequence through the device group coupled to the driving element and the output end of the driving element at the end of the first compensation time.
  • the reference voltage terminal form an electrical circuit.
  • the driving element 112 can control the first positive electrode at the end of the first compensation time ts1 during which the negative electrode of the first color light-emitting device 1111 is connected to the reference voltage terminal O6
  • the signal line Van, the first color light-emitting device 1111, the output terminal O1 and the reference voltage terminal O6 form an electrical circuit.
  • the second positive signal line, the second color light-emitting device 1112, the output terminal O2 and the reference voltage terminal O6 are controlled to form Electrical circuit.
  • the second positive electrode signal line, the third color light-emitting device 1113, the output terminal O3 and the reference voltage terminal O6 are controlled to form Electrical circuit.
  • any one of the plurality of driving elements can control the second end of the device group coupled to it to conduct with its reference voltage end for a second compensation time within the working time period.
  • the driving element 112 can be within the working time period of the first color light-emitting device 1111 (for example, in a display sub-display).
  • the frame F1_1 within any valid level period of the drive control signal PWM1 (for example, within the first valid level period of the drive control signal PWM1), connect the negative electrode of the first color light-emitting device 1111 to the reference voltage terminal O6.
  • the reference voltage loaded on the reference voltage terminal O6 is used to adjust the potential of the negative electrode of the first color light-emitting device 1111 within the second compensation time ts2.
  • the first compensation time and the second compensation time may be sequentially consecutive time periods.
  • the first compensation time ts1 and the second compensation time ts2 corresponding to the first color light-emitting device 1111 are consecutive time periods.
  • the first compensation time and the second compensation time corresponding to the second color light-emitting device 1112 are consecutive time periods.
  • the first compensation time and the second compensation time corresponding to the third color light-emitting device 1113 are consecutive time periods.
  • the device group includes multiple devices (for example, light-emitting devices).
  • the second end of the device group may include negative electrodes of multiple light-emitting devices, and the negative electrode of each light-emitting device is connected to a different output end of the same driving element. connection, then the first compensation time and/or the second compensation time corresponding to each light-emitting device are different, so that the potential of the negative electrode of different light-emitting devices can be accurately adjusted.
  • At least one of the multiple device groups is A device group, the second compensation time corresponding to the device group is smaller than the first compensation time.
  • the second compensation time corresponding to each device in the device group can be made smaller than the first compensation time.
  • the second compensation time corresponding to each light-emitting device can be made smaller than the first compensation time.
  • the second compensation time is less than half of the first compensation time.
  • At least two device groups among multiple device groups respectively correspond to different first compensation times and/or second compensation times; multiple devices belonging to the same device group are implemented For specific gray levels, they may respectively correspond to different first compensation times and/or second compensation times.
  • a device group includes a first color light-emitting device 1111, a second color light-emitting device 1112 and a third color light-emitting device 1113.
  • the first compensation time corresponding to the first color light-emitting device 1111 is 60 ns
  • the second color light-emitting device 1112 corresponds to The first compensation time is 35 ns
  • the first compensation time corresponding to the third color light-emitting device 1113 is 8 ns
  • the second compensation time corresponding to the first color light-emitting device 1111 can be 10 ns
  • the second compensation time corresponding to the second color light-emitting device 1112 can be 10 ns.
  • the compensation time may be 5 ns
  • the second compensation time corresponding to the third color light-emitting device 1113 may be 2 ns.
  • the second compensation time corresponding to at least some device groups among multiple device groups may also be made the same.
  • the second compensation time corresponding to at least part of the device group can be set to 1 ns, which can reduce the design difficulty of the second compensation time.
  • any one of the plurality of driving elements 112 can control the second end of the device group coupled to it according to the pre-stored potential compensation time corresponding to the device group coupled to it.
  • the potential compensation time is the first compensation time.
  • the following description takes the potential compensation time as the sum of the first compensation time and the second compensation time as an example. When the potential compensation time is the first compensation time, the working process can be deduced in this way and will not be described again here.
  • the first compensation time ts1 since the potential of the negative electrode of the light-emitting device is adjusted before it emits light, the parasitic capacitance of the light-emitting device is discharged in advance. However, it is necessary to avoid adjusting the potential of the negative electrode of the light-emitting device in advance, causing the light-emitting device to be inactive. time period to emit light, therefore, the first compensation time ts1 has a maximum value ts1-max. During specific implementation, the first compensation time ts1 should not exceed the maximum value ts1-max. For example, according to the formula: Determine the maximum value ts1-max of the first compensation time ts1.
  • V + represents the voltage of the positive electrode of the light-emitting device
  • V F represents the turn-on voltage of the light-emitting device
  • V s represents the voltage of the negative electrode of the light-emitting device before the start of the first compensation time ts1
  • R LED represents the equivalent resistance of the light-emitting device itself.
  • C LED represents the capacitance of the parasitic capacitance of the light-emitting device itself.
  • the voltage of the positive electrode of the first color light-emitting device is VLED1
  • V + VLED1
  • V F represents the turn-on voltage of the first color light-emitting device
  • V s represents the voltage of the negative electrode of the first color light-emitting device before the start of the first compensation time ts1
  • R LED represents the resistance of its own equivalent resistance of the first color light-emitting device
  • C LED represents its own parasitic capacitance of the first color light-emitting device.
  • Capacitance value; substituted into the above formula, the maximum value of the first compensation time ts1 corresponding to the first color light-emitting device can be determined.
  • the maximum value of the first compensation time ts1 of the other light-emitting devices is calculated in the same way and will not be described again here.
  • the processing control circuit 1122 may also generate a potential adjustment control signal according to the potential compensation time during the light emission period, and send the potential adjustment control signal to the data driving circuit.
  • the data drive circuit can control the second end of the corresponding device group to conduct with its reference voltage end according to the effective level of the received potential adjustment control signal; wherein, the effective level duration of the potential adjustment control signal corresponding to the device group is the potential Compensation time.
  • the processing control circuit 1122 can also generate the potential adjustment control signal OVS1 according to the potential compensation time ts corresponding to the output terminal O1 during the light-emitting period, and control the potential adjustment.
  • the signal OVS1 is sent to the data driving circuit 1121.
  • the data driving circuit 1121 can adjust the effective level (for example, high level) of the control signal OVS1 according to the received potential, and control the negative electrode of the first color light-emitting device 1111 to be conductive with its reference voltage terminal O6.
  • the processing control circuit 1122 can also generate the potential adjustment control signal OVS2 according to the potential compensation time corresponding to the output terminal O2 during the light-emitting period, and send the potential adjustment control signal OVS2 to the data driving circuit 1121.
  • the data driving circuit 1121 can adjust the effective level (eg high level) of the control signal OVS2 according to the received potential, and control the negative electrode of the second color light-emitting device 1112 to be conductive with its reference voltage terminal O6.
  • the processing control circuit 1122 can also generate the potential adjustment control signal OVS3 according to the potential compensation time corresponding to the output terminal O3 during the light-emitting period, and send the potential adjustment control signal OVS3 to the data driving circuit 1121.
  • the data driving circuit 1121 can adjust the effective level (eg high level) of the control signal OVS3 according to the received potential, and control the negative electrode of the third color light-emitting device 1113 to be conductive with its reference voltage terminal O6.
  • the data driving sub-circuit when the data driving circuit includes a data driving sub-circuit, can receive the potential adjustment control signal output by the processing control circuit 1122 and control the coupled device group in response to the potential adjustment control signal.
  • the second terminal is connected to its reference voltage terminal.
  • the data driving sub-circuit 11211 can receive the potential adjustment control signal OVS1, and in response to the effective level (for example, high level) of the potential adjustment control signal OVS1, control the first
  • the negative electrode of a color light-emitting device 1111 is connected to its reference voltage terminal O6.
  • the data driving subcircuit 11212 may receive the potential adjustment control signal OVS2, and in response to the effective level (eg, high level) of the potential adjustment control signal OVS2, control the negative electrode of the second color light-emitting device 1112 to conduct with its reference voltage terminal O6.
  • the data driving sub-circuit 11213 may receive the potential adjustment control signal OVS3, and in response to the effective level (eg high level) of the potential adjustment control signal OVS3, control the negative electrode of the third color light-emitting device 1113 to conduct with its reference voltage terminal O6.
  • the data driving sub-circuit may further include: a potential adjustment circuit, which is coupled to the processing control circuit and the corresponding output terminal respectively. Furthermore, the potential adjustment circuit can receive the potential adjustment control signal of the corresponding device group, and control the second end of the coupled device group to conduct with its reference voltage end according to the received potential adjustment control signal.
  • the data driving sub-circuit 11211 includes: a potential adjustment circuit 112113, and the potential adjustment circuit 112113 can receive the potential adjustment control signal OVS1 and respond to the potential adjustment control signal OVS1. The effective level can connect the negative electrode of the first color light-emitting device 1111 to the reference voltage terminal O6.
  • the data driving subcircuit 11212 includes: a potential adjustment circuit 112123, and the potential adjustment circuit 112123 can receive the potential adjustment control signal OVS2, and in response to the effective level of the potential adjustment control signal OVS2, can connect the negative electrode of the second color light-emitting device 1112 to the reference Voltage terminal O6 is turned on.
  • the data driving sub-circuit 11213 includes: a potential adjustment circuit 112133, and the potential adjustment circuit 112133 can receive the potential adjustment control signal OVS3, and in response to the effective level of the potential adjustment control signal OVS3, can connect the negative electrode of the third color light-emitting device 1113 to the reference Voltage terminal O6 is turned on.
  • the potential adjustment circuit may include switching elements, such as metal-oxide semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), thin film field-effect transistor (Thin Film Transistor, TFT) and other transistors.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • TFT Thin Film Transistor
  • the specific implementation of the potential adjustment circuit can be determined according to the needs of the actual application, and is not limited here.
  • the processing control circuit 1122 may include: a processor 11221 and a control circuit 11222.
  • the processor 11221 can generate drive control signals corresponding to each device group coupled thereto according to the received pixel data information Rda, Gda, and Bda and send them to the data drive subcircuit corresponding to each device group; the processor 11221 also According to the received pixel data information and the pre-stored potential compensation time corresponding to each device group, current amplitude control information and potential adjustment information corresponding to each device group coupled thereto can be generated and provided to the control circuit 11222.
  • control circuit 11222 can generate the current control signal in the lighting control signal corresponding to each device group according to the received current amplitude control information corresponding to each device group, and according to the received potential adjustment information corresponding to each device group, Generate potential adjustment control signals corresponding to each device group, and send the generated current control signals and potential adjustment control signals corresponding to each device group to the data drive subcircuit corresponding to each device group.
  • the processor 11221 can generate the drive control signal PWM1 and current amplitude control information corresponding to the first color light-emitting device 1111 according to the received pixel data information Rda, and According to the pre-stored potential compensation time corresponding to the first color light-emitting device 1111, the potential adjustment information corresponding to the first color light-emitting device 1111 is generated; the processor 11221 can generate the corresponding potential adjustment information of the second color light-emitting device 1112 according to the received pixel data information Gda.
  • the drive control signal PWM2 and current amplitude control information and based on the pre-stored potential compensation time corresponding to the second color light-emitting device 1112, generate the potential adjustment information corresponding to the second color light-emitting device 1112; the processor 11221 can generate the potential adjustment information corresponding to the second color light-emitting device 1112 according to the received
  • the pixel data information Bda generates the drive control signal PWM3 and current amplitude control information corresponding to the third color light-emitting device 1113, and generates the corresponding driving control signal PWM3 and current amplitude control information corresponding to the third color light-emitting device 1113 according to the pre-stored potential compensation time corresponding to the third color light-emitting device 1113. potential adjustment information.
  • the processor 11221 sends the drive control signal PWM1 to the data drive sub-circuit 11211, the drive control signal PWM2 to the data drive sub-circuit 11212, and the drive control signal PWM3 to the data drive sub-circuit 11213.
  • the current amplitude control information and potential adjustment information corresponding to each color light-emitting device are sent to the control circuit 11222.
  • the control circuit 11222 may generate current control signals DAC1, DAC2, and DAC3 according to the current amplitude control information. And, generating potential adjustment control signals OVS1, OVS2, and OVS3 based on the potential adjustment information.
  • control circuit 11222 can send the current control signal DAC1 and the potential adjustment control signal OVS1 to the data driving subcircuit 11211, send the current control signal DAC2 and the potential adjustment control signal OVS2 to the data driving subcircuit 11212, and send the current control signal DAC3 and The potential adjustment control signal OVS3 is sent to the data driving sub-circuit 11213.
  • the potential adjustment circuit 112113 in the data driving subcircuit 11211 can receive the potential adjustment control signal OVS1, and in response to the effective level of the potential adjustment control signal OVS1, can connect the negative electrode of the first color light-emitting device 1111 to the reference voltage terminal O6.
  • the constant current source circuit 112112 can receive the current control signal DAC1 corresponding to the first color light-emitting device 1111, and according to the received current control signal DAC1, output a constant amplitude current IL1 corresponding to the current control signal DAC1.
  • the modulation circuit 112111 can receive the drive control signal PWM1 corresponding to the first color light-emitting device 1111, and input the current IL1 generated by the constant current source circuit 112112 into the coupling according to the effective level (for example, high level) of the received drive control signal PWM1.
  • the connected output terminal O1 is used to control the first positive signal line to form an electrical circuit through at least the first color light-emitting device 1111, the output terminal O1 of the driving element 112, and the reference voltage terminal O6 during the working period, so that the first color emits light.
  • Device 1111 emits light. In this way, the emission brightness and time of the first color light-emitting device 1111 within the display sub-frame can be controlled through the combination of the drive control signal PWM1, the current control signal DAC1 and the potential adjustment control signal OVS1.
  • the potential adjustment circuit 112123 in the data driving subcircuit 11212 can receive the potential adjustment control signal OVS2, and in response to the effective level of the potential adjustment control signal OVS2, can connect the negative electrode of the second color light-emitting device 1112 to the reference voltage terminal O6.
  • the constant current source circuit 112122 may receive the current control signal DAC2 corresponding to the second color light-emitting device 1112, and according to the received current control signal DAC2, output a current IL2 of constant amplitude corresponding to the current control signal DAC2.
  • the modulation circuit 112121 can receive the drive control signal PWM2 corresponding to the second color light-emitting device 1112, and input the current IL2 generated by the constant current source circuit 112122 into the coupling according to the effective level (for example, high level) of the received drive control signal PWM2.
  • the connected output terminal O2 is used to control the second positive signal line to form an electrical circuit through at least the second color light-emitting device 1112, the output terminal O2 of the driving element 112, and the reference voltage terminal O6 during the working period, so that the second color emits light.
  • Device 1112 emits light. That is to say, within the duration of the effective level of the driving control signal PWM2, the second color light-emitting device 1112 can be regarded as being in the working period.
  • the driving control signal PWM2, the current control signal DAC2 and the current control signal DAC2 can be combined with each other to control the lighting brightness and time of the second color light-emitting device 1112 within the display sub-frame.
  • the potential adjustment circuit 112133 in the data driving sub-circuit 11213 can receive the potential adjustment control signal OVS3, and in response to the effective level of the potential adjustment control signal OVS3, can connect the negative electrode of the third color light-emitting device 1113 to the reference voltage terminal O6.
  • the constant current source circuit 112132 can receive the current control signal DAC3 corresponding to the third color light-emitting device 1113, and according to the received current control signal DAC3, output a current IL3 of a constant amplitude corresponding to the current control signal DAC3.
  • the modulation circuit 112131 can receive the drive control signal PWM3 corresponding to the third color light-emitting device 1113, and input the current IL3 generated by the constant current source circuit 112132 into the coupling according to the effective level (for example, high level) of the received drive control signal PWM3.
  • the connected output terminal O3 is used to control the second positive signal line to form an electrical circuit through at least the third color light-emitting device 1113, the output terminal O3 of the driving element 112, and the reference voltage terminal O6 during the working period, so that the third color emits light.
  • Device 1113 emits light. That is to say, within the duration of the effective level of the driving control signal PWM3, the third color light-emitting device 1113 can be regarded as being in the working period. In this way, the driving control signal PWM3, the current control signal DAC3 and the current control signal DAC3 can be combined with each other to control the lighting brightness and time of the third color light-emitting device 1113 within the display sub-frame.
  • the potential compensation time may be stored in the processor 11221.
  • the control circuit may store the potential compensation time of the device group corresponding to each driving element 112 coupled thereto.
  • the system circuit stores the potential compensation time of the device group corresponding to each driving element 112 coupled thereto.
  • the driving element 112 can receive and store the potential compensation time sent by the system circuit when the electronic device is turned on, and clear the stored potential compensation time when the electronic device is turned off.
  • the system circuit can send the potential compensation time of the device group corresponding to each driving element 112 to each driving element 112 in the display frame F0.
  • the driving element 112 receives and stores the potential compensation sent by the system circuit in the display frame F0. time.
  • each driving element 112 may further include: at least one of an interface circuit 1123 , a reference voltage circuit 1124 , a decoder circuit 1125 , a voltage stabilizing circuit 1126 and an electrostatic protection circuit 1127 A sort of.
  • the reference voltage circuit 1124 can determine a fixed reference voltage.
  • the electrostatic protection circuit 1127 can be coupled to the addressing signal terminal O5 and the reference voltage terminal O6 respectively, so that the supply voltage VCC input to the addressing signal terminal O5 and the reference voltage VSS input to the reference voltage terminal O6 can be protected against static electricity.
  • the voltage stabilizing circuit 1126 may be coupled to the addressing signal terminal O5 and may regulate the supply voltage VCC input to the addressing signal terminal O5.
  • the decoder circuit 1125 can identify the address carried by the driving data sent by the logic control circuit. When the corresponding address is identified, it outputs a data reception signal to the interface circuit 1123 coupled to the driving signal terminal O4. After receiving the data reception signal, the interface circuit 1123 receives the driving data, decodes the received driving data, and provides it to the processing control circuit 1122, so that the processing control circuit 1122 generates a light emission control signal based on the driving data.
  • the driving element 112 may receive the supply voltage VCC through the addressing signal terminal O5, and input the received supply voltage VCC into the interface circuit 1123.
  • the interface circuit 1123 can decode the received power supply voltage and provide it to the processing control circuit 1122 and the data driving circuit 1121 to supply power to the processing control circuit 1122 and the data driving circuit 1121 .
  • the interface circuit 1123 may decode the received power supply voltage and provide it to the reference voltage circuit.
  • the reference voltage circuit can generate a reference reference voltage based on the received supply voltage.
  • the driving data can be decoded through the interface circuit 1123 and then provided to the processor 11221 in the processing control circuit 1122, so that the processor 11221 generates a driving control signal and a current control signal according to the decoded driving data.
  • the light emission period is taken as the display subframe as an example.
  • the display frame F0 may not display any picture, for example, a black picture is displayed.
  • the t0 phase, the t1 phase, and the t2 phase are executed in sequence. Among them, the processes of the t0 stage and the t1 stage can be described above and will not be described in detail here.
  • the 16-bit reserved control instruction bits P2+P3 and/or the 16-bit reserved control instruction bits P4+P5 in the current setting information Co may carry the first color light-emitting device 1111 and the second color light-emitting device.
  • the device 1112 and the third color light-emitting device 1113 have corresponding potential compensation times respectively. This allows the processor 11221 to store the received potential compensation time.
  • the above potential compensation time may be detected and determined before the electronic device leaves the factory.
  • the method for determining the potential compensation time may be: controlling the brightness of each light-emitting device in the display panel to present a specific gray level (a preset gray level, for example, a low gray level), and using a camera to By taking photos of the display panel, the original brightness data of each part of the display panel can be collected, and the original brightness of the same specific gray scale presented by each light-emitting device is divided into multiple intervals, and each interval is mapped to a potential compensation time. relation.
  • a specific gray level a preset gray level, for example, a low gray level
  • the corresponding interval can be found based on the original brightness data corresponding to each light-emitting device, and then the potential compensation time corresponding to each light-emitting device can be determined.
  • the original brightness presented by each light-emitting device can be divided into eight intervals: L0-L1, L1-L2, L2-L3, L3-L4, L4-L5, L5-L6, L6-L7, L7-L8.
  • the brightness range L0-L1 corresponds to the potential compensation time 0ns
  • the brightness range L1-L2 corresponds to the potential compensation time 5ns
  • the brightness range L2-L3 corresponds to the potential compensation time 10ns
  • the brightness range L3-L4 corresponds to the potential compensation time 20ns
  • the brightness range L4-L5 corresponds to The potential compensation time is 40ns
  • the brightness range L5-L6 corresponds to the potential compensation time 50ns
  • the brightness range L6-L7 corresponds to the potential compensation time 60ns
  • the brightness range L7-L8 corresponds to the potential compensation time 70ns.
  • the corresponding brightness of the original brightness data when the light-emitting device displays a specific gray scale is in the L6-L7 range, it can be determined that the corresponding potential compensation time of the light-emitting device when displaying a specific gray scale is 60 ns.
  • the determined potential compensation time corresponding to each light-emitting device when displaying a specific gray scale is stored, for example, in the system circuit 300 .
  • Embodiments of the present disclosure also provide a display driving method, which can be applied to the above-mentioned electronic equipment, and the display driving method can include: controlling the positive signal line and the reference voltage terminal of the driving element within the working period of a light-emitting cycle. Form an electrical circuit. Wherein, before the working period of the light-emitting cycle, the potential of the second end of the device group coupled to the driving element is adjusted.
  • the working principle and specific implementation of the display driving method are basically the same as the working principle and specific implementation of the electronic device in the above embodiment. Therefore, the working method of the display driving method can be referred to the electronic device in the above embodiment. The specific implementation method is implemented and will not be described again here.
  • embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions
  • the device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.
  • These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device.
  • Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

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Abstract

本公开实施例提供的电子设备及显示驱动方法，包括：多个器件组和多个驱动元件；多个器件组中的至少一个器件组的第一端与正极信号线耦接，多个器件组中的至少一个器件组的第二端与多个驱动元件中的任一个驱动元件的输出端耦接，多个驱动元件中的任一个驱动元件的参考电压端被配置为与参考信号线耦接；多个驱动元件中的任一个驱动元件被配置为：控制正极信号线与其参考电压端在一个发光周期的工作时间段内形成电气回路；以及，在发光周期的工作时间段之前，调节与其耦接的器件组的第二端的电位。

Description

电子设备及显示驱动方法 技术领域
本公开涉及发光技术领域，特别涉及电子设备及显示驱动方法。
背景技术
发光二极管(Light-Emitting Diode，LED)显示是指将传统LED阵列化、微缩化后定址巨量转移到电路基板上，形成超小间距LED，将毫米级别的LED长度进一步微缩到微米级，以达到超高像素、超高解析率，理论上能够适应各种尺寸屏幕的技术。
发明内容
本公开实施例提供的电子设备，包括：
多个器件组和多个驱动元件；
所述多个器件组中的至少一个器件组的第一端与正极信号线耦接，所述多个器件组中的至少一个器件组的第二端与所述多个驱动元件中的任一个驱动元件的输出端耦接，所述多个驱动元件中的任一个驱动元件的参考电压端被配置为与参考信号线耦接；
所述多个驱动元件中的任一个驱动元件被配置为：控制所述正极信号线与其参考电压端在一个发光周期的工作时间段内形成电气回路；以及，在所述发光周期的工作时间段之前，调节与其耦接的器件组的第二端的电位。
在一些示例中，所述多个驱动元件中的任一个驱动元件进一步被配置为：在所述工作时间段之前，控制与其耦接的所述器件组的第二端与其参考电压端导通第一补偿时间。
在一些示例中，所述多个驱动元件中的任一个驱动元件进一步被配置为：在所述第一补偿时间的结束时刻，控制所述正极信号线至少依次经由与所述驱动元件耦接的器件组、所述驱动元件的输出端、以及所述参考电压端形成 电气回路。
在一些示例中，所述多个驱动元件中的任一个驱动元件还被配置为：在所述工作时间段之内，控制与其耦接的所述器件组的第二端与其参考电压端导通第二补偿时间。
在一些示例中，所述第一补偿时间和所述第二补偿时间为依次连续的时间段。
在一些示例中，对于所述多个器件组中的至少一个器件组，所述器件组对应的所述第二补偿时间小于所述第一补偿时间。
在一些示例中，对于所述多个器件组中的至少一个器件组，所述器件组对应的所述第二补偿时间小于所述第一补偿时间的一半。
在一些示例中，所述至少一个器件组包括多个器件；
所述多个器件中的每个器件一一对应有所述第一补偿时间和所述第二补偿时间，且所述多个器件中的每个器件对应的所述第二补偿时间小于所述第一补偿时间的一半。
在一些示例中，所述多个器件中的至少两个器件，其分别对应不同的第一补偿时间；其中，第一补偿时间相对更大的，其对应的第二补偿时间相对更大。
在一些示例中，所述多个器件中的至少部分所述器件对应的所述第二补偿时间相同。
在一些示例中，所述多个驱动元件中的任一个驱动元件进一步被配置为：根据预先存储的与其耦接的器件组对应的电位补偿时间，控制与其耦接的所述器件组的第二端与其参考电压端导通所述电位补偿时间；其中，所述电位补偿时间为所述第一补偿时间；或者，所述电位补偿时间为所述第一补偿时间和所述第二补偿时间之和。
在一些示例中，所述多个驱动元件中的任一个所述驱动元件包括：处理控制电路以及数据驱动电路；所述数据驱动电路分别与所述处理控制电路、所述输出端以及所述参考电压端耦接；
所述处理控制电路被配置为在所述发光周期内，生成发光控制信号，并将所述发光控制信号发送给所述数据驱动电路；以及，根据所述电位补偿时间，生成电位调节控制信号，并将所述电位调节控制信号发送给所述数据驱动电路；
所述数据驱动电路被配置为在所述发光周期内，根据接收到的所述发光控制信号，控制所述正极信号线依次经由与所述驱动元件耦接的器件组、所述驱动元件的输出端、以及参考电压端形成电气回路；以及根据接收到的电位调节控制信号的有效电平，控制对应的所述器件组的第二端与其参考电压端导通；其中，所述器件组对应的所述电位调节控制信号的有效电平时长为所述电位补偿时间。
在一些示例中，所述数据驱动电路包括：至少一个数据驱动子电路；一个所述数据驱动子电路与一个所述输出端耦接；
所述数据驱动子电路被配置为接收耦接的所述器件组对应的发光控制信号和电位调节控制信号，以及，响应于所述发光控制信号控制所述正极信号线依次经由与所述驱动元件耦接的器件组、所述驱动元件的输出端、以及参考电压端形成电气回路；以及响应于所述电位调节控制信号，控制耦接的所述器件组的第二端与其参考电压端导通。
在一些示例中，所述发光控制信号包括驱动控制信号和电流控制信号；
所述数据驱动子电路包括：调制电路、恒流源电路以及电位调节电路；其中，所述恒流源电路分别与所述处理控制电路以及所述调制电路耦接，所述调制电路与对应的输出端耦接；所述电位调节电路分别与所述处理控制电路以及对应的输出端耦接；
所述恒流源电路被配置为接收对应的器件组的电流控制信号，并根据接收到的所述电流控制信号，输出对应所述电流控制信号的恒定幅值的电流；
所述调制电路被配置为接收对应的器件组的驱动控制信号，并根据接收到的所述驱动控制信号的有效电平，将所述恒流源电路产生的电流输入耦接的所述输出端，以在所述工作时间段内控制所述正极信号线至少依次经由与 所述驱动元件耦接的器件组、所述驱动元件的输出端、以及参考电压端形成电气回路；
所述电位调节电路被配置为接收对应的器件组的电位调节控制信号，并根据接收到的所述电位调节控制信号控制耦接的所述器件组的第二端与其参考电压端导通。
在一些示例中，所述电子设备还包括：控制电路；所述控制电路分别与所述多个驱动元件耦接；
所述控制电路被配置为存储有的耦接的各所述驱动元件对应的所述器件组的电位补偿时间；以及，在所述电子设备开机时，将各所述驱动元件对应的所述器件组的电位补偿时间发送给各所述驱动元件；
所述驱动元件被配置为在所述电子设备开机时，接收并存储系统电路发送的电位补偿时间；并在所述电子设备关机时，清空存储的所述电位补偿时间。
在一些示例中，所述多个驱动元件中的任一个驱动元件的驱动信号端被配置为与驱动信号线耦接；
所述控制电路还被配置为与所述驱动信号线耦接，并且存储有耦接的各所述驱动元件的地址；以及向所述驱动信号线传输携带有对应所述驱动元件的地址的驱动数据；
所述驱动元件还被配置为在识别到所述驱动数据中对应的地址时，接收所述驱动数据，并根据所述驱动数据生成所述发光控制信号。
在一些示例中，所述多个驱动元件中的任一个驱动元件的寻址信号端被配置为与选址信号线耦接；
所述控制电路还被配置为与所述选址信号线耦接，并向所述选址信号线输入供电电压；
所述驱动元件还被配置为通过所述寻址信号端接收所述供电电压。
本公开实施例提供的显示驱动方法，应用于电子设备，所述电子设备包括多个器件组和多个驱动元件；
所述显示驱动方法包括：
控制所述正极信号线与其参考电压端在一个发光周期的工作时间段内形成电气回路；
其中，在所述发光周期的工作时间段之前，调节与其耦接的器件组的第二端的电位。
附图说明
图1为本公开实施例提供的电子设备的一些结构示意图；
图2为本公开实施例提供的显示面板的一些结构示意图；
图3为本公开实施例提供的显示面板的一些局部结构示意图；
图4为本公开实施例提供的显示面板的另一些局部结构示意图；
图5为本公开实施例提供的显示面板的又一些局部结构示意图；
图6为本公开实施例提供的显示面板的一些布局结构示意图；
图7为图6所示的布局结构示意图中沿AA’方向上的剖视结构示意图；
图8为本公开实施例提供的电子设备的另一些结构示意图；
图9为本公开实施例提供的一些信号时序图；
图10为本公开实施例提供的另一些信号时序图；
图11为本公开实施例提供的又一些信号时序图；
图12为本公开实施例提供的又一些信号时序图；
图13为本公开实施例提供的驱动元件的一些结构示意图；
图14为本公开实施例提供的驱动元件的一些局部结构示意图；
图15为本公开实施例提供的驱动元件的另一些局部结构示意图；
图16为本公开实施例提供的又一些信号时序图；
图17为本公开实施例提供的又一些信号时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公 开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
在具体实施时，在本公开实施例中，电子设备可以为显示装置，则功能单元为像素单元。示例性地，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
如图1所示，电子设备包括阵列排布的多个驱动元件，排列成M行N列。例如，在N＝4，M＝4时，多个驱动元件可以排列成4行4列，根据各驱动元件在衬底基板上的物理位置将其标记为：A(1，1)、A(1，2)、A(1，3)、A(1，4)、A(2，1)、A(2，2)、A(2，3)、A(2，4)、A(3，1)、A(3，2)、A(3，3)、A(3，4)、A(4，1)、A(4，2)、A(4，3)、A(4，4)。需要说明的是，图1仅是对驱动元件在衬底基板上的位置进行了一种可能的示意。在实际应用中，驱动元件的数量(即N和M的具体数值)可以根据实 际应用中的需求进行确定，在此不作限定。
在本公开一些实施例中，电子设备还包括多个器件组，一个器件组的第一端可以与正极信号线耦接，该器件组的第二端可以与一个驱动元件112的输出端耦接。如图2至图4所示，一个器件组ZL和一个驱动元件112构成一个功能单元P，并且，每一个功能单元P中，器件组ZL的第一端与正极信号线耦接，器件组ZL的第二*端与驱动元件112的输出端耦接。如图5所示，四个器件组ZL_1～ZL_4和一/个驱动元件112构成一个功能单元P，并且，每一个功能单元P中，器件组74/8ZL_1～ZL_4的第一端与正极信号线耦接，器件组ZL_1～ZL_4的第二端分别与74/8驱动元件112的不同输出端耦接。本公开对每一个功能单元中的器件组/的数量不作限定。
在本公开一些实施例中，一个器件组包括至少一个器件。例如，一个器件组包括多个器件。示例性地，该器件可以设置为发光器件，则一个器件组可以包括至少一个发光器件。示例性地，器件组的第一端可以为发光器件的正极，第二端可以为至少一个发光器件的负极。例如，如图2至图5所示，每一个器件组可以包括三个发光器件(如1111～1113)。当然，在实际应用中，器件组中器件的功能类型、具体数量，可以根据实际应用的需求进行确定，在此不作限定。下面以每一个器件组可以包括三个发光器件为例进行说明。
在本公开一些实施例中，一个器件组ZL包括多个器件，在一个驱动元件控制一个器件组的情况下，驱动元件112的输出端的数量可以与器件组ZL中器件的数量相同。示例性地，如图2与3所示，一个器件组ZL包括三个发光器件，则驱动元件112可以具有三个输出端，并且，一个输出端与一个子像素中的发光器件的负极耦接。当然，也不限于此。示例性地，如图4所示，一个器件组ZL包括六个发光器件，但六个发光器件分成三组，每组中的两个发光器件并联连接，每组一一对应设置于一个子像素中，则驱动元件112依然可以仅具有三个输出端，并且，一个输出端与存在并联关系的两个发光器件的负极同时耦接。
在本公开一些实施例中，在一个驱动元件控制多个器件组的情况下，驱 动元件112的输出端的数量可以与多个器件组ZL中所有器件的数量相关。示例性地，如图5所示，一个驱动元件控制四个器件组ZL_1～ZL_4，每个器件组包括三个发光器件，那么驱动元件112具有12个输出端，并且，一个输出端与一个发光器件的负极耦接。
在本公开一些实施例中，如图2所示，显示面板中还可以包括：多条第一正极信号线Va1……Van……VaN(1≤n≤N，n为整数)、多条第二正极信号线Vb1……Vbn……VbN、多条参考信号线G1……Gn……GN、多条选址信号线S1……Sm……SM(1≤m≤M，m为整数)、多条选址信号转接线Q1……Qm……QM、多条驱动信号线D1……Dn……DN以及多条辅助信号线W1……Wm……WM。示例性地，可以使一列功能单元P对应多条第一正极信号线至少一条第一正极信号线、多条第二正极信号线中的至少一条第二正极信号线，多条参考信号线中的至少一条参考信号线以及多条驱动信号线中的至少一条驱动信号线。并且，可以使一行功能单元P对应多条选址信号线中的至少一条选址信号线，多条辅助信号线中的至少一条辅助信号线以及多条选址信号转接线中的至少一条选址信号转接线。例如，可以使该一列功能单元P对应一条第一正极信号线、一条第二正极信号线，一条参考信号线以及一条驱动信号线。并且，可以使一行功能单元P对应一条选址信号线，一条辅助信号线以及一条选址信号转接线。可选地，各第一正极信号线、各第二正极信号线、各参考信号线以及各驱动信号线可以设置在相邻两个功能单元列之间的间隙中。各选址信号线，各辅助信号线以及各选址信号转接线可以设置在相邻两个功能单元行之间的间隙中。当然，在实际应用中，功能单元和上述信号线的对应方式，可以根据实际应用的需求进行确定，在此不作限定。
在本公开一些实施例中，如图2所示，每一条辅助信号线Wm可以与至少一条参考信号线Gn耦接，以降低参考信号线Gn的电阻，降低参考信号线Gn的压降，减小参考信号线Gn上的信号延迟。以及，各选址信号转接线Qm可以与选址信号线Sm一一对应设置。例如，每一条辅助信号线Wm可以与每一条参考信号线Gn耦接，选址信号转接线Q1与选址信号线S1对应耦接， 选址信号转接线Qm与选址信号线Sm对应耦接，选址信号转接线QM与选址信号线SM对应耦接。
在本公开一些实施例中，第一正极信号线Van上可以传输第一正极电压VLED1，第二正极信号线Vbn上可以传输第二正极电压VLED2，参考信号线Gn上可以传输参考电压VSS，选址信号线Sm上可以传输供电电压VCC和选址信息，驱动信号线Dn上可以传输驱动数据。
在本公开一些实施例中，如图2至图5所示，每个器件组可以包括三种不同颜色的发光器件(如第一颜色发光器件1111、第二颜色发光器件1112、第三颜色发光器件1113)。驱动元件112可以具有输出端O1～O3、驱动信号端O4、寻址信号端O5和参考电压端O6。其中，输出端O1与第一颜色发光器件1111的负极R-耦接，输出端O2与第二颜色发光器件1112的负极G-耦接，输出端O3与第三颜色发光器件1113的负极B-耦接，驱动信号端O4通过第一过孔p1与驱动信号线Dn耦接，寻址信号端O5与选址信号线Sm耦接，参考电压端O6通过第一过孔p2与参考信号线Gn耦接，且辅助信号线Vm通过第一过孔p5与参考信号线Gn耦接。第一颜色发光器件1111的正极R+与第一正极信号线Van耦接，第二颜色发光器件1112的正极G+通过第一过孔p4与第二正极信号线Vbn耦接，第三颜色发光器件1113的正极B+通过第一过孔p4与第二正极信号线Vbn耦接。选址信号线Sm通过第一过孔p3与选址信号转接线Qm耦接。需要说明的是，为了较清楚地突出各结构的连接关系，图6中只示意出了驱动元件112的端子(例如，O1～O6)和发光器件的正极和负极(例如R+、R-、G+、G-、B+、B-)，省略了驱动元件112以及发光器件的主体部分。
在本公开一些实施例中，第一颜色发光器件1111可以为红色发光器件，第二颜色发光器件1112可以为绿色发光器件，第三颜色发光器件1113可以为蓝色发光器件。在驱动红色发光器件、绿色发光器件以及蓝色发光器件发相同亮度的光时，红色发光器件的正极R+所需施加的电压通常大于绿色发光器件的正极G+所需施加的电压和蓝色发光器件的正极B+所需施加的电压。因 此，若将红色发光器件、绿色发光器件以及蓝色发光器件的正极均耦接同一条正极信号线，则该正极信号线上需要加载的电压会相对较大一些，这样不仅增加了功耗，还会使绿色发光器件以及蓝色发光器件的正极加载的电压过大，降低其使用寿命。因此，分别设置第一正极信号线Van和第二正极信号线Vbn，将红色发光器件的正极R+耦接第二正极信号线Vbn，将绿色发光器件的正极G+以及蓝色发光器件的正极B+耦接第一正极信号线Van。在实际应用中，可以将第二正极信号线Vbn上施加的第二正极电压VLED2高于第一正极信号线Van上施加的第一正极电压VLED1，不仅可以使红色发光器件能够实现其发光亮度，还可以降低功耗，改善绿色发光器件以及蓝色发光器件的使用寿命。
在一些示例中，结合图2、图3、图6以及图7所示，显示面板可以包括：衬底基板010、位于衬底基板010上的缓冲层011，位于缓冲层011背离衬底基板010一侧的第一金属层012，位于第一金属层012背离衬底基板010一侧的绝缘层013，位于绝缘层013背离衬底基板010一侧的第二金属层014，位于第二金属层014背离衬底基板010一侧的平坦层015，以及位于平坦层015背离衬底基板010一侧的钝化层016。并且，发光器件和驱动元件112设置于钝化层016远离衬底基板010的一侧。
在一些示例中，结合图2、图3、图6以及图7所示，第一金属层012可以包括相互间隔设置的多条第一正极信号线Van、多条第二正极信号线Vbn、多条参考信号线Gn、多条选址信号转接线Qm以及多条驱动信号线Dn。示例性地，多条第一正极信号线Va1、多条第二正极信号线Vb1、多条参考信号线Gn、多条选址信号转接线Qm以及多条驱动信号线Dn可以沿第一方向FS1排列，沿第二方向FS2延伸。示例性地，如图3所示，第二方向FS2与第一方向FS1垂直设置。在实际应用中，第二方向FS2可以为列方向，第一方向FS1可以为行方向。或者，第二方向FS2可以为行方向，第一方向FS1可以为的列方向。
示例性地，如图6与图7所示，第二金属层014可以包括多个第一电极 144、多个信号连接部141、多个连接焊盘142以及多个连接走线143。示例性地，可以使一个功能单元中设置多个第一电极144、一个信号连接部141、多个连接焊盘142以及多个连接走线143。并且，多个连接焊盘142可以用于连接发光器件和驱动元件112。需要说明的是，部分第一电极144可以通过第一过孔p2与参考信号线Gn耦接，部分第一电极144可以通过第一过孔p1与驱动信号线Dn耦接，部分第一电极144可以与选址信号线Sm耦接。
在一些实施例中，不同类型的信号线由于其传输的信号类型不同，故不同类型的信号线的线宽也不尽相同。若信号线沿第一方向FS1延伸，则信号线的宽度指信号线在垂直于其主体延伸方向(例如第二方向FS2)上的宽度。例如，如图6所示，参考信号线Gn的宽度大于数据线Dn的宽度。
示例性地，如图6与图7所示，平坦层015包括多个第二过孔a2，多个第二过孔a2贯穿平坦层015，以暴露出第二金属层014。钝化层016可以包括多个第三过孔a3，多个第三过孔a3贯穿至平坦层015。其中，一个第三过孔a3和一个第二过孔a2位置对应，形成由钝化层016贯穿至第二金属层014的连接焊盘142的贯穿过孔。例如，发光器件可以通过贯穿平坦层015和钝化层016的贯穿过孔与两个连接焊盘142连接，驱动元件112通过贯穿平坦层015和钝化层016的贯穿过孔与六个连接焊盘142连接，从而在信号线传输的信号以及驱动元件112的控制下，驱动发光器件发光。
示例性地，如图6与图7所示，发光器件的正极和负极以及驱动元件112的输出端至参考电压端O6可以通过焊接材料S(例如焊锡、锡银铜合金、锡铜合金等)与对应的连接焊盘142耦接。例如，驱动元件112的输出端O3可以通过焊接材料S与一个连接焊盘142耦接，第三颜色发光器件1113的负极B-也可以通过焊接材料S与一个连接焊盘142耦接，且耦接负极B-的连接焊盘142可以通过连接走线143与耦接参考电压端O6的连接焊盘142耦接。第三颜色发光器件1113的正极B+也可以通过焊接材料S与一个连接焊盘142耦接，耦接正极B+的连接焊盘142可以通过一个信号连接部141耦接，该信号连接部141可以通过第一过孔p4与第一正极信号线Va1耦接。以及，驱动 元件112的参考电压端O6也可以通过焊接材料S与一个连接焊盘142耦接，耦接参考电压端O6的连接焊盘142与一个第一电极144耦接，该第一电极144可以通过第一过孔p2与参考信号线Gn耦接。
示例性地，如图6与图7所示，每条第一正极信号线Van并不是各处具有相同宽度的信号线，为了方便信号线合理布局，在有些位置，第一正极信号线Van的宽度较宽，有些位置，第一正极信号线Van的宽度较窄。在本公开一些实施例中，第一正极信号线Van的宽度可以是第一正极信号线Van在其延伸方向(第一方向FS1)上的平均宽度，并且第一正极信号线Van在第一方向FS1上的平均宽度是指将第一正极信号线Van的各位置处的宽度加权求和得到的值。同理，第二正极信号线Vbn、参考信号线Gn、选址信号转接线Qn、驱动信号线Dn均有类似的特性。
示例性地，可以使参考信号线Gn的平均宽度L3大于第一正极信号线Van的平均宽度L2，或第二正极信号线Vbn的平均宽度L1，或选址信号转接线Qn的平均宽度L5，或驱动信号线Dn的平均宽度L4，在此不作限定。
在本公开一些实施例中，发光器件例如可以为迷你发光二极管(Mini LED)，也可以为微型发光二极管(Micro LED)。示例性地，该发光器件在衬底基板上的正投影可以呈四边形，其长边或宽边的尺寸可以在80μm-350μm之间取值。发光器件可以通过表面贴装技术(SMT)或巨量转移技术设于衬底基板上。
在本公开一些实施例中，电子设备还可以包括控制电路，该控制电路分别与多个驱动元件112中的每一个驱动元件112耦接。如图1所示，控制电路可以包括逻辑控制电路200以及系统电路300。系统电路300从电视网络接口等接收与显示画面相关的初始信号，对初始信号进行一系列渲染、解码处理生成图像信号，同时生成帧刷新信号FB，并在帧刷新信号FB的脉冲出现设定沿时，将图像信号输出给逻辑控制电路200。逻辑控制电路200接收来自系统电路300的图像信号，经过进一步转换处理后通过显示面板100中的各第一正极信号线Va1、各第二正极信号线Vb1、各参考信号线Gn、各选址信 号转接线Qm以及驱动信号线Dn向驱动元件或器件组输出对应的驱动信号。
示例性地，如图8所示，电子设备可以包括多个显示面板(如100_1、100_2)和多个逻辑控制电路(如200_1、200_2)。其中，一个显示面板对应一个逻辑控制电路，所有逻辑控制电路(如200_1、200_2)与一个系统电路300耦接。这样通过多个显示面板拼接，可以得到更大尺寸的显示面板。
在本公开一些实施例中，在帧刷新信号的脉冲出现设定沿时，系统电路300可以将对应的一个显示帧的图像信号发送给逻辑控制电路。示例性地，帧刷新信号的设定沿可以为下降沿。示例性地，如图9所示，FB代表帧刷新信号，该帧刷新信号FB具有多个脉冲，在每个脉冲的下降沿出现时，则将下一显示帧的图像信号发送给逻辑控制电路。并且，在每一个脉冲的下降沿出现时，系统电路300向逻辑控制电路输出对应显示帧的图像信号。例如，在该帧刷新信号FB的第一个脉冲的下降沿出现时，逻辑控制电路接收显示帧F1的图像信号。在该帧刷新信号FB的第二个脉冲的下降沿出现时，逻辑控制电路接收显示帧F2的图像信号。在该帧刷新信号FB的第三个脉冲的下降沿出现时，逻辑控制电路接收显示帧F3的图像信号。需要说明的是，帧刷新信号的设定沿也可以为上升沿，其实施方式可以参照帧刷新信号的设定沿为下降沿，在此不作赘述。
在本公开一些实施例中，每个显示帧又包括多个显示子帧，在一个显示帧内，逻辑控制电路以第一频率向驱动元件重复发送相同的驱动数据K次，第一频率即为帧刷新信号FB的频率与K的乘积。K的取值可以为32、64等，在此不做限定。
在本公开一些实施例中，逻辑控制电路预先存储有与之耦接的每一个驱动元件的地址。并且，为了控制逻辑控制电路耦接的每一个驱动元件尽可能的同步工作，逻辑控制电路可以在每一个显示帧内生成行同步信号，并在生成的行同步信号的脉冲出现设定沿时，向耦接的驱动元件输出对应的驱动数据，行同步信号的频率即为第一频率。示例性地，在一个显示帧内，行同步信号的设定沿的数量可以为K，这样可以在行同步信号的脉冲出现设定沿时， 向驱动元件发送驱动数据。
示例性地，结合图8与图9所示，行同步信号HB的设定沿为下降沿，帧刷新信号FB的设定沿为下降沿。系统电路300接收与显示帧Fn所要显示的画面相关的初始信号。例如，系统电路300接收与显示帧F1所要显示的画面相关的初始信号，对该初始信号进行一系列渲染、解码处理后，根据预先存储的逻辑控制电路200_1对应的地址ID_1以及逻辑控制电路200_2对应的地址ID_2进行拆分，拆分出逻辑控制电路200_1对应的图像信号TX1和逻辑控制电路200_2分别对应的图像信号(图9以逻辑控制电路200_1对应的图像信号TX1为例，逻辑控制电路200_2对应的图像信号未示出)。同时，生成帧刷新信号FB，在帧刷新信号FB的下降沿出现时，可以将对应逻辑控制电路200_1的图像信号TX1发送给逻辑控制电路200_1，以及将对应逻辑控制电路200_2的图像信号发送给逻辑控制电路200_2。以逻辑控制电路200_1为例，逻辑控制电路200_1接收到图像信号TX1后，根据图像信号TX1生成耦接的驱动元件112对应的驱动数据，并生成行同步信号HB，在该行同步信号HB的第k个下降沿出现时(k为正整数，且1≤k≤K)，逻辑控制电路200_1可以向驱动元件112提供驱动数据。各个驱动元件112可以将驱动数据中与自己对应地址对应的部分解码并二次处理后，驱动耦接的发光器件发光。
逻辑控制电路200_2的工作过程可以参照逻辑控制电路200_1的工作过程，具体在此不作赘述。需要说明的是，行同步信号的设定沿也可以设置为上升沿，其实现方式可以参照行同步信号的设定沿为下降沿时的实现方式，在此不作赘述。
在本公开一些实施例中，任一个驱动元件112可以控制正极信号线与其参考电压端O6在一个发光周期的工作时间段内形成电气回路。由于正极信号线与器件组中发光器件的第一端耦接，驱动元件112的参考电压端O6与器件组中发光器件的第二端耦接，在正极信号线依次通过耦接的器件组、驱动元件112的输出端、以及参考电压端O6之间形成电气回路时，可以控制发光器件在不同电流幅值和/或不同占空比的电流信号的控制下进行发光。示例性地， 每个发光周期即对应一个显示子帧，工作时间段即为形成上述电气回路的时间阶段。例如，正极信号线包括第一正极信号线和第二正极信号线，任一个驱动元件112可以控制第一正极信号线依次通过耦接的第一颜色发光器件1111、驱动元件112的输出端、以及参考电压端O6在每一个显示子帧的工作时间段内形成电气回路，可以使第一颜色发光器件1111发光。以及，控制第二正极信号线依次通过耦接的第二颜色发光器件1112、驱动元件112的输出端、以及其参考电压端O6在每一个显示子帧的工作时间段内形成电气回路，可以使第二颜色发光器件1112发光。以及，控制第二正极信号线依次通过耦接的第三颜色发光器件1113、驱动元件112的输出端、以及其参考电压端O6在每一个显示子帧的工作时间段内形成电气回路，可以使第三颜色发光器件1113发光。
在本公开一些实施例中，电子设备的工作过程可以包括地址分配阶段t1及数据信号传输阶段t3。以电子设备的逻辑控制电路200_1和显示面板110_1为例，结合图10和图11所示的信号时序图进行说明。
在地址分配阶段t1，逻辑控制电路200_1可以依次向各选址信号线Sm输入选址信息sm(m为正整数，且1≤m≤M)。驱动元件112可以接收对应的选址信息sm。图11为本公开实施例中选址信息的时序示意图，举例来说，逻辑控制电路200_1向选址信号线S1传输包括地址ID为00000001的选址信息s1，沿第一方向FS1上排列且与选址信号线S1连接的多个驱动元件112接收选址信息s1。逻辑控制电路200_1向选址信号线S2传输包括地址ID为00000010的选址信息s2，沿第一方向FS1上排列且与选址信号线S2连接的多个驱动元件112接收选址信息s2。其余同理，可以此类推，完成向各功能单元中的驱动元件112的地址分配过程。
以及，在数据信号传输阶段t3，即行同步信号HB的第一个下降沿出现时，逻辑控制电路200_1可以向各驱动信号线Dn分别提供带有与之耦接的各驱动元件112的地址的驱动数据da。驱动元件112可以在识别到驱动数据中对应的地址时，接收驱动数据，并根据驱动数据，生成发光控制信号，以控 制正极信号线依次经由与驱动元件112耦接的器件组、驱动元件112的输出端、以及参考电压端O6形成电气回路。示例性地，每个驱动数据da可以包括按特定顺序(例如特定顺序可以为驱动元件的物理位置顺次排序)依次排列的多个子数据信息dam(m为正整数，且1≤m≤M)，这样可以向各驱动信号线Dn依次输入多个子数据信息dam，从而使得驱动信号线Dn依次向对应的功能单元列中的各驱动元件112传输对应的子数据信息dam。其中，子数据信息可以包括：各功能单元P对应的地址ID，以及与该地址ID对应且与该驱动信号线Dn耦接的功能单元P的像素数据信息。驱动元件112在识别到子数据信息dam中的地址ID与在地址分配阶段t1接收到的地址ID相同时，可以接收该子数据信息dam，并根据驱动数据，生成驱动元件112的各输出端对应的发光控制信号，以控制耦接的正极信号线(例如，第一正极信号线和/或第二正极信号线)依次经由与驱动元件112耦接的器件组、驱动元件112的输出端、以及参考电压端O6形成电气回路。
在一些示例中，以图3所示的显示面板的结构、逻辑控制电路200_1以及显示面板100_1为例，在数据信号传输阶段t3，逻辑控制电路200_1向驱动信号线Dn输入包括子数据信息da1～daM的数据信息，与驱动信号线Dn耦接的驱动元件112分别从包括子数据信息da1～daM的数据信息中，获取与其地址ID匹配的子数据信息。驱动元件112可以根据子数据信息，生成与输出端O1耦接的第一颜色发光器件1111对应的发光控制信号EM1、与输出端O2耦接的第二颜色发光器件1112对应的发光控制信号EM2、以及与输出端O3耦接的第三颜色发光器件1113对应的发光控制信号EM3。在发光控制信号EM1的控制下，可以实现至少一条正极信号线依次经由与该第一颜色发光器件1111、该驱动元件112的输出端O1、以及参考电压端O6形成电气回路，从而使第一颜色发光器件1111发光；在发光控制信号EM2的控制下，可以实现至少一条正极信号线依次经由与该第二颜色发光器件1112、该驱动元件112的输出端O2、以及参考电压端O6形成电气回路，从而使第二颜色发光器件1112发光；在发光控制信号EM3的控制下，可以实现至少一条正极信号线依 次经由与该第三颜色发光器件1113、该驱动元件112的输出端O4、以及参考电压端O6形成电气回路，从而使第三颜色发光器件1113发光。
需要说明的是，每个驱动数据da中包括了在第二方向FS2排列的M个驱动元件对应的子数据信息的集合，子数据信息中包括了与M个驱动元件中的每个驱动元件所连接的器件组的驱动信息。
示例性地，如图11所示，选址信息sm可以包括：依次设置的起始指令SoT、地址ID、间隔指令DCX及结束指令EoT。在实际应用中，各选址信号线Sm对应的选址信息sm中的地址ID不同，从而区分位于不同行驱动元件的地址。示例性地，选址信息sm的长度可以设置为12bit，其中，起始指令SoT可以设为1bit，地址ID可以设为8bit、间隔指令DCX可以设为1bit，结束指令EoT可以设为2bit。
在本公开一些实施例中，逻辑控制电路还可以向选址信号线Sm输入供电电压，驱动元件112可以通过寻址信号端O5接收选址信号线Sm传输的供电电压。示例性地，如图11所示，可以通过区分选址信号线Sm传输的信号幅值，来区分选址功能(如传输选址信息)和其他功能(如传输供电电压VCC)。例如，信号幅值的电平V2(例如电压值为3.3V)时执行选址功能，信号幅值的电平V1(例如电压值为1.8V)时执行显示功能(如传输供电电压VCC)。实际工作时，首先选址信号线Sm传输的信号幅值需要从电平V0(例如0V)升高至电平V1以使与选址信号线Sm连接的元器件进入工作状态，随后信号幅值从电平V1变化至以电平V2为基准波动后，则选址信号线Sm执行选址功能，通过调制选址信号线Sm传输信号的波动变化规律。例如，信号在第一幅值V2H和第二幅值V2L之间变化，且V1<V2L<V2<V2H，通过调制第一幅值V1和第二幅值V2的变化规律，可以将选址信息sm调制到该信号中，从而使在传输电能的同时传输对应的地址。例如，选址信息sm以起始指令SoT作为开始，然后传输地址ID及间隔指令DCX，最后以结束指令EoT结束该像素行的地址分配。当信号幅值从以电平V2为基准波动再回到电平V1后并一直保持电平V1的情况下，选址信号线Sm可以用于传输供电电压。也 就是说，选址信号线Sm传输的电平V1，可以作为供电电压。
在本公开一些实施例中，以图3所示的结构为例，如图3与图10所示，上述子数据信息(以da1为例)可以包括：起始指令SoT、地址ID、数据传输指令DCX、间隔指令IoT、像素数据信息Rda、Gda、Bda及结束指令EoT。其中，数据传输指令DCX为设定值时，表示进行数据传输，例如DCX＝1时，表示数据传输，当驱动元件112识别到DCX的值为1时，将子数据信息中的像素数据信息传输给对应的发光二极管。并且，像素数据信息Rda表示驱动第一颜色发光器件1111发光所需的信息，像素数据信息Gda表示驱动第二颜色发光器件1112发光所需的信息，像素数据信息Bda表示驱动第三颜色发光器件1113发光所需的信息。示例性地，每个子数据信息的长度可以设置为63bit，其中，以子数据信息da1为例，子数据信息da1的长度可以设置为63bit，其中，起始指令SoT占1bit，地址ID占8bit，数据传输指令DCX占1bit，间隔指令IoT占1bit，像素数据信息Rda、Gda或Bda分别占16bit，结束指令EoT占2bit，此外，相邻的像素数据信息之间也可以设置间隔指令IoT。
可以理解的是，在t1阶段之前，本公开的驱动元件112可能处于睡眠状态，该睡眠状态为低功耗工作模式或非工作状态。通过选址信号线Sm向驱动元件112的寻址信号端O5输入供电电压VCC，以使驱动元件112解除睡眠状态，即图10中的t0阶段。
在另一些示例中，以图5所示的显示面板的结构、逻辑控制电路200_1以及显示面板100_1为例，结合图12，在数据信号传输阶段t3，逻辑控制电路200_1向驱动信号线Dn依次输入子数据信息da1～daM，与驱动信号线Dn耦接的驱动元件112分别从包括子数据信息da1～daM的驱动数据中，获取与其地址ID匹配的子数据信息。
驱动元件112可以根据子数据信息，生成与输出端O1_1耦接的第一颜色发光器件1111对应的发光控制信号EM1_1、与输出端O1_2耦接的第一颜色发光器件1111对应的发光控制信号EM1_2、与输出端O1_3耦接的第一颜色发光器件1111对应的发光控制信号EM1_3、与输出端O1_4耦接的第一颜色 发光器件1111对应的发光控制信号EM1_4、与输出端O2_1耦接的第二颜色发光器件1112对应的发光控制信号EM2_1、与输出端O2_2耦接的第二颜色发光器件1112对应的发光控制信号EM2_2、与输出端O2_3耦接的第二颜色发光器件1112对应的发光控制信号EM2_3、与输出端O2_4耦接的第二颜色发光器件1112对应的发光控制信号EM2_4、与输出端O3_1耦接的第三颜色发光器件1113对应的发光控制信号EM3_1、与输出端O3_2耦接的第三颜色发光器件1113对应的发光控制信号EM3_2、与输出端O3_3耦接的第三颜色发光器件1113对应的发光控制信号EM3_3、以及与输出端O3_4耦接的第三颜色发光器件1113对应的发光控制信号EM3_4。在发光控制信号EM1_1～EM1_4的控制下，可以实现至少一条正极信号线依次经由与该第一颜色发光器件1111、该驱动元件112的输出端O1(包括O1_1～O1_4中的任一个)、以及参考电压端O6形成电气回路，从而使对应的第一颜色发光器件1111发光；在发光控制信号EM2_1～EM2_4的控制下，可以实现至少一条正极信号线依次经由与该第二颜色发光器件1112、该驱动元件112的输出端O2(包括O2_1～O2_4中的任一个)、以及参考电压端O6形成电气回路，从而使对应的第二颜色发光器件1112发光；在发光控制信号EM3_1～EM3_4的控制下，可以实现至少一条正极信号线依次经由与该第三颜色发光器件1113、该驱动元件112的输出端O2(包括O3_1～O3_4中的任一个)、以及参考电压端O6形成电气回路，从而使对应的第三颜色发光器件1113发光。
需要说明的是，图5所示的显示面板在地址分配阶段t1和t0阶段的工作过程，可以与前述的图3所示的显示面板在地址分配阶段t1和t0阶段的工作过程基本相同，在此不作赘述。
在本公开一些实施例中，在功能单元中包括多个器件组时，结合图5与图12所示，子数据信息(以da1为例)可以包括：起始指令SoT、地址ID、数据传输指令DCX、间隔指令IoT、像素数据信息Rda1～Rda4、Gda1～Gda4、Bda1～Bda4及结束指令EoT。其中，数据传输指令DCX为设定值时，表示进行数据传输，例如DCX＝1时，表示数据传输，当驱动元件112识别到DCX 的值为1时，将子数据信息中的像素数据信息传输给对应的发光二极管。并且，像素数据信息Rda1～Rda4表示驱动与该驱动元件112耦接的4个第一颜色发光器件1111发光所需的信息，像素数据信息Gda1～Gda4表示驱动与该驱动元件112耦接的4个第二颜色发光器件1112发光所需的信息，像素数据信息Bda1～Bda4表示驱动与该驱动元件112耦接的4个第三颜色发光器件1113发光所需的信息。示例性地，每个子数据信息的长度可以设置为63bit，其中，以子数据信息da1为例，起始指令SoT占1bit，地址ID占8bit，数据传输指令DCX占1bit，间隔指令IoT占1bit，子像素数据Rda1、Rda2、Rda3、Rda4共占16bit，子像素数据Gda1、Gda2、Gda3、Gda4共占16bit，子像素数据Bda1、Bda2、Bda3、Bda4共占16bit，结束指令EoT占2bit，此外，任意相邻的两个子数据信息之间可以设置间隔指令IoT。可以理解的是，由于一个驱动元件112驱动12个发光器件，而与该驱动元件112连接的四个像素1之间的序号关系，可以通过驱动元件112内部的数字逻辑电路实现，以将像素数据信息中对应各发光器件的子像素数据的准确分发到对应的输出端。
在本公开一些实施例中，每一个显示帧还可以包括：在数据信号传输阶段t3之前的电流设定阶段t2，例如电流设定阶段t2可以位于地址分配阶段t1与数据信号传输阶段t3之间。在电流设定阶段t2，逻辑控制电路200_1向各驱动信号线Dn输入设有地址ID的电流设定信息Co。驱动元件112可以在识别到电流设定信息Co中对应的地址时，接收电流设定信息Co，以根据接收到的电流设定信息Co，控制驱动元件112的驱动电流的大小，进而进一步精确控制对应功能单元的出光亮度。示例性地，结合图8与图10所示，在电流设定阶段t2，逻辑控制电路200_1向各驱动信号线Dn输入电流设定信息Co。电流设定信息Co中可以设有地址ID。驱动元件112从驱动信号线Dn上传输的电流设定信息Co中，接收与之地址对应的电流设定信息。
可选地，电流设定信息Co的长度可以为63bit，具体可以包括：1bit的起始指令SoT、8bits的地址ID、1bit的电流设定指令DCX、1bit的间隔指令IoT、由帧起始指令C和控制指令P1(例如表示需要提供某一输出端所耦接的发光 二极管的电流幅值校正系数)共同组成的16bits数据、1bit的间隔指令IoT、16bits的预留控制指令位P2+P3、1bit的间隔指令IoT、16bits的预留控制指令位P4+P5，以及2bits的结束指令EoT。其中，电流设定指令DCX为设定值时表示进行电流设定，例如DCX为0时，表示进行电流设定。
可以理解的是，显示面板在逐个显示帧显示画面的过程中，可以在电子设备开机后进入的第一个显示帧不显示画面(例如显示全黑)，而在第一个显示帧中进行t0阶段和t1阶段的过程，第二个以及之后的显示帧，电子设备可以仅需执行t2阶段和t3阶段。这样可以使每一个显示帧中的每一个显示子帧分别具有t2阶段和t3阶段的过程。或者，也可以在第一个显示帧中进行t0阶段、t1阶段以及t2阶段的过程，第二个以及之后的显示帧，电子设备可以仅需执行t3阶段的过程。这样可以使每一个显示帧中的每一个显示子帧分别具有t3阶段的过程。也就是说，在如图9所示的信号时序图中，在显示帧F1之前，还可以具有显示帧F0，在显示帧F0可以执行t0阶段和t1阶段的过程或执行t0阶段至t2阶段的过程。在显示帧F1～F3中的每一个显示子帧分别执行t3阶段的过程。
在本公开一些实施例中，如图13所示，多个驱动元件112中的任一个驱动元件112可以包括：处理控制电路1122和数据驱动电路1121。其中，处理控制电路1122分别与驱动信号端O4、寻址信号端O5耦接，数据驱动电路1121分别与处理控制电路1122、驱动元件112的输出端、寻址信号端O5以及参考电压端O6耦接。并且，数据驱动电路1121通过输出端与对应的器件组中的发光器件的第二端耦接。处理控制电路1122可以在发光周期(发光周期例如可以为显示子帧)内，在识别到驱动数据中对应的地址时，通过驱动信号端O4接收驱动数据，并根据驱动数据，生成发光控制信号，并将发光控制信号发送给数据驱动电路1121。并且，数据驱动电路1121空调在该发光周期内，根据接收到的发光控制信号，控制正极信号线(如第一正极信号线和第二正极信号线)依次经由与驱动元件112耦接的器件组中的发光器件、驱动元件112的输出端、以及参考电压端O6形成电气回路，以控制各发光器件通过形 成的电气回路发光。
在本公开一些实施例中，如图13与图14所示，数据驱动电路1121可以包括至少一个数据驱动子电路(如11211、11212、11213)。其中，数据驱动子电路(如11211、11212、11213)分别与处理控制电路1122、寻址信号端O5以及参考电压端O6耦接，且一个数据驱动子电路与一个输出端耦接，即一个数据驱动子电路通过对应的输出端可以与一个子像素中的发光器件的负极耦接。在通过寻址信号端O5输入供电电压VCC时，该供电电压VCC可以输入数据驱动子电路，以为数据驱动子电路供电。在通过参考电压端O6输入参考电压VSS时，该参考电压VSS可以输入数据驱动子电路，以为数据驱动子电路提供低电压。数据驱动子电路(如11211、11212、11213)可以在发光周期内接收耦接的器件组对应的发光控制信号，并响应于发光控制信号控制正极信号线依次经由与驱动元件112耦接的器件组、驱动元件112的输出端、以及参考电压端O6形成电气回路。示例性地，结合图3、图13以及图14所示，数据驱动子电路11211与输出端O1耦接，输出端O1与第一颜色发光器件1111的负极耦接，第一颜色发光器件1111的正极与第一正极信号线耦接，数据驱动子电路11211可以接收对应的第一颜色发光器件1111的发光控制信号EM1，以响应于该发光控制信号EM1，可以驱动第一正极信号线Van、第一颜色发光器件1111、输出端O1以及参考电压端O6之间形成电气回路，以使第一颜色发光器件1111具有电流流过而发光。并且，数据驱动子电路11212与输出端O2耦接，输出端O2与第二颜色发光器件1112的负极耦接，第二颜色发光器件1112的正极与第二正极信号线Vbn耦接，数据驱动子电路11212可以接收对应的第二颜色发光器件1112的发光控制信号EM2，以响应于该发光控制信号EM2，可以驱动第二正极信号线Vbn、第二颜色发光器件1112、输出端O2以及参考电压端O6之间形成电气回路，以使第二颜色发光器件1112具有电流流过而发光。以及，数据驱动子电路11213与输出端O3耦接，输出端O3与第三颜色发光器件1113的负极耦接，第三颜色发光器件1113的正极与第二正极信号线Vbn耦接，数据驱动子电路11213可以接收对应的第 三颜色发光器件1113的发光控制信号EM3，以响应于该发光控制信号EM3，可以驱动第二正极信号线Vbn、第三颜色发光器件1113、输出端O3以及参考电压端O6之间形成电气回路，以使第三颜色发光器件1113具有电流流过而发光。
在本公开一些实施例中，发光控制信号可以包括驱动控制信号和电流控制信号。每个数据驱动子电路可以包括：调制电路以及恒流源电路；其中，恒流源电路分别与处理控制电路1122以及调制电路耦接，调制电路与对应的输出端耦接。其中，恒流源电路可以接收对应的器件组的电流控制信号，并根据接收到的电流控制信号，输出对应电流控制信号的恒定幅值的电流。调制电路可以接收对应的器件组的驱动控制信号，并根据接收到的驱动控制信号的有效电平，将恒流源产生的电流输入耦接的输出端，以在工作时间段内控制正极信号线至少依次经由与驱动元件耦接的器件组、驱动元件的输出端、以及参考电压端形成电气回路。
示例性地，结合图9、图14与图15所示，发光控制信号EM1可以包括驱动控制信号PWM1和电流控制信号DAC1，数据驱动子电路11211包括：调制电路112111以及恒流源电路112112。恒流源电路112112可以接收对应第一颜色发光器件1111的电流控制信号DAC1，并根据接收到的电流控制信号DAC1，输出对应电流控制信号DAC1的恒定幅值的电流IL1。调制电路112111可以接收对应第一颜色发光器件1111的驱动控制信号PWM1，并根据接收到的驱动控制信号PWM1的有效电平(例如高电平)，将恒流源电路112112产生的电流IL1输入耦接的输出端O1，以在工作时间段内控制第一正极信号线Van至少依次经由第一颜色发光器件1111、驱动元件112的输出端O1、以及参考电压端O6形成电气回路，使第一颜色发光器件1111发光。也就是说，驱动控制信号PWM1的有效电平的时长内，可以看作第一颜色发光器件1111处于工作时间段。这样可以通过驱动控制信号PWM1和电流控制信号DAC1相互结合，控制第一颜色发光器件1111在每一个显示帧中的每一个显示子帧的发光亮度。
并且，发光控制信号EM2可以包括驱动控制信号PWM2和电流控制信号DAC2，数据驱动子电路11212包括：调制电路112121以及恒流源电路112122。恒流源电路112122可以接收对应第二颜色发光器件1112的电流控制信号DAC2，并根据接收到的电流控制信号DAC2，输出对应电流控制信号DAC2的恒定幅值的电流IL2。调制电路112121可以接收对应第二颜色发光器件1112的驱动控制信号PWM2，并根据接收到的驱动控制信号PWM2的有效电平(例如高电平)，将恒流源电路112122产生的电流IL2输入耦接的输出端O2，以在工作时间段内控制第二正极信号线Vbn至少依次经由第二颜色发光器件1112、驱动元件112的输出端O2、以及参考电压端O6形成电气回路，使第二颜色发光器件1112发光。也就是说，驱动控制信号PWM2的有效电平的时长内，可以看作第二颜色发光器件1112处于工作时间段。这样可以通过驱动控制信号PWM2和电流控制信号DAC2相互结合，控制第二颜色发光器件1112在每一个显示帧中的每一个显示子帧的发光亮度。
以及，发光控制信号EM3可以包括驱动控制信号PWM3和电流控制信号DAC3，数据驱动子电路11213包括：调制电路112131以及恒流源电路112132。恒流源电路112132可以接收对应第三颜色发光器件1113的电流控制信号DAC3，并根据接收到的电流控制信号DAC3，输出对应电流控制信号DAC3的恒定幅值的电流IL3。调制电路112131可以接收对应第三颜色发光器件1113的驱动控制信号PWM3，并根据接收到的驱动控制信号PWM3的有效电平(例如高电平)，将恒流源电路112132产生的电流IL3输入耦接的输出端O3，以在工作时间段内控制第二正极信号线Vbn至少依次经由第三颜色发光器件1113、驱动元件112的输出端O3、以及参考电压端O6形成电气回路，使第三颜色发光器件1113发光。也就是说，驱动控制信号PWM3的有效电平的时长内，可以看作第三颜色发光器件1113处于工作时间段。这样可以通过驱动控制信号PWM3和电流控制信号DAC3相互结合，控制第三颜色发光器件1113在每一个显示帧中的每一个显示子帧的发光亮度。
需要说明的是，驱动控制信号的有效电平也可以为低电平，在此不作限 定。
综上，在调制电路导通时，上述电气回路导通，器件组发光。在调制电路截止时，上述电气回路断开，器件组不发光。因此，调制电路可以在驱动控制信号PWM的控制下对流经器件组的电流进行调制，使得流经器件组的电流呈现为可以通过脉冲宽度进行调制的电流信号。因此，驱动控制信号PWM可以作为一种脉冲宽度调制信号。并且，调制电路可以根据驱动控制信号PWM的占空比等参数，对流经器件组的电流进行调制，进而控制器件组的工作状态。例如，当器件组含有发光器件时，通过增加驱动控制信号PWM的占空比，可以提高发光器件在一个显示帧(或显示子帧)内的发光总时长，进而提高发光器件在该显示帧(或显示子帧)内的总发光亮度，使得发光器件所在器件组的亮度增大。反之，通过驱动控制信号PWM的占空比，可以降低发光器件在一个显示帧(或显示子帧)内的发光总时长，进而降低发光器件在该显示帧(或显示子帧)的总发光亮度，使得发光器件所在器件组的亮度减小。
示例性地，调制电路可以为开关元件，例如可以为金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)、薄膜场效应晶体管(Thin Film Transistor，TFT)等晶体管。当然，在实际应用中，调制电路的具体实施方式，可以根据实际应用的需求进行确定，在此不作限定。
示例性地，恒流源电路可以具有多种实现方式，例如恒流源电路可以设置为恒流二极管，数字模拟转换器和触发器组合构成的电路，电流镜电流等等。当然，在实际应用中，恒流源电路的具体实施方式，可以根据实际应用的需求进行确定，在此不作限定。
在一些示例中，以第一颜色发光器件1111对应的16bit的像素数据信息Rda为例，其他发光器件对应的16bit的像素数据信息，采用相同的数据类型和编码规则。示例性地，像素数据信息Rda为16bit，则可以具有但不限于如下实施方式：电流控制信号DAC1占用6bit且驱动控制信号PWM1占用10bit； 或者电流控制信号DAC1占用5bit且驱动控制信号PWM1占用11bit；或者电流控制信号DAC1占用4bit且驱动控制信号PWM1占用12bit；或者电流控制信号DAC1占用3bit且驱动控制信号PWM1占用13bit。
以电流控制信号DAC1占用6bit且驱动控制信号PWM1占用10bit为例，电流控制信号DAC1可以控制恒流源电路112112输出64(2 6)种不同的电流幅值。恒流源电路112112可以具有不同的电流档位，例如2uA、3uA、5uA等等。以电流档位为2uA为例，恒流源电路112112能够输出的电流IL1的最大值即为128uA(2uA*64)，最小值即为2uA(2uA*1)，从而可以使电流IL1幅值一共有64种可选值，进而可以满足第一颜色发光器件1111不同的亮度需求。驱动控制信号PWM1占用10bit，则驱动控制信号PWM1的占空比可以具有1024(2 10)种不同的情况。驱动控制信号PWM1占用的bit数越多，占空比的情况种类越多。
由于每个发光器件的正负极分别与衬底基板上的连接焊盘对应连接，连接焊盘在具有压差的情况下，连接焊盘之间会形成电容，该电容即为发光器件的自身寄生电容，容值在几pF皮法到几十pF。在等效电路中，该电容与发光器件呈并联连接关系。由于电子设备包括多个器件组，每个器件中包括至少一个发光器件，由于每个发光器件因为制作工艺波动或者发光状态的不同，其自身寄生电容的容值不尽相同，因此不同发光器件由关闭状态(即off状态ZT-off)切换到发光状态(即on状态ZT-on)的时间或由发光状态(即on状态ZT-on)切换到关闭状态(即off状态ZT-off)的时间不同，从而导致不同发光器件在应当显示相同亮度的情况下，实际却呈现出不同的亮度，从而影响视觉感受。
可以理解的是，虽然各连接焊盘与信号线之间由于交叠，也会形成电容，但该电容容值较小，在本公开实施例中不做讨论。
示例性地，以第一颜色发光器件1111为例，结合图13至图16所示，图16中，FL1代表第一颜色发光器件1111的负极的电压变化的理论值，FL2代表第一颜色发光器件1111的负极的电压变化的实际值。其中，第一颜色发光 器件1111的正极与第一正极信号线Van耦接，第一颜色发光器件1111的负极通过调制电路112111和恒流源电路112112与参考电压端O6耦接，由于第一颜色发光器件1111自身寄生电容的存在，导致第一颜色发光器件1111的负极电压不能瞬间从高电平(例如2V)被拉低到参考电压VSS(例如1V)，即第一颜色发光器件1111不能迅速由关闭状态(即off状态ZT-off)切换到发光状态(即on状态ZT-on)，从而缩短了第一颜色发光器件1111发光的时间。同样地，驱动元件112在工作时，也会产生类似的自身寄生电容，该寄生电容也会导致第一颜色发光器件1111不能迅速由关闭状态(即off状态ZT-off)切换到发光状态(即on状态ZT-on)，缩短第一颜色发光器件1111发光的时间(即即on状态ZT-on的时间)。
可以理解的是，发光器件处于发光状态(即on状态ZT-on)时，发光器件的正负极电压差只要大于其启亮电压，就可以发光。因此，发光器件的负极电压不需要被降低至参考电压VSS，发光器件才能发光，而是发光器件的负极电压的电压值加上该发光器件的启亮电压小于该发光器件的正极电压，发光器件就可以处于发光状态(即on状态ZT-on)。
为了改善上述问题，本公开实施例提供的驱动元件112还可以在发光周期的工作时间段之前，调节与其耦接的器件组的第二端的电位，例如，将器件组的第二端的电位下拉。示例性地，结合图13与图16所示，器件组包括第一颜色发光器件1111、第二颜色发光器件1112、第三颜色发光器件1113；器件组的第二端包括第一颜色发光器件1111的负极、第二颜色发光器件1112的负极、第三颜色发光器件1113的负极；其中，第一颜色发光器件1111的负极与驱动元件112的输出端O1连接，第二颜色发光器件1112的负极与驱动元件112的输出端O2连接，第三颜色发光器件1113的负极与驱动元件112的输出端O3连接。FL3代表第一颜色发光器件1111的负极的电压经过电位调节电路调节后的实际值。驱动元件112可以在第一颜色发光器件1111的工作时间段之前，调节第一颜色发光器件1111的负极的电位，这样可以提前使得第一颜色发光器件1111的负极电位降低至能够使得第一颜色发光器件1111 点亮的临界状态，从而可以使第一颜色发光器件1111在工作时间段开始时可以迅速由关闭状态(即off状态ZT-off)切换到发光状态(即on状态ZT-on)，进而可以使第一颜色发光器件1111处于发光状态(即on状态ZT-on)的实际时间尽可能与理论值相同。同样地，驱动元件112可以在第二颜色发光器件1112的工作时间段之前，调节第二颜色发光器件1112的负极的电位，这样可以提前使得第二颜色发光器件1112的负极电位降低至能够使得第二颜色发光器件1112点亮的临界状态，从而可以使第二颜色发光器件1112在工作时间段开始时可以迅速由关闭状态(即off状态ZT-off)切换到发光状态(即on状态ZT-on)，进而可以使第二颜色发光器件1112处于发光状态(即on状态ZT-on)的实际时间尽可能与理论值相同。同样地，驱动元件112可以在第三颜色发光器件1113的工作时间段之前，调节第三颜色发光器件1113的负极的电位，这样可以提前使得第三颜色发光器件1113的负极电位降低至能够使得第三颜色发光器件1113点亮的临界状态，从而可以使第三颜色发光器件1113在工作时间段开始时可以迅速由关闭状态(即off状态ZT-off)切换到发光状态(即on状态ZT-on)，进而可以使第三颜色发光器件1113处于发光状态(即on状态ZT-on)的实际时间尽可能与理论值相同。
在本公开一些实施例中，多个驱动元件中的任一个驱动元件，可以在工作时间段之前，控制与其耦接的器件组的第二端与其参考电压端导通第一补偿时间，以采用参考电压端加载的参考电压，在第一补偿时间内调节与其耦接的器件组的第二端的电位。示例性地，结合图9与图13以及图17所示，驱动元件112可以在第一颜色发光器件1111的工作时间段之前(例如，在一个显示子帧F1_1内，驱动控制信号PWM1的第一个上升沿来临之前)，将第一颜色发光器件1111的负极与参考电压端O6导通第一补偿时间ts1，以采用参考电压端O6加载的参考电压VSS，在第一补偿时间ts1内调节第一颜色发光器件1111的负极的电位。以及，在第二颜色发光器件1112的工作时间段之前，将第二颜色发光器件1112的负极与参考电压端O6导通第一补偿时间，以采用参考电压端O6加载的参考电压，在第一补偿时间内调节第二颜色发光 器件1112的负极的电位。以及，在第三颜色发光器件1113的工作时间段之前，将第三颜色发光器件1113的负极与参考电压端O6导通第一补偿时间，以采用参考电压端O6加载的参考电压，在第一补偿时间内调节第三颜色发光器件1113的负极的电位。
在本公开一些实施例中，多个驱动元件中的任一个驱动元件，可以在第一补偿时间的结束时刻，控制正极信号线至少依次经由与驱动元件耦接的器件组、驱动元件的输出端、以及参考电压端形成电气回路。示例性地，结合图9、图13以及图17所示，驱动元件112可以在第一颜色发光器件1111的负极与参考电压端O6导通的第一补偿时间ts1的结束时刻，控制第一正极信号线Van、第一颜色发光器件1111、输出端O1以及参考电压端O6形成电气回路。以及，在第二颜色发光器件1112的负极与参考电压端O6导通的第一补偿时间的结束时刻，控制第二正极信号线、第二颜色发光器件1112、输出端O2以及参考电压端O6形成电气回路。以及，在第三颜色发光器件1113的负极与参考电压端O6导通的第一补偿时间的结束时刻，控制第二正极信号线、第三颜色发光器件1113、输出端O3以及参考电压端O6形成电气回路。
在本公开一些实施例中，多个驱动元件中的任一个驱动元件，可以在工作时间段之内，控制与其耦接的器件组的第二端与其参考电压端导通第二补偿时间。示例性地，结合图9与图13以及图17所示，以第一颜色发光器件1111为例，驱动元件112可以在第一颜色发光器件1111的工作时间段之内(例如，在一个显示子帧F1_1内，驱动控制信号PWM1的任意有效电平时间段内，例如是驱动控制信号PWM1的第一个有效电平时间段内)，将第一颜色发光器件1111的负极与参考电压端O6导通第二补偿时间ts2，以采用参考电压端O6加载的参考电压，在第二补偿时间ts2内调节第一颜色发光器件1111的负极的电位。
在本公开一些实施例中，可以使第一补偿时间和第二补偿时间为依次连续的时间段。示例性地，结合图9与图13以及图17所示，第一颜色发光器件1111对应的第一补偿时间ts1和第二补偿时间ts2为依次连续的时间段。第 二颜色发光器件1112对应的第一补偿时间和第二补偿时间为依次连续的时间段。第三颜色发光器件1113对应的第一补偿时间和第二补偿时间为依次连续的时间段。
在本公开一些实施例中，器件组中包括多个器件(例如发光器件)，器件组的第二端可以包括多个发光器件的负极，每个发光器件的负极与同一驱动元件的不同输出端连接，那么，每个发光器件对应的第一补偿时间和/或第二补偿时间不尽相同，从而可以对不同发光器件的负极的电位进行精准调整。
由于第二补偿时间与发光器件的工作时间段存在交叠时间段，为了避免第二补偿时间对发光器件正常工作时的亮度影响，在本公开一些实施例中，对于多个器件组中的至少一个器件组，器件组对应的第二补偿时间小于第一补偿时间。具体地，可以使器件组中每个器件对应的第二补偿时间小于第一补偿时间，例如，可以使每一个发光器件对应的第二补偿时间小于第一补偿时间。在具体实施时，第二补偿时间小于第一补偿时间的一半。
在本公开一些实施例中，多个器件组中的至少两个器件组，其分别对应不同的第一补偿时间和/或第二补偿时间；属于同一个器件组中的多个器件，在实现特定灰阶时，其可以分别对应不同的第一补偿时间和/或第二补偿时间。例如，一个器件组中包括第一颜色发光器件1111、第二颜色发光器件1112和第三颜色发光器件1113，第一颜色发光器件1111对应的第一补偿时间为60ns，第二颜色发光器件1112对应的第一补偿时间为35ns，第三颜色发光器件1113对应的第一补偿时间为8ns；则第一颜色发光器件1111对应的第二补偿时间可以为10ns，第二颜色发光器件1112对应的第二补偿时间可以为5ns，第三颜色发光器件1113对应的第二补偿时间可以为2ns。
在本公开一些实施例中，也可以使多个器件组中的至少部分器件组对应的第二补偿时间相同。示例性地，可以使至少部分器件组对应的第二补偿时间均设置为1ns，这样可以降低第二补偿时间的设计难度。
在本公开一些实施例中，多个驱动元件112中的任一个驱动元件112，可以根据预先存储的与其耦接的器件组对应的电位补偿时间，控制与其耦接的 器件组的第二端与其参考电压端O6导通的电位补偿时间；其中，电位补偿时间为第一补偿时间和第二补偿时间之和。当然，电位补偿时间为第一补偿时间。下面以电位补偿时间为第一补偿时间和第二补偿时间之和为例进行说明。在电位补偿时间为第一补偿时间时，其工作过程可以此类推，在此不作赘述。
在本公开一些实施例中，由于在发光器件发光之前调节其负极的电位，从而让发光器件的自身寄生电容提前放电，但是需要避免因提前调节发光器件的负极的电位而导致发光器件在非工作时间段发光，因此，第一补偿时间ts1存在最大值ts1-max，在具体实施时，第一补偿时间ts1不应超过该最大值ts1-max。示例性地，可以根据公式：
Figure PCTCN2022088732-appb-000001
确定第一补偿时间ts1的最大值ts1-max。其中，V +代表发光器件的正极的电压，V F代表发光器件的启亮电压，V s代表在第一补偿时间ts1开始前发光器件的负极的电压，R LED代表发光器件自身等效电阻的阻值，C LED代表发光器件自身寄生电容的容值。示例性地，结合图16所示，以第一颜色发光器件为例，第一颜色发光器件的正极的电压为VLED1，则V +＝VLED1，V F代表第一颜色发光器件的启亮电压，V s代表在第一补偿时间ts1开始前第一颜色发光器件负极的电压，R LED代表第一颜色发光器件的自身等效电阻的阻值，C LED代表第一颜色发光器件的自身寄生电容的容值；代入上述公式，可以确定出第一颜色发光器件对应的第一补偿时间ts1的最大值。其余发光器件的第一补偿时间ts1的最大值计算方式同理，在此不作赘述。
在本公开一些实施例中，处理控制电路1122还可以在发光周期内，根据电位补偿时间，生成电位调节控制信号，并将电位调节控制信号发送给数据驱动电路。数据驱动电路可以根据接收到的电位调节控制信号的有效电平，控制对应的器件组的第二端与其参考电压端导通；其中，器件组对应的电位调节控制信号的有效电平时长为电位补偿时间。示例性地，结合图3、图13至图15所示，处理控制电路1122还可以在发光周期内，根据输出端O1对应的电位补偿时间ts，生成电位调节控制信号OVS1，并将电位调节控制信号 OVS1发送给数据驱动电路1121。数据驱动电路1121可以根据接收到的电位调节控制信号OVS1的有效电平(例如高电平)，控制第一颜色发光器件1111的负极与其参考电压端O6导通。处理控制电路1122还可以在发光周期内，根据输出端O2对应的电位补偿时间，生成电位调节控制信号OVS2，并将电位调节控制信号OVS2发送给数据驱动电路1121。数据驱动电路1121可以根据接收到的电位调节控制信号OVS2的有效电平(例如高电平)，控制第二颜色发光器件1112的负极与其参考电压端O6导通。以及，处理控制电路1122还可以在发光周期内，根据输出端O3对应的电位补偿时间，生成电位调节控制信号OVS3，并将电位调节控制信号OVS3发送给数据驱动电路1121。数据驱动电路1121可以根据接收到的电位调节控制信号OVS3的有效电平(例如高电平)，控制第三颜色发光器件1113的负极与其参考电压端O6导通。
在本公开一些实施例中，在数据驱动电路包括数据驱动子电路时，数据驱动子电路可以接收处理控制电路1122输出的电位调节控制信号，并响应于电位调节控制信号，控制耦接的器件组的第二端与其参考电压端导通。示例性地，结合图3、图13至图15所示，数据驱动子电路11211可以接收电位调节控制信号OVS1，并响应于电位调节控制信号OVS1的有效电平(例如高电平)，控制第一颜色发光器件1111的负极与其参考电压端O6导通。数据驱动子电路11212可以接收电位调节控制信号OVS2，并响应于电位调节控制信号OVS2的有效电平(例如高电平)，控制第二颜色发光器件1112的负极与其参考电压端O6导通。数据驱动子电路11213可以接收电位调节控制信号OVS3，并响应于电位调节控制信号OVS3的有效电平(例如高电平)，控制第三颜色发光器件1113的负极与其参考电压端O6导通。
在本公开一些实施例中，数据驱动子电路还可以包括：电位调节电路，该电位调节电路分别与处理控制电路以及对应的输出端耦接。并且，电位调节电路可以接收对应的器件组的电位调节控制信号，并根据接收到的电位调节控制信号控制耦接的器件组的第二端与其参考电压端导通。示例性地，结合图3、图13至图15所示，数据驱动子电路11211包括：电位调节电路112113， 且电位调节电路112113可以接收电位调节控制信号OVS1，并响应于电位调节控制信号OVS1的有效电平，可以将第一颜色发光器件1111的负极与参考电压端O6导通。数据驱动子电路11212包括：电位调节电路112123，且电位调节电路112123可以接收电位调节控制信号OVS2，并响应于电位调节控制信号OVS2的有效电平，可以将第二颜色发光器件1112的负极与参考电压端O6导通。数据驱动子电路11213包括：电位调节电路112133，且电位调节电路112133可以接收电位调节控制信号OVS3，并响应于电位调节控制信号OVS3的有效电平，可以将第三颜色发光器件1113的负极与参考电压端O6导通。
示例性地，电位调节电路可以包括开关元件，例如可以为金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)、薄膜场效应晶体管(Thin Film Transistor，TFT)等晶体管。当然，在实际应用中，电位调节电路的具体实施方式，可以根据实际应用的需求进行确定，在此不作限定。
在本公开一些实施例中，如图13至图15所示，处理控制电路1122可以包括：处理器11221和控制电路11222。其中，处理器11221可以根据接收到的像素数据信息Rda、Gda、Bda，生成与之耦接的各器件组对应的驱动控制信号并发送给各器件组对应的数据驱动子电路；处理器11221还可以根据接收到的像素数据信息以及根据预先存储的各器件组对应的电位补偿时间，生成与之耦接的各器件组对应的电流幅值控制信息和电位调节信息，提供给控制电路11222。以及，控制电路11222可以根据接收到的各器件组对应的电流幅值控制信息，生成各器件组对应的发光控制信号中的电流控制信号，以及根据接收到的各器件组对应的电位调节信息，生成各器件组对应的电位调节控制信号，并将生成的各器件组对应的电流控制信号和电位调节控制信号发送给各器件组对应的数据驱动子电路。
示例性地，结合图3、图13至图15所示，处理器11221可以根据接收到的像素数据信息Rda，生成第一颜色发光器件1111对应的驱动控制信号PWM1 和电流幅值控制信息，以及根据预先存储的第一颜色发光器件1111对应的电位补偿时间，生成第一颜色发光器件1111对应的电位调节信息；处理器11221可以根据接收到的像素数据信息Gda，生成第二颜色发光器件1112对应的驱动控制信号PWM2和电流幅值控制信息，以及根据预先存储的第二颜色发光器件1112对应的电位补偿时间，生成第二颜色发光器件1112对应的电位调节信息；处理器11221可以根据接收到的像素数据信息Bda，生成第三颜色发光器件1113对应的驱动控制信号PWM3和电流幅值控制信息，以及根据预先存储的第三颜色发光器件1113对应的电位补偿时间，生成第三颜色发光器件1113对应的电位调节信息。
之后，处理器11221将驱动控制信号PWM1发送给数据驱动子电路11211，将驱动控制信号PWM2发送给数据驱动子电路11212，将驱动控制信号PWM3发送给数据驱动子电路11213。以及，将各个颜色发光器件对应的电流幅值控制信息和电位调节信息发送给控制电路11222。控制电路11222可以根据电流幅值控制信息生成电流控制信号DAC1、DAC2、DAC3。以及，根据电位调节信息生成电位调节控制信号OVS1、OVS2、OVS3。之后，控制电路11222可以将电流控制信号DAC1和电位调节控制信号OVS1发送给数据驱动子电路11211，将电流控制信号DAC2和电位调节控制信号OVS2发送给数据驱动子电路11212，将电流控制信号DAC3和电位调节控制信号OVS3发送给数据驱动子电路11213。
数据驱动子电路11211中的电位调节电路112113可以接收电位调节控制信号OVS1，并响应于电位调节控制信号OVS1的有效电平，可以将第一颜色发光器件1111的负极与参考电压端O6导通。恒流源电路112112可以接收对应第一颜色发光器件1111的电流控制信号DAC1，并根据接收到的电流控制信号DAC1，输出对应电流控制信号DAC1的恒定幅值的电流IL1。调制电路112111可以接收对应第一颜色发光器件1111的驱动控制信号PWM1，并根据接收到的驱动控制信号PWM1的有效电平(例如高电平)，将恒流源电路112112产生的电流IL1输入耦接的输出端O1，以在工作时间段内控制第一正 极信号线至少依次经由第一颜色发光器件1111、驱动元件112的输出端O1、以及参考电压端O6形成电气回路，使第一颜色发光器件1111发光。这样可以通过驱动控制信号PWM1、电流控制信号DAC1以及电位调节控制信号OVS1的相互结合，控制第一颜色发光器件1111在显示子帧内的发光亮度以及时间。
数据驱动子电路11212中的电位调节电路112123可以接收电位调节控制信号OVS2，并响应于电位调节控制信号OVS2的有效电平，可以将第二颜色发光器件1112的负极与参考电压端O6导通。恒流源电路112122可以接收对应第二颜色发光器件1112的电流控制信号DAC2，并根据接收到的电流控制信号DAC2，输出对应电流控制信号DAC2的恒定幅值的电流IL2。调制电路112121可以接收对应第二颜色发光器件1112的驱动控制信号PWM2，并根据接收到的驱动控制信号PWM2的有效电平(例如高电平)，将恒流源电路112122产生的电流IL2输入耦接的输出端O2，以在工作时间段内控制第二正极信号线至少依次经由第二颜色发光器件1112、驱动元件112的输出端O2、以及参考电压端O6形成电气回路，使第二颜色发光器件1112发光。也就是说，驱动控制信号PWM2的有效电平的时长内，可以看作第二颜色发光器件1112处于工作时间段。这样可以通过驱动控制信号PWM2、电流控制信号DAC2以及电流控制信号DAC2相互结合，控制第二颜色发光器件1112在显示子帧内的发光亮度以及时间。
数据驱动子电路11213中的电位调节电路112133可以接收电位调节控制信号OVS3，并响应于电位调节控制信号OVS3的有效电平，可以将第三颜色发光器件1113的负极与参考电压端O6导通。恒流源电路112132可以接收对应第三颜色发光器件1113的电流控制信号DAC3，并根据接收到的电流控制信号DAC3，输出对应电流控制信号DAC3的恒定幅值的电流IL3。调制电路112131可以接收对应第三颜色发光器件1113的驱动控制信号PWM3，并根据接收到的驱动控制信号PWM3的有效电平(例如高电平)，将恒流源电路112132产生的电流IL3输入耦接的输出端O3，以在工作时间段内控制第二正 极信号线至少依次经由第三颜色发光器件1113、驱动元件112的输出端O3、以及参考电压端O6形成电气回路，使第三颜色发光器件1113发光。也就是说，驱动控制信号PWM3的有效电平的时长内，可以看作第三颜色发光器件1113处于工作时间段。这样可以通过驱动控制信号PWM3、电流控制信号DAC3以及电流控制信号DAC3相互结合，控制第三颜色发光器件1113在显示子帧内的发光亮度以及时间。
在本公开一些实施例中，电位补偿时间可以存储在处理器11221中。为了降低处理器11221的存储需求，示例性地，控制电路可以存储与之耦接的各驱动元件112对应的器件组的电位补偿时间。例如，系统电路存储与之耦接的各驱动元件112对应的器件组的电位补偿时间。以及，在电子设备开机时，系统电路将各驱动元件112对应的器件组的电位补偿时间发送给各驱动元件112。并且，驱动元件112可以在电子设备开机时，接收并存储系统电路发送的电位补偿时间；并在电子设备关机时，清空存储的电位补偿时间。示例性地，系统电路可以在显示帧F0中将各驱动元件112对应的器件组的电位补偿时间发送给各驱动元件112，驱动元件112在显示帧F0中，接收并存储系统电路发送的电位补偿时间。
在本公开一些实施例中，如图13所示，每个驱动元件112还可以包括：接口电路1123、基准电压电路1124、译码器电路1125、稳压电路1126以及静电保护电路1127中的至少一种。其中，基准电压电路1124可以确定一个固定的基准电压。静电保护电路1127可以分别与寻址信号端O5和参考电压端O6耦接，这样可以对寻址信号端O5输入的供电电压VCC和参考电压端O6输入的参考电压VSS进行静电防护。稳压电路1126可以与寻址信号端O5耦接，可以对寻址信号端O5输入的供电电压VCC进行稳压。译码器电路1125可以识别逻辑控制电路发送的驱动数据携带的地址，在识别到对应的地址时，向耦接于驱动信号端O4的接口电路1123输出数据接收信号。接口电路1123在接收到数据接收信号后，接收驱动数据，并将接收到的驱动数据进行解码后，提供给处理控制电路1122，以使处理控制电路1122根据驱动数据生成发 光控制信号。驱动元件112可以通过寻址信号端O5接收供电电压VCC，并将接收到的供电电压VCC输入接口电路1123。接口电路1123可以将接收到的供电电压进行解码后，提供给处理控制电路1122和数据驱动电路1121，以对处理控制电路1122和数据驱动电路1121供电。以及，接口电路1123可以将接收到的供电电压进行解码后，提供给基准电压电路。基准电压电路可以根据接收到的供电电压，生成参考基准电压。以及，驱动数据可以通过接口电路1123进行解码后，提供给处理控制电路1122中的处理器11221，以使处理器11221根据解码后的驱动数据，产生驱动控制信号和电流控制信号。
以下结合图3、图8至图11、以及图13至图17，对本公开实施例中的电子设备的工作过程进行详细说明。其中，以发光周期为显示子帧为例。
电子设备开机时，显示帧F0可以不显示任何画面，例如呈现出黑画面，在显示帧F0，依次执行t0阶段、t1阶段、t2阶段。其中，t0阶段和t1阶段的过程可以前述描述，在此不作赘述。在t2阶段中，电流设定信息Co中的16bits的预留控制指令位P2+P3和/或16bits的预留控制指令位P4+P5，可以携带有第一颜色发光器件1111、第二颜色发光器件1112以及第三颜色发光器件1113分别一一对应的电位补偿时间。这样可以使处理器11221将接收到的电位补偿时间进行存储。
需要说明的是，上述电位补偿时间可以是在电子设备未出厂前进行检测确定的。示例性地，确定电位补偿时间的方法可以为：控制显示面板中的各发光器件呈现特定灰阶(预先设定的一个灰阶，例如可以为低灰阶)的亮度，通过相机对点亮后的显示面板进行拍照，可以采集到显示面板各处的原始亮度数据，并且，将个发光器件所呈现的相同特定灰阶的原始亮度划分为多个区间，每个区间与一个电位补偿时间存在映射关系。对于特定灰阶，可以根据每一个发光器件对应的原始亮度数据，找到其对应的区间，进而可以确定每一个发光器件对应的电位补偿时间。例如，在显示同一个特定灰阶时，各发光器件呈现出的原始亮度可划分为8个区间：L0-L1，L1-L2，L2-L3，L3-L4，L4-L5，L5-L6，L6-L7，L7-L8。亮度范围L0-L1对应电位补偿时间0ns，亮 度范围L1-L2对应电位补偿时间5ns，亮度范围L2-L3对应电位补偿时间10ns，亮度范围L3-L4对应电位补偿时间20ns，亮度范围L4-L5对应电位补偿时间40ns，亮度范围L5-L6对应电位补偿时间50ns，亮度范围L6-L7对应电位补偿时间60ns，亮度范围L7-L8对应电位补偿时间70ns。若发光器件显示特定灰阶时的原始亮度数据对应亮度在L6-L7范围内，则可以确定该发光器件在显示特定灰阶时对应的电位补偿时间为60ns。相应地，将确定出的每一个发光器件在显示特定灰阶时对应的电位补偿时间进行存储，例如存储在系统电路300中。
本公开实施例还提供了显示驱动方法，该显示驱动方法可以应用于上述电子设备，并且，该显示驱动方法可以包括：控制正极信号线与驱动元件参考电压端在一个发光周期的工作时间段内形成电气回路。其中，在发光周期的工作时间段之前，调节与该驱动元件耦接的器件组的第二端的电位。需要说明的是，该显示驱动方法的工作原理和具体实施方式与上述实施例中电子设备的工作原理和具体实施方式基本相同，因此，该显示驱动方法的工作方法可参见上述实施例中电子设备的具体实施方式进行实施，在此不再赘述。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本公开是参照根据本公开实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的 装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (18)

  1. 一种电子设备，包括：
    多个器件组和多个驱动元件；
    所述多个器件组中的至少一个器件组的第一端与正极信号线耦接，所述多个器件组中的至少一个器件组的第二端与所述多个驱动元件中的任一个驱动元件的输出端耦接，所述多个驱动元件中的任一个驱动元件的参考电压端被配置为与参考信号线耦接；
    所述多个驱动元件中的任一个驱动元件被配置为：控制所述正极信号线与其参考电压端在一个发光周期的工作时间段内形成电气回路；以及，在所述发光周期的工作时间段之前，调节与其耦接的器件组的第二端的电位。
  2. 如权利要求1所述的电子设备，其中，所述多个驱动元件中的任一个驱动元件进一步被配置为：在所述工作时间段之前，控制与其耦接的所述器件组的第二端与其参考电压端导通第一补偿时间。
  3. 如权利要求2所述的电子设备，其中，所述多个驱动元件中的任一个驱动元件进一步被配置为：在所述第一补偿时间的结束时刻，控制所述正极信号线至少依次经由与所述驱动元件耦接的器件组、所述驱动元件的输出端、以及所述参考电压端形成电气回路。
  4. 如权利要求2或3所述的电子设备，其中，所述多个驱动元件中的任一个驱动元件还被配置为：在所述工作时间段之内，控制与其耦接的所述器件组的第二端与其参考电压端导通第二补偿时间。
  5. 如权利要求4所述的电子设备，其中，所述第一补偿时间和所述第二补偿时间为依次连续的时间段。
  6. 如权利要求5所述的电子设备，其中，对于所述多个器件组中的至少一个器件组，所述器件组对应的所述第二补偿时间小于所述第一补偿时间。
  7. 如权利要求6所述的电子设备，其中，对于所述多个器件组中的至少一个器件组，所述器件组对应的所述第二补偿时间小于所述第一补偿时间的 一半。
  8. 如权利要求7所述的电子设备，其中，所述至少一个器件组包括多个器件；
    所述多个器件中的每个器件具有各自对应的第一补偿时间和所述第二补偿时间，且所述多个器件中的每个器件对应的所述第二补偿时间小于所述第一补偿时间的一半。
  9. 如权利要求8所述的电子设备，其中，所述多个器件中的至少两个器件，其分别对应不同的第一补偿时间；其中，第一补偿时间相对更大的，其对应的第二补偿时间相对更大。
  10. 如权利要求8所述的电子设备，其中，所述多个器件中的至少部分所述器件对应的所述第二补偿时间相同。
  11. 如权利要求2-10任一项所述的电子设备，其中，所述多个驱动元件中的任一个驱动元件进一步被配置为：根据预先存储的与其耦接的器件组对应的电位补偿时间，控制与其耦接的所述器件组的第二端与其参考电压端导通所述电位补偿时间；其中，所述电位补偿时间为所述第一补偿时间；或者，所述电位补偿时间为所述第一补偿时间和所述第二补偿时间之和。
  12. 如权利要求11所述的电子设备，其中，所述多个驱动元件中的任一个所述驱动元件包括：处理控制电路以及数据驱动电路；所述数据驱动电路分别与所述处理控制电路、所述输出端以及所述参考电压端耦接；
    所述处理控制电路被配置为在所述发光周期内，生成发光控制信号，并将所述发光控制信号发送给所述数据驱动电路；以及，根据所述电位补偿时间，生成电位调节控制信号，并将所述电位调节控制信号发送给所述数据驱动电路；
    所述数据驱动电路被配置为在所述发光周期内，根据接收到的所述发光控制信号，控制所述正极信号线依次经由与所述驱动元件耦接的器件组、所述驱动元件的输出端、以及参考电压端形成电气回路；以及根据接收到的电位调节控制信号的有效电平，控制对应的所述器件组的第二端与其参考电压 端导通；其中，所述器件组对应的所述电位调节控制信号的有效电平时长为所述电位补偿时间。
  13. 如权利要求12所述的电子设备，其中，所述数据驱动电路包括：至少一个数据驱动子电路；一个所述数据驱动子电路与一个所述输出端耦接；
    所述数据驱动子电路被配置为接收耦接的所述器件组对应的发光控制信号和电位调节控制信号，以及，响应于所述发光控制信号控制所述正极信号线依次经由与所述驱动元件耦接的器件组、所述驱动元件的输出端、以及参考电压端形成电气回路；以及响应于所述电位调节控制信号，控制耦接的所述器件组的第二端与其参考电压端导通。
  14. 如权利要求13所述的电子设备，其中，所述发光控制信号包括驱动控制信号和电流控制信号；
    所述数据驱动子电路包括：调制电路、恒流源电路以及电位调节电路；其中，所述恒流源电路分别与所述处理控制电路以及所述调制电路耦接，所述调制电路与对应的输出端耦接；所述电位调节电路分别与所述处理控制电路以及对应的输出端耦接；
    所述恒流源电路被配置为接收对应的器件组的电流控制信号，并根据接收到的所述电流控制信号，输出对应所述电流控制信号的恒定幅值的电流；
    所述调制电路被配置为接收对应的器件组的驱动控制信号，并根据接收到的所述驱动控制信号的有效电平，将所述恒流源电路产生的电流输入耦接的所述输出端，以在所述工作时间段内控制所述正极信号线至少依次经由与所述驱动元件耦接的器件组、所述驱动元件的输出端、以及参考电压端形成电气回路；
    所述电位调节电路被配置为接收对应的器件组的电位调节控制信号，并根据接收到的所述电位调节控制信号控制耦接的所述器件组的第二端与其参考电压端导通。
  15. 如权利要求12-14任一项所述的电子设备，其中，所述电子设备还包括：控制电路；所述控制电路分别与所述多个驱动元件耦接；
    所述控制电路被配置为存储有的耦接的各所述驱动元件对应的所述器件组的电位补偿时间；以及，在所述电子设备开机时，将各所述驱动元件对应的所述器件组的电位补偿时间发送给各所述驱动元件；
    所述驱动元件被配置为在所述电子设备开机时，接收并存储系统电路发送的电位补偿时间；并在所述电子设备关机时，清空存储的所述电位补偿时间。
  16. 如权利要求15所述的电子设备，其中，所述多个驱动元件中的任一个驱动元件的驱动信号端被配置为与驱动信号线耦接；
    所述控制电路还被配置为与所述驱动信号线耦接，并且存储有耦接的各所述驱动元件的地址；以及向所述驱动信号线传输携带有对应所述驱动元件的地址的驱动数据；
    所述驱动元件还被配置为在识别到所述驱动数据中对应的地址时，接收所述驱动数据，并根据所述驱动数据生成所述发光控制信号。
  17. 如权利要求16所述的电子设备，其中，所述多个驱动元件中的任一个驱动元件的寻址信号端被配置为与选址信号线耦接；
    所述控制电路还被配置为与所述选址信号线耦接，并向所述选址信号线输入供电电压；
    所述驱动元件还被配置为通过所述寻址信号端接收所述供电电压。
  18. 一种显示驱动方法，应用于电子设备，所述电子设备包括多个器件组和多个驱动元件；
    所述显示驱动方法包括：
    控制所述正极信号线与其参考电压端在一个发光周期的工作时间段内形成电气回路；
    其中，在所述发光周期的工作时间段之前，调节与其耦接的器件组的第二端的电位。
PCT/CN2022/088732 2022-04-24 2022-04-24 电子设备及显示驱动方法 WO2023205935A1 (zh)

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