WO2019184071A1 - 显示装置及其阵列基板 - Google Patents

显示装置及其阵列基板 Download PDF

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Publication number
WO2019184071A1
WO2019184071A1 PCT/CN2018/087844 CN2018087844W WO2019184071A1 WO 2019184071 A1 WO2019184071 A1 WO 2019184071A1 CN 2018087844 W CN2018087844 W CN 2018087844W WO 2019184071 A1 WO2019184071 A1 WO 2019184071A1
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Prior art keywords
line
metal
layer
data line
array substrate
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PCT/CN2018/087844
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English (en)
French (fr)
Inventor
韩约白
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武汉华星光电技术有限公司
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Priority to US16/076,252 priority Critical patent/US20210082961A1/en
Publication of WO2019184071A1 publication Critical patent/WO2019184071A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to the field of display devices, and in particular, to a display device and an array substrate thereof.
  • Low-temperature polysilicon panels have become the star products in flat panel display products due to their high resolution, high mobility, low power consumption, etc., and are widely used in major mobile phones such as Apple, Samsung, Huawei, Huawei and Meizu.
  • On the tablet computer due to the complicated process of the low-temperature polysilicon device array process, multiple masks are required. Therefore, if the number of times the mask is used can be reduced in the low-temperature polysilicon process, the production cost can be effectively reduced.
  • In-Cell Touch Panel process it is generally required to perform Masks 13 times.
  • M2 is usually used in the industry to transmit touch signals, which can realize 9 Masks, but due to the excessive density of M2, Causes problems such as a decrease in aperture ratio.
  • the present invention provides a display device and an array substrate thereof, which can improve the aperture ratio of the entire display device and reduce power consumption.
  • the array substrate includes a plurality of pixel units arranged in an array, each of the pixel units including a pixel electrode, a thin film transistor, a touch electrode, a scan line, and a data a line, the scan line is disposed along a first direction, the data line is disposed along a second direction, the scan line intersects the data line, and the pixel electrode passes through the thin film transistor and the scan line and the data line Connecting, the pixel unit further includes a first metal line and a second metal line disposed along the first direction, the first metal line and the scan line are in the same layer, the second metal line and the data line Located in the same layer, the two adjacent first metal lines in the first direction are connected by the second metal line, and the first metal line is connected to the second metal line through the first via The second metal line is connected to the touch electrode through a second via.
  • the data line covers a portion of the first metal line in the first direction.
  • the first metal wire includes a vertical portion extending in the first direction and a horizontal portion extending from both ends of the vertical portion and extending toward the second direction, the data line covering the vertical portion, The horizontal portion is connected to the second metal line through the first via.
  • the horizontal portion is parallel to the scan line.
  • the second metal line is parallel to the data line.
  • the second metal line and the pixel electrode are located on both sides of the data line.
  • the second metal line is located in a display area of the array substrate.
  • the thin film transistor is of a top gate type.
  • the pixel unit includes a substrate, a first buffer layer, a light shielding layer, a second buffer layer, a polysilicon layer, a gate insulating layer, a first metal layer, a first interlayer dielectric layer, a second metal layer, and a second An interlayer dielectric layer, a touch electrode, a third interlayer dielectric layer, and a pixel electrode, wherein the first metal layer is used to form the scan line and the first metal line, and the second metal layer is used to form a The data line and the second metal line.
  • the present invention also provides a display device comprising the array substrate of any of the above.
  • the pixel unit of the array substrate provided by the present invention includes a first metal line and a second metal line disposed along a first direction, the first metal line and the scan line are located in a same layer, the second metal line and the The data lines are located in the same layer, and the two adjacent first metal lines in the first direction are connected by the second metal line, and the first metal line passes through the first via and the second metal a wire connection, the second metal wire is connected to the touch electrode through the second via hole, and the second metal wire is used as a bridge wire between the touch electrode and the first metal wire, and is transmitted through the first metal wire
  • the control signal prevents the transmission line of the touch signal from being directly disposed on the metal layer where the data line is located, so that the density of the metal layer where the data line is located is too large to limit the size of the pixel, thereby improving the aperture ratio and reducing the power consumption.
  • 1 is a schematic structural view of an array substrate
  • FIG. 2 is a schematic structural view of an array substrate not including a second metal layer in FIG. 1;
  • Figure 3 is a cross-sectional view of A in Figure 1 in a first direction
  • FIG. 4 is a schematic structural view of a display device.
  • FIG. 1 of the present embodiment is a schematic structural view of an array substrate with a non-conductive film layer, a pixel electrode and a touch electrode omitted, and FIG. 2 is a second metal layer not included in FIG. 1 .
  • FIG. 3 is a cross-sectional view of the A of FIG. 1 in a first direction.
  • the structure of the array substrate of the present embodiment will be described in detail below with reference to FIGS.
  • the array substrate 1 provided in this embodiment includes a plurality of pixel units 10 arranged in an array, each of the pixel units 10 including a pixel electrode 11, a thin film transistor 12, a touch electrode 13, a scan line 14, and a data line 15, and the scan line 14
  • the data line 15 is disposed along the second direction
  • the scan line 14 intersects the data line 15
  • the pixel electrode 11 is connected to the scan line 14 and the data line 15 through the thin film transistor 12
  • the pixel unit 10 further includes a first direction
  • the first metal line 16 and the second metal line 17, the first metal line 16 and the scan line 14 are in the same layer
  • the second metal line 17 and the data line 15 are in the same layer
  • a metal wire 16 is connected between the second metal wires 17, the first metal wire 16 is connected to the second metal wire 17 through the first via hole 20, and the second metal wire 17 is connected to the touch electrode 13 through the second via hole 21.
  • the first direction is the x-axis direction in FIG. 1
  • the second direction is the y-axis direction in FIG. 1
  • the first direction is perpendicular to the second direction
  • the plurality of scanning lines 14 arranged in the first direction are arranged in the second direction.
  • the plurality of data lines 15 intersect and form a plurality of pixel units 10 arranged in an array in a grid shape, and a pixel unit 10 is formed in a region where each grid is located.
  • the array substrate 1 includes a display area and a non-display area, wherein the area where the thin film transistor 12 is located is a non-display area of the array substrate 1.
  • the pixel electrode 11 and the touch electrode 13 in this embodiment are both transparent electrodes.
  • the touch electrode 13 is configured to receive the touch signal and transmit the touch signal to the second metal line 17 through the second via 21, and the second metal line 17 transmits the touch signal to the first metal through the first via 20
  • the line 16 and the second metal line 17 serve as a bridge between the touch electrode 13 and the first metal line 16 , and the touch signal is transmitted through the first metal line 16 to prevent the transmission line of the touch signal from being directly disposed on the data line 15 .
  • the density of the metal layer where the data line 15 is located is too large to limit the size of the pixel, thereby increasing the aperture ratio and reducing power consumption.
  • the data line 15 covers the portion of the first metal line 16 in the first direction, that is, the projection of the data line 15 in the plane of the first metal line 16 coincides with the portion of the first metal line 16 on the x-axis.
  • the first metal line 16 does not affect the size of the pixels of the array substrate 1, thereby further increasing the aperture ratio and reducing power consumption.
  • the first metal wire 16 includes a vertical portion 16a extending in the first direction and a horizontal portion 16b bent from both ends of the vertical portion 16a toward the second direction, and the data line 15 covers the vertical portion 16a, that is, the data line
  • the projection in the plane in which the first metal line 16 is located coincides with the vertical portion 16a.
  • the horizontal portion 16b is connected to the second metal wire 17 through the first via hole 20.
  • the second metal wires 17 are respectively connected to the adjacent two first metal wires 16 in the first direction through the via holes 20.
  • the horizontal portion 16b is parallel to the scanning line 14, the second metal line 17 is parallel to the data line 15, and the second metal line 17 is bridged with the scanning line 14.
  • the second metal line 17 and the pixel electrode 11 are located on both sides of the data line 15.
  • the second metal line 17 is located in the display area of the array substrate 1.
  • the thin film transistor 12 in this embodiment is of a top gate type.
  • the pixel unit 10 includes a substrate 22, a first buffer layer 23, a light shielding layer 24, a second buffer layer 25, a polysilicon layer 26, a gate insulating layer 27, and a first A metal layer 31, a first interlayer dielectric layer 28, a second metal layer 32, a second interlayer dielectric layer 29, a touch electrode 13, a third interlayer dielectric layer 33, and a pixel electrode 11.
  • the first buffer layer 23 is disposed on the substrate 22, the light shielding layer 24 is disposed on the first buffer layer 23, and the second buffer layer 25 is disposed on the first buffer layer 23 and covers the light shielding layer 24.
  • the polysilicon layer 26 is disposed on the second buffer layer 25, and the gate insulating layer 27 is disposed on the second buffer layer 25 and covers the polysilicon layer 26.
  • the first metal layer 31 is disposed on the gate insulating layer 27 for forming the first metal line 16 and the scan line 14.
  • the scan line 14 serves as the gate of the thin film transistor 12, and the first interlayer dielectric layer 28 covers the first metal layer. 31.
  • the second metal layer 32 is disposed on the first interlayer dielectric layer 28, and the second metal layer 32 is used to form the second metal line 17 and the data line 15.
  • the second interlayer dielectric layer 29 is disposed on the second metal layer 32.
  • the touch electrode 13 is disposed on the second interlayer dielectric layer 29.
  • the third interlayer dielectric layer 31 covers the touch electrode 13.
  • the pixel electrode 11 is disposed on the second layer. On the three-layer dielectric layer 31.
  • the source of the thin film transistor 12 is connected to the data line, and the drain of the thin film transistor 12 is connected to the pixel electrode 11.
  • This embodiment further provides a display device, which may be an LCD or an OLED. There is no limit here.
  • the display device is an LCD, and the display device includes an array substrate 1 , a CF substrate 2 , and a liquid crystal layer 3 .
  • the array substrate 1 and the CF substrate 2 are disposed on the cell, and the liquid crystal layer 3 is disposed on the array substrate 1 and the CF substrate.
  • the display device can increase the aperture ratio of the entire display device and reduce the power consumption of the display device by using the array substrate 1 described above.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • General Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种显示装置及其阵列基板，所述阵列基板包括呈阵列设置的多个像素单元，每一个像素单元包括像素电极、薄膜晶体管、触控电极、扫描线及数据线，扫描线沿第一方向设置，数据线沿第二方向设置，扫描线与数据线交叉，像素电极通过薄膜晶体管与扫描线、数据线连接，像素单元还包括沿第一方向设置的第一金属线和第二金属线，第一金属线与扫描线位于同一层，第二金属线与数据线位于同一层，在第一方向上的相邻两个第一金属线之间通过第二金属线连接，第一金属线通过第一过孔与第二金属线连接，第二金属线通过第二过孔与触控电极连接。本发明的阵列基板能够避免将触控信号的传输线直接设置在数据线所在的金属层上而限制像素的大小。

Description

显示装置及其阵列基板 技术领域
本发明涉及显示装置技术领域，尤其涉及一种显示装置及其阵列基板。
背景技术
低温多晶硅面板借着其高分辨率、高迁移率、低功耗等诸多优点已成为了目前平板显示产品中的明星产品，被广泛应用在例如苹果、三星、华为、小米、魅族等各大手机及平板电脑上，由于低温多晶硅器件阵列工艺制程复杂，需要多次光罩(Mask)，因此，在低温多晶硅制程中如果能够降低光罩使用次数将会有效的降低生产成本。在目前生产的In-Cell Touch Panel工艺过程中，一般需要13次Mask，而为了节约成本，目前行业内通常使用M2传递触控信号，可实现9次Mask，但由于M2密度过大，将会造成开口率降低等问题。
发明内容
为了解决上述问题，本发明提供一种显示装置及其阵列基板，能够提升整个显示装置的开口率、降低功耗。
本发明提出的具体技术方案为：提供一种阵列基板，所述阵列基板包括呈阵列设置的多个像素单元，每一个所述像素单元包括像素电极、薄膜晶体管、触控电极、扫描线及数据线，所述扫描线沿第一方向设置，所述数据线沿第二方向设置，所述扫描线与所述数据线交叉，所述像素电极通过所述薄膜晶体管与所述扫描线、数据线连接，所述像素单元还包括沿第一方向设置的第一金属线和第二金属线，所述第一金属线与所述扫描线位于同一层，所述第二金属线与所述数据线位于同一层，在第一方向上的相邻两个所述第一金属线之间通过所述第二金属线连接，所述第一金属线通过第一过孔与所述第二金属线连接，所述第二金属线通过第二过孔与所述触控电极连接。
进一步地，所述数据线覆盖所述第一金属线位于第一方向上的部分。
进一步地，所述第一金属线包括沿第一方向延伸的垂直部以及由所述垂直部的两端朝向第二方向弯折延伸出的水平部，所述数据线覆盖所述垂直部，所述水平部通过第一过孔与所述第二金属线连接。
进一步地，所述水平部与所述扫描线平行。
进一步地，所述第二金属线与所述数据线平行。
进一步地，所述第二金属线与所述像素电极位于所述数据线的两侧。
进一步地，所述第二金属线位于所述阵列基板的显示区域内。
进一步地，所述薄膜晶体管为顶栅型。
进一步地，所述像素单元包括衬底、第一缓冲层、遮光层、第二缓冲层、多晶硅层、栅绝缘层、第一金属层、第一层间介质层、第二金属层、第二层间介质层、触控电极、第三层间介质层及像素电极，所述第一金属层用于形成所述扫描线和所述第一金属线，所述第二金属层用于形成所述数据线和所述第二金属线。
本发明还提供了一种显示装置，所述显示装置包括如上任一所述的阵列基板。
本发明提出的阵列基板的像素单元包括沿第一方向设置的第一金属线和第二金属线，所述第一金属线与所述扫描线位于同一层，所述第二金属线与所述数据线位于同一层，在第一方向上的相邻两个所述第一金属线之间通过所述第二金属线连接，所述第一金属线通过第一过孔与所述第二金属线连接，所述第二金属线通过第二过孔与所述触控电极连接，将第二金属线作为触控电极与第一金属线之间的桥接线，通过第一金属线来传递触控信号，避免将触控信号的传输线直接设置在数据线所在的金属层上，造成数据线所在的金属层的密度过大而限制像素的大小，从而提升了开口率、降低功耗。
附图说明
图1为阵列基板的结构示意图；
图2为图1中不包括第二金属层的阵列基板的结构示意图；
图3为图1中的A处在第一方向上的截面图；
图4为显示装置的结构示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。在附图中，相同的标号将始终被用于表示相同的元件。
参照图1、图2及图3，本实施例的图1为省略了不导电膜层及像素电极和触控电极的阵列基板的结构示意图，图2为图1中不包括第二金属层的阵列基板的结构示意图，图3为图1中的A处在第一方向上的截面图。下面参照图1-3对本实施例的阵列基板的结构进行详细的描述。
本实施例提供的阵列基板1包括呈阵列设置的多个像素单元10，每一个像素单元10包括像素电极11、薄膜晶体管12、触控电极13、扫描线14及数据线15，扫描线14沿第一方向设置，数据线15沿第二方向设置，扫描线14与数据线15交叉，像素电极11通过薄膜晶体管12与扫描线14、数据线15连接，像素单元10还包括沿第一方向设置的第一金属线16和第二金属线17，第一金属线16与扫描线14位于同一层，第二金属线17与数据线15位于同一层，在第一方向上的相邻两个第一金属线16之间通过第二金属线17连接，第一金属线16通过第一过孔20与第二金属线17连接，第二金属线17通过第二过孔21与触控电极13连接。
第一方向为图1中的x轴方向，第二方向为图1中的y轴方向，第一方向与第二方向垂直，沿第一方向排列的多个扫描线14与沿第二方向排列的多个数据线15交叉并呈网格状形成阵列排布的多个像素单元10，每一个网格所在区域形成一个像素单元10。阵列基板1包括显示区域和非显示区域，其中，薄膜晶体管12所在的区域为阵列基板1的非显示区域。本实施例中的像素电极11和触控电极13都为透明电极。
触控电极13用于接收触控信号并通过第二过孔21将触控信号传递给第二金属线17，第二金属线17再通过第一过孔20将触控信号传递给第一金属线16，第二金属线17作为触控电极13与第一金属线16之间的桥接线，通过第一金属线 16来传递触控信号，避免将触控信号的传输线直接设置在数据线15所在的金属层上，造成数据线15所在的金属层的密度过大而限制像素的大小，从而提升了开口率、降低功耗。
较佳地，数据线15覆盖第一金属线16位于第一方向上的部分，即数据线15在第一金属线16所在的平面内的投影与第一金属线16位于x轴上的部分重合。这样，第一金属线16不会影响阵列基板1的像素的大小，从而进一步地提升了开口率、降低功耗。
具体地，第一金属线16包括沿第一方向延伸的垂直部16a以及由垂直部16a的两端朝向第二方向弯折延伸出的水平部16b，数据线15覆盖垂直部16a，即数据线15在第一金属线16所在的平面内的投影与垂直部16a重合。水平部16b通过第一过孔20与第二金属线17连接。第二金属线17通过过孔20分别与在第一方向上的相邻两个第一金属线16连接。
水平部16b与扫描线14平行，第二金属线17与数据线15平行，第二金属线17与扫描线14跨接。第二金属线17与像素电极11位于数据线15的两侧。第二金属线17位于阵列基板1的显示区域内。
本实施例中的薄膜晶体管12为顶栅型，具体地，像素单元10包括衬底22、第一缓冲层23、遮光层24、第二缓冲层25、多晶硅层26、栅绝缘层27、第一金属层31、第一层间介质层28、第二金属层32、第二层间介质层29、触控电极13、第三层间介质层33及像素电极11。
第一缓冲层23设置于衬底22上，遮光层24设置于第一缓冲层23上，第二缓冲层25设置于第一缓冲层23上并覆盖遮光层24。多晶硅层26设置于第二缓冲层25上，栅绝缘层27设置于第二缓冲层25上并覆盖多晶硅层26。第一金属层31设置于栅绝缘层27上，其用于形成第一金属线16和扫描线14，扫描线14作为薄膜晶体管12的栅极，第一层间介质层28覆盖第一金属层31，第二金属层32设置于第一层间介质层28上，第二金属层32用于形成第二金属线17和数据线15。第二层间介质层29覆盖于第二金属层32上，触控电极13设置于第二层间介质层29上，第三层间介质层31覆盖触控电极13，像素电极11设置于第三层间介质层31上。薄膜晶体管12的源极与数据线连接，薄膜晶体管12的漏极与像素电极11连接。
本实施例还提供了一种显示装置，该显示装置可以是LCD，也可以是OLED。这里不做限定。
参照图4，以显示装置为LCD为例，显示装置包括阵列基板1、CF基板2及液晶层3，阵列基板1与CF基板2对盒设置，液晶层3夹设于阵列基板1与CF基板2之间，显示装置通过采用上述阵列基板1可以提升整个显示装置的开口率、降低显示装置的功耗。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (18)

  1. 一种阵列基板，其中，包括呈阵列设置的多个像素单元，每一个所述像素单元包括像素电极、薄膜晶体管、触控电极、扫描线及数据线，所述扫描线沿第一方向设置，所述数据线沿第二方向设置，所述扫描线与所述数据线交叉，所述像素电极通过所述薄膜晶体管与所述扫描线、数据线连接，所述像素单元还包括沿第一方向设置的第一金属线和第二金属线，所述第一金属线与所述扫描线位于同一层，所述第二金属线与所述数据线位于同一层，在第一方向上的相邻两个所述第一金属线之间通过所述第二金属线连接，所述第一金属线通过第一过孔与所述第二金属线连接，所述第二金属线通过第二过孔与所述触控电极连接。
  2. 根据权利要求1所述的阵列基板，其中，所述数据线覆盖所述第一金属线位于第一方向上的部分。
  3. 根据权利要求2所述的阵列基板，其中，所述第一金属线包括沿第一方向延伸的垂直部以及由所述垂直部的两端朝向第二方向弯折延伸出的水平部，所述数据线覆盖所述垂直部，所述水平部通过第一过孔与所述第二金属线连接。
  4. 根据权利要求3所述的阵列基板，其中，所述水平部与所述扫描线平行。
  5. 根据权利要求1所述的阵列基板，其中，所述第二金属线与所述数据线平行。
  6. 根据权利要求1所述的阵列基板，其中，所述第二金属线与所述像素电极位于所述数据线的两侧。
  7. 根据权利要求6所述的阵列基板，其中，所述第二金属线位于所述阵列基板的显示区域内。
  8. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管为顶栅型。
  9. 根据权利要求7所述的阵列基板，其中，所述像素单元包括衬底、第一缓冲层、遮光层、第二缓冲层、多晶硅层、栅绝缘层、第一金属层、第一层间介质层、第二金属层、第二层间介质层、触控电极、第三层间介质层及像素电 极，所述第一金属层用于形成所述扫描线和所述第一金属线，所述第二金属层用于形成所述数据线和所述第二金属线。
  10. 一种显示装置，其中，包括阵列基板，所述阵列基板包括呈阵列设置的多个像素单元，每一个所述像素单元包括像素电极、薄膜晶体管、触控电极、扫描线及数据线，所述扫描线沿第一方向设置，所述数据线沿第二方向设置，所述扫描线与所述数据线交叉，所述像素电极通过所述薄膜晶体管与所述扫描线、数据线连接，所述像素单元还包括沿第一方向设置的第一金属线和第二金属线，所述第一金属线与所述扫描线位于同一层，所述第二金属线与所述数据线位于同一层，在第一方向上的相邻两个所述第一金属线之间通过所述第二金属线连接，所述第一金属线通过第一过孔与所述第二金属线连接，所述第二金属线通过第二过孔与所述触控电极连接。
  11. 根据权利要求10所述的显示装置，其中，所述数据线覆盖所述第一金属线位于第一方向上的部分。
  12. 根据权利要求11所述的显示装置，其中，所述第一金属线包括沿第一方向延伸的垂直部以及由所述垂直部的两端朝向第二方向弯折延伸出的水平部，所述数据线覆盖所述垂直部，所述水平部通过第一过孔与所述第二金属线连接。
  13. 根据权利要求12所述的显示装置，其中，所述水平部与所述扫描线平行。
  14. 根据权利要求10所述的显示装置，其中，所述第二金属线与所述数据线平行。
  15. 根据权利要求10所述的显示装置，其中，所述第二金属线与所述像素电极位于所述数据线的两侧。
  16. 根据权利要求15所述的显示装置，其中，所述第二金属线位于所述阵列基板的显示区域内。
  17. 根据权利要求10所述的显示装置，其中，所述薄膜晶体管为顶栅型。
  18. 根据权利要求16所述的显示装置，其中，所述像素单元包括衬底、第一缓冲层、遮光层、第二缓冲层、多晶硅层、栅绝缘层、第一金属层、第一层 间介质层、第二金属层、第二层间介质层、触控电极、第三层间介质层及像素电极，所述第一金属层用于形成所述扫描线和所述第一金属线，所述第二金属层用于形成所述数据线和所述第二金属线。
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