WO2017059752A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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WO2017059752A1
WO2017059752A1 PCT/CN2016/096887 CN2016096887W WO2017059752A1 WO 2017059752 A1 WO2017059752 A1 WO 2017059752A1 CN 2016096887 W CN2016096887 W CN 2016096887W WO 2017059752 A1 WO2017059752 A1 WO 2017059752A1
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data lines
array substrate
data
integrated circuit
lines
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PCT/CN2016/096887
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English (en)
French (fr)
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栗峰
王宝强
朴相镇
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/329,513 priority Critical patent/US10141347B2/en
Publication of WO2017059752A1 publication Critical patent/WO2017059752A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to an array substrate and a display device.
  • the existing display device Due to the lateral distribution of the eyes of the person, in order to adapt to the human eye, the existing display device generally adopts a wide-screen display panel, that is, the length of the long side of the display panel is significantly larger than the length of the wide side.
  • the display panel is provided with a plurality of gate lines parallel to the long sides and a plurality of data lines parallel to the wide sides, wherein the integrated circuit for transmitting data signals to the data lines is located in the frame of the long side, and the integration of the scanning signals is transmitted to the gate lines.
  • the circuit is in the border of the wide side. Since the human eye is different in sensitivity to the long side border and the wide side border, in the actual viewing process, for the long side border of the same width and the wide side border, the human eye is more likely to feel the long side border interference. Viewing, and the presence of an integrated circuit that transmits data signals to the data lines makes it difficult to reduce the width of the long side frame.
  • the technical problem to be solved by the present invention is how to reduce the width of the frame of the long side in the array substrate.
  • an array substrate comprising: a plurality of first data lines parallel to a broad side of the array substrate; and a plurality of second data lines parallel to a long side of the array substrate; a first integrated circuit disposed in the frame of the wide side; wherein the plurality of second data lines are connected to the first integrated circuit and the plurality of first data lines; The second data line transmits data signals to the plurality of first data lines.
  • a display device comprising the above array substrate.
  • FIG. 1 shows a schematic view of an array substrate in accordance with one embodiment of the present invention
  • Figure 2 is a schematic view showing the structure in the dotted line of Figure 1;
  • FIG. 3 is a schematic view showing an array substrate according to another embodiment of the present invention.
  • FIG. 4 is a schematic view showing an array substrate according to still another embodiment of the present invention.
  • FIG. 5 shows a schematic diagram of an array substrate according to still another embodiment of the present invention.
  • an array substrate includes: a plurality of first data lines 1 extending parallel to the wide side 10, that is, extending in a vertical direction; and a plurality of second data lines 2, Parallel to the long side 20, that is, extending in the horizontal direction; the first integrated circuit 3 is disposed in the bezel 11 of the wide side, and the plurality of second data lines 2 are used for connecting the first integrated circuit 3 and the plurality of first data Line 1; the first integrated circuit 3 transmits data signals to the plurality of first data lines 1 through the plurality of second data lines 2.
  • the first data line 1 and the second data line 2 are perpendicular to each other.
  • the integrated circuit By placing the first integrated circuit 3 transmitting the data signal to the first data line 1 on the side of the wide side In the frame 11, the integrated circuit is no longer disposed in the frame of the long side, so that the frame width of the long side can be reduced, and the viewing effect of the user is improved.
  • the array substrate further includes: m gate lines 4 parallel to the long side 20 for transmitting a scan signal to each pixel, wherein the plurality of second data lines 2 are m second data lines 2 Each of the second data lines 2 is parallel to the gate line 4.
  • the number of the second data lines 2 may be set equal to the number of the gate lines 4, and the second data lines 2 may be further disposed in parallel with the gate lines 4, for example, in each of the gate lines 4.
  • a second data line 2 is disposed on one side.
  • the array substrate further includes a source drain, and the plurality of first data lines 1 are n first data lines 1, wherein the n first data lines 1 are in the same layer as the source and drain, m strips
  • the two data lines 2 are located in the same layer as the m gate lines 4, and a gate insulating layer is disposed between the n first data lines 1 and the m second data lines 2, and the first data line 1 and the second data line 2 pass The via holes in the gate insulating layer are connected.
  • the first data line 1 and the source and drain electrodes By disposing the first data line 1 and the source and drain electrodes in the same layer and the second data line 2 and the gate line 4 in the same layer, the first data line can be formed when the source and drain electrodes are formed, when the gate line 4 is formed.
  • the first data line 1 is formed to facilitate the simplification of the fabrication process.
  • n of the second data lines 2 of the second data lines 2 are connected to the n first data lines 1 and the other second of the m second data lines 2 Data line 2 is left floating.
  • At least one second data line 2 is required to correspond to one first data line 1, that is, m ⁇ n.
  • the gate line in this embodiment may adopt a Triple Gate structure, that is, an array substrate with a resolution of p*q, wherein the number of gate lines is 3q, and for a general array substrate, 3q>p, that is, m>n Therefore, the n second data lines 2 of the m second data lines 2 may be correspondingly connected to the n first data lines, so that the first integrated circuit 3 can normally pass through the n second data lines 2 to n.
  • the first data line 1 transmits a data signal.
  • a second data line 2 that is suspended is placed every second predetermined number (at least one) of the second data lines 2.
  • at least one second data line 2 connected to the first data line 1 is disposed between adjacent two suspended second data lines.
  • the suspended second data line 2 Since the suspended second data line 2 is not electrically connected to other lines, no signal is transmitted and heat is not generated. Therefore, setting a suspended second data line 2 every second predetermined number of data lines 2 can reduce the concentrated heat generation of the plurality of second data lines 2.
  • n of the second data lines 2 of the second data lines 2 are connected one by one to the n first data lines 1, and the other of the m second data lines 2
  • Two data lines 2 (as shown in Figure 5):
  • Each of the two second data lines 2 of the x 2 second data lines 2 is connected to each of the first data lines 1 of the n 2 first data lines 1, each of the n 2 first data lines 1
  • the distance from the first data line to the first integrated circuit 3 is less than the first distance D1 and greater than or equal to the second distance D2,
  • Each of the 1 x n lines per second data of second data lines y n 2 n i is connected to the first data lines in each of the first data line 2 1, the first data lines n i
  • the distance from the first data line to the first integrated circuit 3 is less than the n-1th distance and greater than or equal to the nth distance
  • y n is an integer divisible by x n
  • n is an integer greater than 1
  • x 1 + x 2 +... + x n mn
  • n 1 + n 2 + ...+n i n.
  • the second data line may be connected to a portion of the first data that is farther away from the first integrated circuit 3, so that the first integrated circuit 3 reaches the resistance and arrival of the farther first data line 1.
  • the resistance of the closer first data line 1 is similar to reduce the delay of the data signal reaching the farther first data line 1.
  • each of the first data lines 1 may be connected to three second data lines 2; a portion of the first data line of the first integrated circuit 3 that is farther (less than the first distance D1 and greater than or equal to the second distance D2), each of the first data lines 1 may be connected to two second data lines 2; A portion of the first data line of the circuit 3 closest (less than the second distance D2), and each of the first data lines 1 may be connected to a second data line 2.
  • the n second data lines 2 and n are After the first data lines 1 are connected one by one, it can be ensured that the first integrated circuit 3 can normally transmit data signals to the n first data lines 1 through the n second data lines 2.
  • a plurality of second data lines 2 may be connected to the first data line 1 that is far from the first integrated circuit 3, and a second data line 1 that is closer to the first integrated circuit 3 is connected to the second data line. 2, such that the resistance of the first integrated circuit 3 reaching the farther first data line 1 is close to the resistance of the first data line 1 reaching the closer, to reduce the delay of the data signal reaching the farther first data line 1 .
  • the embodiment is only an example, and the number of the second data lines 2 connected to the first data line 1 may be set according to specific needs. For example, as shown in FIG. 3, each of the first integrated circuits 3 may be farther away.
  • the first data line 1 is connected to the two second data lines 2, and a second data line 2 is connected to each of the first data lines 1 which are closer to the first integrated circuit 3.
  • m n
  • m second data lines 2 are connected to the n first data lines 1 one by one.
  • the array substrate further includes: a second integrated circuit 5 disposed in a frame opposite the wide side of the first integrated circuit 3 for transmitting a scan signal to the gate line 4. .
  • the widths of the left and right sides of the array substrate are balanced.
  • first integrated circuits 3 each of which transmits a data signal to a predetermined number of second data lines 2 that are less than a predetermined distance apart.
  • each of the first integrated circuits 3 can be connected to the second data line 2 that is closer to the second integrated circuit 3, so that the distance between each of the first integrated circuits 3 to the second data lines 2 is not too far, and the data is reduced.
  • the transmission delay of the signal is not too far, and the data is reduced.
  • the embodiment of the invention further provides a display device comprising the array substrate of any of the above.
  • the display device in this embodiment may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • the long-side frame in the wide-screen display screen is more likely to affect the user's viewing experience, and the existence of the integrated circuit due to the transmission of data signals to the data line So that the width of the border of the long side is difficult to reduce.
  • the first scheme of transmitting the data signal to the data line is disposed in the frame of the wide side, so that the integrated circuit is no longer disposed in the frame of the long side, thereby reducing the width of the border of the long side, thereby improving the viewing effect of the user. .

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Abstract

提供一种阵列基板和显示装置。该阵列基板包括：多条第一数据线（1），平行于阵列基板的宽边（10）；多条第二数据线（2），平行于阵列基板的长边（20）；第一集成电路（3），设置在宽边（10）的边框（11）中；其中，多条第二数据线（2）连接第一集成电路（3）和多条第一数据线（1）；第一集成电路（3）通过多条第二数据线（2）向多条第一数据线（1）传输数据信号。通过将向数据线传输数据信号的第一集成电路设置在宽边的边框中，使得长边的边框中不再设置集成电路，便于降低长边的边框宽度，从而提高用户的观看效果。

Description

阵列基板和显示装置 技术领域
本发明实施例涉及显示技术领域，具体而言，涉及一种阵列基板和一种显示装置。
背景技术
由于人的双眼横向分布，为了适应人眼观看，现有的显示装置一般采用宽屏的显示面板，即显示面板的长边长度明显大于宽边长度。
显示面板中分布有多条与长边平行的栅线和多条与宽边平行的数据线，其中向数据线传输数据信号的集成电路位于长边的边框中，向栅线传输扫描信号的集成电路位于宽边的边框中。由于人眼对于长边的边框和宽边的边框敏感程度是不同的，在实际观看过程中，对于相同宽度的长边的边框以及宽边的边框，人眼更容易感觉到长边的边框干扰观看，而由于向数据线传输数据信号的集成电路的存在，使得长边的边框宽度难以降低。
发明内容
本发明所要解决的技术问题是，如何降低阵列基板中长边的边框宽度。
根据本发明第一方面，提出了一种阵列基板，包括：多条第一数据线，平行于所述阵列基板的宽边；多条第二数据线，平行于所述阵列基板的长边；第一集成电路，设置在所述宽边的边框中；其中，所述多条第二数据线连接所述第一集成电路和所述多条第一数据线；所述第一集成电路通过多条第二数据线向多条第一数据线传输数据信号。
根据本发明第二方面，还提出了一种显示装置，包括上述的阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1示出了根据本发明一个实施例的阵列基板的示意图；
图2示出了图1中虚线内的结构示意图；
图3示出了根据本发明另一个实施例的阵列基板的示意图；
图4示出了根据本发明又一个实施例的阵列基板的示意图；
图5示出了根据本发明再一个实施例的阵列基板的示意图
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
如图1和图2所示，根据本发明一个实施例的阵列基板，包括：多条第一数据线1，平行于宽边10，即沿竖直方向延伸；多条第二数据线2，平行于长边20，即沿水平方向延伸；第一集成电路3，设置在宽边的边框11中，所述多条第二数据线2用于连接第一集成电路3和多条第一数据线1；第一集成电路3通过多条第二数据线2向多条第一数据线1传输数据信号。第一数据线1与第二数据线2相互垂直。
通过将向第一数据线1传输数据信号的第一集成电路3设置在宽边的边 框11中，使得长边的边框中不再设置集成电路，从而可以降低长边的边框宽度，提高用户的观看效果。
至少一些实施例中，阵列基板还包括：m条栅线4，平行于长边20，用于向每个像素传输扫描信号，其中，多条第二数据线2为m条第二数据线2，每条第二数据线2与栅线4平行。
在本实施例中，可以将第二数据线2的数量设置为与栅线4的数量相等，进一步可以将第二数据线2设置为与栅线4平行，例如可以在每条栅线4的一侧设置一条第二数据线2。
至少一些实施例中，阵列基板还包括源漏极，多条第一数据线1为n条第一数据线1，其中，n条第一数据线1与源漏极位于同一层，m条第二数据线2与m条栅线4位于同一层，在n条第一数据线1和m条第二数据线2之间设置有栅绝缘层，第一数据线1和第二数据线2通过栅绝缘层中的过孔相连。
通过将第一数据线1与源漏极设置在同一层，将第二数据线2与栅线4设置在同一层，可以在形成源漏极时形成第一数据线，在形成栅线4时形成第一数据线1，便于简化制作工艺。
至少一些实施例中，m>n，m条第二数据线2中的n条第二数据线2一一对应连接n条第一数据线1，m条第二数据线2中的其他第二数据线2悬空设置。
为了保证每条第一数据线1能够正常向像素传输数据信号，至少要保证一条第二数据线2对应一条第一数据线1，也即要保证m≥n。
本实施例中的栅线可以采用Triple Gate结构，也即对于分辨率为p*q的阵列基板，其中栅线的数量为3q，而对于一般阵列基板而言3q>p，也即m>n，因此可以设置m条第二数据线2中的n条第二数据线2对应连接至n条第一数据线，以使得第一集成电路3可以正常地通过n条第二数据线2向n条第一数据线1传输数据信号。
至少一些实施例中，每隔预设条数(至少一条)的第二数据线2设置一条悬空的第二数据线2。换言之，相邻两条悬空的第二数据线之间设置至少一条与所述第一数据线1相连的第二数据线2。
由于悬空的第二数据线2不与其他线路导通，不传输信号，也不会发热。因此每隔预设条数的第二数据线2设置一条悬空的第二数据线2可以降低多条第二数据线2的集中发热量。
至少一些实施例中，m>n，m条第二数据线2中的n条第二数据线2一一对应连接n条第一数据线1，在m条第二数据线2中的其他第二数据线2中(如图5所示)：
x1条第二数据线2中每y1条第二数据线2连接至n1条第一数据线1中的每条第一数据线，该n1条第一数据线1中的每条第一数据线到所述第一集成电路3的距离大于或等于第一距离D1，
x2条第二数据线2中每y2条第二数据线2连接至n2条第一数据线1中的每条第一数据线，该n2条第一数据线1中的每条第一数据线到所述第一集成电路3的距离小于第一距离D1且大于或等于第二距离D2，
…
xn条第二数据线2中每yn条第二数据线2连接至ni条第一数据线1中的每条第一数据线，该ni条第一数据线1中的每条第一数据线到所述第一集成电路3的距离小于第n-1距离且大于或等于第n距离，
其中，xn和i均为大于0的整数，yn为可整除xn的整数，n为大于1的整数，x1+x2+…+xn＝m-n，并且n1+n2+…+ni＝n。
在本实施例中，可以为距离第一集成电路3越远的部分第一数据连接越多的第二数据线，从而使得第一集成电路3到达较远的第一数据线1的电阻与到达较近的第一数据线1的电阻相近，以减小数据信号到达较远的第一数据线1的延迟。
例如，如图5所示，对于距离第一集成电路3最远(大于等于第一距离D1)的部分第一数据线，每条第一数据线1可以连接三条第二数据线2；对于距离第一集成电路3较远(小于第一距离D1且大于等于第二距离D2)的部分第一数据线，每条第一数据线1可以连接两条第二数据线2；对于距离第一集成电路3最近(小于第二距离D2)的部分第一数据线，每条第一数据线1可以连接一条第二数据线2。
在第二数据线2多于第一数据线1的情况下，在将n条第二数据线2与n 条第一数据线1一一对应连接后，即可保证第一集成电路3可以正常地通过n条第二数据线2向n条第一数据线1传输数据信号。
例如，可以为距离第一集成电路3较远的第一数据线1连接较多的第二数据线2，距离第一集成电路3较近的第一数据线1连接较少的第二数据线2，从而使得第一集成电路3到达较远的第一数据线1的电阻与到达较近的第一数据线1的电阻相近，以减小数据信号到达较远的第一数据线1的延迟。
当然，本实施例仅是一种示例，可以根据具体需要设置为第一数据线1连接第二数据线2的条数，例如图3所示，可以为距离第一集成电路3较远的每条第一数据线1连接两条第二数据线2，为距离第一集成电路3较近的每条第一数据线1连接一条第二数据线2。
至少一些实施例中，m＝n，m条第二数据线2一一对应连接n条第一数据线1。
如图4所示，至少一些实施例中，阵列基板还包括：第二集成电路5，设置在与第一集成电路3所在宽边相对宽边的边框中，用于向栅线4传输扫描信号。
由于第一集成电路3和第二集成电路5不设置在一侧宽边的边框11中，保证阵列基板左右两侧边框宽度较为平衡。
至少一些实施例中，第一集成电路3为多个，每个第一集成电路3向与其相距小于预设距离的预设数目的第二数据线2传输数据信号。
本实施例中，每个第一集成电路3可以与距离其较近的第二数据线2相连，从而使得每个第一集成电路3到第二数据线2的距离不会过远，降低数据信号的传输延迟。
本发明实施例还提出了一种显示装置，包括上述任一项的阵列基板。
需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上结合附图详细说明了本发明的技术方案，考虑到现有技术中，宽屏显示屏中的长边的边框更容易影响用户的观看体验，而由于向数据线传输数据信号的集成电路的存在，使得长边的边框宽度难以降低。根据本发明的技 术方案，通过将向数据线传输数据信号的第一集成电路设置在宽边的边框中，使得长边的边框中不再设置集成电路，便于降低长边的边框宽度，从而提高用户的观看效果。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请基于并且要求于2015年10月8日递交的中国专利申请第201510644208.1号的优先权，在此全文引用上述中国专利申请公开的内容。

Claims (12)

  1. 一种阵列基板，包括：
    多条第一数据线，平行于所述阵列基板的宽边；
    多条第二数据线，平行于所述阵列基板的长边；
    第一集成电路，设置在所述宽边的边框中；
    其中，所述多条第二数据线连接所述第一集成电路和所述多条第一数据线；所述第一集成电路通过多条第二数据线向多条第一数据线传输数据信号。
  2. 根据权利要求1所述的阵列基板，还包括：
    多条栅线，平行于所述阵列基板的长边，用于向阵列基板上的每个像素传输扫描信号，每条第二数据线与栅线平行。
  3. 根据权利要求2所述的阵列基板，其中，所述多条栅线和所述多条第二数据线位于同一层。
  4. 根据权利要求2所述的阵列基板，还包括源漏极，其中，所述多条第一数据线与所述源极位于同一层，在所述多条第一数据线和所述多条第二数据线之间设置有栅绝缘层，每个第一数据线和其对应的第二数据线通过所述栅绝缘层中的过孔相连。
  5. 根据权利要求2所述的阵列基板，其中，所述多条栅线和所述多条第二数据线的数量彼此相同并且均为m，所述多条第一数据线为n。
  6. 根据权利要求5所述的阵列基板，其中，m>n，
    所述m条第二数据线中的n条第二数据线一一对应连接所述n条第一数据线，
    所述m条第二数据线中的其他第二数据线悬空设置。
  7. 根据权利要求6所述的阵列基板，其中，相邻两条悬空设置的第二数据线之间设置至少一条与所述第一数据线相连的第二数据线。
  8. 根据权利要求5所述的阵列基板，其中，所述m条第二数据线中的n条第二数据线一一对应连接所述n条第一数据线，并且当一部分第一数据线到所述第一集成电路的距离大于或等于第一距离时，为该部分第一数据线每条额外设置一条第二数据线。
  9. 根据权利要求5所述的阵列基板，其中，m＝n，
    所述m条第二数据线一一对应连接所述n条第一数据线。
  10. 根据权利要求2至9中任一项所述的阵列基板，还包括：
    第二集成电路，设置在与所述第一集成电路所在宽边相对宽边的边框中，用于向栅线传输扫描信号。
  11. 根据权利要求1至10中任一项所述的阵列基板，其中，所述第一集成电路为多个，每个第一集成电路与一部分第二数据线相连并且向其传输数据信号。
  12. 一种显示装置，包括权利要求1至11中任一项所述的阵列基板。
PCT/CN2016/096887 2015-10-08 2016-08-26 阵列基板和显示装置 WO2017059752A1 (zh)

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