WO2016157606A1 - 炭化珪素半導体装置およびその製造方法 - Google Patents
炭化珪素半導体装置およびその製造方法 Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 67
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims description 108
- 238000000034 method Methods 0.000 title claims description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000011241 protective layer Substances 0.000 claims abstract description 346
- 239000010410 layer Substances 0.000 claims abstract description 142
- 239000012535 impurity Substances 0.000 claims abstract description 91
- 210000000746 body region Anatomy 0.000 claims abstract description 40
- 238000005468 ion implantation Methods 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 18
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 230000001133 acceleration Effects 0.000 claims description 3
- 230000002441 reversible effect Effects 0.000 claims description 2
- 230000005684 electric field Effects 0.000 description 65
- 230000015556 catabolic process Effects 0.000 description 39
- 230000002829 reductive effect Effects 0.000 description 15
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- 230000015572 biosynthetic process Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000004088 simulation Methods 0.000 description 5
- 108091006146 Channels Proteins 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000002040 relaxant effect Effects 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Definitions
- the present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more particularly to a trench gate type silicon carbide semiconductor device and a manufacturing method thereof.
- Insulated gate semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are widely used as power switching elements.
- MOSFETs Metal Oxide Semiconductor Field Effect Transistors
- IGBTs Insulated Gate Bipolar Transistors
- an on state is obtained by forming a channel in a body region by applying a voltage higher than a threshold voltage to a gate electrode.
- the cell pitch can be reduced by improving the channel width density.
- it is possible to improve the performance of the device such as reducing the size of the device or applying it to a large current.
- silicon carbide semiconductor device a semiconductor device using silicon carbide (SiC) (hereinafter referred to as “silicon carbide semiconductor device”) is attracting attention as a next-generation semiconductor device capable of realizing high breakdown voltage and low loss. Development is also underway for mold types.
- Patent Document 1 discloses a trench gate type SiC-MOSFET using an n-type inversion layer as a channel.
- a p-type electric field shield region is provided in the n-type layer below the trench to shield the electric field from entering the gate oxide film from the n-type layer when the high voltage is cut off.
- the structure reduces the electric field strength of the gate oxide film, particularly the gate oxide film at the corner of the lower part of the groove where electric field concentration is likely to occur, so that the dielectric breakdown of the gate oxide film does not occur.
- the device breakdown voltage corresponding to the insulation characteristics of the SiC material can be obtained.
- the inventors have clarified that a high device withstand voltage corresponding to the excellent insulation characteristics inherent to the SiC material cannot be obtained only by preventing the dielectric breakdown of the gate oxide film. Specifically, if the electric field shield region is designed by paying attention only to preventing the dielectric breakdown of the gate oxide film, avalanche breakdown due to a high electric field applied to the bottom surface of the electric field shield region can easily occur. In this case, since the device breakdown voltage is limited by the avalanche breakdown voltage, it is impossible to obtain a high device breakdown voltage corresponding to the inherent excellent insulating characteristics of the SiC material.
- the present invention has been made to solve the above-described problems, and an object thereof is to provide a silicon carbide semiconductor device having a high breakdown voltage and a method for manufacturing the same.
- a silicon carbide semiconductor device of the present invention includes a first conductivity type drift layer made of silicon carbide, a second conductivity type body region provided on the drift layer, and a first conductivity type provided on the body region.
- a second conductivity type trench bottom surface protective layer provided below the bottom surface of the trench and electrically connected to the source electrode in the drift layer.
- the trench bottom protective layer includes a high concentration protective layer and a first low concentration protective layer provided below the high concentration protective layer and having a lower impurity concentration than the high concentration protective layer.
- the trench bottom protective layer includes the high concentration protective layer having a high impurity concentration, the dielectric breakdown of the gate insulating film on the trench bottom is prevented. Furthermore, since the trench bottom protective layer has the low concentration protective layer below the high concentration protective layer, the avalanche breakdown voltage in the off state can be increased. As described above, it is possible to obtain a high device breakdown voltage corresponding to the inherent excellent insulation characteristics of SiC.
- FIG. 1 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device according to a first embodiment of the present invention.
- 2 is a graph (A) to (C) showing an example of impurity concentration distribution of a trench bottom protective layer in FIG. 1.
- FIG. FIG. 2 is a partial cross-sectional view for illustrating a thickness of each of a low concentration protective layer and a high concentration protective layer in FIG. 1 and a thickness of each of a depletion layer and a non-depletion layer in a trench bottom surface protection layer.
- FIG. 4 is a plan view showing a first example of a pattern arrangement on the entire surface of a semiconductor layer included in the silicon carbide semiconductor device of FIG. 1.
- FIG. 8 is a plan view showing a second example of a pattern arrangement on the surface of the entire semiconductor layer included in the silicon carbide semiconductor device of FIG. 1.
- FIG. 8 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
- FIG. 8 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
- FIG. 8 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
- FIG. 8 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.
- FIG. 8 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1. It is a fragmentary sectional view which shows the structure of the comparative example of FIG. (A) is a contour figure which shows the simulation result of the electric field distribution in the structure A which has a structure of the comparative example of FIG. (B) is a contour figure which shows the simulation result of the electric field distribution in the structure B which has a structure of the comparative example of FIG. (C) is a contour figure which shows the simulation result of the electric field distribution in the structure C which has the structure of this Embodiment of FIG. 13 is a graph showing the relationship between the drain voltage and the drain current in each of the structures A to C in FIGS. 12A to 12C.
- FIG. 15 is a partial cross sectional view schematically showing a step of the method for manufacturing the silicon carbide semiconductor device of FIG. 14. It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device by Embodiment 3 of this invention.
- FIG. 17 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device of FIG. 16.
- FIG. 17 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 16.
- FIG. 17 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 16.
- FIG. 17 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 16.
- FIG. 17 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 16. It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device by Embodiment 4 of this invention.
- FIG. 1 is a cross sectional view schematically showing a configuration of a cell of MOSFET 91 (silicon carbide semiconductor device) according to the present embodiment.
- the MOSFET 91 includes a substrate 1 (semiconductor substrate), a semiconductor layer 21, a gate oxide film 9 (gate insulating film), a gate electrode 10, a source electrode 11, a drain electrode 12, and an interlayer insulating film 16.
- the substrate 1 is an n-type (first conductivity type) silicon carbide semiconductor substrate.
- the plane orientation of the substrate 1 may be any plane orientation such as (0001) plane, (000-1) plane, and (11-20) plane. Moreover, what provided the off angle in each surface orientation may be used.
- the semiconductor layer 21 is made of silicon carbide.
- the semiconductor layer 21 is an epitaxial layer on the substrate 1.
- the semiconductor layer 21 includes an n-type drift layer 2 provided on the substrate 1, a p-type (second conductivity type different from the first conductivity type) body region 5 provided on the drift layer 2, and a body region N-type source region 3 provided on 5, p-type body contact region 4 provided on body region 5, and p-type trench bottom protective layer 15.
- Each of source region 3 and body contact region 4 partially forms surface SF of semiconductor layer 21.
- a trench 6 that penetrates the source region 3 and the body region 5 and reaches the drift layer 2 is provided.
- the inner surface of trench 6 includes a side surface facing body region 5 and a bottom surface that is separated from body region 5 and faces drift layer 2.
- the plane orientation of the side surface of the trench 6 may be any plane orientation such as a (11-20) plane, a (1-100) plane, or a (03-38) plane.
- the n-type impurity concentration (donor concentration) of the drift layer 2 is lower than that of the substrate 1.
- the p-type impurity concentration (acceptor concentration) of the body contact region 4 is higher than that of the body region 5.
- an n-type impurity concentration higher than the n-type impurity concentration of the drift layer 2 is set between the lower portion of the body region 5 and the drift layer 2 in order to suppress current diffusion or extension of the depletion layer from the body region 5.
- region which has may be provided.
- the gate oxide film 9 covers the inner surface of the trench 6.
- Gate electrode 10 is provided on the inner surface of trench 6 with gate oxide film 9 interposed therebetween. In other words, the gate electrode 10 is formed on the gate oxide film 9 and embedded in the trench 6.
- the interlayer insulating film 16 covers the gate electrode 10 disposed in the trench 6.
- Source electrode 11 is formed on surface SF of semiconductor layer 21 and is in contact with each of source region 3 and body contact region 4.
- the source electrode 11 has a portion made of a metal silicide such as Ni or Ti on the semiconductor layer 21, thereby forming an ohmic contact with each of the source region 3 and the body contact region 4. Therefore, the source electrode 11 is ohmically connected to the source region 3.
- the drain electrode 12 is formed on the back surface of the substrate 1.
- the drain electrode 12 is a metal electrode and is made of, for example, Ni.
- trench bottom protective layer 15 will be described in detail below.
- the trench bottom surface protective layer 15 is provided below the bottom surface of the trench 6 in the drift layer 2.
- the trench bottom surface protective layer 15 has a covering surface (upper surface in the drawing) that covers the bottom surface of the trench 6 and a bottom surface (lower surface in the drawing) opposite to the covering surface.
- Trench bottom surface protective layer 15 is formed on drift layer 2 so as to be away from body region 5 and in contact with the bottom surface of trench 6.
- the trench bottom protective layer 15 is for relaxing the electric field at the bottom of the trench 6.
- at least a portion immediately below the bottom surface of the trench 6 is configured by the trench bottom surface protective layer 15.
- the trench bottom protective layer 15 is in contact with the gate oxide film 9 at the bottom of the trench 6.
- the trench bottom protective layer 15 includes a high concentration protective layer 8 and a low concentration protective layer 7 (first low concentration protective layer).
- the high-concentration protective layer 8 is a layer including a portion of the trench bottom protective layer 15 where the p-type impurity concentration has a maximum value.
- High-concentration protective layer 8 faces the bottom surface of trench 6, and is in contact with the bottom surface of trench 6 in the present embodiment.
- the low-concentration protective layer 7 is provided below the high-concentration protective layer 8 in the drawing, and is specifically located on the bottom surface of the high-concentration protective layer 8.
- the low concentration protective layer 7 forms at least a part of the bottom surface of the trench bottom surface protective layer 15.
- the low concentration protective layer 7 is a layer having an impurity concentration lower than the maximum value of the impurity concentration of the high concentration protective layer 8.
- the low concentration protective layer 7 may have an impurity concentration lower than the impurity concentration at any location in the high concentration protective layer 8.
- the low concentration protective layer 7 has a thickness equal to or greater than the thickness of the high concentration protective layer 8.
- the trench bottom protective layer 15 includes the high concentration protective layer 8 and the first low concentration protective layer 7. That is, the top surface of the first low-concentration protective layer 7 is in contact with the bottom surface of the high-concentration protective layer 8, and the top surface of the trench bottom-surface protective layer 15 corresponds to the top surface of the high-concentration protective layer 8.
- the bottom surface corresponds to the bottom surface of the low concentration protective layer 7.
- the high-concentration protective layer 8 is a portion of the trench bottom protective layer 15 that has an impurity concentration greater than half the maximum value of the p-type impurity concentration of the trench bottom protective layer 15.
- dimensions such as the width and thickness of the high-concentration protective layer 8 correspond to the dimensions of a region having an impurity concentration higher than half of the maximum value.
- the impurity concentration of the high concentration protective layer 8 is twice or more the impurity concentration of the low concentration protective layer 7.
- the “impurity concentration of the high concentration protective layer 8” is defined by the maximum value.
- the low concentration protective layer 7 is a portion located deeper than the high concentration protective layer 8 in the trench bottom surface protective layer 15, and has a p-type impurity concentration lower than any portion of the high concentration protective layer 8.
- the “impurity concentration of the low concentration protective layer 7” is defined by the maximum value.
- the trench bottom protective layer 15 has an impurity concentration profile in the thickness direction (longitudinal direction in the figure) as shown in FIGS. 2A to 2C, for example.
- a desirable impurity concentration profile is described below.
- the thickness of the low-concentration protective layer 7 is L 1 and the thickness of the high-concentration protective layer 8 is L 2 , the sum of these, that is, L 1 + L 2 is the trench bottom protective layer 15. It becomes thickness.
- the thickness of the depletion layer extending from the interface between the low concentration protective layer 7 and the drift layer 2 to the trench bottom surface protective layer 15 when a reverse voltage corresponding to the withstand voltage is applied to the MOSFET 91 is defined as d 1 .
- the “breakdown voltage” indicates, for example, the rated voltage described in the specifications of the semiconductor device. Note that the withstand voltage is determined from the current-voltage characteristics when the semiconductor device is off, and is a voltage when the leakage current is sufficiently small.
- the thickness of the non-depleted region NR that is a region that is not depleted that is, the distance from the end of the depletion layer to the upper surface of the high-concentration protective layer 8 is d 2
- L 1 + L 2 d 1 + d 2
- the high-concentration protective layer 8 By forming the high-concentration protective layer 8 near the bottom surface of the trench 6 so that the MOSFET 91 is not completely depleted even when the MOSFET 91 is turned off, d 2 > 0 can be achieved. That is, the end of the depletion layer extending in the trench bottom protective layer 15 can be kept away from the trench 6. As a result, the electric field strength in the non-depleted region NR is kept substantially zero except for the vicinity of the interface between the bottom surface of the trench 6 and the trench bottom surface protection layer 15 that is affected by the gate voltage. That is, the electric field can be prevented from entering the vicinity of the trench 6. Thereby, the electric field strength of the portion of gate oxide film 9 located at the bottom surface of trench 6 can be sufficiently reduced.
- the impurity concentration of the low-concentration protective layer 7 formed below the high-concentration protective layer 8 is made sufficiently depleted by sufficiently reducing the impurity concentration, that is, L 1 ⁇ d 1 , thereby providing the effects described below. Is obtained.
- a high electric field is applied to the bottom surface of the trench bottom surface protective layer 15, that is, the bottom surface of the low concentration protective layer 7.
- a high electric field is applied to the pn junction between the trench bottom protective layer 15 and the drift layer 2. Since the impurity concentration of the low-concentration protective layer 7 forming the p-type region of the pn junction is low, the electric field strength applied to the pn junction can be kept low. Thereby, the avalanche breakdown voltage can be improved.
- the impurity concentration of the low-concentration protective layer 7 forming the p-type region in the pn junction is low, so that the pn junction interface leads to the drift layer 2 that is the n-type region, that is, the on-current path. It is possible to suppress the elongation of the depletion layer. Thereby, an effect of suppressing an increase in on-resistance can be obtained.
- the p-type impurity concentration of the low concentration protective layer 7 is preferably 1.0 ⁇ 10 16 or more and 5.0 ⁇ 10 19 cm ⁇ 3 or less.
- the p-type impurity concentration of the high concentration protective layer 8 is preferably 1.0 ⁇ 10 17 or more and 1.0 ⁇ 10 20 cm ⁇ 3 or less.
- the n-type impurity concentration of the drift layer 2 is preferably 1.0 ⁇ 10 14 to 1.0 ⁇ 10 17 cm ⁇ 3 and is set based on the breakdown voltage of the MOSFET 91 and the like.
- the p-type impurity concentration in the body region 5 is preferably 1.0 ⁇ 10 14 to 5 ⁇ 10 19 cm ⁇ 3 .
- the n-type impurity concentration of the source region 3 is preferably 1.0 ⁇ 10 18 to 1.0 ⁇ 10 21 cm ⁇ 3 .
- the p-type impurity concentration of the body contact region 4 is preferably 1.0 ⁇ 10 18 to 1.0 ⁇ 10 21 cm ⁇ 3 , and is lower than that of the body region 5 in order to reduce the contact resistance with the source electrode 11. Is also raised.
- the thickness of the low concentration protective layer 7 is preferably equal to or greater than the thickness of the high concentration protective layer 8.
- the potential of the trench bottom protective layer 15 is fixed (grounded) by being electrically connected to the source electrode 11. This electrical connection is provided through, for example, adjacent cells. Since the potential of the trench bottom protective layer 15 is fixed, the depletion layer easily spreads from the high concentration protective layer 8 toward the drift layer 2 when the MOSFET 91 is turned off. For this reason, the electric field relaxation effect on the bottom surface of the trench 6 is increased. That is, since the trench bottom protective layer 15 is grounded, the electric field relaxation effect of the gate oxide film 9 on the bottom of the trench 6 can be further enhanced.
- the grounding of the trench bottom protective layer 15 is preferably performed by grounding the high concentration protective layer 8.
- FIG. 4 and 5 show first and second examples of pattern arrangement on the surface SF of the entire semiconductor layer 21, respectively.
- the planar arrangement of the cell structure shown in FIG. 1 can be striped (FIG. 4) or lattice (FIG. 5). Note that the cells are not necessarily aligned. Further, the shape of each cell is not limited to a quadrangle, and other polygonal shapes or shapes having corners having curvature may be used.
- the source region 3 and the body contact region 4 are formed in a stripe shape or an island shape, and the body region 5 (see FIGS. 4 and 5) below the source region 3 and the body contact region 4. (Not shown).
- trenches 6 are formed in a stripe shape or a lattice shape so as to be in contact with the side surface of the source region 3.
- a high concentration protective layer 8 and a low concentration protective layer 7 are formed in the same pattern as the trench 6.
- a termination region 13 is formed on the outer periphery of the region where the cells are arranged.
- the termination region 13 is, for example, a p-type impurity layer. This impurity layer may be formed on the surface SF, or may be formed on the bottom surface of the trench formed on the surface SF.
- the MOSFET 91 When a voltage equal to or higher than the threshold voltage is applied to the gate electrode 10 (FIG. 1), an inversion layer as an n-type channel is formed along the side surface of the trench 6 in the body region 5. As a result, a current path of the same conductivity type is formed between the source electrode 11 and the drift layer 2. Therefore, the MOSFET 91 is turned on. On the other hand, when a voltage equal to or lower than the threshold voltage is applied to the gate electrode 10, no channel is formed in the body region 5, and thus the current path as described above is not formed. For this reason, even if a voltage is applied between the drain electrode 12 and the source electrode 11, almost no current flows between them. That is, the MOSFET 91 is turned off. As described above, the MOSFET 91 can be switched between the on state and the off state by controlling the voltage applied to the gate electrode 10.
- MOSFET 91 Next, a method for manufacturing MOSFET 91 will be described.
- a semiconductor layer 21 supported by the substrate 1 is prepared.
- the semiconductor layer 21 can be formed by epitaxial growth on the substrate 1.
- the n-type impurity concentration of the semiconductor layer 21 corresponds to the n-type impurity concentration of the drift layer 2 described above.
- source region 3, body contact region 4, and body region 5 are formed in the upper portion of semiconductor layer 21 by ion implantation.
- the source region 3 is formed on the surface of the body region 5.
- the remainder of the semiconductor layer 21 is used as the drift layer 2.
- N ions are implanted as donor ions.
- p-type region for example, Al ions are implanted as acceptor ions. Note that the order of forming each region is not particularly limited. All or a part of the region may be formed by epitaxial growth instead of ion implantation.
- a mask 14 having an opening is formed on the semiconductor layer 21. Then, reactive ion etching (RIE) using this mask 14 is performed. As a result, a trench 6 that penetrates the source region 3 and the body region 5 and reaches the drift layer 2 is formed on the surface SF. In other words, the trench 6 penetrating the body region 5 from the surface of the source region 3 is formed.
- RIE reactive ion etching
- the low concentration protective layer 7 is formed by selectively performing p-type ion implantation on the bottom surface of the trench 6. Selective ion implantation can be performed by using the mask 14.
- the formation method of the low concentration protective layer 7 is not limited to the above. For example, it may be formed by epitaxial growth instead of ion implantation. Specifically, the trench 6 is formed deeper by the thickness of the low concentration protective layer 7 to be formed, and then the low concentration protective layer 7 is formed in the trench 6 by epitaxial growth. Alternatively, when the semiconductor layer 21 is formed, the low concentration protective layer 7 may be embedded in advance by ion implantation or epitaxial growth.
- high concentration protective layer 8 is formed with a higher dose than low concentration protective layer 7.
- the ion implantation for forming the low concentration protective layer 7 and the ion implantation for forming the high concentration protective layer 8 are performed with different acceleration energies.
- the high concentration protective layer 8 and the low concentration protective layer 7 provided below the high concentration protective layer 8 and having an impurity concentration lower than the impurity concentration of the high concentration protective layer 8 are formed on the bottom surface of the trench 6.
- the epitaxial growth conditions may be adjusted instead of ion implantation.
- the low concentration protective layer 7 is formed on the bottom surface of the trench 6 by epitaxial growth.
- a high concentration protective layer 8 having an impurity concentration higher than that of the low concentration protective layer 7 is formed on the upper surface of the low concentration protective layer 7 by epitaxial growth.
- the impurity ion implantation concentration profile is the concentration profile of each region in the semiconductor layer 21. Therefore, in this embodiment, two layers of the high-concentration protective layer 8 and the low-concentration protective layer 7 are formed by performing multi-stage ion implantation with different energies, that is, ion implantation with different energy twice or more. Note that concentration distribution of three or more layers may be formed by performing multi-stage ion implantation of three or more stages.
- the concentration distribution by the high concentration protective layer 8 and the low concentration protective layer 7 may be a stepped concentration distribution or a continuously changing distribution.
- the high concentration protective layer 8 may have an impurity concentration peak in the depth direction
- the low concentration protective layer 7 may have a peak smaller than the above peak in the depth direction.
- the peak in the low concentration protective layer 7 may be combined with the peak in the high concentration protective layer 8 to form a shoulder peak.
- the concentration distribution by the high-concentration protective layer 8 and the low-concentration protective layer 7 will be described more specifically with three examples (FIGS. 2A to 2C).
- the high-concentration protective layer 8 includes at least one region RC1 (one in the drawing) in which the impurity concentration is constant in the depth direction.
- the low concentration protective layer 7 includes at least one region RC2 (one in the drawing) in which the impurity concentration is smaller than that of the high concentration protective layer 8 and is constant in the depth direction.
- the shoulder peak of the impurity concentration of the low concentration protective layer 7 exists on the tailing of the peak of the impurity concentration of the high concentration protective layer 8.
- the boundary between the high concentration protective layer 8 and the low concentration protective layer 7 may be defined by an intermediate position between the region RC1 and the region RC2.
- the high-concentration protective layer 8 has a mountain-shaped peak PL1 having an impurity concentration in the depth direction.
- the low concentration protective layer 7 has a mountain peak PL2 having an impurity concentration smaller than that of the mountain peak in the depth direction.
- the “mountain peak” is a peak having a local maximum value unlike the regions RC1 and RC2 (FIG. 2A).
- the boundary between the high concentration protective layer 8 and the low concentration protective layer 7 may be defined by the depth position of the local minimum value QL.
- the impurity concentration profile of the low concentration protective layer 7 includes at least one inclination increasing portion FL (one in the figure) where the inclination of the profile increases in the depth direction. It is out.
- the increase in the impurity concentration at the slope increasing portion FL may be a continuous increase as shown in the figure, or may be a stepwise increase.
- the profile of the low-concentration protective layer 7 increased by passing through the slope increasing portion FL may have a region RC in which the impurity concentration is constant in the depth direction. Further, instead of such a region RC, the profile may have a mountain peak.
- the boundary between the high-concentration protective layer 8 and the low-concentration protective layer 7 may be defined by the depth position where the slope increasing portion FL starts.
- a gate oxide film 9 covering the inner surface of the trench 6 is formed thereafter.
- a gate electrode 10 is formed on the inner surface of the trench 6 via the gate oxide film 9.
- an interlayer insulating film 16 is formed so as to cover the gate electrode 10.
- source electrode 11 is formed so as to be in contact with the surface of source region 3 and the surface of body contact region 4.
- a drain electrode 12 is formed on the back surface of the substrate 1.
- the effect of the MOSFET 91 (FIG. 1) of the present embodiment will be described in comparison with the MOSFET 99 of the comparative example (FIG. 11).
- the low concentration protective layer 7 having a thickness equal to or greater than the thickness of the high concentration protective layer 8 is provided below the high concentration protective layer 8.
- the trench bottom protective layer 15 of the present embodiment has a two-layer structure including a high concentration protective layer 8 below the trench 6 and a low concentration protective layer 7 below the trench.
- the trench bottom protective layer 15c of the MOSFET 99 of the comparative example has a substantially single layer structure.
- the single-layer structure here means that the low-concentration protective layer under the high-concentration protective layer has only a small thickness less than the thickness of the high-concentration protective layer and is substantially constituted only by the high-concentration protective layer. Including what can be said to be.
- FIG. 12A and 12B are simulation results of the electric field distribution in the off state in the structures A and B having the configuration of the MOSFET 99 of the comparative example.
- the impurity concentration of the trench bottom protective layer 15c of the structure B was set higher than the impurity concentration of the trench bottom protective layer 15c of the structure A.
- FIG. 12C shows a simulation result of the electric field distribution in the off state in the structure C as an example of the MOSFET 91 of the present embodiment.
- the impurity concentration of the high-concentration protective layer 8 of the structure C was set higher than that of the trench bottom protective layer 15c of the structure B.
- the vertical direction shows the surface of the semiconductor layer 21 to several ⁇ m below the trench bottom protective layer 15, and the horizontal direction shows the body contact region 4 center to the trench 6 center.
- a region shown in white represents a region having a higher electric field strength
- a region shown in black represents a region having a lower electric field strength.
- the structure A as a comparative example, it was found that a particularly high electric field was applied to both ends of the bottom surface of the trench 6 (corner portions of the trench 6) and the gate oxide film 9 formed there.
- the reason for this is that the trench bottom protective layer 15c is depleted in the vertical direction and is also depleted to some extent in the horizontal direction, so that the corners of the trench 6 and the gate oxide film 9 formed there are formed in the depletion layer. It is thought that it was exposed.
- the electric field concentrates also on the bottom surface of the trench bottom protective layer 15.
- the maximum electric field strength in the gate insulating film 9 was 3.8 MV / cm, and the maximum electric field strength on the bottom surface of the trench bottom protective layer 15c was 3.2 MV / cm.
- the electric field tends to concentrate at these locations.
- the structure B as another comparative example, although the electric field is concentrated at the same place as described above, the high electric field did not enter the vicinity of the trench 6. This is because the trench bottom surface protective layer 15c has a high impurity concentration, so that the area of the bottom surface of the trench 6 covered with a low electric field region that is not depleted becomes large, and the end of the depletion layer becomes the trench 6 This is thought to be due to the distance from the bottom.
- the electric field strength at the bottom surface of the trench bottom surface protective layer 15c is higher than that in the structure A. The reason is considered that the thickness of the depletion layer in the trench bottom protective layer 15c is narrow. Specifically, in the structure B, the maximum electric field strength in the gate insulating film 9 was 2.5 MV / cm, and the maximum electric field strength on the bottom surface of the trench bottom protective layer 15c was 3.3 MV / cm.
- the electric field strength of the corners of the trench 6 and the gate oxide film 9 was kept low, almost the same as the structure B.
- the high concentration protective layer 8 covering the bottom surface of the trench 6 has a high impurity concentration, so that the area of the bottom surface of the trench 6 covered by the low electric field region that is not depleted is increased. Conceivable.
- the electric field strength at the bottom surface of the trench bottom surface protective layer 15 became smaller than the structure A.
- the low-concentration protective layer 7 constituting the bottom surface side of the trench bottom protective layer 15 has a low impurity concentration and a thickness equal to or greater than the thickness of the high-concentration protective layer 8, and as a result, the bottom surface of the trench It is considered that about half of the protective layer 15 is depleted.
- the maximum electric field strength in the gate insulating film 9 was 2.8 MV / cm
- the maximum electric field strength on the bottom surface of the trench bottom protective layer 15 was 3.0 MV / cm.
- FIG. 13 is a graph showing current-voltage characteristics when each of the structures A to C is turned off.
- the breakdown voltage of the structure A as a comparative example was 1330V.
- the “leakage voltage” is a voltage when a certain leak current flows in the current-voltage characteristics at the time of OFF. As the leakage voltage is increased, the breakdown voltage of the semiconductor device can be improved.
- the leakage voltage of the structure B as a comparative example in which the impurity concentration of the trench bottom protective layer 15c is further increased was 1320 V, which is substantially the same.
- the leakage voltage of the structure C as an example was 1420 V, which was larger than the above.
- the high-concentration protective layer 8 maintains a high electric field relaxation effect in the gate oxide film 9 while the low-concentration protective layer 7 increases the avalanche breakdown voltage.
- the reason why the avalanche breakdown voltage is improved is that the low concentration protective layer 7 having a relatively low impurity concentration is disposed on the bottom surface side of the trench bottom surface protective layer 15, thereby depleting the bottom surface of the trench bottom surface protective layer 15. This is because the electric field strength at the pn interface between the trench bottom protective layer 15 and the drift layer 2 is reduced due to the promotion.
- the maximum electric field strength of the gate oxide film 9 and the maximum electric field strength of the pn junction are in a trade-off relationship. Specifically, when the concentration of the entire trench bottom protective layer 15 is lowered as in the structure A, the maximum electric field strength applied to the gate oxide film 9 is increased. On the other hand, when the concentration of the entire trench bottom protective layer 15 is increased as in the structure B, the maximum electric field strength at the pn junction is increased. As a result, the breakdown voltage is low in both cases A and B. On the other hand, according to the structure C, it is possible to reduce both, and the above trade-off relationship can be improved.
- the breakdown voltage can be improved by sufficiently relaxing the electric field of gate oxide film 9 and reducing the electric field strength in SiC.
- the trench bottom protective layer 15 since the trench bottom protective layer 15 has the high concentration protective layer 8, the dielectric breakdown of the gate oxide film 9 on the bottom of the trench 6 is prevented. Furthermore, since the trench bottom protective layer 15 has the low concentration protective layer 7 below the high concentration protective layer 8, the avalanche breakdown voltage in the off state can be increased. As described above, it is possible to obtain a high breakdown voltage corresponding to the inherent excellent insulating characteristics of SiC.
- a voltage drop may occur due to the resistance of the trench bottom protective layer 15.
- current flows in the trench bottom surface protective layer 15 due to depletion charges in the depletion layer extending to the pn interface between the trench bottom surface protective layer 15 and the drift layer 2, and a voltage drop occurs.
- This voltage drop increases as the resistance of the trench bottom protective layer 15 increases. Due to the potential difference due to this voltage drop, an electric field is applied to the gate oxide film 9 on the bottom surface of the trench 6, and there is a concern that the reliability of the gate oxide film 9 is lowered.
- the resistance of the trench bottom protective layer 15 can be reduced by providing the high concentration protective layer 8, the electric field applied to the gate oxide film 9 at the time of switching can be reduced, and the gate oxide film 9 Can be suppressed. Further, the provision of the low concentration protective layer 7 can suppress a decrease in the avalanche breakdown voltage. That is, according to the present embodiment, the reliability of the gate insulating film 9 at the time of switching operation, the reliability of the gate insulating film 9 at the time of steady-off, and the avalanche breakdown voltage characteristics can be achieved.
- the current generated at the time of switching is greater than that in the case where the trench bottom surface protection layer 15 is electrically floating. Since the current flowing in the trench bottom protective layer 15 becomes particularly large because the current flows toward, the above-mentioned advantage becomes remarkable.
- an effect of improving the short-circuit withstand capability can also be obtained.
- the short-circuit tolerance is generally lower than that of Si, and improvement of the short-circuit tolerance is recognized as one of the important issues.
- the short circuit withstand capability is expressed as the time from when the load short circuit occurs until the semiconductor device breaks down. The
- the overcurrent flows through the semiconductor device, the temperature of the semiconductor device becomes high, and the SiC and the gate oxide film 9 are destroyed. Therefore, in order to improve the short circuit withstand capability, it is effective to reduce the overcurrent at the time of the short circuit.
- the high concentration protective layer 8 of the trench bottom surface protective layer 15 is provided, so that the extension of the depletion layer from the trench bottom surface protective layer 15 to the drift layer 2 can be increased. Therefore, the resistance of the path through which the current flows at the time of the short circuit increases, and the overcurrent at the time of the short circuit can be reduced. As a result, the short circuit tolerance can be improved. That is, according to the present embodiment, an effect of improving the short-circuit tolerance can be obtained, and in particular, there is an advantage that the short-circuit tolerance can be improved even when SiC is used.
- ion implantation for forming the low concentration protective layer 7 and the high concentration protective layer 8 is performed after the formation of the trench 6, so that the implantation depth of the ion implantation from the surface SF of the semiconductor layer 21 is the depth of the trench 6. It gets shallower. Correspondingly, the energy at the time of implantation is lowered, so that defects caused by the implantation are reduced. As a result, the quality of the interface between the gate oxide film 9 and the semiconductor layer 21 can be improved. Thereby, for example, leakage current can be suppressed.
- the low concentration protective layer 7 and the high concentration layer are provided at a lower part of the trench 6 in the drift layer 2, that is, at least immediately below the trench 6.
- the protective layer 8 is formed, the low concentration protective layer 7 and the high concentration protective layer 8 may be formed by ion implantation from the surface SF of the semiconductor layer 21 before the trench 6 is formed. In such a case, the low concentration protective layer 7 and the high concentration protective layer 8 may be formed outside the side surface of the trench 6.
- FIG. 14 is a cross sectional view schematically showing a configuration of a cell of MOSFET 92 (silicon carbide semiconductor device) according to the present embodiment.
- the configuration of the trench bottom protective layer 15 is different from that of the first embodiment.
- the width of the low concentration protective layer 7 is smaller than the width of the high concentration protective layer 8.
- the low-concentration protective layer 7 forms only a part of the bottom surface of the trench bottom surface protective layer 15 (the center of the bottom surface in the figure)
- the high concentration protective layer 8 is the other part of the bottom surface of the trench bottom surface protective layer 15 ( In the drawing, both end portions of the bottom surface are formed. Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, description thereof will not be repeated.
- the MOSFET 92 Next, a method for manufacturing the MOSFET 92 will be described. First, steps similar to those up to FIG. 8 of the first embodiment are performed. Next, the step of forming the trench bottom protective layer 15 is performed as follows.
- sidewall mask 17 is formed on the side surface of trench 6.
- An impurity imparting p-type is implanted into the bottom surface of the trench 6 through the trench 6 in which the sidewall mask 17 is formed.
- the low concentration protective layer 7 having a width smaller than the width of the trench 6 is formed.
- the sidewall mask 17 is removed.
- an impurity imparting p-type is implanted into the bottom surface of trench 6 without sidewall mask 17.
- the high concentration protective layer 8 having a width corresponding to the width of the trench 6 is formed.
- the width of the low concentration protective layer 7 is smaller than the width of the high concentration protective layer 8 by the thickness of the mask material in the lateral direction.
- the ion implantation without the side wall mask 17 may be performed before the side wall mask 17 is formed instead of being performed after the side wall mask 17 is removed as described above.
- MOSFET 92 is obtained through substantially the same process as in the first embodiment. According to this manufacturing method, as described above, the width of the high concentration protective layer 8 and the width of the low concentration protective layer 7 can be made different.
- the trench bottom protective layer 15 can be a factor for increasing the on-resistance by constricting the on-current path in the drift layer 2. According to the present embodiment, by reducing the width of the low concentration protective layer 7, the degree to which the on-current path in the drift layer 2 is constricted by the trench bottom surface protective layer 15 is reduced. As a result, an increase in on-resistance due to the provision of the trench bottom protective layer 15 can be suppressed.
- the electric field concentration on the bottom surface of the trench bottom surface protective layer 15 at the time of off is distributed to the bottom surface of the low concentration protective layer 7 and the bottom surface of the high concentration protective layer 8. Therefore, the avalanche breakdown voltage is improved. Thereby, the pressure resistance can be further increased.
- FIG. 16 is a cross sectional view schematically showing a configuration of a cell of MOSFET 93 (silicon carbide semiconductor device) according to the present embodiment.
- the configuration of the trench bottom protective layer 15 is different from that of the first embodiment.
- the width of the low concentration protective layer 7 is formed larger than the width of the high concentration protective layer 8. Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, description thereof will not be repeated.
- MOSFET 93 Next, a method for manufacturing MOSFET 93 will be described below.
- first drift layer 2 a (first layer) made of silicon carbide and having n-type is formed on substrate 1.
- the first drift layer 2a can be formed in the same manner as the semiconductor layer 21 (FIG. 6).
- a mask 14 having an opening partly exposing the first drift layer 2a is formed.
- an impurity imparting p-type is implanted onto the first drift layer 2a.
- the low concentration protective layer 7 is formed on the first drift layer 2a.
- the mask 14 is removed. Instead of the ion implantation, the low concentration protective layer 7 may be formed on the first drift layer 2a by epitaxial growth.
- second drift layer 2b is formed on first drift layer 2a on which low-concentration protective layer 7 is formed.
- the method of forming the second drift layer 2b can be performed in the same manner as the method of forming the semiconductor layer 21 (FIG. 6).
- the second drift layer 2b is an n-type layer made of silicon carbide, and constitutes the drift layer 2 together with the first drift layer 2a.
- the low concentration protective layer 7 is embedded in the drift layer 2 having the first drift layer 2a and the second drift layer 2b.
- the low concentration protective layer 7 having a width larger than the width of the trench 6 (FIG. 16) can be formed.
- body region 5 on drift layer 2 source region 3 and body contact region 4 on body region 5 are formed.
- the semiconductor layer 21 having the surface SF constituted by the drift layer 2, the source region 3, the body contact region 4, and the body region 5 is formed.
- trench 6 is formed in surface SF of semiconductor layer 21 so as to penetrate source region 3 and body region 5 to drift layer 2.
- the width of the trench 6 is made smaller than the width of the low concentration protective layer.
- high-concentration protective layer 8 having p-type is formed.
- the high concentration protective layer 8 is formed by self-aligned implantation using the trench 6.
- the width of the high-concentration protective layer 8 may be smaller than the width of the trench 6 by using the sidewall mask 17 (FIG. 15) at the time of implantation.
- MOSFET 92 is obtained through substantially the same steps as those in FIGS. 7, 8 and 10 in the first embodiment.
- the low-concentration protective layer 7 may be formed, for example, by ion implantation into a region deeper than the bottom surface of the trench 6 after the process shown in FIG.
- the depletion layer easily spreads from the low concentration protective layer 7 at the time of OFF.
- the electric field strength in the drift layer 2 can be kept lower, and the electric field strength applied near the bottom surface of the trench 6 can be reduced.
- the electric field strength of gate oxide film 9 can be reduced. Therefore, the breakdown voltage can be further improved.
- FIG. 22 is a cross sectional view schematically showing a configuration of a cell of MOSFET 94 (silicon carbide semiconductor device) according to the present embodiment.
- the configuration of the trench bottom protective layer 15 is different from that of the first embodiment.
- the trench bottom protective layer 15 of the MOSFET 94 includes a low concentration protective layer 20 (second low concentration protective layer).
- the low concentration protective layer 20 is provided above the high concentration protective layer 8 in the drawing.
- the low concentration protective layer 20 is provided between the high concentration protective layer 8 and the bottom surface of the trench 6. Therefore, in the present embodiment, the high concentration protective layer 8 faces the bottom surface of the trench 6 through the low concentration protective layer 20.
- the low concentration protective layer 20 is in contact with the bottom surface of the trench 6.
- the low concentration protective layer 20 is a portion located shallower than the high concentration protective layer 8 in the trench bottom protective layer 15.
- the low concentration protective layer 20 has an impurity concentration lower than the impurity concentration at any location in the high concentration protective layer 8.
- the “impurity concentration of the low concentration protective layer 20” is defined by the maximum value.
- the impurity concentration of the low concentration protective layer 7 and the impurity concentration of the low concentration protective layer 20 may be equal to or different from each other.
- the low concentration protective layer 20 preferably has a peak with an impurity concentration smaller than that of the high concentration protective layer 8.
- the high concentration protective layer 8 is disposed so as to be in contact with the bottom surface of the low concentration protective layer 20. Therefore, the high concentration protective layer 8 is separated from the bottom surface of the trench 6 by the low concentration protective layer 20.
- MOSFET 94 Next, a method for manufacturing MOSFET 94 will be described. First, steps similar to those up to FIG. 8 of the first embodiment are performed. Next, a low concentration protective layer is formed on the bottom surface of the trench 6 by a method similar to the formation of the low concentration protective layer 7 of FIG. Next, the high concentration protective layer 8 is formed in a shallower region away from the bottom surface of the low concentration protective layer and in a deeper region away from the bottom surface of the trench 6 by ion implantation. Of the low concentration protective layer, a portion deeper than the high concentration protective layer 8 becomes the low concentration protective layer 7, and a shallow portion becomes the low concentration protective layer 20. Thereafter, MOSFET 94 (FIG. 22) is obtained through substantially the same process as in the first embodiment.
- the low concentration protective layer may be formed by epitaxial growth on the bottom surface of the trench 6 instead of ion implantation.
- the low concentration protective layer 7 and the low concentration protective layer 20 may be formed individually. This individual formation can be performed by either ion implantation or epitaxial growth.
- the formation of the low concentration protective layer 7 by ion implantation may be performed in a deeper region away from the bottom surface of the trench 6, or may be performed on the bottom surface of the trench 6.
- the portion between the low-concentration protective layer 7 and the bottom surface of the trench 6 is used as a portion that becomes the high-concentration protective layer 8, and is further used as a portion that becomes the low-concentration protective layer 20. Can be done.
- portions that become the high concentration protective layer 8 and the low concentration protective layer 20 are formed by epitaxial growth on the low concentration protective layer 7.
- the trench bottom protective layer 15 can be a factor for increasing the on-resistance by constricting the on-current path in the drift layer 2.
- a layer having a high impurity concentration is formed immediately below the bottom surface of the trench 6, the width of the depletion layer extending to the drift layer 2 is slightly widened.
- this layer is formed by ion implantation, the implantation region may be enlarged, and as a result, the on-resistance can be further increased.
- the high concentration protective layer 8 having a high impurity concentration is arranged away from the bottom surface of the trench 6. This reduces the increase in on-resistance.
- the high concentration protective layer 8 is formed on the bottom surface of the trench 6 by ion implantation, since the impurity concentration of the high concentration protective layer 8 is high, many ions need to be implanted. As a result, many defects generated by the implantation are formed in the high concentration protective layer 8. Thus, it becomes difficult to directly form the high-quality gate oxide film 9 on the high-concentration protective layer 8 having many defects. The low quality of the gate oxide film 9 can adversely affect the breakdown voltage.
- the high-concentration protective layer 8 that can include many defects is arranged away from the bottom surface of the trench 6. Thereby, the reliability of the gate insulating film can be improved. Therefore, the breakdown voltage can be further increased.
- the MOSFET has been described as the silicon carbide semiconductor device, but the material of the gate insulating film is not limited to the oxide. That is, the silicon carbide semiconductor device may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than the MOSFET. Further, the silicon carbide semiconductor device is not limited to the MISFET, and may be, for example, an IGBT.
- the IGBT can be configured, for example, by changing the conductivity type of the substrate 1 described above from n-type to p-type. In this case, the source electrode 11 and the drain electrode 12 function as an emitter electrode and a collector electrode, respectively.
- the first conductivity type is n-type and the second conductivity type is p-type, but these may be reversed.
- 1 substrate semiconductor substrate
- 2 drift layer 2a first drift layer
- 2b second drift layer 3 source region
- 4 body contact region 5 body region
- 6 trench 7 low concentration protection layer (first low concentration protection layer) Layer
- 8 high-concentration protective layer 9 gate oxide film (gate insulating film)
- 10 gate electrode 11 source electrode, 12 drain electrode, 13 termination region, 14 mask, 15 trench bottom protective layer, 16 interlayer insulating film, 17 Side wall mask (mask), 20 low concentration protective layer (second low concentration protective layer), 21 semiconductor layer, 91-94 MOSFET (silicon carbide semiconductor device).
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Abstract
Description
図1は、本実施の形態に係るMOSFET91(炭化珪素半導体装置)のセルの構成を概略的に示す断面図である。MOSFET91は、基板1(半導体基板)、半導体層21、ゲート酸化膜9(ゲート絶縁膜)、ゲート電極10、ソース電極11、ドレイン電極12、および層間絶縁膜16を有する。
d1>L1、かつd2>0
が満たされることが好ましい。
図14は、本実施の形態に係るMOSFET92(炭化珪素半導体装置)のセルの構成を概略的に示す断面図である。本実施の形態では、実施の形態1と比較して、トレンチ底面保護層15の構成が相違している。具体的には、MOSFET92のトレンチ底面保護層15においては、低濃度保護層7の幅が高濃度保護層8の幅よりも小さく形成されている。このため低濃度保護層7はトレンチ底面保護層15の底面の一部(図中、底面の中央部)のみをなしており、高濃度保護層8がトレンチ底面保護層15の底面の他部(図中、底面の両端部)をなしている。なお、上記以外の構成については、上述した実施の形態1の構成とほぼ同じであるため、その説明を繰り返さない。
図16は、本実施の形態に係るMOSFET93(炭化珪素半導体装置)のセルの構成を概略的に示す断面図である。本実施の形態では、実施の形態1と比較して、トレンチ底面保護層15の構成が相違している。具体的には、MOSFET93のトレンチ底面保護層15においては、低濃度保護層7の幅が高濃度保護層8の幅よりも大きく形成されている。なお、上記以外の構成については、上述した実施の形態1の構成とほぼ同じであるため、その説明を繰り返さない。
図22は、本実施の形態に係るMOSFET94(炭化珪素半導体装置)のセルの構成を概略的に示す断面図である。本実施の形態では、実施の形態1と比較して、トレンチ底面保護層15の構成が相違している。具体的には、MOSFET94のトレンチ底面保護層15は低濃度保護層20(第2低濃度保護層)を含む。低濃度保護層20は、図中、高濃度保護層8よりも上方に設けられている。具体的には低濃度保護層20は高濃度保護層8とトレンチ6の底面との間に設けられている。よって本実施の形態においては、高濃度保護層8は、低濃度保護層20を介してトレンチ6の底面に面している。
Claims (13)
- 炭化珪素からなる第1導電型のドリフト層(2)と、
前記ドリフト層上に設けられた第2導電型のボディ領域(5)と、
前記ボディ領域上に設けられた第1導電型のソース領域(3)と、
前記ソース領域に接続されたソース電極(11)と、
前記ボディ領域と前記ソース領域とを貫通するトレンチの側面上と底面上とに設けられたゲート絶縁膜(9)と、
前記ゲート絶縁膜を介して前記トレンチ内に設けられたゲート電極(10)と、
前記ドリフト層内において、前記トレンチの底面より下方に設けられ、前記ソース電極に電気的に接続された第2導電型のトレンチ底面保護層(15)と、
を備え、
前記トレンチ底面保護層は、
高濃度保護層(8)と、
前記高濃度保護層の下方に設けられ、前記高濃度保護層よりも不純物濃度の低い第1低濃度保護層(7)と、
を有することを特徴とする炭化珪素半導体装置(91~94)。 - 前記第1低濃度保護層の厚さをL1、前記高濃度保護層の厚さをL2、前記炭化珪素半導体装置に逆方向電圧が印加された時に前記第1低濃度保護層と前記ドリフト層との界面から前記トレンチ底面保護層に伸びる空乏層の厚さをd1とし、d2={(L1+L2)-d1}としたとき、
d1>L1、かつd2>0
が満たされる、請求項1に記載の炭化珪素半導体装置。 - 前記高濃度保護層は、不純物濃度が深さ方向に一定となる領域(RC1)を少なくとも1つ含み、前記第1低濃度保護層は、不純物濃度が前記高濃度保護層よりも小さくかつ深さ方向に一定となる領域(RC2)を少なくとも1つ含む、請求項1または2に記載の炭化珪素半導体装置。
- 前記高濃度保護層は深さ方向において不純物濃度の山形ピーク(PL1)を有し、前記第1低濃度保護層は深さ方向において前記山形ピークよりも小さい不純物濃度の山形ピーク(PL2)を有する、請求項1または2に記載の炭化珪素半導体装置。
- 前記第1低濃度保護層の不純物濃度のプロファイルは、深さ方向に向かうにつれてプロファイルの傾きが大きくなる箇所(FL)を少なくとも1つ含む、請求項1または2に記載の炭化珪素半導体装置。
- 前記高濃度保護層の不純物濃度は前記第1低濃度保護層の不純物濃度の2倍以上である、請求項1から5のいずれか1項に記載の炭化珪素半導体装置。
- 前記第1低濃度保護層の幅は前記高濃度保護層の幅よりも小さい、請求項1から6のいずれか1項に記載の炭化珪素半導体装置(92)。
- 前記第1低濃度保護層の幅は前記高濃度保護層の幅よりも大きい、請求項1から6のいずれか1項に記載の炭化珪素半導体装置(93)。
- 前記トレンチ底面保護層は、前記高濃度保護層および前記第1低濃度保護層の2層からなる、請求項1から8のいずれか1項に記載の炭化珪素半導体装置(91~93)。
- 前記トレンチ底面保護層は、前記高濃度保護層よりも上方に、前記高濃度保護層の不純物濃度よりも低い不純物濃度を有する第2低濃度保護層(20)を含む、請求項1から8のいずれか1項に記載の炭化珪素半導体装置(94)。
- 前記第2低濃度保護層は、前記高濃度保護層におけるピークよりも小さい不純物濃度のピークを有する、請求項10に記載の炭化珪素半導体装置。
- 炭化珪素から作られた第1導電型の半導体層(21)が設けられた半導体基板(1)を用意する工程と、
前記半導体層の上部に第2導電型のボディ領域(5)を形成する工程と、
前記ボディ領域の表面に前記第1導電型のソース領域(3)を形成する工程と、
前記ソース領域の表面から前記ボディ領域を貫通するトレンチ(6)を形成する工程と、
前記トレンチの底面に、前記第2導電型の高濃度保護層(8)と、前記高濃度保護層の下方に設けられ前記高濃度保護層の不純物濃度よりも低い不純物濃度を有する前記第2導電型の第1低濃度保護層(7)とを、加速エネルギーの異なる複数回のイオン注入により形成する工程と、
を備えた、炭化珪素半導体装置(91~94)の製造方法。 - 炭化珪素から作られた第1導電型の半導体層(21)が設けられた半導体基板(1)を用意する工程と、
前記半導体層の上部に第2導電型のボディ領域(5)を形成する工程と、
前記ボディ領域の表面に前記第1導電型のソース領域(3)を形成する工程と、
前記ソース領域の表面から前記ボディ領域を貫通するトレンチ(6)を形成する工程と、
前記トレンチの底面に、前記第2導電型の第1低濃度保護層(7)をエピタキシャル成長により形成する工程と、
前記第1低濃度保護層の上面に、前記第1低濃度保護層の不純物濃度よりも高い不純物濃度を有する前記第2導電型の高濃度保護層(8)をエピタキシャル成長により形成する工程と、
を備えた、炭化珪素半導体装置(91~94)の製造方法。
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JP2019197792A (ja) * | 2018-05-09 | 2019-11-14 | 三菱電機株式会社 | 炭化珪素半導体装置、電力変換装置、および炭化珪素半導体装置の製造方法 |
US11984492B2 (en) | 2018-05-09 | 2024-05-14 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device, power converter, and method of manufacturing silicon carbide semiconductor device |
US11245017B2 (en) | 2019-08-02 | 2022-02-08 | Kabushiki Kaisha Toshiba | Semiconductor device, inverter circuit, drive device, vehicle, and elevator |
JP2021129027A (ja) * | 2020-02-13 | 2021-09-02 | 株式会社デンソー | スイッチング素子 |
JP7354868B2 (ja) | 2020-02-13 | 2023-10-03 | 株式会社デンソー | スイッチング素子 |
DE102021123958A1 (de) | 2021-01-07 | 2022-07-07 | Mitsubishi Electric Corporation | Halbleitervorrichtung |
US11621321B2 (en) | 2021-01-07 | 2023-04-04 | Mitsubishi Electric Corporation | Semiconductor device |
WO2022190456A1 (ja) * | 2021-03-11 | 2022-09-15 | 株式会社デンソー | 電界効果トランジスタとその製造方法 |
WO2022270245A1 (ja) * | 2021-06-23 | 2022-12-29 | 住友電気工業株式会社 | 炭化珪素半導体装置 |
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US20180076285A1 (en) | 2018-03-15 |
CN107431091A (zh) | 2017-12-01 |
JPWO2016157606A1 (ja) | 2017-09-14 |
DE112015006403T5 (de) | 2017-12-21 |
JP6266166B2 (ja) | 2018-01-24 |
CN107431091B (zh) | 2020-05-19 |
US10157986B2 (en) | 2018-12-18 |
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