CN108520897A - 金属氧化物半导体场效应晶体管 - Google Patents

金属氧化物半导体场效应晶体管 Download PDF

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CN108520897A
CN108520897A CN201810159802.5A CN201810159802A CN108520897A CN 108520897 A CN108520897 A CN 108520897A CN 201810159802 A CN201810159802 A CN 201810159802A CN 108520897 A CN108520897 A CN 108520897A
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荒内琢士
金原启道
辻村理俊
山下侑佑
浦上泰
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Toyota Motor Corp
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Abstract

本发明涉及金属氧化物半导体场效应晶体管。浮区包含沿着碳化硅衬底的厚度方向布置的高浓度区和低浓度区。低浓度区中p型掺杂剂的浓度低于高浓度区中p型掺杂剂的浓度。高浓度区与低浓度区接触，并且设置在沟槽的底面与低浓度区之间。在通过沿着厚度方向绘制浮区中p型掺杂剂的浓度所得到的图中，在高浓度区和低浓度区之间的边界上出现弯曲点或拐点。在低浓度区中p型掺杂剂的含量等于或高于漂移区的在厚度方向上与所述低浓度区邻接的部分中的n型掺杂剂的含量。

Description

金属氧化物半导体场效应晶体管
技术领域
本发明涉及金属氧化物半导体场效应晶体管。
背景技术
存在一种具有如下结构的金属氧化物半导体场效应晶体管(MOSFET)，在其结构中p型浮区设置在n型漂移区内部。所述浮区设置成与沟槽的底面邻接。所述浮区经由例如沿着沟槽端面延伸的p型连接区而连接至体区。通过这一结构，促进漂移区的消耗，使得半导体器件的耐压性能够增加。通常，通过穿过沟槽的内表面的p型掺杂剂的离子注入而形成浮区。日本未审查专利申请公开号2005-116822描述了一种包含浮区的MOSFET，以及所述MOSFET的制造方法。
发明内容
据要求，根据漂移区中所含n型掺杂剂的量，浮区应该含有特定量的p型掺杂剂。如果浮区中p型掺杂剂的含量相对于漂移区中n型掺杂剂的含量不足，则漂移区无法充分消耗。此外，为了以低电阻将浮区与体区连接，要求浮区的至少一部分应该含有相对高浓度的p型掺杂剂。为满足这些要求，在为形成浮区进行的离子注入中，p型掺杂剂的注入浓度可被设定为相对高的值。
然而，如果增加p型掺杂剂的注入浓度，当注入浓度超过特定的值时，会发生不可忽视数量的晶体缺陷(晶格缺陷)。这种在半导体衬底中的晶体缺陷可能是引起漏电流的渗漏源，导致半导体器件的耐压性降低。如上所述，在浮区中p型掺杂剂的含量和浓度之间存在权衡关系，需要解决这一问题的技术。特别地，在包含碳化硅(SiC)半导体衬底(在下文中，如果适当，则称为“SiC衬底”)的沟槽栅MOSFET中，在许多情况下通过利用SiC的宽带隙特征而提供了相对薄的漂移区。结果，容易增加漂移区中生成的电场的强度。因此，即使在例如硅衬底中可以忽视的晶体缺陷在SiC衬底中也无法忽视。
考虑到上述情况，本发明提供了一种在含有SiC衬底的沟槽栅MOSFET中在浮区中实现合适的p型掺杂剂浓度分布曲线的技术。
本发明的一个方面提供了MOSFET。根据本发明的这一方面的MOSFET包含含有沟槽的SiC衬底；以及设置在所述沟槽中的栅电极。所述SiC衬底包含：n型源区；n型漂移区；p型体区，其设置在所述n型源区和n型漂移区之间；p型浮区，其设置在所述漂移区内，所述p型浮区与沟槽的底面邻接；以及p型连接区，其从所述p型体区延伸到所述p型浮区。所述p型浮区包含沿着SiC衬底的厚度方向布置的高浓度区和低浓度区，所述高浓度区设置在所述沟槽的所述底面和所述低浓度区之间，所述高浓度区与所述低浓度区接触，当通过沿着所述厚度方向绘制所述p型浮区中p型掺杂剂的浓度而获得图时，所述p型掺杂剂的最大浓度在所述高浓度区中高于在所述低浓度区中，并且该图在所述高浓度区和所述低浓度区之间的边界处具有弯曲点或拐点，所述低浓度区中p型掺杂剂的含量等于或高于所述n型漂移区的在厚度方向上与所述低浓度区邻接的部分中的n型掺杂剂的含量。
利用上述结构，浮区中p型掺杂剂的浓度在与沟槽的底面接近的高浓度区中高于在与沟槽的底面隔开的低浓度区中。如上所述，低浓度区中p型掺杂剂的含量等于或高于与低浓度区邻接的漂移区部分中n型掺杂剂的含量。即，低浓度区含有的p型掺杂剂的量使得漂移区能够被充分消耗。因此，即使低浓度区通过漂移区与浮区之间的pn结而消耗，高浓度区也被防止完全消耗。因而，在高浓度区中不会生成强电场。因此，即使在高浓度区中存在相对大量的晶体缺陷，半导体器件的耐压性也得以保持。因此，在为形成高浓度区进行的离子注入中，p型掺杂剂的注入浓度可被设定得相对高，使得浮区与体区以低电阻连接。另一方面，在低浓度区中，由于通过与漂移区的pn结导致的消耗，可生成相对强的电场。然而在低浓度区中，离子注入中p型掺杂剂的注入浓度低，由此晶体缺陷的发生被抑制。因此，即使在低浓度区中生成了相对强的电场，但半导体器件的耐压性得以保持。
考虑到以低电阻将浮区连接到体区，p型掺杂剂的最大浓度比p型掺杂剂的含量具有更高优先等级。因此，在高浓度区中p型掺杂剂的浓度分布曲线可具有相对陡峭的峰值。另一方面，考虑到充分消耗漂移区，p型掺杂剂的含量比p型掺杂剂的最大浓度具有更高的优先等级。因此，低浓度区中p型掺杂剂的浓度分布曲线在晶体缺陷的发生被抑制的范围内可具有相对平坦的形状。基于上述认识，在通过沿厚度方向绘制浮区中p型掺杂剂的浓度所得到的图中，可在高浓度区和低浓度区之间的边界上出现弯曲点或拐点。
在上述方面，当NA表示高浓度区中p型掺杂剂的最大浓度，NB表示低浓度区中p型掺杂剂的最大浓度时，可满足NA/NB≥2.5的条件。换言之，低浓度区中p型掺杂剂的最大浓度NB可最多是高浓度区中p型掺杂剂的最大浓度NA的40％。
利用这一结构，高浓度区与低浓度区之间的p型掺杂剂的浓度上具有足够大的差异。因此，低浓度区中晶体缺陷的发生被抑制，并且高浓度区中的电阻被充分减少。
在上述方面，高浓度区与低浓度区之间的边界可在厚度方向上与沟槽的底面隔开第一距离；低浓度区与n型漂移区之间的边界可在厚度方向上与沟槽的底面隔开第二距离；并且当XA表示第一距离而XB表示第二距离时，可满足XB/XA≥2的条件。这意味着高浓度区可设置在浮区的位于沟槽侧的一半的部分内。
利用这一结构，低浓度区相对宽，使得低浓度区中p型掺杂剂的最大浓度被减少。因此，低浓度区中晶体缺陷的发生被进一步有效地抑制。
在上述方面，低浓度区可以包含沿着碳化硅衬底的厚度方向布置的平坦区和减少区。所述平坦区可以是与高浓度区相接触的区，并且其中p型掺杂剂的浓度相对于所述弯曲点或拐点处p型掺杂剂的浓度处于规定范围内；所述减少区可以是与n型漂移区相接触的区，并且其中p型掺杂剂的浓度在从所述沟槽的所述底面离开的方向上减少。
附图说明
下面将参考附图对本发明示例性方面的特征、优势、以及技术和工业意义进行描述，其中相似的数字表示相似的要素，其中：
图1为示出了根据一个实施方式的半导体器件的结构的截面图，图1为沿图2中的I-I线得到的截面图；
图2为示出了在SiC衬底的上表面中沟槽布置的图；
图3为示出了沟槽端面附近的结构的截面图，图3为沿图2中的III-III线得到的截面图；
图4示出了浮区中p型掺杂剂的浓度分布曲线，该浓度分布曲线通过对浮区中p型掺杂剂的浓度沿着SiC衬底的厚度方向作图而获得；
图5是示出了深度比X和浓度比N的合适数值范围(对应于阴影部分)的图；
图6是示出了半导体器件的制造方法的一个步骤的图，并示出了包含漏区、漂移区和体区的SiC衬底；
图7是示出了半导体器件的制造方法的另一个步骤的图，并示出了其中已经形成有接触区、源区和沟槽的SiC衬底；
图8是示出了半导体器件的制造方法的又一个步骤的图，并示出了其中已经通过p型掺杂剂的离子注入而形成了浮区的SiC衬底；
图9A是示出了浮区中p型掺杂剂的浓度分布曲线的一个具体实例的图；
图9B是示出了浮区中p型掺杂剂的浓度分布曲线的另一个具体实例的图；以及
图9C是示出了浮区中p型掺杂剂的浓度分布曲线的又一个具体实例的图。
具体实施方式
下面，将参考附图对根据一个实施方式的半导体器件10和半导体器件10的制造方法进行描述。该实施方式中的半导体器件10是电力线路中使用的电力半导体器件。半导体器件10特别具有MOSFET结构。尽管半导体器件10的用途并没有特别限制，但半导体器件10可用作电动车辆如混合动力车辆、燃料电池车辆和电动车辆中的电力转换器电路例如转换器或逆变器的开关元件。在下文中，将首先描述半导体器件10的结构，然后将描述半导体器件10的制造方法。注意，下文中描述的半导体器件10和半导体器件10的制造方法各自只是一个实例，在本说明书中描述的技术要素可单独或以各种组合形式应用到各种其他半导体器件及其制造方法。
图1为示出了根据本实施方式的半导体器件10的结构的截面图。图1为半导体器件10的部分截面图。在半导体器件10中重复提供了在图1中示出的单元结构。正如在图1中所示，根据本实施方式的半导体器件10包含SiC衬底12，以及设置在SiC衬底12的上表面12a中形成的每个沟槽13中的栅电极14。栅电极14由导电材料例如多晶硅制成。
正如在图1和图2中所示的，在SiC衬底12的上表面12a中设置了多个沟槽13。沟槽13彼此平行延伸。每个沟槽13具有一对侧表面13a、底面13b和一对端面13c。侧表面13a是在沟槽13的宽度方向上彼此朝向的内表面，端面13c是在沟槽13的纵向上彼此朝向的内表面。在沟槽13中设置了栅绝缘膜14a，栅电极14朝向SiC衬底12，栅绝缘膜14a插在两者之间。栅绝缘膜14a由绝缘材料例如硅氧化物(SiO2)制成。注意，栅电极14和栅绝缘膜14a的材料并不局限于任何具体材料。
半导体器件10还包含设置在SiC衬底12的上表面12a上的源极16，以及设置在SiC衬底12的下表面12b上的漏极18。源极16与SiC衬底12的上表面12a呈欧姆接触，漏极18与SiC衬底12的下表面12b呈欧姆接触。中间层绝缘膜14b设置在源极16与栅电极14之间，使得源极16与栅电极14电绝缘。源极16和漏极18可以由导电材料例如铝(Al)、镍(Ni)、钛(Ti)或金(Au)制成。注意，源极16和漏极18的材料并不局限于任何具体材料。
在本说明书中，SiC衬底12的上表面12a指的是SiC衬底12的一个表面，SiC衬底12的下表面12b指的是SiC衬底12的另一个表面，其位于SiC衬底12的与上表面12a相对侧上。在本说明书中，为了方便，术语“上表面”和“下表面”用于将SiC衬底12的两个相对的表面进行彼此区分，并不旨在表示SiC衬底12的上表面12a总是位于其下表面12b的垂直上方。根据SiC衬底12的情形，上表面12a可位于下表面12b的垂直下方。
SiC衬底12包含漏区32、漂移区34、体区36、接触区38、源区40和浮区42。漏区32沿着SiC衬底12的下表面12b设置，并暴露在下表面12b处。漏区32是含有大量n型掺杂剂的n型区。n型掺杂剂可以是第V族元素(15族元素)，例如磷。漏极18与漏区32呈欧姆接触。
漂移区34设置在漏区32上，并与漏区32邻接。漂移区34为n型区。漂移区34中n型掺杂剂的浓度低于漏区32中n型掺杂剂的浓度。n型掺杂剂可以是第V族元素(15族元素)，例如磷。体区36设置在漂移区34上，并与漂移区34邻接。体区36与漏区32被至少漂移区34隔开。每个体区36是含有大量p型掺杂剂的p型区。p型掺杂剂可以是第III族元素(13族元素)，例如硼(B)或铝(Al)。
接触区38设置在体区36上，并暴露在SiC衬底12的上表面12a处。每个接触区38均是p型区。接触区38中p型掺杂剂的浓度高于体区36中p型掺杂剂的浓度。p型掺杂剂可以是第III族元素(13族元素)，例如硼(B)或铝(Al)。源区40设置在体区36上，并暴露在SiC衬底12的上表面12a处。源区40与漂移区34被至少体区36隔开。每个源区40均是n型区。源区40中n型掺杂剂的浓度高于漂移区34中n型掺杂剂的浓度。n型掺杂剂可以是第V族元素(15族元素)，例如磷。源极16与接触区38和源区40呈欧姆接触。沟槽13从SiC衬底12的上表面12a延伸穿过源区40和体区36进入漂移区34。
每个浮区42均设置在漂移区34内，以便与对应的沟槽13的底面13b邻接。浮区42为p型区。每个浮区42中p型掺杂剂的浓度例如基本上等于每个体区36中p型掺杂剂的浓度，并低于每个接触区38中p型掺杂剂的浓度。p型掺杂剂可以是第III族元素(13族元素)，例如硼(B)或铝(Al)。尽管下面会更详细地描述，但每个浮区42均通过将p型掺杂剂离子注入到与漂移区34相同的n型区中而形成。当p型浮区42设置在n型漂移区34内时，n型漂移区34的消耗加快，使得半导体器件10的耐压性可以增加。
正如在图3中所示，SiC衬底12还包含p型连接区46。每个p型连接区46沿着相应沟槽13的端面13c从体区36延伸到浮区42。浮区42连接到体区36，其中连接区46插在两者之间，使得浮区42的电势维持在与体区36相同的水平上。
正如在图1和图3中所示，每个浮区42包含在SiC衬底12的厚度方向上布置的高浓度区42a和低浓度区42b。在本说明书中，术语“SiC衬底12的厚度方向”指的是与SiC衬底12的上表面12a和下表面12b垂直的方向。SiC衬底12的厚度方向与沟槽13的深度方向一致。低浓度区42b中p型掺杂剂的浓度低于高浓度区42a中p型掺杂剂的浓度。高浓度区42a设置在沟槽13的底面13b和低浓度区42b之间。换言之，高浓度区42a设置在靠近沟槽13的底面13b处，低浓度区42b设置成与沟槽13的底面13b隔开。
参考图4对浮区42中p型掺杂剂的浓度分布曲线进行描述。正如图4中所示，高浓度区42a和低浓度区42b之间的边界42c在SiC衬底12的厚度方向上与沟槽13的底面13b隔开第一距离XA。此外，低浓度区42b和漂移区34之间的边界42d在SiC衬底12的厚度方向上与沟槽13的底面13b隔开第二距离XB。边界42d也作为浮区42的边界，并且是p型掺杂剂的浓度等于漂移区34中n型掺杂剂的浓度的位置。换言之，严格来说，p型掺杂剂的浓度在浮区42的边界42d处并不为零。第二距离XB长于第一距离XA。图4中的点C是在沟槽13的底面13b上的点，点C'是在低浓度区42b和漂移区34之间的边界42d上的点。穿过点C和点C'的直线与SiC衬底12的厚度方向平行，并位于沟槽13的宽度方向上的中心处。在图4中示出的浓度分布曲线中，高浓度区42a中p型掺杂剂的含量SA由以SA标记的面积表示，低浓度区42b中p型掺杂剂的含量SB由以SB标记的面积表示。
正如在图4中所示，当浮区42中p型掺杂剂的浓度沿着SiC衬底12的厚度方向绘制成图时，在图中高浓度区42a和低浓度区42b之间的边界42c处出现了弯曲点(即曲线斜率改变的点)或拐点(即曲线的曲率的符号改变的点)。换言之，图4中图上的弯曲点或拐点的位置对应于高浓度区42a和低浓度区42b之间的边界42c的位置。低浓度区42b中p型掺杂剂的含量SA等于或高于漂移区34的在厚度方向上与低浓度区42b邻接的部分(即，漂移区34的设置在低浓度区42b和漏区32之间的部分)中的n型掺杂剂的含量。换言之，低浓度区42b含有p型掺杂剂的量使得漂移区34能够被充分消耗。严格说来，有必要考虑低浓度区42b中n型掺杂剂的量。然而，低浓度区42b在尺寸上显著小于漂移区34，因此低浓度区42b中n型掺杂剂可以被忽略。
利用上述结构，浮区42中p型掺杂剂的浓度在与沟槽13的底面13b接近的高浓度区42a中高于在与沟槽13的底面13b隔开的低浓度区42b中。如上所述，低浓度区42b含有的p型掺杂剂的量使得漂移区34能够被充分消耗。因此，即使低浓度区42b通过漂移区34与浮区42之间的pn结而被消耗，高浓度区42a也被防止完全消耗。因此，在高浓度区42a中并不生成强电场。从而，即使在高浓度区42a中存在相对大量的晶体缺陷，半导体器件10的耐压性也得以保持。因此，在为形成高浓度区42a进行的离子注入中，p型掺杂剂的注入浓度可被设定得相对高，使得浮区42与体区36以低电阻连接。
另一方面，在低浓度区42b中由于通过与漂移区34的pn结导致的消耗而可生成相对强的电场。然而在低浓度区42b中，离子注入中p型掺杂剂的注入浓度低，由此晶体缺陷的发生被抑制。换言之，在为形成低浓度区42b进行的离子注入中，p型掺杂剂的注入浓度被确定为处于晶体缺陷的发生被抑制的范围内。因此，即使在低浓度区42b中生成了相对强的电场，半导体器件10的耐压性也被保持。当高浓度区42a和低浓度区42b因此被组合使用时，浮区42可以以低电阻连接到体区36而不会诱导漏电流的发生。结果，半导体器件10的耐压性显著增加。
考虑到以低电阻将浮区42连接到体区36，在高浓度区42a中p型掺杂剂的最大浓度NA比p型掺杂剂的含量SA(参见图4)有更高优先等级。因此，在高浓度区42a中p型掺杂剂的浓度分布曲线可具有相对陡峭的峰值。另一方面，考虑到充分消耗漂移区34，在低浓度区42b中p型掺杂剂的含量SB(参见图4)比p型掺杂剂的最大浓度NB具有更高优先等级。因此，低浓度区42b中p型掺杂剂的浓度分布曲线在晶体缺陷的发生被抑制的范围内可具有相对平坦的形状。换言之，在低浓度区42b中，p型掺杂剂的浓度在SiC衬底12的厚度方向上可相对恒定。例如，在低浓度区42b的厚度方向上至少50％的范围中，相对于p型掺杂剂的平均浓度，p型掺杂剂的浓度的变化范围可为至多±30％。基于上述认识，在指示浮区42中p型掺杂剂的浓度分布曲线的图中，如图4所示，在高浓度区42a和低浓度区42b之间的边界42c处可出现弯曲点或拐点。
根据本实施方式的浮区42被设计为使得第二距离XB对第一距离XA的比为2以上。换言之，满足XB/XA≥2的条件。这意味着高浓度区42a设置在浮区42的位于沟槽13侧的一半的部分内。在下文中，XB/XA的值有时被称为深度比X。
在根据本实施方式的浮区42中，高浓度区42a与低浓度区42b之间的p型掺杂剂的浓度存在足够大的差异。具体来说，高浓度区42a中p型掺杂剂的最大浓度NA与低浓度区42b中p型掺杂剂的最大浓度NB之间的关系满足条件NA/NB≥2.5。换言之，低浓度区42b中p型掺杂剂的最大浓度NB最多是高浓度区42a中p型掺杂剂的最大浓度NA的40％。在下文中，NA/NB的值有时被称为浓度比N。
第一距离XA、第二距离XB、高浓度区42a中的最大浓度NA和低浓度区42b中最大浓度NB的值不限于任何特定的数值。正如在图5中所示的，参数XA、XB、NA和NB可以酌情设置在如下范围内，其中深度比X满足条件X＝XB/XA≥2，浓度比N满足条件N＝NA/NB≥2.5(即在阴影区内)，这取决于半导体器件10的其他设计参数。例如，已经证实，当铝用作p型掺杂剂时，在铝离子的注入浓度小于4×1017/cm3的条件下在SiC衬底12中基本上不会出现晶体缺陷。因此，当铝用作p型掺杂剂时，低浓度区42b中最大浓度NB可小于4×1017/cm3。即使当使用其它p型掺杂剂时，据推测p型掺杂剂的注入浓度存在在SiC衬底12中基本上不会出现晶体缺陷的上限。因而，不论p型掺杂剂的种类如何，低浓度区42b中最大浓度NB可被设定为在SiC衬底12中基本上不会出现晶体缺陷的范围内的值。
浮区42中p型掺杂剂的浓度分布曲线可以例如通过下述工序而测定。首先，考虑到漂移区34的厚度以及用于离子注入的仪器的能力等，确定了第二距离XB。此外，提前确定了通过p型掺杂剂离子注入基本上不会在SiC衬底12中出现晶体缺陷的注入浓度的上限。所述上限可通过实验或模拟而获得。接着，确定低浓度区42b中p型掺杂剂的含量SB，使得低浓度区42b中p型掺杂剂的含量SB等于或高于漂移区34的在厚度方向上与低浓度区42b邻接的部分中n型掺杂剂的含量。漂移区34的在厚度方向上与低浓度区42b邻接的该部分中n型掺杂剂的含量可以通过例如将漂移区34中n型掺杂剂的浓度乘以漂移区34的在厚度方向上与低浓度区42b邻接的该部分的厚度(即低浓度区42b和漏区32之间的距离)而获得。接着，确定低浓度区42b的厚度(＝XB-XA)。在该情况下，低浓度区42b的厚度为达到确定的含量SB、同时将低浓度区42b中p型掺杂剂的最大浓度NB限制到等于或低于注入浓度上限的值所需的厚度。通过这种方式，确定了第一距离XA。最后，高浓度区42a所需的最大浓度NA被确定为使得浮区42与体区36以低电阻连接。或者，可以确定高浓度区42a所需的p型掺杂剂的含量SA，然后也可以基于第一距离XA确定高浓度区42a中的最大浓度NA。
在上述工序中，可以确定参数NA、XA和XB，使得深度比X(＝XB/XA)满足条件X≥2，和/或浓度比N(＝NA/NB)满足条件N≥2.5。
接下来将描述半导体器件10的制造方法。注意，下面描述的制造方法仅仅是一个实例，并不旨在限制半导体器件10的制造方法。正如在图6中所示的，准备将要用作漏区32的n型SiC晶片，通过外延生长SiC在漏区32上形成n型漂移区34。接着，通过外延生长SiC在漂移区34上形成p型体区36。由此制造出了具有包含漏区32、漂移区34和体区36的三层结构的SiC衬底12。
接下来，正如图7中所示的，通过SiC衬底12的上表面12a进行离子注入，以形成p型接触区38和n型源区40。然后，在SiC衬底12的上表面12a上形成由例如硅氧化物(SiO2)制成的掩模50，通过干法刻蚀在SiC衬底12的上表面12a中形成沟槽13。接着，如图8中所示的，在掩模50照原样使用的同时，在每个沟槽13中进行p型掺杂剂的离子注入，以形成浮区42。图8中示出的一组箭头P示意性指示了p型掺杂剂离子注入。在这个时候，通过调节离子注入持续时间和注入强度(例如赋予离子的加速能量)而形成高浓度区42a和低浓度区42b。通过退火活化了由此注入到SiC衬底12中的n型掺杂剂和p型掺杂剂。
然后形成栅绝缘膜14a、栅电极14、中间层绝缘膜14b、源极16、和漏极18，通过其他必要工序例如模切完成半导体器件10。
图9A、图9B和图9C示出了浮区42中p型掺杂剂的浓度分布曲线的三个具体实例。在所有这些具体实例中，在高浓度区42a和低浓度区42b之间的边界42c处(即，在与沟槽13的底面13b隔开第一距离XA的位置处)均出现了弯曲点或拐点。此外，在所有这些具体实例中，均满足条件XB/XA≥2和条件NA/NB≥2.5。注意，在图9A、图9B和图9C每个图中的纵坐标轴作为对数指示了p型掺杂剂浓度，因此在图中示出的尺寸并不总是满足条件XB/XA≥2。正如在图9A到图9C中所示的，浮区42中p型掺杂剂的浓度分布曲线可有多种变化，只要在高浓度区42a和低浓度区42b之间的边界42c处出现弯曲点或拐点且低浓度区42b中p型掺杂剂的含量等于或高于漂移区34中n型掺杂剂的含量即可。
虽然已经详细描述了本发明的示例性实施方式，但上述实施方式仅仅是实例，并不旨在限制所附权利要求的范围。说明书和附图中描述的技术要素单独地或以各种组合提供了技术有用性，并且这些技术要素的组合并不限于提交本申请时权利要求书中描述的组合。此外，在说明书和附图中以实施例描述的技术可以同时实现两个或更多个目的，并通过实现了这些目的中的至少一种而提供了技术有用性。

Claims (4)

1.金属氧化物半导体场效应晶体管，其特征在于包含：
包含沟槽的碳化硅衬底；和
设置在所述沟槽中的栅电极，
所述碳化硅衬底包含：
n型源区；
n型漂移区；
p型体区，所述p型体区设置在所述n型源区和所述n型漂移区之间；
p型浮区，所述p型浮区设置在所述漂移区内，所述p型浮区与所述沟槽的底面邻接；和
p型连接区，所述p型连接区从所述p型体区延伸到所述p型浮区，其中
所述p型浮区包含沿着所述碳化硅衬底的厚度方向布置的高浓度区和低浓度区，
所述高浓度区设置在所述沟槽的所述底面和所述低浓度区之间，所述高浓度区与所述低浓度区接触，
当通过沿着所述厚度方向绘制所述p型浮区中p型掺杂剂的浓度而获得图时，所述p型掺杂剂的最大浓度在所述高浓度区中高于在所述低浓度区中，并且所述图在所述高浓度区和所述低浓度区之间的边界处具有弯曲点或拐点，且
所述低浓度区中p型掺杂剂的含量等于或高于所述n型漂移区的在厚度方向上与所述低浓度区邻接的部分中的n型掺杂剂的含量。
2.根据权利要求1所述的金属氧化物半导体场效应晶体管，其特征在于，
当NA表示所述高浓度区中p型掺杂剂的最大浓度，NB表示所述低浓度区中p型掺杂剂的最大浓度时，满足NA/NB≥2.5的条件。
3.根据权利要求1或2所述的金属氧化物半导体场效应晶体管，其特征在于，
所述高浓度区和所述低浓度区之间的所述边界在所述厚度方向上与所述沟槽的所述底面隔开第一距离；
所述低浓度区和所述n型漂移区之间的边界在所述厚度方向上与所述沟槽的所述底面隔开第二距离；且
当XA表示所述第一距离，XB表示所述第二距离时，满足XB/XA≥2的条件。
4.根据权利要求1所述的金属氧化物半导体场效应晶体管，其特征在于，
所述低浓度区包含沿着所述碳化硅衬底的厚度方向布置的平坦区和减少区；
所述平坦区是与所述高浓度区接触的区，在所述平坦区中所述p型掺杂剂的浓度相对于所述弯曲点或所述拐点处所述p型掺杂剂的浓度处于规定范围内；和
所述减少区是与所述n型漂移区接触的区，在所述减少区中所述p型掺杂剂的浓度在从所述沟槽的所述底面离开的方向上减少。
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