WO2020238588A1 - 一种具有掩蔽层结构的碳化硅mosfet器件 - Google Patents

一种具有掩蔽层结构的碳化硅mosfet器件 Download PDF

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Publication number
WO2020238588A1
WO2020238588A1 PCT/CN2020/089348 CN2020089348W WO2020238588A1 WO 2020238588 A1 WO2020238588 A1 WO 2020238588A1 CN 2020089348 W CN2020089348 W CN 2020089348W WO 2020238588 A1 WO2020238588 A1 WO 2020238588A1
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masking layer
type
type source
source region
region
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PCT/CN2020/089348
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English (en)
French (fr)
Inventor
宋庆文
张玉明
汤晓燕
袁昊
何艳静
韩超
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西安电子科技大学
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Priority claimed from CN201910458073.8A external-priority patent/CN110212019A/zh
Priority claimed from CN201910459165.8A external-priority patent/CN110112218A/zh
Application filed by 西安电子科技大学 filed Critical 西安电子科技大学
Publication of WO2020238588A1 publication Critical patent/WO2020238588A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention belongs to the technical field of microelectronics, and specifically relates to a silicon carbide MOSFET device with a masking layer structure.
  • the wide band gap semiconductor material silicon carbide has a large forbidden band width, high critical breakdown electric field, high thermal conductivity and high electron saturation drift speed and other excellent physical and chemical properties, suitable for high temperature, high pressure, high power and radiation resistance Semiconductor devices.
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • Groove gate structure MOSFET is a newly developed high-efficiency power switching device after MOSFET. It adopts trench-type gate structure field effect tube, which not only inherits the high input impedance of MOS field effect tube ( ⁇ 10 8 ⁇ ), and small drive current (About 0.1 ⁇ A), it also has excellent characteristics such as high voltage resistance, large working current, high output power, good trans-conductivity and fast switching speed. Because it combines the advantages of electron tubes and power transistors, it is widely used in switching power supplies, inverters, voltage amplifiers, power amplifiers and other circuits. Therefore, high breakdown voltage, high current, and low on-resistance are the most critical indicators of power MOSFET devices.
  • the present invention provides a silicon carbide MOSFET device with a masking layer structure.
  • the technical problem to be solved by the present invention is realized through the following technical solutions:
  • the present invention provides a silicon carbide MOSFET device with a masking layer structure, which includes a drain electrode, an N-type doped substrate layer, an N-type drift region, and a P-type base region which are sequentially arranged from bottom to top;
  • the P-type base region is provided with a P-type source region and an N-type source region;
  • a trench gate structure is provided inside the P-type base region, the bottom of the trench gate structure extends to the inside of the N-type drift region, and the top of the trench gate structure extends beyond the upper surface of the P-type base region ;
  • a masking layer is provided under the trench gate structure, and the upper surface of the masking layer is in contact with the lower surface of the trench gate structure;
  • Active electrodes are arranged on the P-type source region and the N-type source region;
  • a gate electrode is provided on the trench gate structure.
  • the masking layer only covers a part of the lower surface of the trench gate structure, the length of the masking layer is greater than or equal to 0.5 ⁇ m, and the thickness is 0.5-1 ⁇ m.
  • the masking layer has a T-shaped structure, and includes a first masking part and a second masking part connected up and down, wherein the first masking part and the second masking part are both rectangular structures, and the The length of the first shielding portion is the same as the length of the slot gate structure, and the length of the second shielding portion is smaller than the length of the first shielding portion.
  • the thickness of the first masking portion is 0.3-0.5 ⁇ m
  • the length of the second masking portion is 0.5-1 ⁇ m
  • the thickness is 0.3-0.5 ⁇ m
  • the two P-type source regions are both rod-shaped and are respectively located at two ends of the upper surface of the P-type base region;
  • the two N-type source regions are both rod-shaped, respectively located inside the two P-type source regions and in contact with the P-type source regions on the corresponding side;
  • the trench gate structure includes a gate dielectric trench and a conductive material located inside the gate dielectric trench, wherein the portion of the gate dielectric trench protruding from the upper surface of the P-type base region is simultaneously with the two N Type the side contact of the source area.
  • the P-type source region is ring-shaped and surrounds the upper surface of the P-type base region
  • the N-type source region has a ring shape and is located inside the P-type source region ring;
  • the trench gate structure includes a gate dielectric trench and a conductive material located inside the gate dielectric trench, wherein the portion of the gate dielectric trench extending from the upper surface of the P-type base region is located in the N-type source region The center of the upper surface is in contact with the inner side surface of the N-type source region.
  • the gate electrode is provided on the upper surface of the conductive material.
  • the masking layer is connected to the source electrode through a metal wire.
  • the masking layer is P-type doped, and the doping concentration is 1 ⁇ 10 18 -5 ⁇ 10 18 cm -3 .
  • the masking layer is formed by an epitaxial process.
  • the present invention has the following beneficial effects:
  • the silicon carbide MOSFET device with a masking layer structure of the present invention by adding a masking layer at the bottom of the trench gate, without increasing the cell area of the device, the electric field concentration at the corners of the trench gate structure is reduced and the device is improved.
  • the breakdown voltage by adding a masking layer at the bottom of the trench gate, without increasing the cell area of the device, the electric field concentration at the corners of the trench gate structure is reduced and the device is improved. The breakdown voltage.
  • the silicon carbide MOSFET device with a masking layer structure of the present invention has a smaller masking layer area, which can reduce the JFET resistance between the masking layer and the P-type base region, and effectively increase the on-current of the device.
  • the silicon carbide MOSFET device with a masking layer structure of the present invention by adding a T-shaped masking layer structure at the bottom of the trench gate structure, the electric field concentration at the corners of the trench gate structure is reduced, and the breakdown voltage of the MOSFET device is increased, and Due to the existence of the T-shaped masking layer structure, the overlapping area of the gate electrode and the drain electrode of the device is reduced, the capacitive coupling between the two electrodes is relieved, and the gate-drain capacitance is reduced, so that the gate-drain capacitance is increased during the operation of the device. The amount of charged charge is reduced, which increases the switching speed of the device and reduces the switching power consumption of the device.
  • FIG. 1 is a schematic structural diagram of a silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention
  • FIG. 2 is a schematic diagram of partial dimensions of a silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of another silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention
  • FIG. 4 is a schematic diagram of partial dimensions of another silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention
  • FIG. 5 is a top view of a silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention with electrodes removed;
  • FIG. 6 is a top view of another silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention with electrodes removed;
  • FIGS. 7a-7g are structural schematic diagrams of intermediates in steps of a method for preparing a silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention.
  • FIGS. 8a-8g are structural schematic diagrams of intermediates in the steps of another method for preparing a silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention.
  • the silicon carbide MOSFET device with a masking layer structure of this embodiment includes: The drain electrode 1, the N-type doped substrate layer 2, the N-type drift region 3, and the P-type base region 4 are sequentially arranged from bottom to top.
  • the drain electrode 1 is a Ti/Ni/Al alloy metal layer with a thickness of 2-5 ⁇ m.
  • the N-type doped substrate layer 2 is used as a heavily doped substrate to reduce the on-resistance of the device and transmit current, and has a thickness of 2-5 ⁇ m and a doping concentration of 5 ⁇ 10 18 -1 ⁇ 10 20 cm -3 .
  • the N-type drift region 3 is used as a lightly doped region to bear the voltage of the drain electrode 1 under reverse cut-off operation to prevent the device from being broken down. Its thickness is 8-10 ⁇ m, and the doping concentration is 1 ⁇ 10 15 -1 ⁇ 10 16 cm -3 , because the doping concentration is too high, the on-resistance of the device is reduced, and the breakdown voltage of the device is reduced.
  • the P-type base region 4 is used as a lightly doped P-type source region to isolate the drain electrode 1 from the source electrode 9 and form a conductive channel when the gate electrode 10 is turned on. Its thickness is 0.5-3 ⁇ m. If the thickness is too large, the device conductive channel will be increased. The length of the channel increases the on-resistance, and the doping concentration is 1 ⁇ 10 17 -3 ⁇ 10 17 cm -3 . Because the doping concentration is too high, the threshold voltage of the device is high, and the gate charging speed is reduced. The electrode driving circuit requirements are increased, the doping concentration is too low, the threshold voltage of the device is too low, and it is easy to turn on by mistake. Therefore, the doping concentration is selected as 1 ⁇ 10 17 -3 ⁇ 10 17 cm - 3 after comprehensive consideration.
  • the P-type base region 4 is provided with a P-type source region 5 and an N-type source region 6, and the P-type base region 4 is provided with a trench gate structure 7 inside, and the bottom of the trench gate structure 7 extends to the N-type drift region 3.
  • the top of the trench gate structure 7 extends from the upper surface of the P-type base region 4, the P-type source region 5 and the N-type source region 6 are provided with an active electrode 9, and the trench gate structure 7 is provided with a gate electrode 10.
  • the two P-type source regions 5 are both rod-shaped and are located at both ends of the upper surface of the P-type base region 4, and the two N-type source regions 6 are both rod-shaped.
  • the trench gate structure 7 includes a gate dielectric trench 11 and a conductive material 12 located inside the gate dielectric trench 11. The part of the gate dielectric trench 11 that extends from the upper surface of the P-type base region 4 is simultaneously with the sides of the two N-type source regions 6 contact.
  • the source electrode 9 is provided on the P-type source region 5 and the N-type source region 6, and the gate electrode 10 is provided on the upper surface of the conductive material 12.
  • the P-type source region 5 is used to connect the P-type base region 4 and the source electrode 9.
  • the length c of the P-type source region 5 is 0.25-1 ⁇ m
  • the thickness d is 0.25-1 ⁇ m
  • the doping concentration is 1 ⁇ 10 19 -1 ⁇ 10 20 cm - 3 .
  • the N-type source region 6 is used to collect and conduct current to the source electrode 9, and has a length e of 0.25-1 ⁇ m, a thickness f of 0.25-1 ⁇ m, and a doping concentration of 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 .
  • the gate dielectric trench 11 is a silicon dioxide layer trench used to form a groove-type conductive channel with a thickness g of 50-60 nm.
  • the silicon dioxide layer is prepared by a dry oxygen oxidation process and a wet oxygen oxidation process. to make.
  • the conductive material 12 is filled in the gate dielectric trench 11 through a deposition process to control the turn-on and turn-off of the device.
  • the material is a boron ion-doped polysilicon material with a doping concentration of 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 .
  • the gate electrode 10 is an Al metal layer with a thickness of 2-5 ⁇ m.
  • the P-type source region 5 is ring-shaped and surrounds the upper surface of the P-type base region 4, and the N-type source region 6 is ring-shaped. It is located inside the ring of the P-type source region 5, and the outer side surface of the N-type source region 6 is in contact with the inner side surface of the P-type source region 5.
  • the trench gate structure 7 includes a gate dielectric trench 11 and a conductive material 12 located inside the gate dielectric trench 11, wherein the portion of the gate dielectric trench 11 extending beyond the upper surface of the P-type base region 4 is located on the upper surface of the N-type source region 6. The center is in contact with the inner surface of the N-type source region 6.
  • the source electrode 9 is provided on the P-type source region 5 and the N-type source region 6, and the gate electrode 10 is provided on the upper surface of the conductive material 12.
  • the P-type source region 5 is used to connect the P-type base region 4 and the source electrode 9, the length c is 0.25-1 ⁇ m, the thickness d is 0.25-1 ⁇ m, and the doping concentration is 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 .
  • the N-type source region 6 is used to collect and conduct current to the source electrode 9, and has a length e of 0.25-1 ⁇ m, a thickness f of 0.25-1 ⁇ m, and a doping concentration of 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 .
  • the gate dielectric trench 11 is a silicon dioxide layer trench used to form a groove-type conductive channel with a thickness g of 50-60 nm.
  • the silicon dioxide layer is prepared by a dry oxygen oxidation process and a wet oxygen oxidation process. to make.
  • the conductive material 12 is filled in the gate dielectric trench 11 through a deposition process to control the turn-on and turn-off of the device.
  • the material is a boron ion-doped polysilicon material with a doping concentration of 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 .
  • the gate electrode 10 is an Al metal layer with a thickness of 2-5 ⁇ m.
  • a masking layer 8 is provided under the trench gate structure 7, and the upper surface of the masking layer 8 is in contact with the lower surface of the trench gate structure 7, not in contact with the lower surface of the P-type base region 4, and the masking layer 8 only covers Part of the bottom surface of the trench gate structure 7.
  • the length a of the masking layer 8 is greater than or equal to 0.5 ⁇ m
  • the thickness b is 0.5-1 ⁇ m
  • the masking layer 8 is P-type doped
  • the doping concentration is 1 ⁇ 10 18 -5 ⁇ 10 18 cm -3 . Formed by ion implantation process.
  • the electric field concentration at the corners of the gate dielectric trench 11 causes the device to break down below the ideal breakdown voltage.
  • a masking layer 8 is added at the bottom of the, because the masking layer 8 is a P-type doped region, a PN junction depletion region is formed between the masking layer 8 and the N-type drift region 3, and the drain voltage drop drops at the PN junction when the device is blocked in the forward direction , The electric field distribution of the device is changed, the electric field intensity at the corners of the gate dielectric trench 11 is reduced, and the breakdown voltage of the semiconductor device is increased. Moreover, due to the existence of the masking layer 8, the gate electrode 10 and the drain electrode of the device are reduced.
  • the shortest length of the masking layer 8 is 0.5 ⁇ m. It is considered that if the length is too short, the PN junction formed between the masking layer 8 and the N-type drift region 3 cannot protect the corners of the gate dielectric trench 11 not covered by the masking layer 8. , It is easy to cause the device to be broken down before reaching the rated breakdown voltage, and in the silicon carbide MOSFET device with the masking layer structure of this embodiment, the contact area between the masking layer 8 and the N-type drift region 3 is small, which can be effective Increase the on-current of the device because the larger the PN contact area, the larger the area of the depletion region formed, the smaller the conductive path, and the greater the resistance.
  • the masking layer 8 when the MOSFET device is used in high frequency, the masking layer 8 can be connected to the source electrode 9 through an internal metal connection.
  • the MOSFET device when the MOSFET device is used in a normally-on switch, the masking layer 8 No electrodes are connected.
  • a masking layer 8 is added at the bottom of the trench gate structure 7. Since the masking layer 8 is a P-type doped region, a PN junction loss is formed between the masking layer 8 and the N-type drift region 3. In the dead region, when the device is blocked in the forward direction, the drain voltage drop drops at the PN junction, which changes the electric field distribution of the device, reduces the electric field intensity at the corners of the trench gate structure 7, and increases the breakdown voltage of the semiconductor device.
  • the contact area between the masking layer 8 and the N-type drift region 3 of this embodiment is small, which can effectively increase the on-current of the device.
  • Figures 7a-7g are structural schematic diagrams of intermediates in the steps of a method for preparing a silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention.
  • the method for preparing a MOSFET device of this embodiment is specifically It includes the following steps:
  • a silicon carbide substrate is selected as the N-type doped substrate layer 2, and a nitrogen ion doped 8-10 ⁇ m is epitaxially grown on the upper surface of the silicon carbide substrate.
  • the N-type drift region 3 has a doping concentration of 1 ⁇ 10 15 -1 ⁇ 10 16 cm -3 .
  • a P-type base region is formed. Specifically, referring to FIG. 7b, a P-type base region 4 is epitaxially formed on the upper surface of the N-type drift region 3, the thickness is 0.5-3 ⁇ m, and the doping concentration is 1 ⁇ 10 17 -3 ⁇ 10 17 cm -3 .
  • a P-type source region and an N-type source region are formed. Specifically, referring to FIG. 7c, a P-type source region 5 and an N-type source region 6 are formed on the upper surface of the P-type base region 4 by ion implantation.
  • the P-type source region The doping concentration of 5 is 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3
  • the doping concentration of N-type source region 6 is 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3
  • the thickness of the source region 6 is 0.25-1 ⁇ m.
  • a groove is formed. Specifically, referring to FIG. 7d, a groove is formed by etching. The groove penetrates the N-type source region 6 and the P-type base region 4 and extends into the N-type drift region 3.
  • the groove The length h is 1-3 ⁇ m, and the depth i is 2-3 ⁇ m.
  • the length of the masking layer 8 does not exceed the length of the groove, the shortest is 0.5 ⁇ m, and the thickness is 0.5-1 ⁇ m.
  • a trench gate structure is formed. Specifically, referring to FIG. 7f, a silicon dioxide gate dielectric trench 11 is formed through a dry oxygen oxidation process and a wet oxygen oxidation process.
  • the gate dielectric trench 11 serves as a recessed conductive channel, and its thickness is 50-60nm.
  • a boron ion-doped polysilicon is deposited inside the gate dielectric trench 11 as the conductive material 12. The doping concentration of the boron ion-doped polysilicon is 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 , and the gate dielectric
  • the trench 11 and the conductive material 12 form a trench gate structure 7.
  • the electrode metal is formed. Specifically, referring to FIG. 7g, a metal layer is deposited on the upper surface of the conductive material 12 as the gate electrode 10, and a metal layer is deposited on the upper surfaces of the P-type source region 5 and the N-type source region 6, as The source electrode 9 has a metal layer deposited on the lower surface of the N-type doped substrate layer 2 as the drain electrode 1.
  • the source electrode 9 and the drain electrode 1 are Ti/Ni/Al alloy metal layers, and the gate electrode 10 is an Al metal layer, both of which have a thickness of 2-5 ⁇ m.
  • FIG. 3 is a schematic structural diagram of another silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention.
  • the silicon carbide MOSFET device with a masking layer structure of this embodiment includes a drain electrode 1, an N-type doped substrate layer 2, an N-type drift region 3, and a P-type base region 4 sequentially arranged from bottom to top.
  • the drain electrode 1 is a Ti/Ni/Al alloy metal layer with a thickness of 2-5 ⁇ m.
  • the N-type doped substrate layer 2 is used as a heavily doped substrate to reduce the on-resistance of the device and transmit current, and has a thickness of 2-5 ⁇ m and a doping concentration of 5 ⁇ 10 18 -1 ⁇ 10 20 cm -3 .
  • the N-type drift region 3 is used as a lightly doped region to bear the voltage of the drain electrode 1 under reverse cut-off operation to prevent the device from being broken down. Its thickness is 8-10 ⁇ m, and the doping concentration is 1 ⁇ 10 15 -1 ⁇ 10 16 cm -3 , because the doping concentration is too high, the on-resistance of the device is reduced, and the breakdown voltage of the device is reduced.
  • the P-type base region 4 is used as a lightly doped P-type source region to isolate the drain electrode 1 from the source electrode 9 and form a conductive channel when the gate electrode 10 is turned on.
  • the thickness is 0.5-3 ⁇ m. If the thickness is too large, the device conductive channel will be increased. The on-resistance increases, and the doping concentration is 1 ⁇ 10 17 -3 ⁇ 10 17 cm -3 . Because the doping concentration is too high, the threshold voltage of the device is high, and the gate charging speed is reduced. Drive circuit requirements are increased, the doping concentration is too low, the threshold voltage of the device is low, and it is easy to turn on by mistake, so the doping concentration is selected as 1 ⁇ 10 17 -3 ⁇ 10 17 cm -3 after comprehensive consideration.
  • the P-type base region 4 is provided with a P-type source region 5 and an N-type source region 6, and the P-type base region 4 is provided with a trench gate structure 7 inside, and the bottom of the trench gate structure 7 extends to the N-type drift region 3.
  • the top of the trench gate structure 7 extends from the upper surface of the P-type base region 4, the P-type source region 5 and the N-type source region 6 are provided with an active electrode 9, and the trench gate structure 7 is provided with a gate electrode 10.
  • the two P-type source regions 5 are both rod-shaped and are located at both ends of the upper surface of the P-type base region 4, and the two N-type source regions 6 are both rod-shaped.
  • the trench gate structure 7 includes a gate dielectric trench 11 and a conductive material 12 located inside the gate dielectric trench 11. The part of the gate dielectric trench 11 that extends from the upper surface of the P-type base region 4 is simultaneously with the sides of the two N-type source regions 6 contact.
  • the source electrode 9 is provided on the P-type source region 5 and the N-type source region 6, and the gate electrode 10 is provided on the upper surface of the conductive material 12.
  • the P-type source region 5 is used to connect the P-type base region 4 and the source electrode 9.
  • the length e of the P-type source region 5 is 0.25-1 ⁇ m
  • the thickness f is 0.25-1 ⁇ m
  • the doping concentration is 1 ⁇ 10 19 -1 ⁇ 10 20 cm - 3 .
  • the N-type source region 6 is used to collect and conduct current to the source electrode 9, and has a length g of 0.25-1 ⁇ m, a thickness h of 0.25-1 ⁇ m, and a doping concentration of 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 .
  • the gate dielectric trench 11 is a silicon dioxide layer trench for forming a groove-type conductive channel with a thickness i of 50-60 nm.
  • the silicon dioxide layer is prepared by a dry oxygen oxidation process and a wet oxygen oxidation process. to make.
  • the conductive material 12 is filled in the gate dielectric trench 11 through a deposition process to control the turn-on and turn-off of the device.
  • the material is a boron ion-doped polysilicon material with a doping concentration of 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 .
  • the gate electrode 10 is an Al metal layer with a thickness of 2-5 ⁇ m.
  • the P-type source region 5 is ring-shaped and surrounds the upper surface of the P-type base region 4, and the N-type source region 6 is ring-shaped and is located in the P-type source region 5.
  • the inner side of the ring, and the outer side of the N-type source region 6 is in contact with the inner side of the P-type source region 5.
  • the trench gate structure 7 includes a gate dielectric trench 11 and a conductive material 12 located inside the gate dielectric trench 11, wherein the portion of the gate dielectric trench 11 extending beyond the upper surface of the P-type base region 4 is located on the upper surface of the N-type source region 6.
  • the center is in contact with the inner surface of the N-type source region 6.
  • the source electrode 9 is provided on the P-type source region 5 and the N-type source region 6, and the gate electrode 10 is provided on the upper surface of the conductive material 12.
  • the P-type source region 5 is used to connect the P-type base region 4 and the source electrode 9, with a length e of 0.25-1 ⁇ m, a thickness f of 0.25-1 ⁇ m, and a doping concentration of 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 .
  • the N-type source region 6 is used to collect and conduct current to the source electrode 9, and has a length g of 0.25-1 ⁇ m, a thickness h of 0.25-1 ⁇ m, and a doping concentration of 1 ⁇ 10 19 -1 ⁇ 10 20 cm - 3 .
  • the gate dielectric trench 11 is a silicon dioxide layer trench for forming a groove-type conductive channel with a thickness i of 50-60 nm.
  • the silicon dioxide layer is prepared by a dry oxygen oxidation process and a wet oxygen oxidation process. to make.
  • the conductive material 12 is filled in the gate dielectric trench 11 through a deposition process to control the turn-on and turn-off of the device.
  • the material is a boron ion-doped polysilicon material with a doping concentration of 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 .
  • the gate electrode 10 is an Al metal layer with a thickness of 2-5 ⁇ m.
  • a masking layer 8 is provided under the trench gate structure 7, and the masking layer 8 is a T-shaped structure, and its upper surface is in contact with the lower surface of the trench gate structure 7 and not in contact with the lower surface of the P-type base region 4.
  • the masking layer 8 includes a first masking portion 13 and a second masking portion 14, wherein the first masking portion 13 and the second masking portion 14 are both rectangular structures, and the length a of the first masking portion 13 is the same as the length of the gate dielectric trench 11
  • the length b of the second shielding portion 14 is smaller than the length a of the first shielding portion 13.
  • the thickness c of the first masking portion 13 is 0.3-0.5 ⁇ m
  • the length b of the second masking portion 14 is 0.5-1 ⁇ m
  • the thickness d is 0.3-0.5 ⁇ m.
  • the first masking portion 13 and the second masking portion 14 form a T-shaped structure with a wide top and a narrow bottom.
  • the masking layer 8 is P-type doped with a doping concentration of 1 ⁇ 10 18 -5 ⁇ 10 18 cm -3 , and the masking layer 8 is formed by an epitaxial process.
  • the electric field concentration at the corners of the gate dielectric trench 11 causes the device to break down below the ideal breakdown voltage.
  • a masking layer 8 is added at the bottom of the, because the masking layer 8 is a P-type doped region, a PN junction depletion region is formed between the masking layer 8 and the N-type drift region 3, and the drain voltage drop drops at the PN junction when the device is blocked in the forward direction , The electric field distribution of the device is changed, the electric field intensity at the corners of the gate dielectric trench 11 is reduced, and the breakdown voltage of the semiconductor device is increased. Moreover, due to the existence of the masking layer 8, the gate electrode 10 and the drain electrode of the device are reduced.
  • the masking layer 8 when the MOSFET device is used in high frequency, the masking layer 8 can be connected to the source electrode 9 through an internal metal connection.
  • the masking layer 8 No electrode When the MOSFET device is used in a normally-on switch, the masking layer 8 No electrode can be connected.
  • FIGS. 8a-8g are structural schematic diagrams of intermediates in the steps of another method for manufacturing a silicon carbide MOSFET device with a masking layer structure provided by an embodiment of the present invention.
  • the manufacturing method of the MOSFET device of this embodiment specifically includes the following steps:
  • a silicon carbide substrate is selected as the N-type doped substrate layer 2, and a nitrogen ion doped 8-10 ⁇ m is epitaxially grown on the upper surface of the silicon carbide substrate.
  • the N-type drift region 3 has a doping concentration of 1 ⁇ 10 15 -1 ⁇ 10 16 cm -3 .
  • a P-type base region is formed. Specifically, referring to FIG. 8b, a P-type base region 4 is epitaxially formed on the upper surface of the N-type drift region 3 with a thickness of 0.5-3 ⁇ m and a doping concentration of 1 ⁇ 10 17 -3 ⁇ 10 17 cm -3 .
  • a P-type source region and an N-type source region are formed. Specifically, referring to FIG. 8c, a P-type source region 5 and an N-type source region 6 are formed on the upper surface of the P-type base region 4 by ion implantation.
  • the doping concentration of 5 is 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3
  • the doping concentration of N-type source region 6 is 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3
  • the thickness of the source region 6 is 0.25-1 ⁇ m.
  • a groove is formed. Specifically, referring to FIG. 8d, a groove is formed by etching. The groove penetrates the N-type source region 6 and the P-type base region 4 and extends into the N-type drift region 3.
  • the groove The length l is 1-3 ⁇ m, the depth m is 2-4 ⁇ m, the bottom of the groove is provided with a boss structure, the length j of the boss structure is 0.5-1 ⁇ m, and the depth k is 0.3-0.5 ⁇ m.
  • the boss structure is used to form the second masking portion 14 by extension.
  • a masking layer structure is formed. Specifically, referring to FIG. 8e, the second masking portion 14 is formed by epitaxially filling the boss structure, and the first masking portion 13 is formed by epitaxy on the second masking portion 14. The thickness is 0.3-0.5 ⁇ m.
  • the first masking portion 13 and the second masking portion 14 form a masking layer 8 with a T-shaped structure with a wide upper and a narrow bottom.
  • the masking layer 8 is P-type doped, and the doping concentration is 1 ⁇ 10 18 -5 ⁇ 10 18 cm -3 .
  • a trench gate structure is formed. Specifically, referring to FIG. 8f, a silicon dioxide gate dielectric trench 11 is formed through a dry oxygen oxidation process and a wet oxygen oxidation process.
  • the gate dielectric trench 11 serves as a groove-type conductive channel with a thickness of 50-60nm.
  • a boron ion-doped polysilicon is deposited inside the gate dielectric trench 11 as the conductive material 12. The doping concentration of the boron ion-doped polysilicon is 1 ⁇ 10 19 -1 ⁇ 10 20 cm -3 , and the gate dielectric
  • the trench 11 and the conductive material 12 form a trench gate structure 7.
  • the electrode metal is formed. Specifically, referring to FIG. 8g, a metal layer is deposited on the upper surface of the conductive material 12 as the gate electrode 10, and a metal layer is deposited on the upper surfaces of the P-type source region 5 and the N-type source region 6, as The source electrode 9 has a metal layer deposited on the lower surface of the N-type doped substrate layer 2 as the drain electrode 1.
  • the source electrode 9 and the drain electrode 1 are Ti/Ni/Al alloy metal layers, and the gate electrode 10 is an Al metal layer, both of which have a thickness of 2-5 ⁇ m.

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Abstract

本发明涉及一种具有掩蔽层结构的碳化硅MOSFET器件，包括从下至上依次设置的漏电极、N型掺杂衬底层、N型漂移区和P型基区；所述P型基区上设置有P型源区和N型源区；所述P型基区的内部设置有槽栅结构，所述槽栅结构的底部延伸至所述N型漂移区的内部，所述槽栅结构的顶部延伸出所述P型基区的上表面；所述槽栅结构的下方设置有掩蔽层，且所述掩蔽层的上表面与所述槽栅结构的下表面接触；所述P型源区和所述N型源区上设置有源电极；所述槽栅结构上设置有栅电极。本发明的碳化硅MOSFET器件，通过在槽栅结构的底部增加掩蔽层，提高了器件的击穿电压，而且增大了器件的开关速度，同时也减少了器件的开关功耗。

Description

一种具有掩蔽层结构的碳化硅MOSFET器件 技术领域
本发明属于微电子技术领域，具体涉及一种具有掩蔽层结构的碳化硅MOSFET器件。
背景技术
宽带隙半导体材料碳化硅具有较大的禁带宽度，较高的临界击穿电场，高热导率和高电子饱和漂移速度等优良物理和化学特性，适合制作高温、高压、大功率及抗辐照的半导体器件。在功率电子领域中，功率金属氧化物半导体场效应晶体管(MOSFET，Metal-Oxide-Semiconductor-Field-Effect-Transistor)已经被广泛引入，它具有栅极驱动简单，开关时间短等特点。
槽栅结构MOSFET是继MOSFET之后新发展的一种高效功率开关器件，它采用沟槽型栅极结构场效应管，不仅继承了MOS场效应管输入阻抗高(≥10 8Ω)、驱动电流小(0.1μA左右)的优点，还具有耐高压、工作电流大、输出功率高、跨导线性好和开关速度快等优良特性。由于它将电子管与功率晶体管的优点集于一身，因此在开关电源、逆变器、电压放大器、功率放大器等电路中获得广泛应用。因此高击穿电压、大电流、低导通电阻是功率MOSFET器件最为关键的指标。
目前，在传统的槽栅结构MOSFET器件中已经能够通过设计使其达到较高的耐压水平，但是在实际应用中，槽栅结构MOSFET器件中的栅氧化层拐角处电场集中导致栅介质层击穿，使得器件在低于额定击穿电压下发 生击穿，严重影响到器件的正向阻断特性。
发明内容
为了解决现有技术中存在的上述问题，本发明提供了一种具有掩蔽层结构的碳化硅MOSFET器件。本发明要解决的技术问题通过以下技术方案实现：
本发明提供了一种具有掩蔽层结构的碳化硅MOSFET器件，包括从下至上依次设置的漏电极、N型掺杂衬底层、N型漂移区和P型基区；
所述P型基区上设置有P型源区和N型源区；
所述P型基区的内部设置有槽栅结构，所述槽栅结构的底部延伸至所述N型漂移区的内部，所述槽栅结构的顶部延伸出所述P型基区的上表面；
所述槽栅结构的下方设置有掩蔽层，且所述掩蔽层的上表面与所述槽栅结构的下表面接触；
所述P型源区和所述N型源区上设置有源电极；
所述槽栅结构上设置有栅电极。
在本发明的一个实施例中，所述掩蔽层仅覆盖所述槽栅结构的下表面的一部分，所述掩蔽层的长度大于等于0.5μm，厚度为0.5-1μm。
在本发明的一个实施例中，所述掩蔽层为T型结构，包括上下连接的第一掩蔽部和第二掩蔽部，其中，所述第一掩蔽部和所述第二掩蔽部均为长方形结构，所述第一掩蔽部的长度与所述槽栅结构的长度相同，所述第二掩蔽部的长度小于所述第一掩蔽部的长度。
在本发明的一个实施例中，所述第一掩蔽部的厚度为0.3-0.5μm，所述第二掩蔽部的长度为0.5-1μm，厚度为0.3-0.5μm。
在本发明的一个实施例中，两个所述P型源区均呈杆状，分别位于所 述P型基区上表面的两端；
两个所述N型源区均呈杆状，分别位于两个所述P型源区的内侧且与对应侧的所述P型源区相接触；
所述槽栅结构包括栅介质沟槽和位于所述栅介质沟槽内部的导电材料，其中，所述栅介质沟槽伸出所述P型基区上表面的部分同时与两个所述N型源区的侧面接触。
在本发明的一个实施例中，所述P型源区呈环状，且环绕所述P型基区上表面的四周；
所述N型源区呈环状，位于所述P型源区环状的内侧；
且所述N型源区的外侧面与所述P型源区的内侧面相接触；
所述槽栅结构包括栅介质沟槽和位于所述栅介质沟槽内部的导电材料，其中，所述栅介质沟槽伸出所述P型基区上表面的部分位于所述N型源区上表面的中心，且与所述N型源区的内侧面相接触。
在本发明的一个实施例中，所述栅电极设置在所述导电材料的上表面。
在本发明的一个实施例中，所述掩蔽层通过金属线连接所述源电极。
在本发明的一个实施例中，所述掩蔽层为P型掺杂，掺杂浓度为1×10 18-5×10 18cm -3。
在本发明的一个实施例中，所述掩蔽层通过外延工艺形成。
与现有技术相比，本发明的有益效果在于：
1、本发明的具有掩蔽层结构的碳化硅MOSFET器件，通过在槽栅底部增加掩蔽层，在不增大器件元胞面积的情况下，降低了槽栅结构拐角处的电场聚集，提高了器件的击穿电压。
2、本发明的具有掩蔽层结构的碳化硅MOSFET器件，它的掩蔽层区域 的面积较小，可以减小掩蔽层与P型基区的JFET电阻，有效的增大了器件的导通电流。
3、本发明的具有掩蔽层结构的碳化硅MOSFET器件，通过在槽栅结构的底部增加T型掩蔽层结构，降低了槽栅结构拐角处的电场集中，提高了MOSFET器件的击穿电压，而且由于T型掩蔽层结构的存在，减小了器件的栅电极与漏电极的交叠面积，缓解了两电极之间的电容耦合，减小了栅漏电容，使得器件工作过程中给栅漏电容充电的电荷量减少，增大了器件的开关速度，同时也减少了器件的开关功耗。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
附图说明
图1是本发明实施例提供的一种具有掩蔽层结构的碳化硅MOSFET器件的结构示意图；
图2是本发明实施例提供的一种具有掩蔽层结构的碳化硅MOSFET器件的部分尺寸标注示意图；
图3是本发明实施例提供的另一种具有掩蔽层结构的碳化硅MOSFET器件的结构示意图；
图4是本发明实施例提供的另一种具有掩蔽层结构的碳化硅MOSFET器件的部分尺寸标注示意图；
图5是本发明实施例提供的一种具有掩蔽层结构的碳化硅MOSFET器件除去电极的俯视图；
图6是本发明实施例提供的另一种具有掩蔽层结构的碳化硅MOSFET器件除去电极的俯视图；
图7a-7g是本发明实施例提供的一种具有掩蔽层结构的碳化硅MOSFET器件制备方法步骤的中间体的结构示意图；
图8a-8g是本发明实施例提供的另一种具有掩蔽层结构的碳化硅MOSFET器件制备方法步骤的中间体的结构示意图。
附图标记说明
1-漏电极；2-N型掺杂衬底层；3-N型漂移区；4-P型基区；5-P型源区；6-N型源区；7-槽栅结构；8-掩蔽层；9-源电极；10-栅电极；11-栅介质沟槽；12-导电材料；13-第一掩蔽部；14-第二掩蔽部。
具体实施方式
为了进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及具体实施方式，对依据本发明提出的一种具有掩蔽层结构的碳化硅MOSFET器件进行详细说明。
有关本发明的前述及其他技术内容、特点及功效，在以下配合附图的具体实施方式详细说明中即可清楚地呈现。通过具体实施方式的说明，可对本发明为达成预定目的所采取的技术手段及功效进行更加深入且具体地了解，然而所附附图仅是提供参考与说明之用，并非用来对本发明的技术方案加以限制。
实施例一
请参见图1，图1是本发明实施例提供的一种具有掩蔽层结构的碳化硅MOSFET器件的结构示意图，如图所示，本实施例的具有掩蔽层结构的碳化硅MOSFET器件包括，从下至上依次设置的漏电极1、N型掺杂衬底层 2、N型漂移区3和P型基区4。具体地，漏电极1为Ti/Ni/Al合金金属层，厚度为2-5μm。N型掺杂衬底层2作为重掺杂衬底用于减小器件导通电阻并传输电流，其厚度为2-5μm，掺杂浓度为5×10 18-1×10 20cm -3。N型漂移区3作为轻掺杂区用于反向截至工作下承担漏电极1的电压，防止器件被击穿，其厚度为8-10μm，掺杂浓度为1×10 15-1×10 16cm -3，因为掺杂浓度过高，器件导通电阻减小，器件击穿电压会降低。P型基区4作为轻掺杂P型源区用于将漏电极1与源电极9隔离并在栅电极10开启时形成导电沟道，其厚度为0.5-3μm，厚度过大会增加器件导电沟道的长度，使得导通电阻增大，掺杂浓度为1×10 17-3×10 17cm -3，因为掺杂浓度过高，器件的阈值电压偏高，栅充电速度降低，对器件栅电极驱动电路要求增大，掺杂浓度过低，器件阈值电压偏低，容易误开启，所以综合考虑选择掺杂浓度为1×10 17-3×10 17cm - 3。
进一步地，P型基区4上设置有P型源区5和N型源区6，P型基区4的内部设置有槽栅结构7，槽栅结构7的底部延伸至N型漂移区3的内部，槽栅结构7的顶部延伸出P型基区4的上表面，P型源区5和N型源区6上设置有源电极9，槽栅结构7上设置有栅电极10。
请结合参见图2和图5，如图所示，两个P型源区5均呈杆状，分别位于P型基区4上表面的两端，两个N型源区6均呈杆状，分别位于两个P型源区5的内侧且与对应侧的P型源区相接触。槽栅结构7包括栅介质沟槽11和位于栅介质沟槽11内部的导电材料12，栅介质沟槽11伸出P型基区4上表面的部分同时与两个N型源区6的侧面接触。进一步地，源电极9设置在P型源区5和N型源区6上，栅电极10设置在导电材料12的上表面。在本实施例中，P型源区5用于连接P型基区4和源电极9，P型源 区5的长度c为0.25-1μm，厚度d为0.25-1μm，掺杂浓度为1×10 19-1×10 20cm - 3。N型源区6用于将电流收集并传导至源电极9，其长度e为0.25-1μm，厚度f为0.25-1μm，掺杂浓度为1×10 19-1×10 20cm -3。栅介质沟槽11为二氧化硅层沟槽，用于形成凹槽型的导电沟道，其厚度g为50-60nm，所述二氧化硅层通过干氧氧化工艺与湿氧氧化工艺制备而成。导电材料12通过淀积工艺填充在栅介质沟槽11的内部，用于控制器件的开启与关断，其材料为硼离子掺杂的多晶硅材料，掺杂浓度为1×10 19-1×10 20cm -3。栅电极10为Al金属层，厚度为2-5μm。
请结合参加图2和图6，如图所示，在其他实施例中，P型源区5呈环状，且环绕P型基区4上表面的四周，N型源区6呈环状，位于P型源区5环状的内侧，且N型源区6的外侧面与P型源区5的内侧面相接触。槽栅结构7包括栅介质沟槽11和位于栅介质沟槽11内部的导电材料12，其中，栅介质沟槽11伸出P型基区4上表面的部分位于N型源区6上表面的中心，且与N型源区6的内侧面相接触。进一步地，源电极9设置在P型源区5和N型源区6上，栅电极10设置在导电材料12的上表面。在本实施例中，P型源区5用于连接P型基区4和源电极9，其长度c为0.25-1μm，厚度d为0.25-1μm，掺杂浓度为1×10 19-1×10 20cm -3。N型源区6用于将电流收集并传导至源电极9，其长度e为0.25-1μm，厚度f为0.25-1μm，掺杂浓度为1×10 19-1×10 20cm -3。栅介质沟槽11为二氧化硅层沟槽，用于形成凹槽型的导电沟道，其厚度g为50-60nm，所述二氧化硅层通过干氧氧化工艺与湿氧氧化工艺制备而成。导电材料12通过淀积工艺填充在栅介质沟槽11的内部，用于控制器件的开启与关断，其材料为硼离子掺杂的多晶硅材料，掺杂浓度为1×10 19-1×10 20cm -3。栅电极10为Al金属层，厚度为2-5μm。
更进一步地，槽栅结构7的下方设置有掩蔽层8，掩蔽层8的上表面与槽栅结构7的下表面接触，未与P型基区4的下表面接触，且掩蔽层8仅覆盖槽栅结构7的下表面的一部分。在本实施例中，掩蔽层8的长度a≥0.5μm，厚度b为0.5-1μm，掩蔽层8为P型掺杂，掺杂浓度为1×10 18-5×10 18cm -3，通过离子注入工艺形成。
在半导体器件中，若没有掩蔽层8，当器件处于正向阻断工作模式下，由于栅介质沟槽11拐角处电场聚集使得器件在小于理想击穿电压下击穿，在栅介质沟槽11的底部增加掩蔽层8，由于掩蔽层8为P型掺杂区，与N型漂移区3之间形成PN结耗尽区，器件正向阻断时漏极压降降落于所述PN结处，改变了器件的电场分布，降低了栅介质沟槽11拐角处的电场强度，提高了半导体器件的击穿电压，而且，由于掩蔽层8的存在，减小了器件的栅电极10与漏电极1的交叠面积，缓解了两电极之间的电容耦合，减小了栅漏电容，使得器件工作过程中给栅漏电容充电的电荷量减少，增大了器件的开关速度，同时也减少了器件的开关功耗。
掩蔽层8的长度最短为0.5μm是考虑到如果长度太短，掩蔽层8与N型漂移区3之间形成的PN结对没有被掩蔽层8覆盖的栅介质沟槽11拐角起不到保护作用，容易使得器件在达不到额定击穿电压之前被击穿，而且本实施例的具有掩蔽层结构的碳化硅MOSFET器件，掩蔽层8与N型漂移区3的接触面积较小，可以有效的增大器件的导通电流，这是因为PN接触面积越大，形成的耗尽区面积越大，导电路径越小，电阻越大。
在本实施例中，当所述MOSFET器件应用在高频时，可以通过内部金属连线将掩蔽层8与源电极9相连接，当所述MOSFET器件应用在常开型开关时，掩蔽层8不连接电极。
本实施例的具有掩蔽层结构的碳化硅MOSFET器件，通过在槽栅结构7的底部增加掩蔽层8，由于掩蔽层8为P型掺杂区，与N型漂移区3之间形成PN结耗尽区，器件正向阻断时漏极压降降落于所述PN结处，改变了器件的电场分布，降低了槽栅结构7拐角处的电场强度，提高了半导体器件的击穿电压，而且本实施例的掩蔽层8与N型漂移区3的接触面积较小，可以有效的增大器件的导通电流。
请参见图7a-7g，图7a-7g是本发明实施例提供的一种具有掩蔽层结构的碳化硅MOSFET器件制备方法步骤的中间体的结构示意图，本实施例的MOSFET器件的制备方法，具体包括以下步骤：
在衬底上进行外延生长，具体地，请参见图7a，选择碳化硅衬底作为N型掺杂衬底层2，在所述碳化硅衬底上表面外延生长8-10μm的氮离子掺杂的N型漂移区3，掺杂浓度为1×10 15-1×10 16cm -3。
形成P型基区，具体地，请参见图7b，在N型漂移区3的上表面外延形成P型基区4，厚度为0.5-3μm，掺杂浓度为1×10 17-3×10 17cm -3。
形成P型源区和N型源区，具体地，请参见图7c，在P型基区4的上表面通过离子注入的方式形成P型源区5和N型源区6，P型源区5的掺杂浓度为1×10 19-1×10 20cm -3，N型源区6的掺杂浓度为1×10 19-1×10 20cm -3，P型源区5和N型源区6的厚度为0.25-1μm。
形成凹槽，具体地，请参见图7d，通过刻蚀形成凹槽，所述凹槽贯穿N型源区6和P型基区4，并延伸至N型漂移区3中，所述凹槽的长度h为1-3μm，深度i为2-3μm。
形成掩蔽层，具体地，请参见图7e，先刻蚀形成凹槽，再通过离子注入工艺形成掩蔽层8，其为P型掺杂，掺杂浓度为1×10 18-5×10 18cm -3，掩蔽 层8的长度不超过所述凹槽的长度，最短为0.5μm，厚度为0.5-1μm。
形成槽栅结构，具体地，请参见图7f，通过干氧氧化工艺与湿氧氧化工艺形成二氧化硅栅介质沟槽11，栅介质沟槽11作为凹槽型的导电沟道，其厚度为50-60nm。在栅介质沟槽11的内部淀积硼离子掺杂的多晶硅，作为导电材料12，所述硼离子掺杂的多晶硅的掺杂浓度为1×10 19-1×10 20cm -3，栅介质沟槽11和导电材料12形成槽栅结构7。
形成电极金属，具体地，请参见图7g，在导电材料12的上表面淀积金属层，作为栅电极10，在P型源区5和N型源区6的上表面淀积金属层，作为源电极9，在N型掺杂衬底层2的下表面淀积金属层，作为漏电极1。源电极9和漏电极1为Ti/Ni/Al合金金属层，栅电极10为Al金属层，其厚度均为2-5μm。
实施例二
本实施例提供了另一种具有掩蔽层结构的碳化硅MOSFET器件，请参见图3，图3是本发明实施例提供的另一种具有掩蔽层结构的碳化硅MOSFET器件的结构示意图，如图所示，本实施例的具有掩蔽层结构的碳化硅MOSFET器件包括，从下至上依次设置的漏电极1、N型掺杂衬底层2、N型漂移区3和P型基区4。具体地，漏电极1为Ti/Ni/Al合金金属层，厚度为2-5μm。N型掺杂衬底层2作为重掺杂衬底用于减小器件导通电阻并传输电流，其厚度为2-5μm，掺杂浓度为5×10 18-1×10 20cm -3。N型漂移区3作为轻掺杂区用于反向截至工作下承担漏电极1的电压，防止器件被击穿，其厚度为8-10μm，掺杂浓度为1×10 15-1×10 16cm -3，因为掺杂浓度过高，器件导通电阻减小，器件击穿电压会降低。P型基区4作为轻掺杂P型源区用于将漏电极1与源电极9隔离并在栅电极10开启时形成导电沟道，厚度 为0.5-3μm，厚度过大会增加器件导电沟道的长度，使得导通电阻增大，掺杂浓度为1×10 17-3×10 17cm -3，因为掺杂浓度过高，器件的阈值电压偏高，栅充电速度降低，对器件栅电极驱动电路要求增大，掺杂浓度过低，器件阈值电压偏低，容易误开启，所以综合考虑选择掺杂浓度为1×10 17-3×10 17cm -3。
进一步地，P型基区4上设置有P型源区5和N型源区6，P型基区4的内部设置有槽栅结构7，槽栅结构7的底部延伸至N型漂移区3的内部，槽栅结构7的顶部延伸出P型基区4的上表面，P型源区5和N型源区6上设置有源电极9，槽栅结构7上设置有栅电极10。
请结合参见图4和图5，如图所示，两个P型源区5均呈杆状，分别位于P型基区4上表面的两端，两个N型源区6均呈杆状，分别位于两个P型源区5的内侧且与对应侧的P型源区相接触。槽栅结构7包括栅介质沟槽11和位于栅介质沟槽11内部的导电材料12，栅介质沟槽11伸出P型基区4上表面的部分同时与两个N型源区6的侧面接触。进一步地，源电极9设置在P型源区5和N型源区6上，栅电极10设置在导电材料12的上表面。在本实施例中，P型源区5用于连接P型基区4和源电极9，P型源区5的长度e为0.25-1μm，厚度f为0.25-1μm，掺杂浓度为1×10 19-1×10 20cm - 3。N型源区6用于将电流收集并传导至源电极9，其长度g为0.25-1μm，厚度h为0.25-1μm，掺杂浓度为1×10 19-1×10 20cm -3。栅介质沟槽11为二氧化硅层沟槽，用于形成凹槽型的导电沟道，其厚度i为50-60nm，所述二氧化硅层通过干氧氧化工艺与湿氧氧化工艺制备而成。导电材料12通过淀积工艺填充在栅介质沟槽11的内部，用于控制器件的开启与关断，其材料为硼离子掺杂的多晶硅材料，掺杂浓度为1×10 19-1×10 20cm -3。栅电极10为Al金属层，厚度为2-5μm。
请结合参见图4和图6，如图所示，P型源区5呈环状，且环绕P型基区4上表面的四周，N型源区6呈环状，位于P型源区5环状的内侧，且N型源区6的外侧面与P型源区5的内侧面相接触。槽栅结构7包括栅介质沟槽11和位于栅介质沟槽11内部的导电材料12，其中，栅介质沟槽11伸出P型基区4上表面的部分位于N型源区6上表面的中心，且与N型源区6的内侧面相接触。进一步地，源电极9设置在P型源区5和N型源区6上，栅电极10设置在导电材料12的上表面。在本实施例中，P型源区5用于连接P型基区4和源电极9，其长度e为0.25-1μm，厚度f为0.25-1μm，掺杂浓度为1×10 19-1×10 20cm -3。N型源区6用于将电流收集并传导至源电极9，其长度g为0.25-1μm，厚度h为0.25-1μm，掺杂浓度为1×10 19-1×10 20cm - 3。栅介质沟槽11为二氧化硅层沟槽，用于形成凹槽型的导电沟道，其厚度i为50-60nm，所述二氧化硅层通过干氧氧化工艺与湿氧氧化工艺制备而成。导电材料12通过淀积工艺填充在栅介质沟槽11的内部，用于控制器件的开启与关断，其材料为硼离子掺杂的多晶硅材料，掺杂浓度为1×10 19-1×10 20cm -3。栅电极10为Al金属层，厚度为2-5μm。
更进一步地，槽栅结构7的下方设置有掩蔽层8，掩蔽层8为T型结构，其上表面与槽栅结构7的下表面接触，且未与P型基区4的下表面接触。具体地，掩蔽层8包括第一掩蔽部13和第二掩蔽部14，其中，第一掩蔽部13和第二掩蔽部14均为长方形结构，且第一掩蔽部13的长度a与栅介质沟槽11的长度相同，第二掩蔽部14的长度b小于第一掩蔽部13的长度a。在本实施例中，第一掩蔽部13的厚度c为0.3-0.5μm，第二掩蔽部14的长度b为0.5-1μm，厚度d为0.3-0.5μm。第一掩蔽部13和第二掩蔽部14形成上宽下窄的T型结构。
在本实施例中，掩蔽层8为P型掺杂，掺杂浓度为1×10 18-5×10 18cm -3，掩蔽层8通过外延工艺形成。在半导体器件中，若没有掩蔽层8，当器件处于正向阻断工作模式下，由于栅介质沟槽11拐角处电场聚集使得器件在小于理想击穿电压下击穿，在栅介质沟槽11的底部增加掩蔽层8，由于掩蔽层8为P型掺杂区，与N型漂移区3之间形成PN结耗尽区，器件正向阻断时漏极压降降落于所述PN结处，改变了器件的电场分布，降低了栅介质沟槽11拐角处的电场强度，提高了半导体器件的击穿电压，而且，由于掩蔽层8的存在，减小了器件的栅电极10与漏电极1的交叠面积，缓解了两电极之间的电容耦合，减小了栅漏电容，使得器件工作过程中给栅漏电容充电的电荷量减少，增大了器件的开关速度，同时也减少了器件的开关功耗。
在本实施例中，当所述MOSFET器件应用在高频时，可以通过内部金属连线将掩蔽层8与源电极9相连接，当所述MOSFET器件应用在常开型开关时，掩蔽层8可不连接电极。
请参见图8a-8g，图8a-8g是本发明实施例提供的另一种具有掩蔽层结构的碳化硅MOSFET器件制备方法步骤的中间体的结构示意图。本实施例的MOSFET器件的制备方法，具体包括以下步骤：
在衬底上进行外延生长，具体地，请参见图8a，选择碳化硅衬底作为N型掺杂衬底层2，在所述碳化硅衬底上表面外延生长8-10μm的氮离子掺杂的N型漂移区3，掺杂浓度为1×10 15-1×10 16cm -3。
形成P型基区，具体地，请参见图8b，在N型漂移区3的上表面外延形成P型基区4，厚度为0.5-3μm，掺杂浓度为1×10 17-3×10 17cm -3。
形成P型源区和N型源区，具体地，请参见图8c，在P型基区4的上表面通过离子注入的方式形成P型源区5和N型源区6，P型源区5的掺 杂浓度为1×10 19-1×10 20cm -3，N型源区6的掺杂浓度为1×10 19-1×10 20cm -3，P型源区5和N型源区6的厚度为0.25-1μm。
形成凹槽，具体地，请参见图8d，通过刻蚀形成凹槽，所述凹槽贯穿N型源区6和P型基区4，并延伸至N型漂移区3中，所述凹槽的长度l为1-3μm，深度m为2-4μm，所述凹槽的底部设置有凸台结构，所述凸台结构的长度j为0.5-1μm，深度k为0.3-0.5μm，所述凸台结构用于外延形成第二掩蔽部14。
形成掩蔽层结构，具体地，请参见图8e，通过外延填满所述凸台结构，形成第二掩蔽部14，并在第二掩蔽部14的上方继续外延形成第一掩蔽部13，第一掩蔽部13的厚度为0.3-0.5μm，第一掩蔽部13和第二掩蔽部14形成上宽下窄的T型结构的掩蔽层8，掩蔽层8为P型掺杂，掺杂浓度为1×10 18-5×10 18cm -3。
形成槽栅结构，具体地，请参见图8f，通过干氧氧化工艺与湿氧氧化工艺形成二氧化硅栅介质沟槽11，栅介质沟槽11作为凹槽型的导电沟道，其厚度为50-60nm。在栅介质沟槽11的内部淀积硼离子掺杂的多晶硅，作为导电材料12，所述硼离子掺杂的多晶硅的掺杂浓度为1×10 19-1×10 20cm -3，栅介质沟槽11和导电材料12形成槽栅结构7。
形成电极金属，具体地，请参见图8g，在导电材料12的上表面淀积金属层，作为栅电极10，在P型源区5和N型源区6的上表面淀积金属层，作为源电极9，在N型掺杂衬底层2的下表面淀积金属层，作为漏电极1。源电极9和漏电极1为Ti/Ni/Al合金金属层，栅电极10为Al金属层，其厚度均为2-5μm。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明， 不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种具有掩蔽层结构的碳化硅MOSFET器件，其特征在于，包括从下至上依次设置的漏电极(1)、N型掺杂衬底层(2)、N型漂移区(3)和P型基区(4)；
    所述P型基区(4)上设置有P型源区(5)和N型源区(6)；
    所述P型基区(4)的内部设置有槽栅结构(7)，所述槽栅结构(7)的底部延伸至所述N型漂移区(3)的内部，所述槽栅结构(7)的顶部延伸出所述P型基区(4)的上表面；
    所述槽栅结构(7)的下方设置有掩蔽层(8)，且所述掩蔽层(8)的上表面与所述槽栅结构(7)的下表面接触；
    所述P型源区(5)和所述N型源区(6)上设置有源电极(9)；
    所述槽栅结构(7)上设置有栅电极(10)。
  2. 根据权利要求1所述的具有掩蔽层结构的碳化硅MOSFET器件，其特征在于，所述掩蔽层(8)仅覆盖所述槽栅结构(7)的下表面的一部分，所述掩蔽层(8)的长度大于等于0.5μm，厚度为0.5-1μm。
  3. 根据权利要求1所述的具有掩蔽层结构的碳化硅MOSFET器件，其特征在于，所述掩蔽层(8)为T型结构，包括上下连接的第一掩蔽部(13)和第二掩蔽部(14)，其中，所述第一掩蔽部(13)和所述第二掩蔽部(14)均为长方形结构，所述第一掩蔽部(13)的长度与所述槽栅结构(7)的长度相同，所述第二掩蔽部(14)的长度小于所述第一掩蔽部(13)的长度。
  4. 根据权利要求3所述的具有掩蔽层结构的碳化硅MOSFET器件，其特征在于，所述第一掩蔽部(13)的厚度为0.3-0.5μm，所述第二掩蔽部(14)的长度为0.5-1μm，厚度为0.3-0.5μm。
  5. 根据权利要求1所述的具有掩蔽层结构的碳化硅MOSFET器件， 其特征在于，两个所述P型源区(5)均呈杆状，分别位于所述P型基区(4)上表面的两端；
    两个所述N型源区(6)均呈杆状，分别位于两个所述P型源区(5)的内侧且与对应侧的所述P型源区(5)相接触；
    所述槽栅结构(7)包括栅介质沟槽(11)和位于所述栅介质沟槽(11)内部的导电材料(12)，其中，所述栅介质沟槽(11)伸出所述P型基区(4)上表面的部分同时与两个所述N型源区(6)的侧面接触。
  6. 根据权利要求1所述的具有掩蔽层结构的碳化硅MOSFET器件，其特征在于，所述P型源区(5)呈环状，且环绕所述P型基区(4)上表面的四周；
    所述N型源区(6)呈环状，位于所述P型源区(5)环状的内侧；
    且所述N型源区(6)的外侧面与所述P型源区(5)的内侧面相接触；
    所述槽栅结构(7)包括栅介质沟槽(11)和位于所述栅介质沟槽(11)内部的导电材料(12)，其中，所述栅介质沟槽(11)伸出所述P型基区(4)上表面的部分位于所述N型源区(6)上表面的中心，且与所述N型源区(6)的内侧面相接触。
  7. 根据权利要求5或6所述的具有掩蔽层结构的碳化硅MOSFET器件，其特征在于，所述栅电极(10)设置在所述导电材料(12)的上表面。
  8. 根据权利要求1所述的具有掩蔽层结构的碳化硅MOSFET器件，其特征在于，所述掩蔽层(8)通过金属线连接所述源电极(9)。
  9. 根据权利要求1所述的具有掩蔽层结构的碳化硅MOSFET器件，其特征在于，所述掩蔽层(8)为P型掺杂，掺杂浓度为1×10 18-5×10 18cm -3。
  10. 根据权利要求1所述的具有掩蔽层结构的碳化硅MOSFET器件， 其特征在于，所述掩蔽层(8)通过外延工艺形成。
PCT/CN2020/089348 2019-05-29 2020-05-09 一种具有掩蔽层结构的碳化硅mosfet器件 WO2020238588A1 (zh)

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