WO2014097645A1 - 電子部品パッケージおよびその製造方法 - Google Patents
電子部品パッケージおよびその製造方法 Download PDFInfo
- Publication number
- WO2014097645A1 WO2014097645A1 PCT/JP2013/007505 JP2013007505W WO2014097645A1 WO 2014097645 A1 WO2014097645 A1 WO 2014097645A1 JP 2013007505 W JP2013007505 W JP 2013007505W WO 2014097645 A1 WO2014097645 A1 WO 2014097645A1
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- Prior art keywords
- electronic component
- metal
- plating layer
- layer
- metal plating
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 61
- 229910052751 metal Inorganic materials 0.000 claims abstract description 472
- 239000002184 metal Substances 0.000 claims abstract description 472
- 238000007747 plating Methods 0.000 claims abstract description 318
- 239000011888 foil Substances 0.000 claims abstract description 163
- 229920005989 resin Polymers 0.000 claims abstract description 80
- 239000011347 resin Substances 0.000 claims abstract description 80
- 238000007789 sealing Methods 0.000 claims abstract description 65
- 239000002243 precursor Substances 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 422
- 238000000034 method Methods 0.000 claims description 87
- 239000000853 adhesive Substances 0.000 claims description 57
- 230000001070 adhesive effect Effects 0.000 claims description 57
- 239000012790 adhesive layer Substances 0.000 claims description 36
- 125000006850 spacer group Chemical group 0.000 claims description 35
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 230000000149 penetrating effect Effects 0.000 claims description 16
- 239000007769 metal material Substances 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 14
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 11
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 17
- 230000017525 heat dissipation Effects 0.000 description 12
- 239000010936 titanium Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 239000010409 thin film Substances 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- 206010040844 Skin exfoliation Diseases 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 239000011651 chromium Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 230000035515 penetration Effects 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 238000004080 punching Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229920002050 silicone resin Polymers 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 229920000178 Acrylic resin Polymers 0.000 description 4
- 239000004925 Acrylic resin Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229920002799 BoPET Polymers 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000007606 doctor blade method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910052580 B4C Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910007637 SnAg Inorganic materials 0.000 description 1
- 229910007116 SnPb Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052586 apatite Inorganic materials 0.000 description 1
- INAHAJYZKVIDIZ-UHFFFAOYSA-N boron carbide Chemical compound B12B3B4C32B41 INAHAJYZKVIDIZ-UHFFFAOYSA-N 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000002845 discoloration Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- VSIIXMUUUJUKCM-UHFFFAOYSA-D pentacalcium;fluoride;triphosphate Chemical compound [F-].[Ca+2].[Ca+2].[Ca+2].[Ca+2].[Ca+2].[O-]P([O-])([O-])=O.[O-]P([O-])([O-])=O.[O-]P([O-])([O-])=O VSIIXMUUUJUKCM-UHFFFAOYSA-D 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000016 photochemical curing Methods 0.000 description 1
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 229920003050 poly-cycloolefin Polymers 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
- H01L2224/03462—Electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/0382—Applying permanent coating, e.g. in-situ coating
- H01L2224/03825—Plating, e.g. electroplating, electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2746—Plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
- H01L2224/2746—Plating
- H01L2224/27462—Electroplating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
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- H—ELECTRICITY
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- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
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- H—ELECTRICITY
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- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements
Definitions
- the present invention relates to an electronic component package and a manufacturing method thereof. More particularly, the present invention relates to a package product including an electronic component and a manufacturing method thereof.
- a mounting technology for electronic components such as ICs and inductors
- a mounting technology using a circuit board or a lead frame there is a mounting technology using a circuit board or a lead frame. That is, there are “packages using a circuit board”, “packages using a lead frame”, and the like as general electronic component package forms.
- a package using a circuit board has a form in which electronic components are mounted on a circuit board.
- types of such packages there are generally “wire bonding type (W / B type)” and “flip chip type (F / C type)”.
- the “lead frame type” has a form including a lead frame composed of leads, die pads, and the like.
- Various electronic components are bonded by soldering or the like in both lead frame type packages and packages using circuit boards.
- the conventional technology has a problem that heat dissipation characteristics and connection reliability in high-density mounting are not sufficient.
- the present invention has been made in view of such points, and an object of the present invention is to provide an electronic component package that realizes improvement in heat radiation characteristics and connection reliability in high-density mounting, and a method for manufacturing the same.
- a method of manufacturing an electronic component package includes: (I) forming a package precursor in which the electronic component is embedded in the sealing resin layer such that the electrode of the electronic component is exposed from the surface of the sealing resin layer; (Ii) forming a first metal plating layer so as to be joined to the exposed surface of the electrode of the electronic component; (Iii) including a step of opposingly arranging the metal foil in a state of being separated from the first metal plating layer, and (iv) a step of forming the second metal plating layer, In step (iv), the second metal plating layer is formed so as to fill the gap between the first metal plating layer and the metal foil, whereby the metal foil, the first metal plating layer, and the second metal plating are formed. It is characterized by integrating the layers.
- An electronic component package is Sealing resin layer, Electronic components embedded in the sealing resin layer, Having a metal wiring layer bonded to the electrode of the electronic component, The metal wiring layer is directly bonded to the first metal plating layer directly bonded to the electrode of the electronic component, the second metal plating layer directly bonded to the first metal plating layer, and the second metal plating layer. Consists of metal foil joined to The second metal plating layer is positioned at least between the first metal plating layer and the metal foil.
- the electronic component package of the present invention by directly forming a metal plating layer on the electronic component, it is possible to improve heat dissipation characteristics and connection reliability in high-density mounting.
- FIG. 1 is a process sectional view schematically showing a method for manufacturing an electronic component package according to the present invention.
- FIG. 2 is a process cross-sectional view schematically showing the method for manufacturing an electronic component package of the present invention.
- FIG. 3 is a cross-sectional view schematically showing an embodiment using spacer means.
- FIG. 4 is a process cross-sectional view schematically showing the method for manufacturing an electronic component package (first embodiment) of the present invention.
- FIG. 5 is a plan view of a metal foil schematically showing the aspect of the penetrating portion.
- FIG. 6 is a process cross-sectional view schematically showing an aspect of the plating growth height caused by the difference in the opening size of the through portion.
- FIG. 1 is a process sectional view schematically showing a method for manufacturing an electronic component package according to the present invention.
- FIG. 2 is a process cross-sectional view schematically showing the method for manufacturing an electronic component package of the present invention.
- FIG. 3 is a cross-sectional view
- FIG. 7 is a process sectional view schematically showing the method for manufacturing an electronic component package (second embodiment) of the present invention.
- FIG. 8 is a process cross-sectional view schematically showing the electronic component package manufacturing method (second embodiment) of the present invention.
- FIG. 9 is a cross-sectional view (third embodiment) schematically showing an embodiment using an adhesive layer.
- FIG. 10 is a process cross-sectional view schematically showing the electronic component package manufacturing method (fourth embodiment) of the present invention.
- FIG. 11 is a cross-sectional view schematically showing the configuration of the electronic component package of the present invention.
- FIG. 12 is a cross-sectional view schematically showing the configuration of the electronic component package of the present invention (package including spacer means).
- FIG. 13 is a cross-sectional view schematically showing the configuration of the electronic component package of the present invention (package of another embodiment different from FIGS. 11 and 12).
- FIG. 14 is a cross-sectional view schematically showing a configuration of an electronic component package according to the present invention (package of another embodiment different from FIGS. 11 to 13).
- FIG. 15 is a cross-sectional view schematically showing the configuration of the electronic component package (light emitting device package) of the present invention.
- FIG. 16 is a cross-sectional view schematically showing a configuration aspect of a conventional electronic component package.
- a package using a circuit board can realize high-density mounting, but has a problem in terms of heat dissipation because it uses a circuit board. Also, the substrate cost itself cannot be ignored, and the cost is not always satisfactory. Furthermore, the cost for wire bonding and flip chip mounting is not negligible in the first place, and further cost reduction is desired (for example, an expensive mounter is required for flip chip mounting).
- Lead frame type (see FIG. 16B) is not suitable for high-density mounting because the lead frame is difficult to finely process. Furthermore, since both types are soldered, there is a concern about a so-called “solder flash” problem when the whole is sealed with a resin, and it is not necessarily satisfactory in terms of connection reliability. In other words, during heating in module mounting soldering, the solder material used for joining the components in the package may be re-melted, and may leak into a minute gap (flash) or cause a short circuit. .
- the present invention has been made in view of such circumstances.
- the main object of the present invention is to realize favorable heat dissipation characteristics and improved connection reliability in high-density mounting.
- a method for manufacturing an electronic component package comprising: (I) forming a package precursor in which the electronic component is embedded in the sealing resin layer such that the electrode of the electronic component is exposed from the surface of the sealing resin layer; (Ii) forming a first metal plating layer so as to be joined to the exposed surface of the electrode of the electronic component; (Iii) including a step of opposingly arranging the metal foil in a state of being separated from the first metal plating layer, and (iv) a step of forming the second metal plating layer, In step (iv), the second metal plating layer is formed so as to fill the gap between the first metal plating layer and the metal foil, whereby the metal foil, the first metal plating layer, and the second metal plating are formed.
- a method for manufacturing an electronic component package characterized in that the layers are integrated.
- One of the features of the method for manufacturing an electronic component package according to one aspect of the present invention is that a second metal plating layer is formed so that a gap between the first metal plating layer and the metal foil is filled. To form an integrated member of the metal foil, the first metal plating layer, and the second metal plating layer.
- an electronic component package obtained by the above manufacturing method is also provided.
- Such an electronic component package is Sealing resin layer, Electronic components embedded in the sealing resin layer, Having a metal wiring layer bonded to the electrode of the electronic component, The metal wiring layer is directly bonded to the first metal plating layer directly bonded to the electrode of the electronic component, the second metal plating layer directly bonded to the first metal plating layer, and the second metal plating layer. Consists of metal foil joined to The second metal plating layer is positioned at least between the first metal plating layer and the metal foil.
- the metal wiring layer is “a first metal plating layer directly bonded to an electrode of an electronic component” or “a first metal plating layer directly. It is composed of three metal layers and “second metal plating layer bonded” and “metal foil directly bonded to the second metal plating layer”, and between the first metal plating layer and the metal foil. That is, the second metal plating layer is positioned at least.
- the metal wiring layer in one embodiment of the present invention includes a metal foil, the metal wiring layer can be easily provided thicker and can have particularly high heat dissipation characteristics. That is, the first metal plating layer, the second metal plating layer, and the metal foil constituting the metal wiring layer can be formed from a material such as copper having high thermal conductivity, and provided as a “thick metal wiring layer”. Since it can, heat can be efficiently released to the outside through it.
- packaging is achieved without performing “soldering”, that is, a package that does not use “solder material” is realized. Therefore, the disadvantage of “solder flash” is avoided, and “connection reliability” can be improved in that respect.
- the package according to one embodiment of the present invention has a “substrate-less structure”. Because it is “substrate-less”, no substrate is used, which contributes to low-cost manufacturing. Further, since packaging can be performed by a simple process compared to wire bonding and flip chip mounting, the cost can be reduced in this respect. Furthermore, by using the “thick metal foil”, it is possible to form the “thick metal wiring layer” in a short time, and in that respect, the cost can be reduced.
- FIGS. 2A to 2C schematically show processes related to the manufacturing method according to one embodiment of the present invention.
- a package precursor forming step is performed.
- the formation of the package precursor includes a step of placing the electronic component on the adhesive carrier so as to be attached to the adhesive carrier, a step of forming a sealing resin layer on the adhesive carrier so as to cover the electronic component, and
- the method includes a step of peeling the adhesive carrier from the sealing resin layer to expose the electrode of the electronic component from the surface of the sealing resin layer.
- At least one electronic component 30 is arranged on the adhesive carrier 20. That is, the electronic component 30 is mounted on the adhesive carrier 20.
- the arrangement of the electronic component 30 is preferably performed so that the electrode portion 35 is in contact with the adhesive carrier 20. Thereby, the electrode 35 of the electronic component 30 can be suitably exposed in the subsequent peeling operation.
- the electronic component 30 may be any type as long as it is a circuit component / circuit element used in the electronics mounting field. Although it is only an illustration to the last, as a kind of such electronic parts, IC (for example, control IC), an inductor, a semiconductor element (for example, MOS (metal oxide semiconductor)), a capacitor, a power element, a light emitting element (for example, LED), A chip resistor, a chip capacitor, a chip varistor, a chip thermistor, other chip-shaped multilayer filters, connection terminals and the like can be mentioned.
- IC for example, control IC
- MOS metal oxide semiconductor
- the adhesive carrier 20 may be a carrier sheet composed of a substrate and an adhesive layer, for example. That is, as shown in FIG. 1A, a carrier sheet having a two-layer structure in which an adhesive layer 26 is provided on a support base 24 may be used. In terms of performing a suitable mold release process at a later time, it is preferable that the support base material 24 has flexibility.
- the support substrate 24 may be any sheet-like member as long as it does not interfere with processes such as “placement of electronic components” and “formation of a sealing resin layer” performed later.
- the material of the support base 24 may be resin, metal, and / or ceramic.
- the resin of the support base 24 include polyester resins such as polyethylene terephthalate and polyethylene naphthalate, acrylic resins such as polymethyl methacrylate, polycycloolefin resins, and polycarbonates.
- the metal of the support base 24 include iron, copper, aluminum, or an alloy thereof (for example, a stainless material such as SUS may be used).
- the ceramic of the support base 24 examples include apatite, alumina, silica, silicon carbide, silicon nitride, and boron carbide. Since the thickness of the supporting substrate itself is “sheet-like”, it is preferably 0.1 mm to 2.0 mm, more preferably 0.2 mm to 1.0 mm (for example, about 1.0 mm).
- the adhesive layer 26 is not particularly limited as long as it has adhesiveness to electronic components.
- the adhesive layer itself comprises at least one adhesive material selected from the group consisting of acrylic resin adhesives, urethane resin adhesives, silicone resin adhesives, and epoxy resin adhesives. It may be.
- the thickness of the adhesive layer 26 is preferably 2 ⁇ m to 50 ⁇ m, more preferably 5 ⁇ m to 20 ⁇ m (for example, 10 ⁇ m).
- a sealing resin layer 40 is formed on the adhesive carrier 20 so as to cover the electronic component 30, and the electronic component A sealing body is obtained.
- the sealing resin layer 40 can be provided by applying a resin raw material to the adhesive surface of the adhesive carrier 20 by a spin coat method, a doctor blade method, or the like, and then subjecting it to heat treatment or light irradiation (that is, the applied resin).
- the sealing resin layer 40 can be provided by thermally curing or photocuring the raw material).
- the sealing resin layer 40 may be provided by bonding a resin film or the like to the adhesive surface of the adhesive carrier 20 by another method.
- the sealing resin layer 40 can be provided by filling a mold with an uncured powdery or liquid sealing resin and heat curing.
- the material of the sealing resin layer 40 may be any kind of material as long as it provides insulation, and may be, for example, an epoxy resin or a silicone resin.
- the thickness of the sealing resin layer 40 is preferably about 0.5 mm to 5.0 mm, more preferably about 1.2 mm to 1.8 mm.
- the adhesive carrier 20 is peeled from the electronic component sealing body as shown in FIG.
- the electrode 35 of the electronic component 30 is exposed from the surface of the sealing resin layer 40, and the package precursor 100 'is obtained.
- step (ii) is performed. That is, as shown in FIG. 1E, the first metal plating layer 50 ′ is formed so as to be joined to the exposed surface of the electrode of the electronic component.
- a dry plating method is performed on the main surface of the sealing resin layer from which the electrode surface is exposed, and a “dry plating layer bonded to the electrode exposed surface of the electronic component” is formed as the first metal plating layer 50 ′. .
- the dry plating method includes a vacuum plating method (PVD method) and a chemical vapor deposition method (CVD method), and the vacuum plating method (PVD method) further includes sputtering, vacuum deposition, ion plating, and the like.
- PVD method vacuum plating method
- CVD method chemical vapor deposition method
- sputtering may be performed as a dry plating method, thereby forming the first metal plating layer 50 ′ bonded to the electrode exposed surface of the electronic component.
- the first metal plating layer 50 ′ is made of, for example, at least one metal material selected from the group consisting of Ti (titanium), Cr (chromium), Ni (nickel), Cu (copper), and Al (aluminum). It is preferable to include.
- the thickness of the first metal plating layer 50 ′ formed by the dry plating method is relatively thin, for example, preferably 50 nm to 50 ⁇ m, more preferably 100 nm to 5 ⁇ m (for example, about 150 nm). ).
- 1st metal plating layer 50 may be formed not only as a single layer but as a several layer.
- a Ti thin film layer and a Cu thin film layer may be formed by sputtering (more specifically, the Cu thin film layer may be formed after the Ti thin film layer is formed).
- step (iii) is performed.
- the metal foil 55 is disposed to face the first metal plating layer 50 ′ in a state of being separated.
- spacer means 60 as shown in FIG. 3 (a) may be used.
- the metal foil 55 can be spaced apart from the first metal plating layer 50 ′. .
- the spacer means 60 may be a separate member from the first metal plating layer 50 ′ and the metal foil 55 as shown in FIG. 3 (a), or alternatively, the spacer means 60 shown in FIGS. 3 (b) and 3 (c). ), The first metal plating layer 50 ′ or the metal foil 55 may be integrated. In the spacer means 60 which is a separate member from the first metal plating layer 50 ′ and the metal foil 55, the spacer means 60 is arranged on the first metal plating layer 50 ′ prior to the opposing arrangement of the metal foil 55. It is preferable.
- the spacer means 60 in a region that does not overlap with the electrode of the electronic component (for example, the peripheral region of the package precursor 100 ′).
- the spacer means 60 as a separate member may be made of any material as long as it is used for the separation of the metal foil 55 (separation of the first metal plating layer) (for example, the metal member 55 is made of a metal material). Or may be made of a resin material), and may have any size.
- the spacer means 60 integrated with the first metal plating layer 50 ′ or the metal foil 55 uses the first metal plating layer 50 and the metal foil 55 as shown in FIGS. 3 (b) and 3 (c).
- the first metal plating layer 50 ′ having at least one local protrusion 60 ′” or “metal foil 55 having at least one local protrusion 60 ′” may be used.
- Such a protrusion 60 ′ can be formed by, for example, patterning, conductive paste printing, or punching.
- the shape of the protrusion 60 ' is not particularly limited, and may be any of a cylinder, a cone, a polygon, a pyramid, and the like.
- the width dimension (for example, the maximum diameter dimension) of the protrusion 60 ′ is preferably 50 ⁇ m to 1 mm, and the height dimension of the protrusion 60 ′ is preferably 100 ⁇ m or less.
- the plurality of protrusions 60 ′ are preferably provided with a certain distance, and may have an interval of 0.5 mm to 10 mm, for example.
- the thickness of the metal foil 55 arranged oppositely is preferably 9 ⁇ m to 2000 ⁇ m, more preferably 18 ⁇ m to 1000 ⁇ m, still more preferably 200 ⁇ m to 500 ⁇ m (for example, 300 ⁇ m).
- the metal foil 55 preferably includes at least one metal material selected from the group consisting of Cu (copper), Ni (nickel), and Al (aluminum).
- a copper foil may be used as the metal foil 55).
- step (iv) is performed. That is, as shown in FIG. 1G, the second metal plating layer 50 ′′ is formed. As shown in the figure, the second metal plating layer 50 ′′ is formed so that the gap sandwiched between the first metal plating layer 50 ′ and the metal foil 55 is filled, whereby the metal foil 55 and the first metal are formed.
- the plating layer 50 ′ and the second metal plating layer 50 ′′ are integrated with each other.
- a wet plating method is performed, thereby forming a “wet plating layer that fills the gap between the first metal plating layer 50 ′ and the metal foil 55” as the second metal plating layer 50 ′′.
- an electroplating method for example, electrolytic plating
- a chemical plating method for example, a hot dipping method, or the like may be performed.
- One of the characteristics of the manufacturing method of the present invention is that it has a process characteristic such as “a metal layer is directly formed on an electrode exposed surface of an electronic component”. Specifically, after the dry plating method is performed in the step (ii) to form the first metal plating layer 50 ′ bonded to the electrode exposed surface of the electronic component, the wet plating method is performed in the step (iv). A second metal plating layer 50 ′′ is formed to be joined to the first metal plating layer 50 ′. In particular, the second metal plating layer 50 ′′ can be provided thick. In such a process, it can be said that because the dry plating method is performed, a thick plating layer can be formed with good adhesion by the subsequent wet plating method.
- the second metal plating layer 50 ′′ of the wet plating layer is formed so as to fill the gap between the first metal plating layer 50 ′ and the metal foil 55, whereby the metal foil 55
- the first metal plating layer 50 ′ and the second metal plating layer 50 ′′ are integrated. Therefore, it can be understood that the wet plating layer of the second metal plating layer 50 ′′ is formed in order to join the metal foil 55 and the first metal plating layer 50 ′.
- the metal foil 55 is used in the present invention, not only the thickness can be increased, but also the second metal plating layer 50 '' itself used for the bonding can be formed thick as a wet plating layer.
- the integrated metal member 50 "of the first metal plating layer 50 'and the second metal plating layer 50" can be thickened.
- the second metal plating layer 50 ′′ in the step (iv) is preferably formed by plating growth from the surfaces of both the first metal plating layer 50 ′ and the metal foil 55. That is, the second metal plating layer 50 ′′ is formed in the gap between the first metal plating layer 50 ′ and the metal foil 55 so as to grow from the surface of the first metal plating layer 50 ′, and It is preferable to form the second metal plating layer 50 ′′ so as to grow even from the surface of the metal foil 55 (see FIG. 8). As a result, the formation time of the second metal plating layer 50 ′′ provided relatively thick can be effectively reduced.
- the “integrated metal member 50 of the metal foil 55, the first metal plating layer 50 ′ and the second metal plating layer 50 ′′” obtained in the step (iv) is preferably subjected to a patterning process.
- a patterning process it is preferable to form the metal wiring layer 70 (wiring circuit) by patterning the integrated metal member 50.
- desired wiring formation for example, formation of a desired wiring pattern including an extraction electrode
- the patterning process itself is not particularly limited as long as it is a process used in the electronics packaging field.
- a desired patterning process may be performed by using photolithography that performs resist formation, exposure, development, etching, and the like.
- the metal wiring layer may include a metal wiring layer that is not in contact with the electrode of the electronic component in addition to the metal wiring layer bonded to the electrode of the electronic component. This is because heat can be directly radiated from other than the sealing resin surface and the electrode exposed surface of the electronic component.
- the patterning process itself can be performed collectively on the integrated metal member 50, it may be performed on individual components in advance. Specifically, patterning may be performed on the metal foil 55 in advance, for example, prior to joining with the metal plating layer. Similarly, a patterning process may be performed on the first metal plating layer 50 ′ in advance, for example, prior to the opposing arrangement of the metal foil. Such a pre-patterning process itself is not particularly limited as long as it is a process used in the electronics packaging field. For example, the patterning process is performed by using photolithography for resist formation, exposure, development, etching, and the like. You can do it. The metal foil 55 can be patterned by mechanical processing such as punching (punching).
- the solder resist layer 90 is formed on the surface of the sealing resin layer (the surface exposed by peeling of the adhesive carrier) so as to partially cover the metal wiring layer 70. It is preferable.
- the formation of the resist layer 90 may be the same as the solder resist formation generally used in the electronics mounting field.
- an electronic component package 100 as shown in FIG. 2C can be finally obtained. It can.
- the manufacturing method of the present invention can be realized in various specific embodiments. This will be described below.
- a metal foil provided with at least one penetrating portion 55a may be used as the metal foil 55 used in the step (iii) (see FIG. 4A).
- the plating solution spreads more easily to the gap between the first metal plating layer 50 ′ and the metal foil 55 through the through portion 55 a of the metal foil 55, and the second metal plating layer 50 ′′ It can be formed more efficiently. That is, the metal foil 55 has a through-hole 55a through which the plating solution for forming the second metal plating layer effectively penetrates into the “gap portion between the first metal plating layer 50 ′ and the metal foil 55”. May have.
- the plating solution passes through the through portion 55a and penetrates between the first metal plating layer 50 ′ and the metal foil 55, thereby the first metal plating layer 50 ′ and the metal foil.
- a second metal plating layer 50 ′′ is formed in the gap with the substrate 55 (FIG. 4B).
- the second metal plating layer 50 ′′ is formed so as to fill the through portion 55a. Therefore, the metal foil 55 and the first metal plating layer 50 ′ are formed. And the second metal plating layer 50 '' can be suitably integrated.
- the second metal is filled so that not only the “gap portion between the first metal plating layer 50 ′ and the metal foil 55” but also the through portion 55 a of the metal foil 55 is filled.
- the plating layer 50 ′′ is formed (Note that if the electrolytic plating method with a high plating speed is used for forming the second metal plating layer 50 ′′, the filling of the through portion 55a becomes more efficient).
- the second metal plating layer 50 ′′ is formed by plating growth from the inner wall surface of the penetrating portion (see FIG. 8). That is, in a preferred embodiment, not only the surfaces of both the first metal plating layer 50 ′ and the metal foil 55 but also the inner wall surface of the through-hole 55a are plated, thereby forming the second metal plating layer 50 ′′. Form. Thereby, it is possible to further effectively reduce the formation time of the second metal plating layer 50 ′′ provided relatively thick.
- the penetrating portion 55a may have a shape that facilitates filling by plating.
- the penetrating portion 55 a may have a rectangular opening shape on the main surface of the metal foil 45.
- Such a through portion 55a itself can be formed by mechanical processing such as punching (punching).
- the opening shape (rectangular opening shape) of the penetrating portion 55a preferably has a short dimension of about 0.1 mm to 3 mm and a long dimension of about 0.3 to 20 mm (FIG. 5). (See (a)).
- the total area of the opening shape of the penetration part 55a is 10% or less with respect to the area of the main surface of metal foil.
- a mesh structure or the like may be used as a form of the penetration part 55a.
- the plating growth height of the metal plating layer can be changed by changing the opening size of the penetrating portion 55a of the metal foil 55 as shown in FIG. That is, due to the difference in opening size, the growth level of the second metal plating layer 50 ′′ inside the through portion 55a can be changed (in particular, the inside of the through portion 55a can be entirely changed into the second metal plating layer 50 ′. Applies if not filled with '). As shown in the drawing, the level of the second metal plating layer 50 ′′ in the inside of the through portion 55a having a smaller opening size can be relatively increased.
- the height level of the second metal plating layer 50 ′′ in the “narrow through-hole 55a” is the same as that of the second metal plating layer 50 ′′ in the “wide through-hole 55a”. Can be higher than the height level.
- a “metal foil including a plurality of protrusions 60 ′ and a plurality of through portions 55 a” is used as the metal layer 55.
- the “plurality of protrusions 60 ′” function as spacer means, and the “plurality of through portions 55 a” function as plating solution penetration means into the gaps.
- the metal foil 55 when arranging the metal foil, the metal foil 55 is provided such that the protrusion 60 ′ of the metal foil is interposed between the first metal plating layer 50 ′ and the metal foil 55, thereby The metal foil 55 can be suitably disposed opposite to the metal plating layer 50 ′.
- the height of the protrusion 60 ' is changed, the separation distance of the metal foil 55 with respect to the first metal plating layer 50' can be changed.
- the second metal plating layer 50 '' since the plating solution can pass through the through portion 55a, it penetrates between the first metal plating layer 50 'and the metal foil 55, thereby The second metal plating layer 50 ′′ is preferably formed in “the gap between the first metal plating layer 50 ′ and the metal foil 55”. Finally, the second metal plating layer 50 '' is formed so as to fill the through portion 55a.
- step (iv) not only the surfaces of both the first metal plating layer and the metal foil but also the inner wall surface of the penetrating portion is plated and grown.
- the second metal plating layer 50 ′′ is preferably formed.
- an adhesive layer may be used when the metal foils are opposed to each other.
- an adhesive layer 80 may be provided at the tip of a protrusion 60 ′ (for example, a metal foil protrusion) serving as a spacer means.
- the adhesive layer 80 By forming the adhesive layer 80 on the protrusion 60 ′, the first metal plating layer 50 ′ and the metal foil 55 are connected to each other in the step (iii). That is, the first metal plating layer 50 ′ and the metal foil 55 can be fixed to each other. This is because the bonding strength between the metal foil 55 and the first metal plating layer 50 ′ is increased by using the adhesive layer 80. As a result, the metal foil 55, the first metal plating layer 50 ′ and the second metal plating are increased. This means that the integration with the layer 50 ′′ can be made stronger.
- the method for forming the adhesive layer 80 is merely an example, but the first metal plating layer and / or metal foil on which the protrusion 60 ′ is formed is gently applied to the adhesive applied thinly on the flat substrate. Just hold it down. Thereby, an adhesive layer can be formed only at the tip of the protrusion 60 '.
- the adhesive layer may be a thermoplastic or thermosetting material.
- the material of the insulating adhesive layer is selected from the group consisting of an acrylic resin adhesive, a urethane resin adhesive, a silicone resin adhesive, and an epoxy resin adhesive. Those comprising at least one adhesive material are preferred.
- the adhesive layer may be made of at least one material selected from the group consisting of SnPb, SnAg, SnAgCu, SnAu, SnBi, and the like.
- a light emitting element package product can be suitably manufactured. it can.
- the phosphor layer and the transparent resin layer are formed as the sealing resin layer.
- the phosphor layer 44 is formed around the light emitting element, and then the transparent resin layer 46 is formed so as to cover the light emitting element and the phosphor layer.
- a desired light emitting device package can be finally obtained (see, for example, FIGS. 10A to 10I).
- the formation of the phosphor layer and the formation of the transparent resin layer itself may be the same as a method generally used in conventional LED package manufacturing.
- An electronic component package according to one embodiment of the present invention is a package obtained by the above manufacturing method.
- FIG. 11 schematically shows a configuration of an electronic component package according to one embodiment of the present invention.
- the electronic component package 100 includes a sealing resin layer 40, an electronic component 30, and a metal wiring layer 70.
- the electronic component 30 is embedded in the sealing resin layer 40.
- the electronic component 30 is embedded in the sealing resin layer 40 so as to be flush with the sealing resin layer 40. That is, “the surface of the electronic component” and “the surface of the sealing resin layer” are substantially on the same plane. More specifically, it is preferable that the electrode portion 35 of the electronic component 30 is flush with the sealing resin layer 40 (that is, the surface of the electrode of the electronic component and the surface of the sealing resin layer are substantially equal). Preferably on the same plane).
- the type of the electronic component 30 embedded in the sealing resin layer 40 is not limited to one, and a plurality of types of electronic components 30 may be included in the sealing resin layer 40.
- Examples of such electronic components include an IC (for example, a control IC), an inductor, a semiconductor element (for example, a MOS (metal oxide semiconductor)), a capacitor, a power element, a light emitting element (for example, an LED) chip resistor, a chip capacitor, Examples include chip varistors, chip thermistors, other chip-shaped multilayer filters, and connection terminals.
- the electrode part 35 of the electronic component is exposed on the surface of the sealing resin layer 40, and the metal wiring layer 70 is provided so as to be joined to the exposed electrode part 35. .
- the sealing resin layer 40 in which the electronic component 30 is embedded includes, for example, an epoxy resin or a silicone resin.
- the thickness of the sealing resin layer 40 is preferably 0.5 mm to 5.0 mm, more preferably 1.2 mm to 1.8 mm.
- the metal wiring layer 70 provided in the package of the present invention includes a first metal plating layer 50 ′, a second metal plating layer 50 ′′, and a metal foil 55.
- the metal wiring layer 70 is “the first metal plating layer 50 ′ directly bonded to the electrode 35 of the electronic component 30” or “the first metal plating layer 50 ′ directly bonded to the first metal plating layer 50 ′. 2 metal plating layer 50 ′′ ”and“ metal foil 55 directly bonded to the second metal plating layer 50 ′′ ”.
- the second metal plating layer 50 ′′ is positioned at least between the first metal plating layer 50 ′ and the metal foil 55. Yes.
- the first metal plating layer 50 ′ is preferably a dry plating layer. That is, the first metal plating layer 50 ′ is preferably a layer formed by a dry plating method. Therefore, the first metal plating layer 50 ′ preferably includes at least one metal material selected from the group consisting of Ti (titanium), Cr (chromium), Ni (nickel), and Cu (copper). .
- the dry plating layer 50 ' may be made of other metal materials such as Ag (silver), Al (aluminum), Al alloy, Au (gold), Pt (platinum), Sn (tin) and W (tungsten). ) Etc., and may comprise at least one selected from the group consisting of.
- the second metal plating layer 50 ′′ is preferably a layer formed by a wet plating method. That is, the second metal plating layer 50 ′′ is preferably a wet plating layer. Therefore, the second metal plating layer 50 ′′ preferably comprises at least one metal material selected from the group consisting of Cu (copper) and Al (aluminum). The material of the second metal plating layer 50 '' is at least one selected from the group consisting of other metal materials such as silver (Ag), palladium (Pd), platinum (Pt), and nickel (Ni). May be included.
- the material of the second metal plating layer 50 ′′ is preferably one having high thermal conductivity and effectively contributing to the heat dissipation characteristics, and therefore Cu (copper) is particularly preferable.
- the metal foil 55, the first metal plating layer 50 ′, and the second metal plating layer 50 ′′ contain the same metal material.
- the metal foil 55, the first metal plating layer 50 ′, and the second metal plating layer 50 ′′ may all include at least a copper component (for example, the metal foil 55 may be copper).
- the first metal plating layer 50 ′ may include the following Cu thin film layer, and the second metal plating layer 50 ′′ may be a copper layer).
- the first metal plating layer 50 ′ as the dry plating layer is not limited to being configured as a single layer, and may be configured as a plurality of layers.
- the first metal plating layer 50 ' may have a two-layer structure including a Ti thin film layer and a Cu thin film layer thereon.
- the metal foil 55 included in the metal wiring layer 70 includes Cu (copper), Al (aluminum), Ag (silver), Pd (palladium), Pt (platinum), Ni (nickel), Ti (titanium), and Fe (iron). ), Zn (zinc), Zr (zirconium), Nb (niobium), Mo (molybdenum), Sn (tin), Ta (tantalum), and Au (gold), at least one metal material selected from the group consisting of Comprising.
- Cu (copper) and Al (aluminum) are preferable.
- the thickness of the metal foil 55 is preferably 9 ⁇ m to 2000 ⁇ m, more preferably 18 ⁇ m to 1000 ⁇ m, and still more preferably 200 ⁇ m to 500 ⁇ m (for example, about 300 ⁇ m).
- a relatively thick metal foil 55 is used.
- a thicker metal wiring layer 70 is preferably realized, and therefore a preferable wiring circuit configuration is implemented.
- the heat can be suitably radiated through a thick metal wiring layer.
- the electrode surface of the electronic component and the metal plating layer are “surface contact (direct bonding or surface bonding)”, the heat from the electronic component is efficiently transferred to the outside through the metal plating pattern layer. I can escape.
- the thick metal wiring layer 70 the electronic component package of the present invention may increase the mechanical strength as a whole. That is, the metal wiring layer 70 in the present invention can also function as a support layer for electronic components and metal pattern layers.
- the thick metal wiring layer has both a function as a support layer and a function as a heat sink.
- the package of the present invention can have excellent heat dissipation characteristics due to the thick metal wiring layer 70, the effect of increasing the characteristics and operating life of the electronic components can be brought about. Deformation and discoloration of parts and sealing resin can be effectively prevented.
- the electric resistance is excellent as compared with the case of electrical connection via wires or bumps. Therefore, in the package of the present invention, an effect of allowing a larger current to flow can be obtained.
- a light-emitting element package such as an LED package
- a light-emitting element package with higher luminance can be realized by the present invention due to high heat dissipation characteristics, a large current, and the like.
- a resist layer may be provided so as to be a more preferable aspect as a packaged product. That is, a resist layer may be provided for the “metal wiring layer”. More specifically, as shown in FIG. 11, a solder resist layer 90 is preferably provided so as to at least partially cover the metal wiring layer 70. The resist layer 90 may be the same as a solder resist generally used in the electronics mounting field.
- the electronic component package of the present invention includes the spacer means 60 inside the metal wiring layer 70 as shown in FIG. Specifically, the spacer means 60 may be locally interposed between the first metal plating layer 50 ′ and the metal foil 55.
- the spacer means 60 can be used as a stress relaxation member, and an effect of reducing stress that may occur in an electronic component package product can be achieved.
- the electronic component package of the present invention is not shown in FIG. It can have the form as shown in FIG. That is, as shown in the drawing, the spacer means 60 ′ included in the metal wiring layer 70 is “a part of the metal foil 55 extending locally toward the first metal plating layer 50 ′”. . Particularly preferably, a tip portion of a part of the metal foil 55 extending locally toward the first metal plating layer 50 ′ is in contact with the first metal plating layer 50 ′.
- the “part of the locally extending metal foil” corresponds to the “projection portion 60 ′ of the metal foil 55” in the manufacturing method of the present invention described above, and the shape thereof is a cylinder, a cone, or a polygon. Or it can be a pyramid or the like.
- the width dimension (for example, the maximum diameter dimension) of the “projection portion 60 ′ of the metal foil 55” is preferably 50 ⁇ m to 1 mm, and the height is preferably 100 ⁇ m or less.
- the pitch dimension of the “projection portion 60 ′ of the metal foil 55” can be, for example, 0.5 mm to 10 mm.
- the second metal plating layer 50 ′′ is the first metal plating layer 50. It may have an extended form other than the region sandwiched between 'and the metal foil 55. More specifically, the second metal plating layer 50 ′′ extends locally so as to penetrate the metal foil 55. That is, the second metal plating layer 50 ′′ is provided not only in a region sandwiched between the first metal plating layer 50 ′ and the metal foil 55 but also in a through region of the metal foil 55. ing.
- the “locally extending second metal plating layer portion” corresponds to the “penetrating portion 55a of the metal foil 55” in the manufacturing method of the present invention described above.
- the adhesive layer 80 is included inside the metal wiring layer. Specifically, the adhesive layer 80 is provided between the spacer means 60 'and the first metal plating layer 50'. For example, as shown in FIG. 14, between the “a part 60 ′ of the metal foil 55 locally extending toward the first metal plating layer 50 ′” and the “first metal plating layer 50 ′”. An adhesive layer 80 may be provided. In the case where the adhesive layer 80 is conductive, the material can be composed of Ag (silver) or Sn (tin).
- the adhesive layer 80 is made of an insulating material
- the adhesive layer 80 is at least one selected from the group consisting of an acrylic resin adhesive, a urethane resin adhesive, a silicone resin adhesive, and an epoxy resin adhesive. It can comprise the above adhesive material.
- Such an adhesive layer 80 can also be used as a stress relieving member, like the spacer means, and can exert an effect of reducing stress that may occur in the electronic component package product.
- the electronic component package of the present invention can be configured as a light emitting device package. That is, in the case where a light emitting element is included as an electronic component, a light emitting element package as shown in FIG. 15 can be obtained. In such a light emitting device package product, it is preferable that a phosphor layer and a transparent resin layer are provided. Specifically, instead of “the sealing resin layer in which the electronic component is embedded”, as shown in FIG. 15, “the phosphor layer 44 formed on the light emitting element 30” and “the light emitting element 30, the fluorescence A transparent resin layer 46 ”formed so as to cover the body layer 44 is preferably provided. Thus, a light emitting device package product can be realized as the electronic component package 100 of the present invention.
- the materials and thicknesses of the “phosphor layer” and “transparent resin layer” may be those conventionally used in general LED packages.
- the “light emitting element” is an element that emits light, and substantially means, for example, a light emitting diode (LED) and an electronic component including them. Accordingly, the “light emitting element” in the present invention is used to represent an aspect including not only “LED bare chip (ie, LED chip)” but also “discrete type in which the LED chip is molded”. Note that not only the LED chip but also a semiconductor laser chip can be used.
- the dry plating layer 50 ′ can be suitably used as a “reflection layer”.
- the “reflective layer” since the “reflective layer” is positioned directly under the light emitting element, the downward light emitted from the light emitting element can be efficiently reflected by the reflective layer (electronic component support). That is, “light emitted downward” can be directed upward.
- the dry plating layer 50 ' preferably includes a metal selected from the group consisting of Ag (silver) and Al (aluminum).
- First aspect A method for manufacturing an electronic component package, comprising: (I) forming a package precursor in which the electronic component is embedded in the sealing resin layer such that the electrode of the electronic component is exposed from the surface of the sealing resin layer; (Ii) forming a first metal plating layer so as to be joined to the exposed surface of the electrode of the electronic component; (Iii) including a step of opposingly arranging the metal foil in a state of being separated from the first metal plating layer, and (iv) a step of forming the second metal plating layer, In step (iv), the second metal plating layer is formed so as to fill the gap between the first metal plating layer and the metal foil, whereby the metal foil, the first metal plating layer, and the second metal plating are formed.
- Second aspect In the first aspect, the first metal plating layer is formed by performing a dry plating method, and the second metal plating layer is formed by performing a wet plating method. Manufacturing method of component package.
- Third aspect In the first aspect or the second aspect, in the step (iv), plating growth is performed from both surfaces of the first metal plating layer and the metal foil, thereby forming the second metal plating layer.
- a spacer means that is locally disposed between the first metal plating layer and the metal foil is used.
- a method for manufacturing an electronic component package wherein a metal foil is disposed opposite to the first metal plating layer.
- Fifth aspect In the fourth aspect, the spacer means is at least one protrusion provided on the metal foil and / or the first metal plating layer, and the metal foil is formed on the first metal plating layer via the protrusion.
- a method of manufacturing an electronic component package, wherein the electronic component package is disposed to face each other. 6th aspect In said 5th aspect, it has an adhesive layer at the front-end
- step (iii) As the metal foil in the step (iii), a metal foil having at least one penetrating portion is used. In the step (iv), the second metal plating layer is formed so that not only the gap portion but also the through portion is filled.
- step (iv) In the seventh aspect subordinate to the third aspect, in step (iv), not only the surfaces of both the first metal plating layer and the metal foil but also the inner wall surface of the penetrating portion is plated and grown. Thereby, a second metal plating layer is formed, and a method for manufacturing an electronic component package is provided.
- Ninth aspect The electronic component according to any one of the third to eighth aspects subordinate to the second aspect, wherein sputtering is performed as a dry plating method and electroplating is performed as a wet plating method.
- Tenth aspect In any one of the first to ninth aspects, by subjecting the integrated metal foil, the first metal plating layer, and the second metal plating layer to a patterning treatment after step (iv), A method of manufacturing an electronic component package, comprising forming a metal wiring layer.
- the formation of the package precursor in step (i) (A) a step of placing electronic components on the adhesive carrier so as to be attached to the adhesive carrier; (B) a step of forming a sealing resin layer on the adhesive carrier so as to cover the electronic component; and (c) an electronic component from the surface of the sealing resin layer by peeling the adhesive carrier from the sealing resin layer.
- a method for manufacturing an electronic component package comprising the step of exposing the electrode.
- Twelfth aspect In the eleventh aspect, including a light emitting element as the electronic component disposed in step (a), In the step (b), instead of forming the sealing resin layer, a phosphor layer is disposed on the light emitting element, and a transparent resin layer is formed so as to cover the light emitting element and the phosphor layer. Manufacturing method.
- a thirteenth aspect an electronic component package, Sealing resin layer, An electronic component embedded in a sealing resin layer, and a metal wiring layer bonded to an electrode of the electronic component; The metal wiring layer is directly bonded to the first metal plating layer directly bonded to the electrode of the electronic component, the second metal plating layer directly bonded to the first metal plating layer, and the second metal plating layer.
- Consists of metal foil joined to An electronic component package wherein at least a second metal plating layer is positioned between the first metal plating layer and the metal foil.
- Fourteenth aspect The electronic component package according to the thirteenth aspect, wherein the first metal plating layer is a dry plating layer and the second metal plating layer is a wet plating layer.
- Fifteenth aspect The electronic component package according to the thirteenth or fourteenth aspect, wherein the second metal plating layer extends locally so as to penetrate the metal foil.
- Sixteenth aspect In any one of the thirteenth to fifteenth aspects, An electronic component package comprising spacer means interposed between the first metal plating layer and the metal foil.
- Seventeenth aspect The electronic component package according to the sixteenth aspect, wherein the spacer means is a part of a metal foil that extends locally toward the first plating layer.
- Eighteenth aspect The electronic component package according to the sixteenth aspect or the seventeenth aspect, further comprising an adhesive layer between the spacer means and the first metal plating layer.
- Nineteenth aspect The electronic component package according to any one of the thirteenth to eighteenth aspects, wherein the metal foil has a thickness of 18 ⁇ m to 1000 ⁇ m.
- the first metal plating layer comprises at least one metal material selected from the group consisting of Ti, Cr, Ni and Cu
- the metal foil includes at least one metal material selected from the group consisting of Cu and Al
- the second metal plating layer includes at least one metal material selected from the group consisting of Cu, Ni and Al.
- An electronic component package characterized by comprising. Twenty-first aspect : The electronic component package according to any one of the thirteenth to twentieth aspects, wherein the electronic component includes a light emitting element.
- the peeled adhesive carrier may be reused. That is, in the present invention, the “adhesive carrier once used” can be used in another electronic component package manufacturing performed later.
- an alignment mark may be prepared in advance on the adhesive carrier in order to recognize the arrangement position of the electronic component 30.
- an alignment mark layer may be pasted on the adhesive carrier prior to the placement of the electronic component 30.
- An electronic component package was produced according to the present invention.
- an SUS304 plate (about 100 mm ⁇ about 100 mm-about 1.0 mmt) is prepared as a support base for the adhesive carrier, and an adhesive film (double-sided adhesive film composed of an adhesive layer, a PET film and a slightly adhesive layer, about A pressure-sensitive adhesive layer (100 mm ⁇ about 100 mm ⁇ about 150 ⁇ mt) was attached to a supporting substrate to obtain an adhesive carrier.
- the electronic component was placed on the adhesive carrier with the center point of the adhesive carrier as the reference position (that is, the component was mounted).
- the amount of sealing resin (liquid epoxy resin) corresponding to the number of packaging parts mounted was weighed, and the resin was placed on a carrier on which the parts were mounted, followed by vacuum defoaming.
- the carrier set in the hot press jig was subjected to temporary curing with a hot press, and then the jig was removed and the sealing resin was completely cured with a dryer.
- the adhesive carrier was peeled from the electronic component sealing body in which the electronic component was embedded in the sealing resin, and then washed and dried. Thereby, a package precursor was obtained.
- the package precursor was set in a sputtering apparatus and subjected to a plating process, thereby forming a Ti sputter layer of about 30 nm and a Cu sputter layer of about 100 nm.
- a metal foil was placed opposite to the obtained sputtered layer in a separated state.
- a metal foil having a penetrating portion and a protruding portion was used.
- a copper foil having a thickness of about 0.2 mm was prepared, and resist formation, development, etching, peeling treatment, and the like were performed on the copper foil to form a penetrating portion and a protruding portion.
- Rectangular through holes of about 0.5 mm ⁇ about 5 mm were formed as the through portions at intervals of about 5 mm, and cylindrical projections having a diameter of about 0.3 mm and a height of about 80 ⁇ m were formed as the projections.
- An adhesive layer was formed on the tip of the metal foil protrusion. Specifically, an Ag paste was applied on a glass substrate by a doctor blade method at about 50 ⁇ mt, and a protrusion of a metal foil was gently placed on the Ag paste to form an adhesive layer. The metal foil on which the adhesive layer was formed was set on the package precursor, and baked in nitrogen to be cured and fixed.
- the package precursor on which the metal foil was fixed was subjected to electrolytic copper plating, and the electrolytic copper plating was formed so as to fill in the “gap portion between the metal foil and the sputter layer” and the “penetration portion of the metal foil”. .
- the metal foil, the sputter layer, and the electrolytic copper plating were integrated with each other.
- the integrated metal layer was subjected to a patterning process to form a metal wiring layer.
- bumpless metal plating layer can be integrated with a thick metal foil on the “electrode exposed surface of the electronic component” exposed by peeling off the adhesive carrier, and the metal plating layer and the thick metal foil can be formed. It was also confirmed that can be suitably used as a heat sink.
- the present invention can be suitably used for various applications in the electronics mounting field.
- the present invention can be suitably applied to a power supply package (POL converter, for example, a step-down DC-DC converter), an LED package, a component built-in module, and the like.
- POL converter for example, a step-down DC-DC converter
- LED package for example, a LED package
- component built-in module for example, a component built-in module, and the like.
- Adhesive carrier Adhesive carrier supporting substrate 26 Adhesive layer of adhesive carrier 30 Electronic component 35 Electrode of electronic component 40 Sealing resin layer 50 ′ First metal plating layer 50 ′′ Second metal plating layer 55 Metal foil 55a Penetration part 60 Spacer means 60 'Local protrusion part used as spacer means 70 Metal wiring layer 80 Adhesive layer 90 Resist layer 100' Electronic component package precursor 100 Electronic component package
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Abstract
Description
(i)電子部品の電極が封止樹脂層の表面から露出するように電子部品が封止樹脂層に埋設されたパッケージ前駆体を形成する工程、
(ii)電子部品の電極の露出面と接合するように第1金属めっき層を形成する工程、
(iii)第1金属めっき層に対して離隔した状態で金属箔を対向配置する工程、ならびに
(iv)第2金属めっき層を形成する工程
を含んで成り、
工程(iv)では、第1金属めっき層および金属箔に挟まれた間隙部が満たされるように第2金属めっき層を形成し、それによって、金属箔と第1金属めっき層と第2金属めっき層とを一体化させることを特徴とする。
封止樹脂層、
封止樹脂層に埋設された電子部品、
電子部品の電極に接合されている金属配線層
を有して成り、
金属配線層が、電子部品の電極に直接的に接合された第1金属めっき層、第1金属めっき層に直接的に接合された第2金属めっき層、および、第2金属めっき層に直接的に接合された金属箔から構成されており、
第1金属めっき層と金属箔との間に第2金属めっき層が少なくとも位置付けられていることを特徴とする。
本発明者は、「背景技術」の欄において記載した従来のパッケージ技術に関し、以下の問題が生じることを見出した。
(i)電子部品の電極が封止樹脂層の表面から露出するように電子部品が封止樹脂層に埋設されたパッケージ前駆体を形成する工程、
(ii)電子部品の電極の露出面と接合するように第1金属めっき層を形成する工程、
(iii)第1金属めっき層に対して離隔した状態で金属箔を対向配置する工程、ならびに
(iv)第2金属めっき層を形成する工程
を含んで成り、
工程(iv)では、第1金属めっき層および金属箔に挟まれた間隙部が満たされるように第2金属めっき層を形成し、それによって、金属箔と第1金属めっき層と第2金属めっき層とを一体化させることを特徴とする、電子部品パッケージの製造方法が提供される。
封止樹脂層、
封止樹脂層に埋設された電子部品、
電子部品の電極に接合されている金属配線層
を有して成り、
金属配線層が、電子部品の電極に直接的に接合された第1金属めっき層、第1金属めっき層に直接的に接合された第2金属めっき層、および、第2金属めっき層に直接的に接合された金属箔から構成されており、
第1金属めっき層と金属箔との間に第2金属めっき層が少なくとも位置付けられていることを特徴とする。
本発明の一態様に係る電子部品パッケージの製造方法について説明する。図1(a)~(h)および図2(a)~(c)に本発明の一態様に係る製造方法に関連したプロセスを模式的に示している。
本発明においては、工程(iii)で用いる金属箔55として、貫通部55aを少なくとも1つ備えた金属箔を用いてもよい(図4(a)参照)。これにより、金属箔55の貫通部55aを介して、第1金属めっき層50'と金属箔55との間隙部にめっき溶液がより容易に行き渡ることになり、第2金属めっき層50''をより効率的に形成することができる。つまり、第2金属めっき層を形成するためのめっき溶液が「第1金属めっき層50'と金属箔55との間隙部」へと効果的に浸透していくための貫通部55aを金属箔55が備えていてもよい。
かかる実施態様は、図7および図8に示すように、金属層55として「複数の突起部60’および複数の貫通部55aを備えた金属箔」を用いる態様である。
本発明では、金属箔の対向配置に際して接着層を利用してもよい。例えば、図9(a)および9(b)に示すように、スペーサ手段となる突起部60’(例えば、金属箔の突起部)の先端部分に接着層80を設けてよい。接着層80を突起部60’に形成することで、工程(iii)では第1金属めっき層50'と金属箔55とが相互に接続される。つまり、第1金属めっき層50'と金属箔55との間が相互に固定化され得る。これは、接着層80を用いることによって、金属箔55と第1金属めっき層50'との接合強度が増加し、結果的に、金属箔55と第1金属めっき層50'と第2金属めっき層50''との一体化をより強固にできることを意味している。
本発明は、電子部品に発光素子が含まれる場合(つまり、粘着性キャリアに配置する電子部品として発光素子が含まれている場合)であっても、好適に発光素子パッケージ品を製造することができる。かかる場合、封止樹脂層の形成として、蛍光体層および透明樹脂層の形成を行う。具体的には、発光素子の周囲に蛍光体層44を形成し、次いで、発光素子および蛍光体層を覆うように透明樹脂層46を形成する。これによって、最終的に所望の発光素子パッケージを得ることができる(例えば図10(a)~(i)参照)。蛍光体層の形成および透明樹脂層の形成自体は、常套的なLEDパッケージ製造で一般に用いられている方法と同様であってよい。
次に本発明の一態様に係る電子部品パッケージについて説明する。本発明の一態様に係る電子部品パッケージは上記製造方法で得られるパッケージである。
第1態様:電子部品パッケージを製造するための方法であって、
(i)電子部品の電極が封止樹脂層の表面から露出するように電子部品が封止樹脂層に埋設されたパッケージ前駆体を形成する工程、
(ii)電子部品の電極の露出面と接合するように第1金属めっき層を形成する工程、
(iii)第1金属めっき層に対して離隔した状態で金属箔を対向配置する工程、ならびに
(iv)第2金属めっき層を形成する工程
を含んで成り、
工程(iv)では、第1金属めっき層および金属箔に挟まれた間隙部が満たされるように第2金属めっき層を形成し、それによって、金属箔と第1金属めっき層と第2金属めっき層とを一体化させることを特徴とする、電子部品パッケージの製造方法。
第2態様:上記第1態様において、乾式めっき法を実施することによって第1金属めっき層を形成する一方、湿式めっき法を実施することによって第2金属めっき層を形成することを特徴とする電子部品パッケージの製造方法。
第3態様:上記第1態様または第2態様において、工程(iv)では、第1金属めっき層および金属箔の双方の表面からめっき成長させ、それによって、第2金属めっき層を形成することを特徴とする電子部品パッケージの製造方法。
第4態様:上記第1態様~第3態様のいずれかにおいて、工程(iii)では、第1金属めっき層と金属箔との間にて局所的に配置されるスペーサ手段を用い、スペーサ手段を介して金属箔を第1金属めっき層に対して対向配置することを特徴とする電子部品パッケージの製造方法。
第5態様:上記第4態様において、スペーサ手段が、金属箔および/または第1金属めっき層に設けられた少なくとも1つの突起部であり、突起部を介して金属箔を第1金属めっき層に対向配置することを特徴とする電子部品パッケージの製造方法。
第6態様:上記第5態様において、突起部の先端に接着層を有して成り、対向配置に際しては接着層によって第1金属めっき層と金属箔との間を相互に固定化することを特徴とする電子部品パッケージの製造方法。
第7態様:上記第1態様~第6態様のいずれかにおいて、
工程(iii)の金属箔として、少なくとも一つの貫通部を有する金属箔を用い、
工程(iv)では、間隙部のみならず貫通部が満たされるように第2金属めっき層を形成することを特徴とする電子部品パッケージの製造方法。
第8態様:上記第3態様に従属する上記第7態様において、工程(iv)では、第1金属めっき層および金属箔の双方の表面のみならず、貫通部の内壁面からもめっき成長させ、それによって、第2金属めっき層を形成することを特徴とする電子部品パッケージの製造方法。
第9態様:上記第2態様に従属する上記第3態様~第8態様のいずれかにおいて、乾式めっき法としてスパッタリングを実施する一方、湿式めっき法として電気めっきを実施することを特徴とする電子部品パッケージの製造方法。
第10態様:上記第1態様~第9態様のいずれかにおいて、工程(iv)の後に、一体化した金属箔と第1金属めっき層と第2金属めっき層とをパターニング処理に付すことによって、金属配線層を形成することを特徴とする電子部品パッケージの製造方法。
第11態様:上記第1態様~第10態様のいずれかにおいて、工程(i)のパッケージ前駆体の形成は、
(a)粘着性キャリアに貼り付けられるように電子部品を該粘着性キャリアに配置する工程、
(b)電子部品を覆うように粘着性キャリア上に封止樹脂層を形成する工程、ならびに
(c)封止樹脂層から粘着性キャリアを剥離することによって、封止樹脂層の表面から電子部品の前記電極を露出させる工程
を含んで成ることを特徴とする電子部品パッケージの製造方法。
第12態様:上記第11態様において、工程(a)で配置する電子部品として発光素子を含み、
工程(b)では封止樹脂層の形成に代えて、発光素子上に蛍光体層を配置し、発光素子および蛍光体層を覆うように透明樹脂層を形成することを特徴とする電子部品パッケージの製造方法。
第13態様:電子部品パッケージであって、
封止樹脂層、
封止樹脂層に埋設された電子部品、および
電子部品の電極に接合されている金属配線層
を有して成り、
金属配線層が、電子部品の電極に直接的に接合された第1金属めっき層、第1金属めっき層に直接的に接合された第2金属めっき層、および、第2金属めっき層に直接的に接合された金属箔から構成されており、
第1金属めっき層と金属箔との間に第2金属めっき層が少なくとも位置付けられていることを特徴とする、電子部品パッケージ。
第14態様:上記第13態様において、第1金属めっき層が乾式めっき層から成る一方、第2金属めっき層が湿式めっき層から成ることを特徴とする電子部品パッケージ。
第15態様:上記第13態様または第14態様において、金属箔を貫通するように第2金属めっき層が局所的に延在していることを特徴とする電子部品パッケージ。
第16態様:上記第13態様~第15態様のいずれかにおいて、
第1金属めっき層と金属箔との間に介在したスペーサ手段が設けられていることを特徴とする電子部品パッケージ。
第17態様:上記第16態様において、スペーサ手段が、第1めっき層に向かって局所的に延在する金属箔の一部であることを特徴とする電子部品パッケージ。
第18態様:上記第16態様または第17態様において、スペーサ手段と第1金属めっき層との間に接着剤層を更に有して成ることを特徴とする電子部品パッケージ。
第19態様:上記第13態様~第18態様のいずれかにおいて、金属箔が18μm~1000μmの厚さを有することを特徴とする電子部品パッケージ。
第20態様:上記第13態様~第19態様のいずれかにおいて、第1金属めっき層がTi、Cr、NiおよびCuから成る群から選択される少なくとも1種類の金属材料を含んで成り、
金属箔がCu、Alから成る群から選択される少なくとも1種類の金属材料を含んで成り、また
第2金属めっき層がCu、NiおよびAlから成る群から選択される少なくとも1種類の金属材料を含んで成ることを特徴とする電子部品パッケージ。
第21態様:上記第13態様~第20態様のいずれかにおいて、電子部品として発光素子が含まれていることを特徴とする電子部品パッケージ。
24 粘着性キャリアの支持基板
26 粘着性キャリアの粘着層
30 電子部品
35 電子部品の電極
40 封止樹脂層
50’ 第1金属めっき層
50'' 第2金属めっき層
55 金属箔
55a 貫通部
60 スペーサ手段
60’ スペーサ手段となる局所的な突起部
70 金属配線層
80 接着層
90 レジスト層
100’ 電子部品パッケージ前駆体
100 電子部品パッケージ
Claims (21)
- 電子部品パッケージを製造するための方法であって、
(i)電子部品の電極が封止樹脂層の表面から露出するように該電子部品が該封止樹脂層に埋設されたパッケージ前駆体を形成する工程、
(ii)前記電子部品の前記電極の露出面と接合するように第1金属めっき層を形成する工程、
(iii)前記第1金属めっき層に対して離隔した状態で金属箔を対向配置する工程、ならびに
(iv)第2金属めっき層を形成する工程
を含んで成り、
前記工程(iv)では、前記第1金属めっき層および前記金属箔に挟まれた間隙部が満たされるように前記第2金属めっき層を形成し、それによって、前記金属箔と前記第1金属めっき層と前記第2金属めっき層とを一体化させることを特徴とする、電子部品パッケージの製造方法。 - 乾式めっき法を実施することによって前記第1金属めっき層を形成する一方、湿式めっき法を実施することによって前記第2金属めっき層を形成することを特徴とする、請求項1に記載の電子部品パッケージの製造方法。
- 前記工程(iv)では、前記第1金属めっき層および前記金属箔の双方の表面からめっき成長させ、それによって、前記第2金属めっき層を形成することを特徴とする、請求項1に記載の電子部品パッケージの製造方法。
- 前記工程(iii)では、前記第1金属めっき層と前記金属箔との間にて局所的に配置されるスペーサ手段を用い、該スペーサ手段を介して前記金属箔を前記第1金属めっき層に対して対向配置することを特徴とする、請求項1に記載の電子部品パッケージの製造方法。
- 前記スペーサ手段が、前記金属箔および/または前記第1金属めっき層に設けられた少なくとも1つの突起部であり、該突起部を介して前記金属箔を前記第1金属めっき層に対向配置することを特徴とする、請求項4に記載の電子部品パッケージの製造方法。
- 前記突起部の先端に接着層を有して成り、前記対向配置に際しては該接着層によって前記第1金属めっき層と前記金属箔との間を相互に固定化することを特徴とする、請求項5に記載の電子部品パッケージの製造方法。
- 前記工程(iii)の前記金属箔として、少なくとも一つの貫通部を有する金属箔を用い、
前記工程(iv)では、前記間隙部のみならず前記貫通部が満たされるように前記第2金属めっき層を形成することを特徴とする、請求項1に記載の電子部品パッケージの製造方法。 - 前記工程(iv)では、前記第1金属めっき層および前記金属箔の双方の表面からめっき成長させて、前記第2金属めっき層を形成し、また
前記工程(iv)では、前記第1金属めっき層および前記金属箔の双方の前記表面のみならず、前記貫通部の内壁面からも前記めっき成長させ、それによって、前記第2金属めっき層を形成することを特徴とする、請求項7に記載の電子部品パッケージの製造方法。 - 乾式めっき法を実施することによって前記第1金属めっき層を形成する一方、湿式めっき法を実施することによって前記第2金属めっき層を形成し、該乾式めっき法としてスパッタリングを実施する一方、該湿式めっき法として電気めっきを実施することを特徴とする、請求項3に記載の電子部品パッケージの製造方法。
- 前記工程(iv)の後に、前記一体化した前記金属箔と第1金属めっき層と第2金属めっき層とをパターニング処理に付すことによって、金属配線層を形成することを特徴とする、請求項1に記載の電子部品パッケージの製造方法。
- 前記工程(i)の前記パッケージ前駆体の形成は、
(a)粘着性キャリアに貼り付けられるように前記電子部品を該粘着性キャリアに配置する工程、
(b)前記電子部品を覆うように前記粘着性キャリア上に封止樹脂層を形成する工程、ならびに
(c)前記封止樹脂層から前記粘着性キャリアを剥離することによって、前記封止樹脂層の表面から前記電子部品の前記電極を露出させる工程
を含んで成ることを特徴とする、請求項1に記載の電子部品パッケージの製造方法。 - 前記工程(a)で配置する前記電子部品として発光素子を含み、
前記工程(b)では前記封止樹脂層の形成に代えて、前記発光素子上に蛍光体層を配置し、該発光素子および該蛍光体層を覆うように透明樹脂層を形成することを特徴とする、請求項11に記載の電子部品パッケージの製造方法。 - 電子部品パッケージであって、
封止樹脂層、
前記封止樹脂層に埋設された電子部品、および
前記電子部品の電極に接合されている金属配線層
を有して成り、
前記金属配線層が、前記電子部品の電極に直接的に接合された第1金属めっき層、該第1金属めっき層に直接的に接合された第2金属めっき層、および、該第2金属めっき層に直接的に接合された金属箔から構成されており、
前記第1金属めっき層と前記金属箔との間に前記第2金属めっき層が少なくとも位置付けられていることを特徴とする、電子部品パッケージ。 - 前記第1金属めっき層が乾式めっき層から成る一方、前記第2金属めっき層が湿式めっき層から成ることを特徴とする、請求項13に記載の電子部品パッケージ。
- 前記金属箔を貫通するように前記第2金属めっき層が局所的に延在していることを特徴とする、請求項13に記載の電子部品パッケージ。
- 前記第1金属めっき層と前記金属箔との間に介在したスペーサ手段が設けられていることを特徴とする、請求項13に記載の電子部品パッケージ。
- 前記スペーサ手段が、前記第1めっき層に向かって局所的に延在する前記金属箔の一部であることを特徴とする、請求項16に記載の電子部品パッケージ。
- 前記スペーサ手段と前記第1金属めっき層との間に接着剤層を更に有して成ることを特徴とする、請求項16に記載の電子部品パッケージ。
- 前記金属箔が18μm~1000μmの厚さを有することを特徴とする、請求項13に記載の電子部品パッケージ。
- 前記第1金属めっき層がTi、Cr、NiおよびCuから成る群から選択される少なくとも1種類の金属材料を含んで成り、
前記金属箔がCu、Alから成る群から選択される少なくとも1種類の金属材料を含んで成り、また
前記第2金属めっき層がCu、NiおよびAlから成る群から選択される少なくとも1種類の金属材料を含んで成ることを特徴とする、請求項13に記載の電子部品パッケージ。 - 前記電子部品として発光素子が含まれていることを特徴とする、請求項13に記載の電子部品パッケージ。
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Also Published As
Publication number | Publication date |
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US9825209B2 (en) | 2017-11-21 |
US20150221842A1 (en) | 2015-08-06 |
JPWO2014097645A1 (ja) | 2017-01-12 |
JP5624699B1 (ja) | 2014-11-12 |
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