WO2014097454A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2014097454A1
WO2014097454A1 PCT/JP2012/083100 JP2012083100W WO2014097454A1 WO 2014097454 A1 WO2014097454 A1 WO 2014097454A1 JP 2012083100 W JP2012083100 W JP 2012083100W WO 2014097454 A1 WO2014097454 A1 WO 2014097454A1
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Prior art keywords
layer
semiconductor substrate
anode
electrode
diode
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PCT/JP2012/083100
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English (en)
French (fr)
Japanese (ja)
Inventor
亀山　悟
圭佑 木村
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トヨタ自動車株式会社
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Application filed by トヨタ自動車株式会社 filed Critical トヨタ自動車株式会社
Priority to CN201280077788.5A priority Critical patent/CN104871312B/zh
Priority to DE112012007249.9T priority patent/DE112012007249B4/de
Priority to PCT/JP2012/083100 priority patent/WO2014097454A1/ja
Priority to US14/443,199 priority patent/US10074719B2/en
Priority to JP2014552840A priority patent/JP5924420B2/ja
Publication of WO2014097454A1 publication Critical patent/WO2014097454A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Definitions

  • the technology described in this specification relates to a semiconductor device.
  • Japanese Patent Publication No. 2012-43890 discloses a semiconductor device in which an IGBT region and a diode region are formed on the same semiconductor substrate.
  • a surface electrode is provided on the front surface of the semiconductor substrate, and a back electrode is provided on the back surface of the semiconductor substrate.
  • the IGBT region includes a first conductivity type collector layer in contact with the back electrode, a second conductivity type IGBT drift layer provided on the surface side of the semiconductor substrate with respect to the collector layer, and an IGBT drift layer.
  • a first conductivity type body layer that is provided on the surface side of the semiconductor substrate and is in contact with the surface electrode, and a trench that extends from the surface of the semiconductor substrate to the IGBT drift layer.
  • a gate electrode insulated from the surface electrode, and a second conductivity type emitter layer that is partially provided between the body layer and the surface electrode and is in contact with the insulating film of the gate electrode and the surface electrode .
  • the diode region is provided with a high second conductivity type cathode layer in contact with the back electrode, and a second conductivity type diode having an impurity concentration lower than that of the cathode layer.
  • the drift layer is provided on the surface side of the semiconductor substrate with respect to the diode drift layer.
  • the first conductivity type anode layer is in contact with the surface electrode, and the trench extends from the surface of the semiconductor substrate to the diode drift layer.
  • a first conductivity type that is disposed between the trench electrode insulated from the semiconductor substrate by the insulating film and between the anode layer and the surface electrode, and is in contact with the surface electrode and has a higher impurity concentration than the anode layer;
  • the anode contact layer is provided.
  • the diode region is partitioned into unit diode regions by a gate electrode or a trench electrode.
  • the anode contact layer is widely formed in the diode region, the amount of holes injected from the anode contact layer to the diode drift layer increases during diode operation, and switching loss increases. For this reason, in order to improve the switching loss during the diode operation, it is preferable to reduce the proportion of the anode contact layer in the diode region. However, if the anode contact layer is simply reduced, forward voltage fluctuations due to gate interference increase during diode operation.
  • This specification discloses a semiconductor device in which an IGBT region and a diode region are formed on the same semiconductor substrate.
  • a surface electrode is provided on the front surface of the semiconductor substrate, and a back electrode is provided on the back surface of the semiconductor substrate.
  • the IGBT region includes a first conductivity type collector layer in contact with the back electrode, a second conductivity type IGBT drift layer provided on the surface side of the semiconductor substrate with respect to the collector layer, and an IGBT drift layer.
  • a first conductivity type body layer that is provided on the surface side of the semiconductor substrate and is in contact with the surface electrode, and a trench that extends from the surface of the semiconductor substrate to the IGBT drift layer.
  • a gate electrode insulated from the surface electrode, and a second conductivity type emitter layer that is partially provided between the body layer and the surface electrode and is in contact with the insulating film of the gate electrode and the surface electrode .
  • the diode region is provided with a high second conductivity type cathode layer in contact with the back electrode, and a second conductivity type diode having an impurity concentration lower than that of the cathode layer.
  • the drift layer is provided on the surface side of the semiconductor substrate with respect to the diode drift layer.
  • the first conductivity type anode layer is in contact with the surface electrode, and the trench extends from the surface of the semiconductor substrate to the diode drift layer.
  • An anode contact layer of one conductivity type is provided.
  • the diode region is partitioned into unit diode regions by a gate electrode or a trench electrode. In the unit diode region adjacent to the IGBT region, when the surface of the semiconductor substrate is viewed in plan, the anode layer and the anode contact layer are mixedly arranged, and at least at the place facing the emitter layer with the gate electrode interposed therebetween, An anode contact layer is disposed.
  • the anode contact layer is not formed entirely but partially formed in the unit diode region adjacent to the IGBT region. With this configuration, the amount of holes injected from the anode contact layer into the diode drift layer during diode operation is reduced. The reverse recovery characteristic of the diode region can be improved and the switching loss can be reduced.
  • the influence of gate interference during diode operation can be suppressed. That is, even when a gate voltage is applied to the gate electrode in the IGBT region and a channel connecting the emitter layer and the IGBT drift layer is formed in the vicinity of the gate electrode during diode operation, a unit adjacent to the IGBT region is formed. In the diode region, since the anode contact layer is formed at a position facing the emitter layer with the gate electrode interposed therebetween, it is possible to suppress the reduction of holes due to the formation of the channel. Thereby, fluctuations in the forward voltage due to gate interference during diode operation can be suppressed.
  • FIG. 1 is a plan view of a semiconductor device according to Example 1.
  • FIG. FIG. 2 is a sectional view taken along line II-II in FIG.
  • FIG. 3 is a sectional view taken along line III-III in FIG. 1. It is a top view of the semiconductor device which concerns on a modification. It is a top view of the semiconductor device which concerns on a modification. It is a top view of the semiconductor device which concerns on a modification. It is a top view of the semiconductor device which concerns on a modification.
  • anode contact layers and anode layers are alternately arranged in the unit diode region adjacent to the IGBT region in the direction in which the gate electrode extends when the surface of the semiconductor substrate is viewed in plan view. Can be configured.
  • the anode contact layer is left in a portion facing the emitter layer with the gate electrode interposed therebetween, and the proportion of the anode contact layer in the unit diode region is reduced. Can be made.
  • the semiconductor device disclosed in this specification includes an anode contact layer in the vicinity of a gate electrode in a unit diode region adjacent to the IGBT region in a direction orthogonal to the direction in which the gate electrode extends when the surface of the semiconductor substrate is viewed in plan view.
  • the anode layer is arranged in the center of the unit diode region.
  • the anode contact layer is left in a portion facing the emitter layer with the gate electrode interposed therebetween, and the proportion of the anode contact layer in the unit diode region is reduced. Can be made.
  • the semiconductor device 2 shown in FIG. 1 to FIG. 3 is an RC-IGBT in which an IGBT and a diode are formed on the same semiconductor substrate 4.
  • the semiconductor device 2 has a plurality of IGBT regions and a plurality of diode regions alternately arranged, and has a plurality of boundaries between the IGBT regions and the diode regions.
  • 1 to 3 illustrate one of the boundaries between the plurality of IGBT regions and the diode region, and each of the plurality of boundaries of the semiconductor device 2 has the same configuration as in FIGS. ing.
  • the semiconductor device 2 includes a semiconductor substrate 4, a dummy gate 8, an insulating gate 10 and a surface insulating film 12 formed on the surface side of the semiconductor substrate 4, a surface electrode 6 in contact with the surface of the semiconductor substrate 4, and the semiconductor substrate 4 And a back electrode 14 in contact with the back surface.
  • the dummy gate 8 and the insulated gate 10 are formed on the semiconductor substrate 4 at a substantially constant interval.
  • the semiconductor substrate 4 includes a diode region 16 and an IGBT region 18.
  • the diode region 16 is made of an anode contact layer 20 made of a p-type semiconductor having a high impurity concentration, an anode layer 22 made of a p-type semiconductor, and an n-type semiconductor having a low impurity concentration.
  • a drift layer 24, a buffer layer 26 made of an n-type semiconductor, and a cathode layer 28 made of an n-type semiconductor having a high impurity concentration are formed.
  • the anode contact layer 20 and the anode layer 22 are exposed on the surface of the semiconductor substrate 4 and are in contact with the surface electrode 6.
  • the anode contact layer 20 is partially formed on the surface layer portion of the anode layer 22.
  • the drift layer 24 is formed on the back surface of the anode layer 22.
  • the buffer layer 26 is formed on the back surface of the drift layer 24.
  • the cathode layer 28 is formed on the back surface of the buffer layer 26. The cathode layer 28 is exposed on the back surface of the semiconductor substrate 4 and is in contact with the back electrode 14.
  • the IGBT region 18 includes a body contact layer 30 made of a p-type semiconductor having a high impurity concentration, an emitter layer 32 made of an n-type semiconductor having a high impurity concentration, a body layer 34 made of a p-type semiconductor, and an n having a low impurity concentration.
  • a drift layer 24 made of a p-type semiconductor, a buffer layer 26 made of an n-type semiconductor, and a collector layer 36 made of a p-type semiconductor having a high impurity concentration are formed.
  • the body contact layer 30, the emitter layer 32, and the body layer 34 are exposed on the surface of the semiconductor substrate 4 and are in contact with the surface electrode 6.
  • the body contact layer 30 and the emitter layer 32 are partially formed on the surface layer portion of the body layer 34.
  • the drift layer 24 is formed on the back surface of the body layer 34.
  • the buffer layer 26 is formed on the back surface of the drift layer 24.
  • the collector layer 36 is formed on the back surface of the buffer layer 26. The collector layer 36 is exposed on the back surface of the semiconductor substrate 4 and is in contact with the back electrode 14.
  • the drift layer 24 (also referred to as a diode drift layer) in the diode region 16 and the drift layer 24 (also referred to as an IGBT drift layer) in the IGBT region 18 are formed as a common layer.
  • the buffer layer 26 in the diode region 16 and the buffer layer 26 in the IGBT region 18 are formed as a common layer.
  • the anode layer 22 in the diode region 16 and the body layer 34 in the IGBT region 18 are formed as a common layer. In other words, the anode layer 22 in the diode region 16 and the body layer 34 in the IGBT region 18 have a common depth and impurity concentration from the surface of the semiconductor substrate 4.
  • the dummy gate 8 penetrates the anode layer 22 from the surface side of the semiconductor substrate 4 and reaches the inside of the drift layer 24 in the diode region 16.
  • the dummy gate 8 includes a dummy gate insulating film 40 formed inside a trench 38 formed on the surface side of the semiconductor substrate 4, and a dummy gate electrode covered with the dummy gate insulating film 40 and filled in the trench 38. 42.
  • the dummy gate electrode 42 is in contact with the surface electrode 6 and is electrically connected to the surface electrode 6.
  • the insulated gate 10 penetrates the body layer 34 from the surface side of the semiconductor substrate 4 and reaches the inside of the drift layer 24 in the IGBT region 18.
  • the insulated gate 10 includes a gate insulating film 46 formed on the inner wall of the trench 44 formed on the surface side of the semiconductor substrate 4 and a gate electrode 48 covered with the gate insulating film 46 and filled in the trench 44. I have.
  • the gate electrode 48 is isolated from the surface electrode 6 by the surface insulating film 12.
  • the gate electrode 48 is electrically connected to a gate electrode terminal (not shown).
  • the diode region 16 is composed of a plurality of unit diode regions partitioned by the trench 38 of the dummy gate 8 or the trench 44 of the insulated gate 10.
  • the IGBT region 18 is composed of a plurality of unit IGBT regions partitioned by the trench 44 of the insulated gate 10.
  • a unit diode region adjacent to the IGBT region 18 is referred to as a unit diode region 16a
  • a unit IGBT region adjacent to the unit diode region 16a is referred to as a unit IGBT region 18a.
  • the emitter layer 32 is between two insulated gates 10 arranged side by side in a direction (Y direction in the figure) in which the insulated gate 10 extends from one insulated gate 10 to the other insulated gate 10. It arrange
  • the body layer 34 is partitioned into a rectangular range by the insulated gate 10 and the emitter layer 32, and the body contact layer 30 is disposed near the center of the partitioned body layer 34. Has been.
  • the anode contact layer 20 is disposed only in a region close to the insulated gate 10 or the dummy gate 8.
  • the anode contact layer 20 is disposed only on the extension line in the direction in which the emitter layer 32 extends in the IGBT region 18. That is, in the unit diode region 16a adjacent to the IGBT region 18, the anode contact layer 20 is disposed at a position facing the emitter layer 32 of the unit IGBT region 18a adjacent to the unit diode region 16a with the insulating gate 10 interposed therebetween. Yes.
  • the anode contact layer 20 and the anode layer 22 are alternately arranged in the vicinity of the insulating gate 10 in the direction in which the insulating gate 10 extends (Y direction in the figure).
  • the anode contact layer 20 is disposed in the vicinity of the insulating gate 10 in the unit diode region 16a adjacent to the unit IGBT region 18a in the direction orthogonal to the direction in which the insulating gate 10 extends (X direction in the figure).
  • the anode layer 22 is disposed at the center of the unit diode region 16a.
  • the impurity concentration of the anode layer 22 at a location facing the emitter layer 32 with the insulating gate 10 interposed therebetween is higher.
  • the impurity concentration of the anode layer 22 in the unit diode region 16a adjacent to the unit IGBT region 18a is a maximum value at a location facing the emitter layer 32 with the insulated gate 10 interposed therebetween.
  • the anode contact layer 20 is formed in a unit diode region 16a adjacent to the unit IGBT region 18a at a location facing the emitter layer 32 with the insulating gate 10 interposed therebetween.
  • the influence of gate interference during diode operation can be suppressed. That is, even when a gate voltage is applied to the gate electrode 48 of the unit IGBT region 18a and a channel connecting the emitter layer 32 and the drift layer 24 is formed in the vicinity of the insulated gate 10 during diode operation, Since the anode contact layer 20 is formed at a position facing the emitter layer 32 across the insulated gate 10 in the diode region 16a, the reduction of holes due to the formation of the channel can be suppressed. Thereby, fluctuations in the forward voltage due to gate interference during diode operation can be suppressed.
  • the anode contact layer 20 is not formed entirely but partially formed in the unit diode region 16a adjacent to the unit IGBT region 18a. With this configuration, the amount of holes injected from the anode contact layer 20 into the drift layer 24 during diode operation is reduced. The reverse recovery characteristic of the diode region 16 can be improved and the switching loss can be reduced.
  • the arrangement of the anode contact layer 20 in the diode region 16 is not limited to that in the above embodiment.
  • the anode contact layer 20 has a direction (X direction in the figure) orthogonal to the direction (Y direction in the figure) in which the insulated gate 10 or the dummy gate 8 extends. It may be arranged to extend.
  • the anode contact layer 20 is disposed only on the extension line in the direction in which the emitter layer 32 extends in the IGBT region 18.
  • the anode contact layer 20 and the anode layer 22 are alternately arranged in the direction in which the insulated gate 10 extends (Y direction in the drawing). .
  • the anode contact layer 20 may be formed in a ladder shape having a partial opening.
  • the anode contact layer 20 and the anode layer are formed in the center of the unit diode region 16a with respect to the direction in which the insulated gate 10 extends (Y direction in the figure). 22 are alternately arranged.
  • the anode contact layer is located in the vicinity of the insulating gate 10 in the direction orthogonal to the direction in which the insulating gate 10 extends (X direction in the figure). 20 is disposed, and the anode layer 22 is disposed in the center of the unit diode region 16a.
  • the arrangement of the emitter layer 32 in the IGBT region 18 is not limited to that in the above embodiment.
  • the emitter layers 32 may be arranged in a lattice pattern as in the semiconductor device 54 of the modification shown in FIG.
  • the emitter layer 32 may be arranged in a ladder shape having a partial opening.
  • the anode contact layer 20 in the diode region 16 is disposed at a location facing the emitter layer 32 with the insulated gate 10 interposed therebetween.
  • the anode contact layer 20 in the diode region 16 extends parallel to the direction (Y direction) in which the insulated gate 10 or the dummy gate 8 extends at a location close to the insulated gate 10 or the dummy gate 8. Is arranged.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/JP2012/083100 2012-12-20 2012-12-20 半導体装置 WO2014097454A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201280077788.5A CN104871312B (zh) 2012-12-20 2012-12-20 半导体装置
DE112012007249.9T DE112012007249B4 (de) 2012-12-20 2012-12-20 Halbleitervorrichtung
PCT/JP2012/083100 WO2014097454A1 (ja) 2012-12-20 2012-12-20 半導体装置
US14/443,199 US10074719B2 (en) 2012-12-20 2012-12-20 Semiconductor device in which an insulated-gate bipolar transistor ( IGBT) region and a diode region are formed on one semiconductor substrate
JP2014552840A JP5924420B2 (ja) 2012-12-20 2012-12-20 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2012/083100 WO2014097454A1 (ja) 2012-12-20 2012-12-20 半導体装置

Publications (1)

Publication Number Publication Date
WO2014097454A1 true WO2014097454A1 (ja) 2014-06-26

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PCT/JP2012/083100 WO2014097454A1 (ja) 2012-12-20 2012-12-20 半導体装置

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Country Link
US (1) US10074719B2 (de)
JP (1) JP5924420B2 (de)
CN (1) CN104871312B (de)
DE (1) DE112012007249B4 (de)
WO (1) WO2014097454A1 (de)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015177058A (ja) * 2014-03-14 2015-10-05 株式会社東芝 半導体装置
WO2016009714A1 (ja) * 2014-07-14 2016-01-21 トヨタ自動車株式会社 半導体装置
WO2016021299A1 (ja) * 2014-08-06 2016-02-11 トヨタ自動車株式会社 半導体装置及び半導体装置の製造方法
JP2016100464A (ja) * 2014-11-21 2016-05-30 三菱電機株式会社 逆導通型半導体装置
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