CN106206573A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN106206573A
CN106206573A CN201610363603.7A CN201610363603A CN106206573A CN 106206573 A CN106206573 A CN 106206573A CN 201610363603 A CN201610363603 A CN 201610363603A CN 106206573 A CN106206573 A CN 106206573A
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semiconductor substrate
positive contact
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CN106206573B (zh
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妹尾贤
添野明高
平林康弘
久野敬史
山下侑佑
町田悟
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Denso Corp
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Toyota Motor Corp
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Abstract

本发明提供一种半导体装置。在对半导体基板进行俯视观察时，存在如下范围，即，柱区露出于半导体基板的表面的柱露出范围、柱区与阳极接触区的深部侧相接的柱接触范围、阳极区与阳极接触区的深部侧相接的阳极接触范围。在柱接触范围与阳极接触范围所并排的方向上的柱接触范围的宽度与阳极接触范围的宽度相比而较窄。

Description

半导体装置
技术领域
本说明书公开的技术涉及一种半导体装置。
背景技术
如图11所示，专利文献1(日本特开2013-048230号公报)所公开的半导体装置101具备半导体基板102、被形成在半导体基板102的表面150上的表面电极105、被形成在半导体基板102的背面160上的背面电极106。在同一半导体基板102上形成有IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极性晶体管)区103和二极管区104。
IGBT区103具备：n型的漂移区113；n型的势垒区115，其被形成于漂移区113的表面侧；p型的体区116，其被形成于势垒区115的表面侧；n型的发射区117，其被形成于体区116的表面侧，且与表面电极105导通；p型的体接触区118，其被形成于体区116的表面侧且与发射区117不同的位置处，并且与体区116相比杂质浓度较高，且与表面电极105导通。此外，IGBT区103具备多个栅极沟槽130，所述栅极沟槽130从半导体基板102的表面150起贯穿发射区117、体区116和势垒区115并延伸至到达漂移区113的深度为止。此外，IGBT区103具备n型的柱区120，所述n型的柱区120在栅极沟槽130与栅极沟槽130之间从半导体基板102的表面150起贯穿体区116并延伸至到达势垒区115的深度为止，且与表面电极105和势垒区115导通。
二极管区104具备：n型的漂移区113；n型的势垒区125，其被形成于漂移区113的表面侧；p型的阳极区123，其被形成于势垒区125的表面侧；p型的阳极接触区124，其被形成于阳极区123的表面侧，并且与阳极区123相比杂质浓度较高，且与表面电极105导通。此外，二极管区104具备多个栅极沟槽130，所述栅极沟槽130从半导体基板102的表面150起贯穿阳极接触区124、阳极区123和势垒区125并延伸至到达漂移区113的深度为止。此外，二极管区104具备n型的柱区120，所述n型的柱区120在栅极沟槽130与栅极沟槽130之间从半导体基板102的表面150起贯穿阳极区123并延伸至到达势垒区125的深度为止，且与表面电极105和势垒区125导通。在该半导体装置101中，阳极接触区124与柱区120分离开来。
另外，在漂移区113的背面侧形成有n型的缓冲区112。IGBT区103具备被形成于缓冲区112的背面侧的p型的集电区111。二极管区104具备被形成于缓冲区112的背面侧的n型的阴极区121。在栅极沟槽130的内部形成有栅极电极132和栅极绝缘膜131。在栅极电极132之上配置有层间绝缘膜133。
发明内容
发明所要解决的课题
在上述的半导体装置101中，为了使电流容易流向IGBT区103，而考虑到提高沿着IGBT区103的栅极沟槽130而形成的通道的密度(IGBT区103的每单位面积的通道的数量)。为此，考虑到使IGBT区103中的栅极沟槽130与栅极沟槽130之间的间隔缩窄，并增加半导体基板102的每单位面积的栅极沟槽130的数量从而提高栅极沟槽130的密度。
在形成多个栅极沟槽130时，由于通常以相同的工序来形成IGBT区103中的栅极沟槽130与二极管区104中的栅极沟槽130，因此在提高IGBT区103的栅极沟槽130的密度时，如果未随之也提高二极管区104的栅极沟槽130的密度，则二极管区104的耐压将下降。当二极管区104的栅极沟槽130的密度提高时，二极管区104中的栅极沟槽130与栅极沟槽130之间的间隔将变窄。
当二极管区104中的栅极沟槽130与栅极沟槽130之间的间隔变窄时，用于在该栅极沟槽130与栅极沟槽130之间形成柱区120的区域将变窄。此外，用于形成阳极接触区124的区域也将变窄。其结果为，在二极管区104中形成阳极接触区124与柱区120时，阳极接触区124与柱区120之间的间隔变密，从而考虑到阳极接触区124与柱区120重叠而使两者发生接触的情况。当p型的阳极接触区124与n型的柱区120发生接触时，通过阳极接触区124与柱区120而形成了pn结二极管。
在这种半导体装置中，当将二极管接通时(当施加相对于二极管区104的正向电压时)，空穴将从通过接触而形成pn结二极管的阳极接触区124流入到柱区120中，并且多余的空穴被蓄积于半导体基板102中。如果这样，则在恢复二极管时(在施加了相对于二极管区104的反向电压时)，在被蓄积于半导体基板102中的空穴被喷出到表面电极105上之前需要时间，从而有时会使开关速度变慢。
因此，在本说明书中，提供一种即使提高了栅极沟槽的密度，也能够抑制从阳极接触区向柱区流入的空穴的量的技术。
用于解决课题的方法
在本说明书所公开的半导体装置中，在同一半导体基板上形成有IGBT区和二极管区，且在半导体基板的表面上形成有表面电极。所述半导体装置的特征在于，IGBT区具备：n型的漂移区；n型的势垒区，其被形成于漂移区的表面侧；p型的体区，其被形成于势垒区的表面侧；n型的发射区，其被形成于体区的表面侧，且与表面电极导通；p型的体接触区，其被形成于体区的表面侧且与发射区不同的位置处，并且与体区相比杂质浓度较高，且与表面电极导通。此外，IGBT区具备：多个栅极沟槽，其从半导体基板的表面起贯穿发射区、体区和势垒区并延伸至到达漂移区的深度为止；n型的柱区，其在栅极沟槽与栅极沟槽之间从半导体基板的表面起贯穿体区并延伸至到达势垒区的深度为止，且与表面电极和势垒区导通。二极管区具备：n型的漂移区；n型的势垒区，其被形成于漂移区的表面侧；p型的阳极区，其被形成于势垒区的表面侧；p型的阳极接触区，其被形成于阳极区的表面侧的至少一部分上，并且与阳极区相比杂质浓度较高，且与表面电极导通。此外，二极管区具备：多个栅极沟槽，其从半导体基板的表面起至少贯穿阳极区和势垒区并延伸至到达漂移区的深度为止；n型的柱区，其在栅极沟槽与栅极沟槽之间从半导体基板的表面起贯穿阳极接触区与阳极区并延伸至到达势垒区的深度为止，且与表面电极和势垒区导通。在对半导体基板进行俯视观察时，存在如下范围，即，柱区露出于半导体基板的表面的柱露出范围、柱区与阳极接触区的深部侧相接的柱接触范围、阳极区与阳极接触区的深部侧相接的阳极接触范围。在柱接触范围与阳极接触范围所并排的方向上的柱接触范围的宽度与所述阳极接触范围的宽度相比而较窄。
在该半导体装置中，还可以为，在二极管区中，阳极接触区的一端部与柱区相接，另一端部延伸至栅极沟槽为止。即，阳极接触区可以以跨及阳极区的表面侧的整个宽度的方式而被形成。
在上述的半导体装置中，由于容许阳极接触区与柱区相接，因此能够使用于形成阳极接触区与柱区的栅极沟槽与栅极沟槽之间的区域缩窄。因此，能够使栅极沟槽的数量增加，从而提高栅极沟槽的密度。
此外，在上述的半导体装置中，通过p型的阳极接触区与n型的柱区相接，从而形成了pn结二极管。在该半导体装置中，当使二极管接通时(当施加了相对于二极管区的正向电压时)，空穴将从形成pn结二极管的阳极接触区流入柱区。此时，根据上述的结构，由于在阳极接触区的深部侧柱区所接触的柱接触范围的宽度窄于在阳极接触区的深部侧阳极区所接触的阳极接触范围的宽度，因此能够缩小阳极接触区与柱区的接触面积。由此，能够抑制从阳极接触区向柱区流入的空穴的量。根据上述的半导体装置，即使提高了栅极沟槽的密度，也能够抑制从阳极接触区向柱区流入的空穴的量。
其结果为，由于在半导体基板上未蓄积有多余的空穴，且在恢复二极管时(在施加了相对于二极管区的反向电压时)，至被存储于半导体基板上的空穴被喷出到表面电极上为止的时间变短，因此能够加快开关速度。
附图说明
图1为第一实施例所涉及的半导体装置的剖视图。
图2为图1的主要部分Ⅱ的剖视图。
图3为表示图2的Ⅲ-Ⅲ剖面的杂质浓度的分布的图。
图4为对图2所记载的半导体基板进行俯视观察时的图。
图5为图2的主要部分V的剖视图。
图6为表示图2的VI-VI剖面的杂质浓度的分布的图。
图7为第二实施例所涉及的半导体装置的剖视图。
图8为第三实施例所涉及的半导体装置的主要部分的剖视图。
图9为表示杂质浓度的分布的一个示例的图。
图10为其他实施例所涉及的半导体装置的剖视图。
图11为现有的半导体装置的剖视图。
具体实施方式
如图1所示，第一实施例所涉及的半导体装置1具备半导体基板2、被形成在半导体基板2的表面50上的表面电极5、和被形成在半导体基板2的背面60上的背面电极6。
半导体基板2具备IGBT区3与二极管区4。IGBT区3与二极管区4以邻接的方式而被形成。在同一半导体基板2上，形成有IGBT区3与二极管区4。IGBT区3与二极管区4在横向(x方向)上并排形成。在半导体基板2上形成有半导体元件。在半导体基板2的IGBT区3中，形成有IGBT(InsulatedGate Bipolar Transistor：绝缘栅双极性晶体管)。在半导体基板2的二极管区4中，形成有FWD(Free Wheeling Diode：续流二极管)。IGBT与FWD以反并列的状态而被形成。由此，形成了RC-ICBT(Reverse ConductingInsulated Gate Bipolar Transistor：反向导通绝缘栅双极性晶体管)。
表面电极5与背面电极6例如使用一个或多个铝(Al)、铝硅(AlSi)、钛(Ti)、镍(Ni)、以及金(Au)等的金属而被形成。表面电极5覆盖了半导体基板2的表面50。背面电极6覆盖了半导体基板2的背面60。表面电极5与背面电极6分别以跨及半导体基板2的IGBT区3与二极管区4的方式而被形成。
在半导体基板2的IGBT区3上，以从背面60侧朝向表面50侧的顺序，依次形成有集电区11、缓冲区12、漂移区13、势垒区15、体区16、发射区17、以及体接触区18。此外，在半导体基板2的二极管区4上，以从背面60侧朝向表面50侧的顺序，依次形成有阴极区21、缓冲区12、漂移区13、势垒区25、阳极区23、以及阳极接触区24。缓冲区12与漂移区13以在IGBT区3与二极管区4中共同的方式而被形成。此外，在半导体基板2上形成有多个柱区20。此外，在半导体基板2上形成有多个栅极沟槽30。
IGBT区3
集电区11为p型区域。在集电区11中，杂质浓度较高。集电区11被形成于缓冲区12的背面侧。集电区11被形成在露出于半导体基板2的背面60的范围内。集电区11与背面电极6欧姆接触。集电区11与背面电极6导通。
缓冲区12为n型区域。缓冲区12被形成于集电区11的表面侧。缓冲区12被形成于集电区11与漂移区13之间。
漂移区13为n型区域。漂移区13的杂质浓度低于缓冲区12的杂质浓度。漂移区13被形成于缓冲区12的表面侧。漂移区13被形成于缓冲区12与势垒区15之间。
势垒区15为n型区域。势垒区15的杂质浓度高于漂移区13的杂质浓度。势垒区15被形成于漂移区13的表面侧。势垒区15被形成于漂移区13与体区16之间。势垒区15的横向(x方向)的端部与栅极沟槽30相接。
体区16为p型区域。体区16的杂质浓度低于集电区11的杂质浓度。体区16被形成于势垒区15的表面侧。体区16被形成于势垒区15、发射区17以及体接触区18之间。体区16被形成在与栅极沟槽30相接的范围内。当栅极沟槽30内的栅极电极32成为导通电位时，在与栅极沟槽30相接的体区16内将形成有通道(channel)。
发射区17为n型区域。发射区17的杂质浓度高于势垒区15的杂质浓度。发射区17被形成于体区16的表面侧。发射区17被形成在与栅极沟槽30相接的范围内。发射区17在露出于半导体基板2的表面50的范围内被形成为岛状。发射区17与表面电极5欧姆接触。发射区17与表面电极5导通。
体接触区18为p型区域。体接触区18的杂质浓度高于体区16的杂质浓度。体接触区18被形成于体区16的表面侧。体接触区18被形成于与发射区17不同的位置处。体接触区18在露出于半导体基板2的表面50的范围内被形成为岛状。体接触区18与表面电极5欧姆接触。体接触区18与表面电极5导通。
二极管区4
阴极区21为n型区域。阴极区21的杂质浓度高于缓冲区12的杂质浓度。阴极区21被形成于缓冲区12的背面侧。阴极区21被形成在露出于半导体基板2的背面60的范围内。阴极区21与背面电极6欧姆接触。阴极区21与背面电极6导通。
缓冲区12为n型区域。缓冲区12被形成于阴极区21的表面侧。缓冲区12被形成于阴极区21与漂移区13之间。漂移区13被形成于缓冲区12与势垒区25之间。缓冲区12与漂移区13以跨及IGBT区3与二极管区4的方式而被形成。
势垒区25为n型区域。势垒区25的杂质浓度高于漂移区13的杂质浓度。势垒区25被形成于漂移区13的表面侧。在缓冲区12与势垒区25之间形成有漂移区13。势垒区25被形成于漂移区13与阳极区23之间。势垒区25的横向(x方向)的端部与栅极沟槽30相接。
阳极区23为p型区域。阳极区23的杂质浓度与体区16的杂质浓度相等。阳极区23被形成于势垒区25的表面侧。阳极区23被形成于势垒区25与阳极接触区24之间。阳极区23被形成在与栅极沟槽30相接的范围内。
阳极接触区24为p型区域。阳极接触区24的杂质浓度高于阳极区23的杂质浓度。阳极接触区24被形成于阳极区23的表面侧。阳极接触区24在露出于半导体基板2的表面50的范围内被形成为岛状。阳极接触区24与表面电极5欧姆接触。阳极接触区24与表面电极5导通。
如图2所示，阳极接触区24被形成为，IGBT区3与二极管区4所并排的方向(x方向)上的宽度随着从半导体基板2的表面50向半导体基板2的深度方向(z方向)远离而减小。阳极接触区24的下端部242的x方向上的宽度与上端部241的x方向上的宽度相比而较窄。
如图3所示，阳极接触区24的杂质浓度沿着半导体基板2的深度方向(z方向)而连续地变化。阳极接触区24的杂质浓度随着从半导体基板2的表面50向半导体基板2的深度方向(z方向)远离而连续地降低。阳极接触区24的下端部242的杂质浓度低于阳极接触区24的上端部241的杂质浓度。但是，阳极接触区24的下端部242的杂质浓度高于阳极接触区24的上端部241的杂质浓度的1/2。
如图1所示，多个栅极沟槽30在x方向上以等间隔的方式而被形成。栅极沟槽30从半导体基板2的表面50向背面60侧(z方向)延伸。在IGBT区3中，栅极沟槽30从半导体基板2的表面50起贯穿发射区17、体区16和势垒区15并延伸至到达漂移区13的深度为止。在二极管区4中，栅极沟槽30从半导体基板2的表面50起贯穿阳极区23和势垒区25并延伸至到达漂移区13的深度为止。在栅极沟槽30的内部形成有栅极电极32与栅极绝缘膜31。
栅极电极32被收纳于栅极沟槽30的内部。栅极电极32被收纳于与栅极绝缘膜31相比靠内侧处。栅极电极32例如由铝(Al)或多晶硅(Poly Si)形成。在栅极电极32之上配置有层间绝缘膜33。层间绝缘膜33使栅极电极32与表面电极5绝缘。
栅极绝缘膜31例如由二氧化硅(SiO2)形成。栅极绝缘膜31覆盖了栅极沟槽30的内表面。栅极绝缘膜31被配置于栅极电极32与半导体基板2之间。栅极绝缘膜31使栅极电极32与半导体基板2绝缘。
柱区20被形成于栅极沟槽30与栅极沟槽30之间。柱区20为n型区域。柱区20的杂质浓度与势垒区15、25的杂质浓度相等。柱区20的杂质浓度高于漂移区13的杂质浓度。在IGBT区3中，柱区20从半导体基板2的表面50起贯穿体接触区18和体区16并延伸至到达势垒区15的位置为止。在二极管区4中，柱区20从半导体基板2的表面50起贯穿阳极接触区24与阳极区23并延伸至到达势垒区25的位置为止。柱区20与表面电极5和势垒区15或25连接。柱区20与表面电极5肖特基接触。柱区20与表面电极5和势垒区15或25导通。
如图2所示，柱区20的一部分与阳极接触区24相接，柱区20的另一部分与阳极区23相接。此外，阳极接触区24的一部分与柱区20接触，阳极接触区24的另一部分与阳极区23接触。阳极接触区24的一部分伸出到柱区20侧，阳极接触区24的另一部分伸出到阳极区23中。阳极接触区24与柱区20的边界面71弯曲。边界面71主要向半导体基板2的深度方向(纵向)延伸。
如图4所示，在对半导体基板2进行俯视观察时存在如下范围，即，柱区20到达半导体基板2的表面50的柱露出范围41、柱区20与阳极接触区24的深部侧相接的柱接触范围42、阳极区23与阳极接触区24的深部侧相接的阳极接触范围43。柱露出范围41、柱接触范围42和阳极接触范围43在多个栅极沟槽30所并排的方向(x方向)上并排。在x方向上，柱露出范围41与柱接触范围42邻接，柱接触范围42与阳极接触范围43邻接。
在对半导体基板2的表面50进行观察时，柱露出范围41被形成于，与柱区20和阳极接触区24的边界b1相比靠柱区20侧处。柱接触范围42被形成于，与柱区20和阳极接触区24的边界b1相比靠阳极接触区24侧处。此外，在对深于半导体基板2的表面50的位置进行观察时，柱接触范围42被形成于，与柱区20和阳极区23的边界b2相比靠柱区20侧处。阳极接触范围43被形成于，与柱区20和阳极区23的边界b2相比靠阳极区23侧处。此外，在对半导体基板2的表面50进行观察时，阳极接触范围43被形成于，与阳极接触区24和阳极区23的边界b3相比靠阳极接触区24侧处。阳极区23、阳极接触区24、柱区20、以及栅极沟槽30在y方向上并行地延伸。
在柱露出范围41、柱接触范围42和阳极接触范围43所并排的方向(x方向)上，柱接触范围42的宽度w42与柱露出范围41的宽度w41相比而较窄。此外，在x方向上，柱接触范围42的宽度w42与阳极接触范围43的宽度w43相比而较窄。在对柱露出范围41的宽度w41、柱接触范围42的宽度w42和阳极接触范围43的宽度w43进行比较时，能够对半导体基板2的表面50和深于表面50的位置的双方进行观察从而进行比较。
此外，如图5所示，柱接触范围42随着从半导体基板2的表面50向半导体基板2的深度方向远离而减少。在柱接触范围42与阳极接触范围43所并排的方向(x方向)上的柱接触范围42的宽度下降。柱接触范围42的下端部422的宽度w422窄于柱接触范围42的上端部421的宽度w421。但是，柱接触范围42的下端部422的宽度w422大于柱接触范围42的上端部421的宽度w421的1/2。
柱区20具备浓度降低范围44。浓度降低范围44被形成在柱区20的上端部处。浓度降低范围44被形成在露出于半导体基板2的表面50的范围内。如图6所示，柱区20的杂质浓度沿着半导体基板2的深度方向(z方向)连续地变化。在浓度降低范围44中，柱区20的杂质浓度随着从半导体基板2的表面50向半导体基板2的深度方向(z方向)远离而连续地降低。柱区20的杂质浓度的峰值的位置存在于与浓度降低范围44相比而较深的位置处。柱区20的杂质浓度的峰值的位置存在于与阳极接触区24的下端部242相比而较深的位置处。
接下来，对具备上述结构的半导体装置的动作进行说明。在使用半导体装置1时，向表面电极5与背面电极6之间施加使背面电极6成为正极的电压(即，相对于IGBT区3的正向电压)。此外，在栅极电极32上施加导通电位(在体区16上形成通道所需的电位以上的电位)。由此，使半导体装置1的IGBT接通。
在半导体装置1的IGBT接通时，在与栅极沟槽30相接的范围的体区16中形成有通道。而且，电子从表面电极5起经由发射区17、体区16中所形成的通道、以及势垒区15而流到漂移区13中。之后，电子经由缓冲区12以及集电区11而流到背面电极6上。此外，空穴从背面电极6起经由集电区11、缓冲区12、漂移区13、势垒区15、体区16、以及体接触区18而流到表面电极5上。
接下来，当将栅极电极32的电位从导通电位切换为断开电位时，体区16中所形成的通道将消失。由此，半导体装置1的IGBT被关断。此外，在表面电极5与背面电极6之间被施加有使表面电极5成为正极的电压(即，相对于二极管区4的正向电压)。由此，半导体装置1的二极管(FWD)接通。当二极管(FWD)接通时，空穴从表面电极5起经由阳极接触区24、阳极区23、势垒区25、漂移区13、缓冲区12、以及阴极区21而流到背面电极6上。此外，电子从背面电极6起经由阴极区21、缓冲区12、漂移区13、势垒区25、阳极区23、以及阳极接触区24而流到表面电极5上。
之后，向表面电极5与背面电极6之间施加使背面电极6成为正极的电压(即，相对于二极管区4的反向电压(相对于IGBT区3的正向电压))。由此，半导体装置1的二极管(FWD)被恢复。当二极管(FWD)被恢复时，被蓄积于半导体基板2的二极管区4中的空穴将被喷出到表面电极5上，而电子则被喷出到背面电极6上。
如根据上述的说明而明确的那样，在上述的半导体装置1中，在对半导体基板2进行俯视观察时存在如下范围，即，柱区20露出于半导体基板2的表面的柱露出范围41、柱区20与阳极接触区24的深部侧相接的柱接触范围42、阳极区23与阳极接触区24的深部侧相接的阳极接触范围43。而且，在柱接触范围42与阳极接触范围43所并排的方向上的柱接触范围42的宽度w42与阳极接触范围的宽度w43相比而较窄。根据这种结构，由于阳极接触区24与柱区20未分离、两者相接，因此能够缩窄用于形成阳极接触区24与柱区20的区域。因此，能够缩窄栅极沟槽30与栅极沟槽30之间的间隔，从而能够使被形成在半导体基板2上的栅极沟槽30的数量增加。因此，能够使半导体基板2的每单位面积的栅极沟槽30的数量增加，从而提高栅极沟槽30的密度。
此外，在上述的半导体装置1中，通过p型的阳极接触区24与n型的柱区20相接从而形成了pn结二极管。在该半导体装置1中，当二极管(FWD)接通(施加了相对于二极管区4的正向电压)时，如上文所述那样，不仅空穴从表面电极5起经由阳极接触区24、阳极区23、势垒区25、漂移区13、缓冲区12、以及阴极区21而流到背面电极6上，而且空穴还从表面电极5起经由阳极接触区24、柱区20、势垒区25、漂移区13、缓冲区12、以及阴极区21而流到背面电极6上。即，当二极管(FWD)接通时，空穴从p型的阳极接触区24流入n型的柱区20。此时，根据上述的结构，柱区20与阳极接触区24的深部侧相接的柱接触范围42的宽度w42和阳极区23与阳极接触区24的深部侧相接的阳极接触范围43的宽度w43相比而较窄。因此，与阳极接触区24和阳极区23的接触范围相比，能够更加抑制阳极接触区24和柱区20的接触范围。由此，能够使从阳极接触区24向柱区20流入的空穴的量与从阳极接触区24向阳极区23流入的空穴的量相比而减少。因此，能够抑制从阳极接触区24向柱区20流入的空穴的量。以上，根据上述的半导体装置1，即使提高了栅极沟槽30的密度，也能够抑制从阳极接触区24向柱区20流入的空穴的量。
其结果为，由于在接通二极管(FWD)时在半导体基板2中并未蓄积有多余的空穴，因此，之后，在对二极管进行恢复时，能够在被蓄积于半导体基板2中的空穴被喷出到表面电极5之前缩短时间。由此，能够使开关速度加快。
此外，在上述的半导体装置1中，当向表面电极5与背面电极6之间施加电压时，将有电压被施加于半导体基板2的深度方向(纵向)上。此时，由于当阳极接触区24与柱区20的边界面71朝向半导体基板2的深度方向(纵向)时，电压的施加方向与边界面71所朝向的方向一致，因此空穴易于从阳极接触区24流入柱区20。但是，根据上述的结构，由于柱接触范围42的下端部422的宽度w422大于柱接触范围42的上端部421的宽度w421的1/2，而使柱接触范围42的下端部422的宽度w422与上端部421的宽度w421之差变小，因此阳极接触区24与柱区20的边界面71的斜度变大，从而使边界面71朝向沿着半导体基板2的表面50的方向(横向)。因此，即使在半导体基板2的深度方向上被施加有电压，由于电压的施加方向与边界面71所朝向的方向不同，因此空穴也不易从阳极接触区24流入柱区20。由此，能够进一步抑制从阳极接触区24向柱区20流入的空穴的量。
此外，在上述的半导体装置1中，阳极接触区24的下端部242中的p型杂质浓度高于阳极接触区24的上端部241中的p型杂质浓度的1/2。由此，由于在阳极接触区24的下端部242与上端部241处杂质浓度之差较小，因此热扩散后的阳极接触区24的下端部242的宽度与上端部241的宽度之差较小。其结果为，由于阳极接触区24与柱区20的边界面71的倾斜度变大，因此，同样地，空穴也不易从阳极接触区24流入柱区20。
此外，在上述的半导体装置1中，柱区20具备浓度降低范围44，在所述浓度降低范围44中，n型杂质浓度随着从半导体基板2的表面50向半导体基板2的深度方向远离而连续地降低。由此，由于半导体基板2的表面50上的柱区20的n型杂质浓度变高，因此能够阻碍在半导体基板2的表面50上与柱区20邻接的阳极接触区24向沿着半导体基板2的表面50的方向扩散的情况。由此，由于阳极接触区24的上端部241不易向沿着半导体基板2的表面50的方向(横向)扩散，因此阳极接触区24的上端部241的宽度与下端部242的宽度之差变得更小。其结果为，由于阳极接触区24与柱区20的边界面71的倾斜度变大，因此，同样地，空穴也不易从阳极接触区24流入柱区20。
虽然以上对一个实施方式进行了说明，但具体的方式并不限定于上述实施方式。在以下的说明中，对于与上述的说明中的结构相同的结构，标记相同的符号并省略说明。
第二实施例
在第二实施例所涉及的半导体装置1中，如图7所示，在被形成于二极管区4中的多个柱区20中，最靠近IGBT区3的柱区201中的柱接触范围42的宽度w42a，与最靠近的柱区201以外的柱区20中的柱接触范围42的宽度w42b相比而较小。即，在二极管区4的多个单元的柱接触范围42中，最靠近IGBT区3的单元中的柱接触范围42的宽度w42a最窄。在IGBT区3与二极管区4所邻接的部分中，在二极管(FWD)接通时，由于有空穴从IGBT区3流入二极管区4，因此空穴容易被蓄积于二极管区4中。但是，根据上述的结构，在最靠近IGBT区3的柱区201中，阳极接触区24与柱区20的接触范围被抑制了。由此，在靠近IGBT区3的二极管区4中，能够抑制从阳极接触区24流入柱区20的空穴的量。其结果为，能够在使靠近IGBT区3的部分中的被存储于半导体基板2的空穴被喷出到表面电极5之前缩短时间，从而使开关速度加快。
第三实施例
此外，虽然在上述实施例中，阳极接触区24仅被形成于阳极区23的表面侧的一部分中，但并不限定于该结构。在第三实施例所涉及的半导体装置1中，如图8所示，阳极接触区24也可以被形成于阳极区23的表面侧的全部区域中。栅极沟槽30贯穿阳极接触区24并在半导体基板2的深度方向上延伸。
其他实施例
此外，形成阳极接触区24与柱区20的方法并未被特别限定。例如，作为半导体装置的制造方法的一个示例，而使阳极接触区24在栅极沟槽30被形成于半导体基板2上之后，形成于半导体基板2上。此外，也使柱区20在栅极沟槽30被形成于半导体基板2上之后，形成于半导体基板2上。
此外，在形成阳极接触区24时，在向半导体基板2注入杂质之后，不通过退火工序来实施热扩散，而是通过对层间绝缘膜33进行回流处理(reflowprocess)时的热来实施热扩散。此外，同样地，在形成柱区20时，在向半导体基板2注入杂质之后，不通过退火工序来实施热扩散，而是通过对层间绝缘膜33进行回流处理时的热来实施热扩散。对层间绝缘膜33进行回流处理时的温度例如为850℃～1050℃。此外，对层间绝缘膜33进行回流处理时的处理时间例如为10分～120分。
此外，阳极区23的杂质浓度的峰值的位置并未被特别限定。在图9所示的示例中，阳极区23的杂质浓度的峰值位于与阳极接触区24的下端部242相比而更深的位置处。为了形成阳极区23而注入了杂质的范围的一部分与为了形成阳极接触区24而注入了杂质的范围的一部分重叠。此外，柱区20的杂质浓度的峰值的位置未被特别限定。
此外，半导体基板2的结构并不限定于上述的实施例。在其他实施例中，如图10所示，也可以在半导体基板2的IGBT区3与二极管区4中形成电场扩展防止区27。电场扩展防止区27为p型区域。电场扩展防止区27的杂质浓度与体区16的杂质浓度相等。此外，电场扩展防止区27的杂质浓度与阳极区23的杂质浓度相等。电场扩展防止区27被形成于漂移区13的表面侧。电场扩展防止区27被形成于势垒区15、25的背面侧。电场扩展防止区27被形成于漂移区13与势垒区15、25之间。
根据图10所示的结构，在接通二极管(FWD)时，电子从背面电极6经由半导体基板2而流到表面电极5上。此时，由于电场扩展防止区27的存在而能够抑制向阳极接触区24流入的电子的量。伴随于此，能够抑制从阳极接触区24向柱区20流入的空穴的量。
虽然以上对本发明的具体示例进行了详细说明，但这些只不过是例示，并非对权利要求进行限定。在权利要求所记载的技术中，包括对上文所例示的具体示例进行了各种变形、变更的内容。本说明书或附图中所说明的技术要素单独或通过各种组合而发挥技术上的有用性，且并不限定于申请时权利要求所记载的组合。此外，本说明书或附图中所例示的技术能够同时实现多个目的，而实现其中的一个目的本身就具有技术上的有用性。
以下对本说明书所公开的技术要素的一个示例进行说明。另外，下文所记载的技术要素为分别独立的技术要素，并且以单独的方式或通过各种组合而发挥技术上的有用性。
1、柱接触范围的宽度随着从半导体基板的表面向半导体基板的深度方向远离而减小。优选为，柱接触范围的下端部的宽度大于柱接触范围的上端部的宽度的1/2。
根据这种结构，由于柱接触范围的下端部的宽度与上端部的宽度之差较小，因此阳极接触区与柱区的边界面的倾斜度较大，从而边界面将朝向沿着半导体基板的表面的方向(横向)。因此，即使在半导体基板的深度方向(纵向)上被施加有电压，由于电压的施加方向与边界面所朝向的方向不同，因此空穴也不易从阳极接触区流入柱区。由此，能够抑制从阳极接触区向柱区流入的空穴的量。
2、阳极接触区的杂质浓度随着从半导体基板的表面向半导体基板的深度方向远离而连续地降低。优选为，阳极接触区的下端部的杂质浓度大于阳极接触区的上端部的杂质浓度的1/2。
根据这种结构，由于阳极接触区的下端部与上端部的杂质浓度之差较小，因此阳极接触区的下端部与上端部的扩散量之差较小。由此，阳极接触区的下端部的宽度与上端部的宽度之差较小。其结果为，阳极接触区与柱区的边界面的倾斜度变大，从而使边界面朝向沿着半导体基板的表面的方向(横向)。因此，与上文所述相同，即使在半导体基板的深度方向(纵向)上被施加有电压，由于电压的施加方向与边界面所朝向的方向不同，因此空穴也不易从阳极接触区流入柱区。因此，能够抑制从阳极接触区向柱区流入的空穴的量。
3、优选为，柱区具备浓度降低范围，在所述浓度降低范围中，杂质浓度随着从半导体基板的表面向半导体基板的深度方向远离而连续地降低。
根据这种结构，由于半导体基板的表面上的柱区的n型杂质浓度较高，因此能够阻碍在半导体基板的表面上与柱区邻接的阳极接触区向沿着半导体基板的表面的方向(横向)扩散的情况。由此，由于阳极接触区的上端部不易向沿着半导体基板的表面的方向(横向)扩散，因此阳极接触区的上端部的宽度与下端部的宽度之差变得更小。其结果为，阳极接触区与柱区的边界面的倾斜度变大，从而使边界面朝向沿着半导体基板的表面的方向(横向)。因此，与上文所述相同，即使在半导体基板的深度方向(纵向)上被施加有电压，由于电压的施加方向与边界面所朝向的方向不同，因此空穴也不易从阳极接触区流入柱区。因此，能够抑制从阳极接触区向柱区流入的空穴的量。
4、优选为，在被形成于二极管区的多个柱区中的、最靠近IGBT区的柱区中的柱接触范围的宽度，与最靠近的柱区以外的柱区中的柱接触范围的宽度相比而较窄。
在靠近IGBT区的部分中，由于有空穴从IGBT区流入二极管区，因此多余的空穴容易被蓄积于半导体基板中。因此，根据上述的结构，能够使从最靠近IGBT区的阳极接触区向柱区流入的空穴的量与除此以外的从阳极接触区向柱区流入的空穴的量相比而得到抑制。
此外，能够在使靠近IGBT区的部分中的、将被蓄积于半导体基板的空穴被喷出到表面电极上之前缩短时间，从而能够使开关速度加快。此外，由于能够抑制流入到靠近IGBT区的部分的空穴的量，因此能够抑制靠近IGBT区的部分的发热。

Claims (5)

1.一种半导体装置，其为在同一半导体基板上形成有绝缘栅双极性晶体管区和二极管区，且在所述半导体基板的表面上形成有表面电极的半导体装置，所述半导体装置的特征在于，
所述绝缘栅双极性晶体管区具备：
n型的漂移区；
n型的势垒区，其被形成于所述漂移区的表面侧；
p型的体区，其被形成于所述势垒区的表面侧；
n型的发射区，其被形成于所述体区的表面侧，且与所述表面电极导通；
p型的体接触区，其被形成于所述体区的表面侧且与所述发射区不同的位置处，并且与所述体区相比杂质浓度较高，且与所述表面电极导通；
多个栅极沟槽，其从所述半导体基板的表面起贯穿所述发射区、所述体区和所述势垒区并延伸至到达所述漂移区的深度为止；
n型的柱区，其在所述栅极沟槽与所述栅极沟槽之间从所述半导体基板的表面起贯穿所述体区并延伸至到达所述势垒区的深度为止，且与所述表面电极和所述势垒区导通；
所述二极管区具备：
n型的漂移区；
n型的势垒区，其被形成于所述漂移区的表面侧；
p型的阳极区，其被形成于所述势垒区的表面侧；
p型的阳极接触区，其被形成于所述阳极区的表面侧的至少一部分上，并且与所述阳极区相比杂质浓度较高，且与所述表面电极导通；
多个栅极沟槽，其从所述半导体基板的表面起至少贯穿所述阳极区和所述势垒区并延伸至到达所述漂移区的深度为止；
n型的柱区，其在所述栅极沟槽与所述栅极沟槽之间从所述半导体基板的表面起贯穿所述阳极接触区与所述阳极区并延伸至到达所述势垒区的深度为止，且与所述表面电极和所述势垒区导通，
在对所述半导体基板进行俯视观察时，存在如下范围，即，所述柱区露出于所述半导体基板的表面的柱露出范围、所述柱区与所述阳极接触区的深部侧相接的柱接触范围、所述阳极区与所述阳极接触区的深部侧相接的阳极接触范围，
在所述柱接触范围与所述阳极接触范围所并排的方向上的所述柱接触范围的宽度与所述阳极接触范围的宽度相比而较窄。
2.如权利要求1所述的半导体装置，其中，
所述柱接触范围的宽度随着从所述半导体基板的表面向所述半导体基板的深度方向远离而减小，
所述柱接触范围的下端部的宽度大于所述柱接触范围的上端部的宽度的二分之一。
3.如权利要求1或2所述的半导体装置，其中，
所述阳极接触区的杂质浓度随着从所述半导体基板的表面向所述半导体基板的深度方向远离而连续地降低，
所述阳极接触区的下端部的杂质浓度高于所述阳极接触区的上端部的杂质浓度的二分之一。
4.如权利要求1所述的半导体装置，其中，
所述柱区具备浓度降低范围，在所述浓度降低范围中，杂质浓度随着从所述半导体基板的表面向所述半导体基板的深度方向远离而连续地降低。
5.如权利要求1所述的半导体装置，其中，
在被形成于所述二极管区的多个所述柱区中的、最靠近所述绝缘栅双极性晶体管区的所述柱区中的所述柱接触范围的宽度，与所述最靠近的柱区以外的柱区中的所述柱接触范围的宽度相比而较窄。
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