WO2014034874A1 - 薄膜トランジスタおよび表示装置 - Google Patents
薄膜トランジスタおよび表示装置 Download PDFInfo
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- WO2014034874A1 WO2014034874A1 PCT/JP2013/073373 JP2013073373W WO2014034874A1 WO 2014034874 A1 WO2014034874 A1 WO 2014034874A1 JP 2013073373 W JP2013073373 W JP 2013073373W WO 2014034874 A1 WO2014034874 A1 WO 2014034874A1
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- oxide semiconductor
- semiconductor layer
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- gate insulating
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13069—Thin film transistor [TFT]
Definitions
- the present invention relates to a thin film transistor (TFT) used in a display device such as a liquid crystal display or an organic EL display, and a display device including the thin film transistor.
- TFT thin film transistor
- Amorphous (amorphous) oxide semiconductors have higher carrier mobility (also referred to as field-effect mobility, hereinafter sometimes referred to simply as “mobility”) compared to general-purpose amorphous silicon (a-Si). Because it has a large optical band gap and can be formed at low temperatures, it is expected to be applied to next-generation displays that require large size, high resolution, and high-speed driving, and resin substrates with low heat resistance (Patent Literature) 1).
- an amorphous oxide semiconductor made of indium, gallium, zinc, and oxygen (In-Ga-Zn-O, hereinafter sometimes referred to as "IGZO") has extremely high carrier mobility. Therefore, it is preferably used.
- IGZO amorphous oxide semiconductor made of indium, gallium, zinc, and oxygen
- TFT thin film transistor
- TFT characteristics transistor characteristics, TFT characteristics.
- the on-current the maximum drain current when a positive voltage is applied to the gate electrode and the drain electrode
- the off-current a negative voltage is applied to the gate electrode and a positive voltage is applied to the drain voltage
- SS value Subthreshold Swing: gate voltage required to increase the drain current by one digit
- threshold voltage positive voltage is applied to the drain electrode
- a TFT using an oxide semiconductor layer such as IGZO is required to have excellent resistance (stress resistance) to stress such as voltage application and light irradiation.
- stress resistance stress resistance
- a voltage is continuously applied to the gate electrode or when a blue band light that is absorbed in the semiconductor layer is irradiated, charges are trapped at the interface between the gate insulating film and the semiconductor layer of the thin film transistor, and the semiconductor layer
- the threshold voltage is greatly changed (shifted) to the negative side due to the change in charge of the TFT, thereby changing the switching characteristics of the TFT. If the switching characteristics change due to stress due to light irradiation or voltage application, the reliability of the display device itself is reduced.
- the threshold voltage shift causes a decrease in the reliability of a display device itself such as a liquid crystal display or an organic EL display equipped with a TFT, so that the stress resistance is improved (the amount of change before and after the stress application is small). Is strongly desired.
- Patent Document 2 As a technique for improving the electrical characteristics of the TFT, for example, Patent Document 2 can be cited.
- Patent Document 2 the hydrogen concentration of an insulating layer (including a gate insulating layer) in contact with an oxide semiconductor layer that forms a channel region is reduced to less than 6 ⁇ 10 20 atoms / cm 3 , and hydrogen into the oxide semiconductor layer is reduced.
- a technique for suppressing the diffusion of the above is disclosed.
- When hydrogen diffuses into the oxide semiconductor layer, carriers in the oxide semiconductor layer become excessive. For this reason, the threshold voltage fluctuates in the negative direction, and no voltage is applied to the gate electrode (Vg Even at 0V, drain current flows (normally on), resulting in a transistor with poor electrical characteristics.
- Patent Document 2 diffusion of hydrogen into the oxide semiconductor layer is suppressed by making the insulating layer in contact with the oxide semiconductor layer an oxide insulating layer with reduced hydrogen concentration. It is described that the electric characteristics of the transistor are improved because oxygen is supplied to the defect from the insulating layer. Patent Document 2 describes that the hydrogen concentration in the insulating layer for exhibiting such an effect needs to be reduced to less than 6 ⁇ 10 20 atoms / cm 3 . Further, when such an insulating layer with reduced hydrogen concentration is formed by a plasma CVD method, a gas that does not contain hydrogen in the molecular structure is selected and used as the deposition gas (that is, with the commonly used SiH 4) . It is also described that it is essential to use SiF 4 instead. However, Patent Document 2 does not give any attention to improvement of stress tolerance (particularly, reduction of threshold voltage change due to light or bias stress).
- the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a thin film transistor including an oxide semiconductor layer thin film with a small amount of change in threshold voltage with respect to light and bias stress, and excellent stress resistance. Another object of the present invention is to provide a thin film transistor and a display device including the thin film transistor.
- the thin film transistor of the present invention that has solved the above problems includes a gate electrode, a single oxide semiconductor layer used for a channel layer, an etch stopper layer for protecting the surface of the oxide semiconductor layer, a source A thin film transistor including a drain electrode and a gate insulating film disposed between the gate electrode and the channel layer, wherein the metal element constituting the oxide semiconductor layer is composed of In, Zn, and Sn
- the hydrogen concentration in the gate insulating film that is in direct contact with the oxide semiconductor layer is controlled to 4 atomic% or less.
- the gate insulating film has a single layer structure or a stacked structure of two or more layers.
- hydrogen in a layer in direct contact with the oxide semiconductor layer is used.
- the concentration is controlled to 4 atomic% or less.
- the oxide semiconductor layer has a content (atomic%) of each metal element with respect to all metal elements excluding oxygen as [In], [Zn], and [Sn], respectively.
- the present invention includes a display device including any of the thin film transistors described above.
- the hydrogen concentration in the gate insulating film in direct contact with the oxide semiconductor layer is reduced to an appropriate range, the switching characteristics and the stress resistance are excellent (specifically, before and after applying a negative bias).
- the threshold voltage shift amount is small, and the threshold voltage shift amount before and after light irradiation and negative bias application is small.)
- a thin film transistor can be provided.
- a highly reliable display device can be obtained by using the thin film transistor of the present invention.
- FIG. 1 is a schematic cross-sectional view for explaining a thin film transistor of the present invention.
- the inventors of the present invention have developed a stress resistance (before and after negative bias application and threshold voltage before and after light irradiation and negative bias application) when an oxide semiconductor layer composed of a predetermined metal element is used as an active layer of a TFT.
- a stress resistance before and after negative bias application and threshold voltage before and after light irradiation and negative bias application
- studies have been made repeatedly.
- the intended purpose is achieved if the hydrogen concentration in the gate insulating film in direct contact with the oxide semiconductor layer is reduced within an appropriate range.
- such a gate insulating film has at least conditions for forming a gate insulating film in direct contact with the oxide semiconductor layer by a plasma CVD method (for example, temperature, film formation power density, and deposition gas against N 2 O.
- a plasma CVD method for example, temperature, film formation power density, and deposition gas against N 2 O.
- the present inventors have found that the flow rate ratio of SiH 4 can be appropriately controlled, and the present invention has been completed.
- the thin film transistor of the present invention includes a gate electrode, a single oxide semiconductor layer used for a channel layer, an etch stopper layer for protecting the surface of the oxide semiconductor layer, and a source / drain electrode (“S / A thin film transistor including a gate insulating film disposed between the gate electrode and the channel layer, and a metal element constituting the oxide semiconductor layer includes In, It is characterized in that it is composed of Zn and Sn and the hydrogen concentration in the gate insulating film in direct contact with the oxide semiconductor layer is controlled to 4 atomic% or less.
- [In], [Zn], and [Sn] are the contents (atomic%) of In, Zn, and Sn with respect to all metal elements (In, Zn, and Sn) excluding oxygen (O). means.
- excellent stress resistance means (a) a stress application test (NBTS) in which a negative bias is applied to the gate electrode, and (b) white light on the sample.
- NBTS stress application test
- LNBTS stress application test
- the shift amount ⁇ Vth (absolute value) of the threshold voltage (Vth) before and after the stress application test is less than 5.0 V.
- the shift amount ⁇ Vth (absolute value) is less than 5.0 V
- the SS value is less than 0.55 V / decade
- the change amount ⁇ Ion (absolute value) of the on-current (Ion) before and after the stress application test is less than 10%.
- Patent Document 2 a technique for improving the electrical characteristics by reducing the hydrogen concentration in the gate insulating layer is disclosed, but differs from the present invention in the following points.
- Patent Document 2 describes the threshold voltage.
- NBTS negative bias stress resistance
- LNBTS negative bias + light irradiation stress resistance
- the range of the hydrogen concentration in the gate insulating layer is also different. This is because the film forming methods for obtaining the gate insulating layer are different (details will be described later). That is, as described above, in Patent Document 2, the gate insulating layer is selected by using SiF 4 that is not normally used as the deposition gas, without using SiH 4 that is normally used for forming the gate insulating layer.
- the present invention is based on the premise that SiH 4 which is usually used for film formation of the gate insulating layer is used, and gate insulation is achieved by appropriately controlling the gas flow ratio, temperature, film formation power density, and the like.
- the hydrogen concentration in the layer is reduced to 4 atomic% or less. If the amount of hydrogen is extremely reduced as in Patent Document 2, the film formation temperature at the time of forming the gate insulating layer becomes too high, the input power becomes too high, or the film formation rate becomes extremely slow. The tact time increases and is not appropriate. Therefore, from the viewpoint of practical use, it is desirable that the lower limit of the hydrogen concentration in the gate insulating layer in the present invention exceeds the upper limit (less than 0.667 atomic%) of Patent Document 2 (0.667 atomic% or more). .
- FIG. 1 is a schematic cross-sectional view for explaining a preferred embodiment of a TFT according to the present invention, and the present invention is not limited to this.
- FIG. 1 illustrates a bottom-gate TFT, but the invention is not limited to this.
- a top-gate TFT including a gate insulating film and a gate electrode on an oxide semiconductor layer in this order from the substrate side.
- a TFT may be used.
- a gate electrode 2 and a gate insulating film 3 are sequentially formed on a substrate 1, and an oxide semiconductor layer 4 is formed on the gate insulating film 3.
- a source / drain electrode 5 is formed on the oxide semiconductor layer 4, a protective film (insulating film) 6 is formed thereon, and the transparent conductive film 8 is electrically connected to the drain electrode 5 through the contact hole 7. It is connected.
- An etch stopper layer 9 for protecting the surface of the oxide semiconductor layer 4 is formed on the oxide semiconductor layer 4.
- substrate 1 used for this invention is normally used in the field
- the gate electrode 2 is formed on the substrate 1.
- the type of the gate electrode 2 is not particularly limited, and those commonly used in the technical field of the present invention can be used. Specifically, metals such as Al and Cu having a low electrical resistivity, refractory metals such as Mo, Cr, and Ti having high heat resistance, and alloys thereof can be preferably used.
- the method for forming the gate electrode 2 is not particularly limited, and a commonly used method can be employed.
- the gate insulating film 3 is formed.
- the gate insulating film 3 is disposed between the gate electrode 2 and the oxide semiconductor layer 4 used as a channel layer.
- the present invention is characterized in that the hydrogen concentration in the gate insulating film 3 in direct contact with the oxide semiconductor layer is controlled to 4 atomic% or less. According to the experimental results of the present inventors, the resistance to bias stress and light + negative bias stress is remarkably improved by controlling the amount of hydrogen in the gate insulating film 3 in contact with the oxide semiconductor layer 4 at the interface. (See Examples below).
- the gate insulating film 3 may be composed of a single layer or may be composed of two or more layers.
- the number of layers in the laminated structure is not particularly limited, but in consideration of productivity, workability, and the like, it is preferable that the layers are generally laminated in three or less layers.
- the hydrogen concentration in the layer in direct contact with the oxide semiconductor layer 4 may be controlled to 4 atomic% or less, and the hydrogen concentration in the layer not in direct contact is not particularly limited. .
- the hydrogen concentration in the gate insulating film 3 is preferably as small as possible, preferably 3.5 atomic percent or less, more preferably 3 atomic percent or less.
- the lower limit of the hydrogen concentration in the gate insulating film 3 is not particularly limited from the viewpoint of the above characteristics, the upper limit (less than 0.667 atomic%) of Patent Document 2 is considered in consideration of the film forming method of the gate insulating film 3 described later. ) Is preferably exceeded (0.667 atomic% or more).
- the hydrogen concentration in the gate insulating film can be reduced to a predetermined range by appropriately controlling the film forming conditions in the plasma CVD method.
- the temperature during film formation it is preferable to first control the temperature during film formation to approximately 250 ° C. or higher.
- the hydrogen concentration cannot be sufficiently reduced, and the stress resistance is lowered. This is presumably because the density of the film formed decreases as the film formation temperature decreases, and the Si—H bonds in the SiO 2 film increase.
- a more preferable film forming temperature is 270 ° C. or higher, and further preferably 300 ° C. or higher.
- the upper limit is preferably controlled to about 450 ° C. or less in consideration of the upper limit temperature of the apparatus to be used.
- the power density during film formation is approximately 0.6 W / cm 2 or more.
- the hydrogen concentration cannot be sufficiently reduced, and the stress resistance is lowered. This is presumably because if the film formation power density is too low, the film density decreases and Si—H bonds are incorporated into the film.
- a more preferable film forming power density is 0.66 W / cm 2 or more, and more preferably 0.7 W / cm 2 or more.
- the gas in the film formation to minimize the SiH 4 relative to N 2 O, i.e., it is preferable to flow ratio represented by SiH 4 / N 2 O (volume ratio) is constant below.
- this flow rate ratio is high, the film density of SiO 2 is reduced and it is considered that many Si—H bonds are contained.
- the film forming conditions other than the above are not particularly limited, and generally used conditions can be adopted.
- the gas pressure is preferably controlled to about 50 to 300 Pa as a gas pressure that stabilizes the discharge.
- the gate insulating film 3 formed by the above method is mainly a silicon oxide film (SiO 2 ), but may contain Si—N bonds as long as the hydrogen content in the film does not increase.
- a silicon oxide film (SiO x ) typified by SiO 2 is dense and exhibits good insulating properties, but has a drawback that the film forming speed is slow. Therefore, by forming the gate insulating film 3 by laminating a SiN x film and a SiO x film, which have a relatively high deposition rate, it is possible to achieve both insulation characteristics and productivity.
- the thickness of the SiN x film is preferably 50 times or less, more preferably 25 times or less with respect to the thickness of the SiO x film.
- the oxide semiconductor layer 4 is formed on the gate insulating film 3.
- the oxide semiconductor layer 4 is usually sandwiched between the gate insulating film 3 and source / drain electrodes (S / D electrodes) 5.
- In has the effect of increasing mobility by increasing the number of carriers.
- the number of carriers increases so that it becomes a conductor and the stability against stress decreases.
- Sn has an effect of improving chemical resistance of the oxide semiconductor layer, such as wet etching. However, when the amount of Sn increases, the etching processability decreases.
- Zn is thought to contribute to the stabilization of the amorphous structure and contributes to the improvement of stability against stress. However, when the Zn content is increased, the oxide semiconductor thin film is crystallized or a residue is generated during etching.
- the oxide semiconductor layer 4 is a single layer.
- a preferable metal ratio of each metal atom constituting the oxide semiconductor layer 4 [a preferable content (atomic%) of each metal element with respect to all metal elements excluding oxygen] is appropriately set so that good TFT characteristics and the like can be obtained. It is preferable to control appropriately.
- the metal ratio of the oxide semiconductor layer 4 is set such that the content (atomic%) of each metal element with respect to all metal elements excluding oxygen is [In], [Zn], and [Sn]. It is preferable that the following relationship is satisfied. Thereby, it becomes possible to effectively exhibit the preferable action of each element described above. 15 ⁇ [In] ⁇ 35 (more preferably, 15 ⁇ [In] ⁇ 25) 50 ⁇ [Zn] ⁇ 60 15 ⁇ [Sn] ⁇ 30
- the preferable film thickness of the oxide semiconductor layer 4 is generally 10 nm or more and 200 nm or less.
- the oxide semiconductor layer 4 is preferably formed by a DC sputtering method or an RF sputtering method using a sputtering target having the same composition as the thin film.
- the film may be formed by a co-sputtering method using a plurality of types of sputtering targets.
- the oxide semiconductor layer 4 is subjected to wet etching and then patterned. Immediately after the patterning, for example, the conditions of temperature: 250 to 350 ° C. (preferably 300 to 350 ° C.) and time: 15 to 120 minutes (preferably 60 to 120 minutes) for improving the film quality of the oxide semiconductor layer 4 Heat treatment (pre-annealing) may be performed. As a result, the on-state current and the field effect mobility of the transistor characteristics are increased, and the transistor performance is improved.
- an etch stopper layer 9 is formed to protect the surface of the oxide semiconductor layer 4.
- the etch stopper layer 9 is damaged by the etching of the oxide semiconductor layer 4, and defects are generated on the surface of the oxide semiconductor layer 4. It is formed for the purpose of preventing the characteristics from deteriorating.
- the type of the etch stopper layer 9 is not particularly limited, and examples thereof include an insulating film such as SiO 2 .
- the etch stopper layer 9 is formed and patterned by a plasma CVD method or the like, and is formed so as to protect the channel surface.
- patterning for electrode formation is performed by performing photolithography and dry etching.
- source / drain electrodes 5 are formed.
- the kind of the source / drain electrode 5 used in the present invention is not particularly limited, and a commonly used one can be used.
- a metal or alloy such as Al, Mo, or Cu may be used, or pure Mo may be used as in the examples described later.
- a metal thin film can be formed by magnetron sputtering, and then patterned by photolithography, and wet etching can be performed to form an electrode.
- Another method for forming the source / drain electrode 5 is, for example, a method in which a metal thin film is formed by a magnetron sputtering method and then formed by a lift-off method. According to this method, it is also possible to process the electrode without performing wet etching.
- a protective film (insulating film) 6 is formed over the oxide semiconductor layer 4.
- the protective film 6 can be formed by, for example, a CVD method. Note that the surface of the oxide semiconductor layer 4 easily becomes a conductor due to plasma damage caused by CVD (probably because oxygen vacancies generated on the surface of the oxide semiconductor become electron donors), and thus the protective film.
- N 2 O plasma irradiation may be performed before film formation of 6. The conditions described in the following document can be adopted as the irradiation conditions of N 2 O plasma. J. et al. Park et al., Appl. Phys. Lett. , 93, 053505 (2008).
- a transparent conductive film 8 is formed.
- the kind of the transparent conductive film 8 is not particularly limited, and commonly used ones such as ITO can be used.
- the present invention includes a display device provided with the TFT.
- Examples of the display device include a liquid crystal display and an organic EL display.
- Example 1 The TFT shown in FIG. 1 was fabricated as follows, and stress resistance and the like were evaluated. However, in this embodiment, the transparent conductive film 8 of FIG. 1 is not formed.
- a 100 nm Mo thin film as a gate electrode 2 and a 250 nm SiO 2 film as a gate insulating film 3 are sequentially formed on a glass substrate 1 (Corning “Eagle 2000”, diameter 100 mm ⁇ thickness 0.7 mm). Filmed.
- the gate electrode 2 was formed by a DC sputtering method using a pure Mo sputtering target. The sputtering conditions were film formation temperature: room temperature, film formation power density: 3.8 W / cm 2 , carrier gas: Ar, gas pressure during film formation: 2 mTorr, and Ar gas flow rate: 20 sccm.
- the gate insulating film 3 was formed using a plasma CVD method using a mixed gas of carrier gas: SiH 4 and N 2 O. Specifically, in this embodiment, an 8-inch circular electrode (area 314 cm 2 ) is used as an electrode of the CVD apparatus, and the temperature, power, and flow rate ratio (volume ratio) of the above gas are shown in Table 1. As a result, a single-layer gate insulating film 3 was formed. The gas pressure was 133 Pa (constant) (not shown in the table).
- an oxide semiconductor layer (film thickness: 40 nm) having the composition shown in Table 1 was formed by a sputtering method under the following conditions using a sputtering target adjusted so that the oxide thin film could be formed.
- Sputtering equipment “CS-200” manufactured by ULVAC, Inc.
- Oxygen partial pressure: 100 ⁇ O 2 / (Ar + O 2 ) 4% by volume
- Each content of the metal element in the oxide semiconductor layer thus obtained was analyzed by an XPS (X-ray Photoelectron Spectroscopy) method. Specifically, after sputtering the range from the outermost surface to a depth of about 5 nm with Ar ions, analysis was performed under the following conditions. Note that the oxide thin film measured by the XPS method was a sample in which a thin film having the same composition as that described above was formed to 40 nm on a Si substrate.
- the oxide semiconductor layer 4 After forming the oxide semiconductor layer 4 as described above, patterning was performed by photolithography and wet etching.
- the wet etchant “ITO-07N” manufactured by Kanto Chemical Co., Ltd., which is an oxalic acid-based wet etching solution for oxide semiconductors, was used.
- a pre-annealing process was performed in order to improve the film quality of the oxide semiconductor layer.
- the pre-annealing process was performed at 350 ° C. for 60 minutes in water vapor at atmospheric pressure.
- an etch stopper layer 9 (thickness: 100 nm) made of SiO 2 was formed.
- the film was formed using a plasma CVD method using “PD-220NL” manufactured by Samco.
- a mixed gas of N 2 O and SiH 4 diluted with nitrogen was used as a carrier gas, and the film was formed under the following conditions.
- source / drain electrodes 5 were formed by DC sputtering using pure Mo. Specifically, in the same manner as the gate electrode described above, a Mo thin film for source / drain electrodes was formed (film thickness was 100 nm), and then the source / drain electrodes were patterned by photolithography.
- a protective film 6 was formed to protect the oxide semiconductor layer 4.
- a laminated film (total film thickness 250 nm) of SiO 2 (film thickness 100 nm) and SiN (film thickness 150 nm) was used.
- the formation of the SiO 2 and SiN was performed using “PD-220NL” manufactured by Samco and using the plasma CVD method.
- an SiO 2 film and an SiN film were formed sequentially.
- a mixed gas of N 2 O and SiH 4 was used for forming the SiO 2 film, and a mixed gas of SiH 4 , N 2 , and NH 3 was used for forming the SiN film.
- the film formation power density was 0.32 W / cm 2 and the film formation temperature was 150 ° C.
- contact holes for probing for transistor characteristic evaluation were formed in the protective film 6 by photolithography and dry etching, and the TFT of FIG. 1 was obtained.
- the stress resistance of each TFT obtained in this way was evaluated as follows.
- NBTS stress tolerance
- the fluctuation value of the threshold voltage when stress was applied for 2 hours was defined as a threshold voltage shift amount ⁇ Vth, and NBTS with ⁇ Vth ⁇ 5.0V was accepted.
- the threshold voltage shift amount ⁇ Vth when the stress was applied for 2 hours was defined as a threshold voltage shift amount ⁇ Vth, and the LNBTS with ⁇ Vth ⁇ 5.0 V was accepted.
- the SS value is the minimum value of the gate voltage required to increase the drain current by one digit.
- the SS value when the stress test (LNBTS) of (2) above was performed was measured, and the SS value ⁇ 0.55 V / decade was accepted.
- the on-current ( ⁇ Ion) is a drain current with a gate voltage of 30 V and a current value when the transistor is in an on state.
- the on-currents before and after the stress test (LNBTS) in (2) above were measured, respectively, and before and after the stress test, the change ⁇ Ion (absolute value) of less than 10% passed (A), 10 % Or more were regarded as rejected (B).
- the gas flow ratio (volume ratio) in each table is the ratio of SiH 4 when N 2 O is 100.
- Table 1 shows the results when IZTO is used as the oxide semiconductor layer and the ratio of each metal element and the film formation conditions (temperature, film formation power density, gas flow ratio) of the gate insulating film are changed. Yes.
- the temperature at which the gate insulating film was formed was 250 ° C. or higher
- the film formation power density was 0.7 W / cm 2 or more
- the gas flow ratio (SiH 4 / N 2 O) was controlled to 0.04 or less.
- 1 to 4, 6, 10 to 13, 15, 18 to 21, and 25 to 28 all have good characteristics under any stress test because the hydrogen concentration in the gate insulating film is reduced to a predetermined range. was gotten.
- these mobilities were all as high as 6 cm 2 / Vs or higher (mobility results are not shown in the table).
- Example 2 The TFT shown in FIG. 1 (the gate insulating film 3 has two layers) was produced as follows, and stress resistance and the like were evaluated. However, in this embodiment, the transparent conductive film 8 of FIG. 1 is not formed.
- a 100 nm Mo thin film was formed on the glass substrate 1 as the gate electrode 2.
- a SiN film is first formed as a lower gate electrode side gate insulating film 3, and then an SiO 2 film is formed thereon as an upper oxide semiconductor layer side gate insulating film 3.
- Both the lower and upper gate insulating films 3 were formed using a plasma CVD method and using an 8-inch circular electrode (area 314 cm 2 ) as an electrode of the CVD apparatus.
- a mixed gas of carrier gas: SiH 4 , N 2, and NH 3 is used, SiH 4 / N 2 gas flow rate: 304 sccm, NH 3 gas flow rate: 100 sccm, N 2
- the film was formed at a gas flow rate of 48 sccm and a film formation power density of 100 W (0.32 W / cm 2 ).
- a mixed gas of carrier gas: SiH 4 and N 2 O is used, and SiH 4 / N 2 gas (a gas obtained by diluting SiH 4 gas to 10% by volume with N 2 gas).
- Flow rate 22 sccm (SiH 4 gas flow rate is 2 sccm), N 2 O gas flow rate: 100 sccm, and deposition power density: 300 W (0.96 W / cm 2 ).
- the temperature was set to 320 ° C. (constant) and the gas pressure was set to 200 Pa (constant) during film formation for both the lower layer and the upper layer.
- Table 2 shows the hydrogen amount and film thickness in the formed gate insulating film.
- an oxide semiconductor layer (film thickness: 40 nm) having the composition shown in Table 2 is formed on the upper gate insulating film 3 using a sputtering target adjusted so that the oxide thin film can be formed.
- a film was formed by a sputtering method.
- Sputtering equipment “CS-200” manufactured by ULVAC, Inc.
- Substrate temperature room temperature
- Oxygen partial pressure: 100 ⁇ O 2 / (Ar + O 2 ) 4% by volume
- Deposition power density 2.55 W / cm 2
- oxide semiconductor layer 4 is formed as described above, patterning is performed by photolithography and wet etching in the same manner as in Example 1, and then a pre-annealing process is performed to improve the film quality of the oxide semiconductor layer. went.
- an etch stopper layer 9 (thickness: 100 nm) made of SiO 2 is formed, and then the etch stopper layer 9 formed is formed. Then, in order to make contact between the oxide semiconductor layer 4 and the source / drain electrodes 5, after performing photolithography, patterning for electrode formation was performed by reactive ion etching (RIE).
- RIE reactive ion etching
- Example 2 In the same manner as in Example 1, pure Mo was used, the source / drain electrodes 5 were formed by DC sputtering, and then the protective film 6 was formed to protect the oxide semiconductor layer 4.
- Table 2 shows the results when the gate insulating film 3 is composed of two layers, a SiN film layer and a SiO 2 film layer, and the ratio between the two layers is changed.
- the SiO 2 film is dense and exhibits good characteristics, while the deposition rate is slow and the productivity tends to be impaired.
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Abstract
Description
15≦[In]≦35、50≦[Zn]≦60、15≦[Sn]≦30
を満足するものである。
(ア)NBTSについて、ストレス印加試験前後のしきい値電圧(Vth)のシフト量ΔVth(絶対値)が5.0V未満
(イ)LNBTSについて、ストレス印加試験前後のしきい値電圧(Vth)のシフト量ΔVth(絶対値)が5.0V未満、SS値が0.55V/decade未満、且つストレス印加試験前後のオン電流(Ion)の変化量ΔIon(絶対値)が10%未満
例えば、SiO2に代表されるシリコン酸化膜(SiOx)は緻密で良好な絶縁特性を発現するものの、成膜速度が遅いという欠点がある。そこで、比較的成膜速度が速いSiNx膜とSiOx膜とを積層してゲート絶縁膜3を構成することにより、絶縁特性と生産性の両立を図ることが可能になる。この場合、絶縁特性を確保するためには、SiNx膜の厚みは、SiOx膜の厚みに対して50倍以下が好ましく、25倍以下がより好ましい。
酸化物半導体層4を構成する各金属原子の好ましいメタル比[酸素を除く全金属元素に対する各金属元素の好ましい含有量(原子%)]は、良好なTFT特性などが得られるように、適宜、適切に制御することが好ましい。
15≦[In]≦35(より好ましくは、15≦[In]≦25)
50≦[Zn]≦60
15≦[Sn]≦30
J.Parkら、Appl.Phys.Lett.,93,053505(2008)。
図1に示すTFTを以下のようにして作製し、ストレス耐性などを評価した。但し、本実施例では、図1の透明導電膜8は成膜していない。
ゲート電極2は純Moのスパッタリングターゲットを使用し、DCスパッタ法により形成した。スパッタリング条件は、成膜温度:室温、成膜パワー密度:3.8W/cm2、キャリアガス:Ar、成膜時のガス圧:2mTorr、Arガス流量:20sccmとした。
スパッタリング装置:株式会社アルバック製「CS-200」
基板温度:室温
ガス圧:1mTorr
酸素分圧:100×O2/(Ar+O2)=4体積%
成膜パワー密度:2.55W/cm2
X線源:Al Kα
X線出力:350W
光電子取り出し角:20°
成膜温度:230℃
ガス圧:133Pa
成膜パワー密度:1.1W/cm2
SiH4/N2Oの流量比(体積比):0.04
本実施例では、ゲート電極に負バイアスをかけるストレス印加試験を行った。ストレス印加条件は以下のとおりである。
・ソース電圧:0V
・ドレイン電圧:10V
・ゲート電圧:-20V
・基板温度:60℃
・ストレス印加時間:2時間
本実施例では、実際の液晶パネル駆動時の環境(ストレス)を模擬して、試料に光(白色光)を照射しながら、ゲート電極に負バイアスをかけ続けるストレス印加試験を行った。ストレス印加条件は以下のとおりである。光源は、液晶ディスプレイのバックライトを模擬して白色LEDを使用した。
・ソース電圧:0V
・ドレイン電圧:10V
・ゲート電圧:-20V
・基板温度:60℃
・ストレス印加時間:2時間
・光源:白色LED(PHILIPS社製LED LXHL-PW01)25000nit
SS値は、ドレイン電流を一桁増加させるのに必要なゲート電圧の最小値である。本実施例では、上記(2)のストレス試験(LNBTS)を行なったときのSS値を測定し、SS値<0.55V/decadeのものを合格とした。
オン電流(ΔIon)とは、ゲート電圧が30Vのドレイン電流で、トランジスタがオン状態のときの電流値である。本実施例では、上記(2)のストレス試験(LNBTS)前後のオン電流をそれぞれ測定し、ストレス試験前後で、その変化量ΔIon(絶対値)が10%未満のものを合格(A)、10%以上のものを不合格(B)とした。
図1に示すTFT(ゲート絶縁膜3は二層)を以下のようにして作製し、ストレス耐性などを評価した。但し、本実施例では、図1の透明導電膜8は成膜していない。
このゲート電極2の上に、まず下層のゲート電極側ゲート絶縁膜3としてSiN膜を成膜し、次いで、その上に上層の酸化物半導体層側ゲート絶縁膜3としてSiO2膜を成膜した。
下層および上層のゲート絶縁膜3はいずれも、プラズマCVD法を用い、CVD装置の電極として8インチの円形電極(面積314cm2)を用いて成膜した。詳しくは、下層のゲート絶縁膜3の形成においては、キャリアガス:SiH4とN2とNH3の混合ガスを用い、SiH4/N2ガス流量:304sccm、NH3ガス流量:100sccm、N2ガス流量:48sccmとし、成膜パワー密度:100W(0.32W/cm2)で成膜した。一方、上層のゲート絶縁膜3の形成においては、キャリアガス:SiH4とN2Oの混合ガスを用い、SiH4/N2ガス(SiH4ガスをN2ガスで10体積%に希釈したガス)流量:22sccm(SiH4ガスの流量は2sccm)、N2Oガス流量:100sccmとし、成膜パワー密度:300W(0.96W/cm2)で成膜した。下層および上層のいずれの成膜時にも、温度は320℃(一定)、ガス圧は200Pa(一定)とした。形成されたゲート絶縁膜中の水素量および膜厚は表2に示す。
スパッタリング装置:株式会社アルバック製「CS-200」
基板温度:室温
ガス圧:1mTorr
酸素分圧:100×O2/(Ar+O2)=4体積%
成膜パワー密度:2.55W/cm2
2 ゲート電極
3 ゲート絶縁膜
4 酸化物半導体層
5 ソース・ドレイン電極
6 保護膜(絶縁膜)
7 コンタクトホール
8 透明導電膜
9 エッチストッパー層
Claims (4)
- ゲート電極と、チャネル層に用いられる単層の酸化物半導体層と、酸化物半導体層の表面を保護するためのエッチストッパー層と、ソース・ドレイン電極と、ゲート電極とチャネル層との間に配置されるゲート絶縁膜とを備えた薄膜トランジスタであって、
前記酸化物半導体層を構成する金属元素は、In、Zn、およびSnで構成されると共に、
前記酸化物半導体層と直接接触する前記ゲート絶縁膜中の水素濃度は4原子%以下に制御されたものであることを特徴とする薄膜トランジスタ。 - 前記ゲート絶縁膜は、単層構造、または二層以上の積層構造を有し、
前記積層構造を有する場合は、前記酸化物半導体層と直接接触する層中の水素濃度が4原子%以下に制御されたものである請求項1に記載の薄膜トランジスタ。 - 前記酸化物半導体層は、酸素を除く全金属元素に対する各金属元素の含有量(原子%)をそれぞれ、[In]、[Zn]、および[Sn]としたとき、
15≦[In]≦35、50≦[Zn]≦60、15≦[Sn]≦30
の関係を満足するものである請求項1に記載の薄膜トランジスタ。 - 請求項1~3のいずれかに記載の薄膜トランジスタを備えた表示装置。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105679832A (zh) * | 2014-12-05 | 2016-06-15 | 三星显示有限公司 | 薄膜晶体管基板及其制造方法 |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5972065B2 (ja) * | 2012-06-20 | 2016-08-17 | 富士フイルム株式会社 | 薄膜トランジスタの製造方法 |
JP2014175503A (ja) * | 2013-03-08 | 2014-09-22 | Kobe Steel Ltd | 薄膜トランジスタの半導体層用酸化物、薄膜トランジスタおよび表示装置 |
KR101919212B1 (ko) | 2014-01-15 | 2018-11-15 | 가부시키가이샤 고베 세이코쇼 | 박막 트랜지스터 |
CN104167449B (zh) * | 2014-08-05 | 2017-09-22 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制备方法、阵列基板和显示装置 |
TWI577032B (zh) * | 2015-04-24 | 2017-04-01 | 群創光電股份有限公司 | 顯示裝置 |
KR102627305B1 (ko) * | 2016-12-30 | 2024-01-18 | 한양대학교 산학협력단 | 박막 트랜지스터 기판 및 표시 장치 |
TWI648844B (zh) | 2017-11-06 | 2019-01-21 | Industrial Technology Research Institute | 薄膜電晶體及其製造方法 |
JP7384777B2 (ja) * | 2019-12-16 | 2023-11-21 | 株式会社神戸製鋼所 | 酸化物半導体薄膜、薄膜トランジスタ及びスパッタリングターゲット |
US11695073B2 (en) | 2020-05-29 | 2023-07-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array gate structures |
DE102021101243A1 (de) * | 2020-05-29 | 2021-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Speicherblock-kanalregionen |
US11710790B2 (en) | 2020-05-29 | 2023-07-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory array channel regions |
US11729987B2 (en) | 2020-06-30 | 2023-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory array source/drain electrode structures |
US11640974B2 (en) | 2020-06-30 | 2023-05-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array isolation structures |
CN115863175A (zh) * | 2022-12-30 | 2023-03-28 | 西湖大学 | 氧化物半导体薄膜及其制备方法、薄膜晶体管、显示器件 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011146692A (ja) * | 2009-12-17 | 2011-07-28 | Semiconductor Energy Lab Co Ltd | 半導体装置、測定装置、比誘電率の測定方法 |
JP2012033913A (ja) * | 2010-07-01 | 2012-02-16 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2012151443A (ja) * | 2011-01-19 | 2012-08-09 | Samsung Electronics Co Ltd | 薄膜トランジスター表示板およびその製造方法 |
JP2012164963A (ja) * | 2010-11-26 | 2012-08-30 | Kobe Steel Ltd | 薄膜トランジスタの半導体層用酸化物およびスパッタリングターゲット、並びに薄膜トランジスタ |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101902048B1 (ko) | 2001-07-17 | 2018-09-27 | 이데미쓰 고산 가부시키가이샤 | 스퍼터링 타겟 및 투명 도전막 |
WO2007026783A1 (ja) | 2005-09-01 | 2007-03-08 | Idemitsu Kosan Co., Ltd. | スパッタリングターゲット、透明導電膜及び透明電極 |
JP4933756B2 (ja) | 2005-09-01 | 2012-05-16 | 出光興産株式会社 | スパッタリングターゲット |
CN101268211B (zh) | 2005-09-20 | 2011-04-13 | 出光兴产株式会社 | 溅射靶、透明导电膜及透明电极 |
JP5188182B2 (ja) | 2005-09-27 | 2013-04-24 | 出光興産株式会社 | スパッタリングターゲット、透明導電膜及びタッチパネル用透明電極 |
JP5358891B2 (ja) | 2006-08-11 | 2013-12-04 | 日立金属株式会社 | 酸化亜鉛焼結体の製造方法 |
JP5305630B2 (ja) * | 2006-12-05 | 2013-10-02 | キヤノン株式会社 | ボトムゲート型薄膜トランジスタの製造方法及び表示装置の製造方法 |
JP5244331B2 (ja) | 2007-03-26 | 2013-07-24 | 出光興産株式会社 | 非晶質酸化物半導体薄膜、その製造方法、薄膜トランジスタの製造方法、電界効果型トランジスタ、発光装置、表示装置及びスパッタリングターゲット |
JP5213458B2 (ja) | 2008-01-08 | 2013-06-19 | キヤノン株式会社 | アモルファス酸化物及び電界効果型トランジスタ |
JP5467728B2 (ja) * | 2008-03-14 | 2014-04-09 | 富士フイルム株式会社 | 薄膜電界効果型トランジスタおよびその製造方法 |
KR100963026B1 (ko) | 2008-06-30 | 2010-06-10 | 삼성모바일디스플레이주식회사 | 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치 |
CN102132414B (zh) * | 2008-08-27 | 2013-05-22 | 出光兴产株式会社 | 场效应型晶体管、其制造方法和溅射靶 |
KR101549295B1 (ko) | 2008-12-12 | 2015-09-01 | 이데미쓰 고산 가부시키가이샤 | 복합 산화물 소결체 및 그것으로 이루어지는 스퍼터링 타겟 |
TWI617029B (zh) | 2009-03-27 | 2018-03-01 | 半導體能源研究所股份有限公司 | 半導體裝置 |
JP2010245366A (ja) * | 2009-04-08 | 2010-10-28 | Fujifilm Corp | 電子素子及びその製造方法、並びに表示装置 |
JP5322787B2 (ja) | 2009-06-11 | 2013-10-23 | 富士フイルム株式会社 | 薄膜トランジスタ及びその製造方法、電気光学装置、並びにセンサー |
CN102473732B (zh) * | 2009-07-27 | 2015-09-16 | 株式会社神户制钢所 | 布线结构以及具备布线结构的显示装置 |
TWI445179B (zh) | 2009-07-27 | 2014-07-11 | Kobe Steel Ltd | A wiring structure and a manufacturing method thereof, and a display device having a wiring structure |
JP5690063B2 (ja) * | 2009-11-18 | 2015-03-25 | 出光興産株式会社 | In−Ga−Zn系酸化物焼結体スパッタリングターゲット及び薄膜トランジスタ |
KR101035357B1 (ko) * | 2009-12-15 | 2011-05-20 | 삼성모바일디스플레이주식회사 | 산화물 반도체 박막 트랜지스터, 그 제조방법 및 산화물 반도체 박막 트랜지스터를 구비한 유기전계 발광소자 |
JP2012124446A (ja) | 2010-04-07 | 2012-06-28 | Kobe Steel Ltd | 薄膜トランジスタの半導体層用酸化物およびスパッタリングターゲット、並びに薄膜トランジスタ |
JP2012033854A (ja) | 2010-04-20 | 2012-02-16 | Kobe Steel Ltd | 薄膜トランジスタの半導体層用酸化物およびスパッタリングターゲット、並びに薄膜トランジスタ |
WO2011145484A1 (en) | 2010-05-21 | 2011-11-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP5718072B2 (ja) | 2010-07-30 | 2015-05-13 | 三星ディスプレイ株式會社Samsung Display Co.,Ltd. | 薄膜トランジスタの半導体層用酸化物およびスパッタリングターゲット、並びに薄膜トランジスタ |
CN107947763B (zh) | 2010-08-06 | 2021-12-28 | 株式会社半导体能源研究所 | 半导体集成电路 |
KR20130099074A (ko) * | 2010-09-03 | 2013-09-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 스퍼터링 타겟 및 반도체 장치의 제작 방법 |
JP2012094853A (ja) | 2010-09-30 | 2012-05-17 | Kobe Steel Ltd | 配線構造 |
JP2012099661A (ja) * | 2010-11-02 | 2012-05-24 | Idemitsu Kosan Co Ltd | 酸化物半導体の製造方法 |
JP2012119664A (ja) | 2010-11-12 | 2012-06-21 | Kobe Steel Ltd | 配線構造 |
JP5651095B2 (ja) | 2010-11-16 | 2015-01-07 | 株式会社コベルコ科研 | 酸化物焼結体およびスパッタリングターゲット |
JP2013070010A (ja) | 2010-11-26 | 2013-04-18 | Kobe Steel Ltd | 薄膜トランジスタの半導体層用酸化物およびスパッタリングターゲット、並びに薄膜トランジスタ |
JP5723262B2 (ja) | 2010-12-02 | 2015-05-27 | 株式会社神戸製鋼所 | 薄膜トランジスタおよびスパッタリングターゲット |
CN103270602A (zh) | 2010-12-28 | 2013-08-28 | 株式会社神户制钢所 | 薄膜晶体管的半导体层用氧化物及溅射靶材,以及薄膜晶体管 |
JP5189674B2 (ja) | 2010-12-28 | 2013-04-24 | 出光興産株式会社 | 酸化物半導体薄膜層を有する積層構造、積層構造の製造方法、薄膜トランジスタ及び表示装置 |
JP5750065B2 (ja) | 2011-02-10 | 2015-07-15 | 株式会社コベルコ科研 | 酸化物焼結体およびスパッタリングターゲット |
JP5750063B2 (ja) | 2011-02-10 | 2015-07-15 | 株式会社コベルコ科研 | 酸化物焼結体およびスパッタリングターゲット |
JP2012180248A (ja) | 2011-03-02 | 2012-09-20 | Kobelco Kaken:Kk | 酸化物焼結体およびスパッタリングターゲット |
JP2012180247A (ja) | 2011-03-02 | 2012-09-20 | Kobelco Kaken:Kk | 酸化物焼結体およびスパッタリングターゲット |
JP5766467B2 (ja) * | 2011-03-02 | 2015-08-19 | 株式会社東芝 | 薄膜トランジスタ及びその製造方法、表示装置 |
JP2013153118A (ja) | 2011-03-09 | 2013-08-08 | Kobe Steel Ltd | 薄膜トランジスタの半導体層用酸化物、上記酸化物を備えた薄膜トランジスタの半導体層および薄膜トランジスタ |
JP5977569B2 (ja) | 2011-04-22 | 2016-08-24 | 株式会社神戸製鋼所 | 薄膜トランジスタ構造、ならびにその構造を備えた薄膜トランジスタおよび表示装置 |
US9660092B2 (en) * | 2011-08-31 | 2017-05-23 | Semiconductor Energy Laboratory Co., Ltd. | Oxide semiconductor thin film transistor including oxygen release layer |
US9082861B2 (en) * | 2011-11-11 | 2015-07-14 | Semiconductor Energy Laboratory Co., Ltd. | Transistor with oxide semiconductor channel having protective layer |
JP6033071B2 (ja) * | 2011-12-23 | 2016-11-30 | 株式会社半導体エネルギー研究所 | 半導体装置 |
-
2013
- 2013-08-13 JP JP2013168290A patent/JP6134230B2/ja not_active Expired - Fee Related
- 2013-08-14 JP JP2013168633A patent/JP6659205B2/ja active Active
- 2013-08-30 WO PCT/JP2013/073372 patent/WO2014034873A1/ja active Application Filing
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- 2013-08-30 CN CN201380044372.8A patent/CN104584200B/zh not_active Expired - Fee Related
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- 2013-08-30 TW TW102131497A patent/TWI514589B/zh not_active IP Right Cessation
- 2013-08-30 KR KR1020157004919A patent/KR20150038351A/ko not_active Application Discontinuation
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- 2013-08-30 US US14/416,213 patent/US9318507B2/en not_active Expired - Fee Related
- 2013-08-30 WO PCT/JP2013/073373 patent/WO2014034874A1/ja active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011146692A (ja) * | 2009-12-17 | 2011-07-28 | Semiconductor Energy Lab Co Ltd | 半導体装置、測定装置、比誘電率の測定方法 |
JP2012033913A (ja) * | 2010-07-01 | 2012-02-16 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2012164963A (ja) * | 2010-11-26 | 2012-08-30 | Kobe Steel Ltd | 薄膜トランジスタの半導体層用酸化物およびスパッタリングターゲット、並びに薄膜トランジスタ |
JP2012151443A (ja) * | 2011-01-19 | 2012-08-09 | Samsung Electronics Co Ltd | 薄膜トランジスター表示板およびその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105679832A (zh) * | 2014-12-05 | 2016-06-15 | 三星显示有限公司 | 薄膜晶体管基板及其制造方法 |
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