Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/60—Schottky-barrier diodes 
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/01—Manufacture or treatment
  • H10D8/051—Manufacture or treatment of Schottky diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/50—PIN diodes 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/60—Schottky-barrier diodes 
  • H10D8/605—Schottky-barrier diodes  of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]

Definitions

• a method of fabricating a rectifier includes providing a semiconductor body of a first conductivity type and forming a first layer on the substrate.
• the first layer has the first type of conductivity and is more lightly doped than the substrate.
• a second layer is formed over the substrate.
• the second layer has a second type of conductivity.
• a metal layer is formed over the second layer.
• the second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer.
• a first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
• FIGs. 1 and 2 show a conventional ⁇ diode and a conventional Schottky rectifier, respectively.
• FIG. 3 shows one embodiment of a Schottky diode constructed in accordance with the principles of the present invention.
• FIG. 7 shows the simulated output characteristics of the device shown in FIG. 6 for different implantation dosages in the transparent regions.
• a lightly doped layer 330 of the second conductivity type (e.g., p- type) is formed over the drift layer 320.
• the lightly doped layer from time to time will be referred to as a transparent layer.
• a metal layer 340 which is formed from a metal (e.g., nickel) capable of forming a silicide is deposited. Once the silicide has been formed, the metal which has not reacted with the semiconductor material is removed by a selective etch.
• a cathode electrode 350 is formed on the backside of the substrate 310 and an anode metal 360 is formed over the metal layer 340.
• the plasma level can be increased with a further increase in the on-state performance, though at the expense of increased switching losses. This trade-off will be further discussed at a later point below.
• FIG. 1 1 shows that the transparent layer 410 (doped p- type in this example) is only inserted in some parts (e.g. sections/areas/cells) of the device.
• the transparent layer 410 is only located between some pairs of adjacent MOS trenches, but not other pairs.
• a conventional TMBS is present in other parts of the device that do not include the transparent layer.
• the structure is effectively an integrated transparent Schottky diode in parallel with a conventional TMBS.
• FIG, 12 is a variation of FIG. 1 1 where the trenches are only present in the conventional TMBS cells, while the transparent layer 410 is present as a planar structure in the rest of the active area of the device.
• the transparent layer shown in the embodiment of FIG. 6 is arranged as regions around the trenches.
• the transparent layer can be formed by ion implantation and/or diffusion techniques using a suitable p-type dopant.
• the implantation energy may be kept low (e.g., 25 KeV).
• the implantation step may be followed by an annealing step (e.g., for 60 minutes at a temperature of 950°C so that the semiconductor surface remains sufficiently smooth to form a quality Schottky contact.
• N- drift region length 5 ⁇ to 200 ⁇

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• High Energy & Nuclear Physics (AREA)
• Health & Medical Sciences (AREA)
• Toxicology (AREA)
• Electrodes Of Semiconductors (AREA)

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• 2011
  • 2011-08-31 US US13/222,249 patent/US8816468B2/en active Active
  • 2011-10-18 TW TW100137738A patent/TWI566422B/zh active
  • 2011-10-20 KR KR1020137012458A patent/KR101987009B1/ko active Active
  • 2011-10-20 CN CN201180050938.9A patent/CN103180961B/zh active Active
  • 2011-10-20 EP EP11835119.6A patent/EP2630663B1/en active Active
  • 2011-10-20 JP JP2013535073A patent/JP5989652B2/ja active Active
  • 2011-10-20 WO PCT/US2011/057012 patent/WO2012054682A2/en not_active Ceased
• 2014
  • 2014-08-14 US US14/459,599 patent/US20140357059A1/en not_active Abandoned
• 2016
  • 2016-08-08 JP JP2016155375A patent/JP6471126B2/ja active Active

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