US7636412B2 - Shift register circuit and image display apparatus equipped with the same - Google Patents

Shift register circuit and image display apparatus equipped with the same Download PDF

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US7636412B2
US7636412B2 US11/734,407 US73440707A US7636412B2 US 7636412 B2 US7636412 B2 US 7636412B2 US 73440707 A US73440707 A US 73440707A US 7636412 B2 US7636412 B2 US 7636412B2
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transistor
input
node
shift register
signal
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US20070248204A1 (en
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Youichi Tobita
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Trivale Technologies LLC
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Mitsubishi Electric Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Definitions

  • the present invention relates to shift register circuits configured only by field effect transistors of the same conductivity type used in scanning line driving circuit and the like of the image display apparatus etc., in particular, to a bi-directional shift register in which the direction of shifting the signal can be reversed.
  • a gate line (scanning line) is arranged for each pixel row (pixel line) of a display panel in which a plurality of pixels are arrayed in a matrix form, and the gate line is sequentially selected and driven at a cycle of one horizontal period of the display signal to update the displayed image.
  • a shift register for performing the shift operation that completes the round in one frame period of the display signal is used for the gate line driving circuit (scanning line driving circuit) to sequentially select and drive the pixel line, that is, the gate line.
  • the shift register used in the gate line driving circuit is desirably configured only by the field effect transistors of the same conductivity type in order to reduce the number of steps in the manufacturing process of the display apparatus.
  • Various shift registers configured only by the field effect transistors of N-type or P-type and display apparatuses mounted with the same are proposed.
  • MOS Metal Oxide Semiconductor
  • TFT Thin Film Transistor
  • the gate line driving circuit is configured by the shift register comprising a plurality of stages. That is, the gate line driving circuit is configured by cascade connecting a plurality of shift register circuits arranged for every pixel line, that is, every gate line.
  • each of the plurality of shift register circuits configuring the gate line driving circuit is referred to as “unit shift register” for the sake of convenience of the explanation.
  • liquid crystal display apparatus of matrix type in which the liquid crystal pixels are arranged in a matrix form
  • the request to change the display pattern such as inverting the displayed image upside down or mirror reversing the same and changing the displaying order when displaying is often made.
  • the display inversion is desired, for example, when applying the liquid crystal display apparatus to an OHP (Overhead Projector) projection apparatus, and using a translucent screen. This is because, when the translucent screen is used, the picture on the screen is inverted as opposed to when projecting the picture from the front side of the screen since the picture is projected from the back side of the screen when seen from the viewer.
  • the change in displaying order is desired when rendition effect is desired in displaying a bar graph, histogram etc. such as gradually appearing the displaying image from the top to the bottom or vice versa, that is, gradually appearing from the bottom to the top.
  • One method of performing display pattern change of such display apparatus includes switching the shift direction of the signal in the gate line driving circuit.
  • the shift register (hereinafter referred to as “bi-directional shift register”) in which the shift direction of the signal can be switched is thus proposed.
  • the unit shift register (hereinafter also referred to as “bi-directional unit shift register”) used in the bi-directional shift register configured only by the field effect transistors of N-channel type is disclosed in FIG. 13 of Japanese Patent Application Laid-Open No. 2001-350438 below (similar circuit is shown in FIG. 3 of the present specification, where the reference number in parentheses below correspond to those in FIG. 3 ).
  • the output stage of the unit shift register is configured by a first transistor (Q 1 ) for providing a clock signal (CLK) input to a clock terminal (CK) to an output terminal (OUT), and a second transistor (Q 2 ) for supplying a reference voltage (VSS) to the output terminal.
  • a gate node (N 1 ) of the first transistor is defined as the first node
  • a gate node (N 2 ) of the second transistor is defined as the second node.
  • the unit shift register includes a third transistor (Q 3 ) for providing a first voltage signal (Vn) to the first node based on the signal input to a predetermined first input terminal (IN 1 ), and a fourth transistor (Q 4 ) for providing a second voltage signal (Vr) to the first node based on the signal input to a predetermined second input terminal (IN 2 ).
  • the first and second voltage signals are signals complementary to each other where when one of the voltage level (hereinafter referred to simply as “level”) is H (High), the other voltage level is L (Low) level.
  • the first transistor is driven by the third and fourth transistors.
  • the second transistor is driven by an inverter (Q 6 , Q 7 ) having the first node as an input end and a second node as an output end.
  • the relevant unit shift register outputs the output signal
  • the first node is at H level due to the operation of the second and third transistors, and the second node is accordingly at L level due to the inverter.
  • the first transistor is thereby turned ON, the second transistor is turned OFF, and the clock signal is transmitted to the output terminal in such state, whereby the output signal is output.
  • the first node is at L level due to the operation of the second and third transistors, and the second node is accordingly at H level due to the inverter.
  • the first transistor is thereby turned OFF, the second transistor is turned ON, and the voltage level of the output terminal is maintained at L level.
  • the relevant unit shift register operates to output the signal input to the first input terminal in a temporally shifted manner.
  • the relevant unit shift register operates to output the signal input to the second input terminal in a temporally shifted manner.
  • the bi-directional unit shift register of FIG. 13 of Japanese Patent Application Laid-Open No. 2001-350438 switches the shift direction of the signal by switching the levels of the first voltage signal and the second voltage signal for driving the first transistor.
  • a first problem of the conventional bi-directional shift register will be described first.
  • the output signal of the previous stage is input to the first input terminal (IN 1 ) of the unit shift register of each stage, and the output signal of the next stage is input to the second input terminal (IN 2 ) (see FIG. 2 of the present specification).
  • the output signal (gate line driving signal) is output only during one specific horizontal period within one frame period from the respective unit shift register, and is not output during other periods since the gate line driving circuit operates to sequentially select each gate line at a cycle of one frame period. Therefore, the third and fourth transistors (Q 3 , Q 4 ) driving the first transistor (Q 1 ) are turned OFF most of the time during one frame period in each unit shift register.
  • the gate of the first transistor that is, the first node (N 1 ) is in the floating state when the third and fourth transistors are turned OFF.
  • the period (non-selective period) in which the output signal is not output continues for a length of about one frame period, during which period, the first node is maintained at L level of floating state, and the first transistor is maintained in the OFF state. If leakage current is generated in the third transistor (when first voltage signal is at H level) or the fourth transistor (when second voltage signal is at H level), the charges involved therewith accumulates at the first node in the floating state, and the potential of the first node gradually rises.
  • the clock signal is continuously input to the clock terminal (CK) (drain of first transistor) even during the non-selective period, and the potential of the first node rises while the clock signal is at H level due to coupling via overlapping capacity between drain and gate of the first transistor.
  • the first node (N 1 ) is at H level of the floating state and the first transistor (Q 1 ) is maintained in the ON state during the period (selective period) the bi-directional unit shift register outputs the output signal.
  • the clock signal of the clock terminal (CK) drain of first transistor
  • the output terminal (OUT) becomes H level following thereto, and the gate line is activated.
  • the first node is boosted while the clock signal is at H level due to coupling via the drain-gate overlapping capacity, the gate-channel capacity, and the gate-source overlapping capacity of the first transistor.
  • the boost of the first node increases the driving ability (ability to flow current) of the first transistor, whereby the relevant unit shift register charges the gate line at high speed.
  • the leakage current tends to be easily generated depending on the voltage resistance property of between the drain and the source.
  • the level of the first node lowers due to the leakage current, the driving ability of the first transistor lowers, and the falling speed of the output signal of when the clock signal returns from H level to L level becomes slower. If the turning OFF of the pixel transistor is delayed, the data in the pixel may be re-written on the data of the next line, and display failure may occur.
  • a control pulse referred as “start pulse” corresponding to the head of each frame of the image signal is input as input signal to the first input terminal (IN 1 ) of the unit shift register of the leading stage in the case of forward shift of shifting the signal in the direction of the previous stage to the subsequent stage and the like.
  • the input signal is sequentially transmitted to each cascade connected unit shift register to the unit shift register of the final stage.
  • a control pulse referred to as “end pulse” corresponding to the end of each frame period of the image signal must be input to the second input terminal (IN 2 ) of the final stage immediately after the unit shift register of the final stage outputs the output signal. Otherwise, the first transistor of the final stage cannot be turned OFF, and the output signal continues to be output from the final stage.
  • the end pulse is less likely to become necessary and is sufficiently with the start pulse since a dummy stage is further arranged in the next stage after the final stage and the output signal thereof is used as the end pulse, or the clock signal having a phase different from the clock signal input to the final stage is used as the end pulse. Therefore, most of the drive controlling devices for controlling the operation of the normal gate line driving circuit for shifting the signal (gate line driving signal) only in one direction output only the start pulse.
  • the start pulse must be input in the reverse shift to shift the signal in the direction of subsequent stage to previous stage in addition to inputting the end pulse to the second input terminal of the final stage. Furthermore, it is not as simple as with shifting in only one direction since the output signal of the dummy stage may become the wrong start pulse when the shift direction is reversed, if the dummy stage is simply arranged. Therefore, the drive controlling device of the gate line driving circuit for shifting the signal in bi-direction mounted with the output circuit of not only the start pulse but also of the end pulse is adopted, which increases the cost of the drive controlling device, that is, increases the cost of the display apparatus.
  • the bi-directional shift register is in the selective period as described above, the first node (N 1 ) is at H level, the second node (N 2 ) is at L level, and thus the first transistor (Q 1 ) is turned ON and the second transistor (Q 2 ) is turned OFF.
  • the first node becomes L level and the first transistor is turned OFF when the output signal of the next stage is input to the second input terminal (IN 2 ) in transitioning from the selective period to the non-selective period.
  • the second node becomes H level by the inverter (Q 6 , Q 7 ) in the unit shift register, and the second transistor is turned ON.
  • the parasitic capacity exists between the gate line and the data line of the display panel, and the voltage change of the data line might be added as noise to the gate line, that is, the output terminal (OUT) of the unit shift register due to coupling therethrough. If the second transistor is not sufficiently turned ON in this case, the charges involved in the noise cannot be discharged from the output terminal, whereby the pixel transistor turns ON, and the wrong data may be written to the pixel. Therefore, the potential of the second node (gate of the second transistor) is preferably raised at high speed when transitioning to the non-selective period. To this end, the on-resistance of the transistors (Q 6 , Q 7 ) configuring the inverter is lowered.
  • the relevant inverter is a ratio type inverter configured by the field effect transistors of the same conductivity type, the pass through current flowing through the inverter when the output of the inverter is at L level increases and the power consumption increases if the on-resistance of the transistor is lowered.
  • the first aim of the present invention is to suppress malfunction caused by the leakage current of the constituting transistor in the bi-directional unit shift register.
  • the second aim is to provide a bi-directional shift register in which input of the end pulse is not necessary.
  • the third aim is to reduce the influence of noise added to the output terminal in the bi-directional unit shift register.
  • the shift register circuit includes first and second input terminals, an output terminal and a clock terminal; as well as first and second voltage signal terminals.
  • the first and second voltage signal terminals are respectively input with first and second voltage signals complementary to each other.
  • the shift register circuit includes the following first to fifth transistors.
  • the first transistor provides a clock signal input to the clock terminal to the output terminal.
  • the second transistor discharges the output terminal.
  • the third transistor provides the first voltage signal to a first node connected with a control electrode of the first transistor based on a first input signal input to the first input terminal.
  • the fourth transistor provides the second voltage signal to the first node based on a second input signal input to the second input terminal.
  • the fifth transistor having a control electrode connected to the second node connected with the control electrode of the second transistor, discharges the first node.
  • the transistor Q 5 is turned ON and the first node is discharged when the first transistor is turned OFF and the second transistor is turned ON, and thus the first node is maintained at L level even if leakage current is generated at the third and fourth transistors, and malfunction caused by the leakage current is prevented.
  • the shift register circuit includes first and second input terminals, an output terminal and a clock terminal; as well as first and second voltage signal terminals.
  • the first and second voltage signal terminals are respectively input with first and second voltage signals complementary to each other.
  • the shift register circuit includes the following first to sixth transistors.
  • the first transistor provides a clock signal input to the clock terminal to the output terminal.
  • the second transistor discharges the output terminal.
  • the third transistor provides the first voltage signal to a first node connected with a control electrode of the first transistor based on a first input signal input to the first input terminal.
  • the fourth transistor provides the second voltage signal to the first node based on a second input signal input to the second input terminal.
  • the fifth transistor provides the second voltage signal to a second node connected with a control electrode of the second transistor based on the first input signal.
  • the sixth transistor provides the first voltage signal to the second node based on the second input signal.
  • the second node is charged and discharged at high speed.
  • the second transistor since the second node is charged at high speed, the second transistor is rapidly and sufficiently turned ON and the influence of noise added to the output terminal via the gate line is suppressed when applied to the gate line driving circuit of the display apparatus.
  • the shift register circuit includes first and second input terminals, an output terminal and a clock terminal; as well as first and second voltage signal terminals.
  • the first and second voltage signal terminals are respectively input with first and second voltage signals complementary to each other.
  • the shift register circuit includes first to sixth transistors and a charging circuit in the following.
  • the first transistor provides a clock signal input to the clock terminal to the output terminal.
  • the second transistor discharges the output terminal.
  • the third transistor provides the first voltage signal to a first node connected with a control electrode of the first transistor based on a first input signal input to the first input terminal.
  • the fourth transistor provides the second voltage signal to the first node based on a second input signal input to the second input terminal.
  • the third transistor connects to the first voltage signal terminal by way of a fifth transistor having a control electrode connected with the control electrode of the third transistor.
  • the fourth transistor connects to the second voltage signal terminal by way of a sixth transistor having a control electrode connected with the control electrode of the fourth transistor.
  • the charging circuit charges a third node, which is a connecting node between the third transistor and the fifth transistor, and a fourth node, which is a connecting node between the fourth transistor and the sixth transistor when the output terminal is activated.
  • the third and fourth nodes are charged when the output terminal is activated.
  • the first node is boosted by the coupling via parasitic capacity of the first transistor, but the generation of leakage current of the third and fourth transistors is suppressed since the third and fourth nodes are being charged. Therefore, the potential of the first node is prevented from falling by the leakage current, whereby the problem of lowering in driving ability of the first transistor is resolved.
  • the shift register circuit according to a fourth aspect of the present invention a shift register comprising a plurality of stages including a first dummy stage at the beginning and a second dummy stage at the end. Each stage includes first and second input terminals, an output terminal and a clock terminal; as well as first and second voltage signal terminals. The first and second voltage signal terminals are respectively input with first and second voltage signals complementary to each other.
  • the shift register circuit includes the following first to fourth transistors.
  • the first transistor provides a clock signal input to the clock terminal to the output terminal.
  • the second transistor discharges the output terminal.
  • the third transistor provides the first voltage signal to a first node connected with a control electrode of the first transistor based on a first input signal input to the first input terminal.
  • the fourth transistor provides the second voltage signal to the first node based on a second input signal input to the second input terminal.
  • a predetermined first control pulse is input to the first input terminal of the leading stage excluding the first dummy stage, and an output signal of the previous stage is input to the first input terminal of subsequent stage. Furthermore, a predetermined second control pulse is input to the second input terminal of the final stage excluding the second dummy stage, and an output signal of the next stage is input to the second input terminal of the previous stage.
  • the leading stage includes a fifth transistor for discharging the first node of the leading stage based on the output signal of the first dummy stage; and the final stage includes a sixth transistor for discharging the first node of the final stage based on the output signal of the second dummy stage.
  • the final stage is inactivated by the output signal of the second dummy stage in the forward shift of shifting the signal from the previous stage to the subsequent stage, and the leading stage is inactivated by the output signal of the first dummy stage in the reverse shift of shifting the signal from subsequent stage to previous stage. That is, the output signal of the second dummy stage functions as end pulse in the forward shift, and the output signal of the first dummy stage function as end pulse in the reverse shift. Therefore, the end pulse does not need to be externally input for driving the shift register circuit. That is, the operation of the bi-directional shift is performed using the drive controlling device that does not include an end pulse generation circuit, whereby cost is reduced.
  • FIG. 1 is a schematic block diagram showing a configuration of a display apparatus according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing a configuration example of a gate line driving circuit using a bi-directional unit shift register
  • FIG. 3 is a circuit diagram of a conventional bi-directional unit shift register
  • FIG. 4 is a timing chart showing the operation of the gate line driving circuit
  • FIG. 5 is a block diagram showing a configuration example of the gate line driving circuit using the bi-directional unit shift register
  • FIG. 6 is a timing chart showing the operation of the gate line driving circuit
  • FIG. 7 is a circuit diagram of a bi-directional unit shift register according to a first embodiment
  • FIG. 8 is a timing chart showing the operation of the bi-directional unit shift register according to the first embodiment
  • FIG. 9 is a circuit diagram of a bi-directional unit shift register according to a second embodiment.
  • FIG. 10 is a circuit diagram of a bi-directional unit shift register according to a third embodiment
  • FIG. 11 is a circuit diagram of a bi-directional unit shift register according to a fourth embodiment.
  • FIG. 12 is a timing chart showing the operation of the bi-directional unit shift register according to the fourth embodiment.
  • FIG. 13 is a circuit diagram of a bi-directional unit shift register according to a fifth embodiment
  • FIG. 14 is a timing chart showing the operation of the bi-directional unit shift register according to the fifth embodiment.
  • FIG. 15 is a circuit diagram of a bi-directional unit shift register according to a sixth embodiment.
  • FIG. 16 is a circuit diagram of a bi-directional unit shift register according to a seventh embodiment
  • FIG. 17 is a circuit diagram of a bi-directional unit shift register according to an eighth embodiment.
  • FIG. 18 is a circuit diagram of a bi-directional unit shift register according to the eighth embodiment.
  • FIG. 19 is a circuit diagram of a bi-directional unit shift register according to the eighth embodiment.
  • FIG. 20 is a circuit diagram of a bi-directional unit shift register according to the eighth embodiment.
  • FIG. 21 is a circuit diagram of a bi-directional unit shift register according to the eighth embodiment.
  • FIG. 22 is a circuit diagram of a bi-directional unit shift register according to the eighth embodiment.
  • FIG. 23 is a circuit diagram of a bi-directional unit shift register according to the eighth embodiment.
  • FIG. 24 is a block diagram showing a configuration example of the gate line driving circuit using the bi-directional unit shift register according to a ninth embodiment
  • FIG. 25 is a circuit diagram showing a configuration example of the gate line driving circuit according to the ninth embodiment.
  • FIG. 26 is a circuit diagram showing a configuration example of the gate line driving circuit according to the ninth embodiment.
  • FIG. 27 is a timing chart showing the operation of the gate line driving circuit according to the ninth embodiment.
  • FIG. 28 is a timing chart showing the operation of the gate line driving circuit according to the ninth embodiment.
  • FIG. 29 is a circuit diagram showing a configuration example of the gate line driving circuit according to the ninth embodiment.
  • FIG. 30 is a circuit diagram showing a configuration example of the gate line driving circuit according to the ninth embodiment.
  • FIG. 1 is a schematic block diagram showing the configuration of a display apparatus according to a first embodiment of the present invention, showing the entire configuration of a liquid crystal display apparatus 10 as one example of the display apparatus.
  • the liquid crystal display apparatus 10 includes a liquid crystal array section 20 , a gate line driving circuit (scanning line driving circuit) 30 , and a source driver 40 .
  • the bi-directional shift register according to the embodiment of the present invention is mounted on the gate line driving circuit 30 , and is integrally formed with the liquid crystal array section 20 .
  • the liquid crystal array section 20 includes a plurality of pixels 25 arranged in a matrix form.
  • the gate lines GL 1 , GL 2 , . . . are arranged on each row of pixels (hereinafter referred to also as “pixel line”), and the data lines DL 1 , DL 2 , . . . (collectively referred to as “data line DL”) are arranged on each column of pixels (hereinafter referred to also as “pixel column”).
  • FIG. 1 shows the pixels 25 in first and second columns on the first row, and the gate line GL 1 as well as the data lines DL 1 , DL 2 corresponding thereto by way of example.
  • Each pixel 25 includes a pixel switch element 26 arranged between the corresponding data line DL and the pixel node Np, and a capacitor 27 and a liquid crystal display element 28 connected in parallel between the pixel node Np and a common electrode node NC.
  • the orientation of the liquid crystals in the liquid crystal display element 28 changes according to the voltage difference between the pixel node Np and the common electrode node NC, and the display luminance of the liquid crystal display element 28 changes in response thereto.
  • the luminance of each pixel can be controlled by the display voltage transmitted to the pixel node Np via the data line DL and the pixel switch element 26 .
  • the intermediate luminance can be obtained by applying the intermediate voltage difference between the voltage difference corresponding to the maximum luminance and the voltage difference corresponding to the minimum luminance to between the pixel node Np and the common electrode node NC. Therefore, the tone-wise luminance can be obtained by setting the display voltage in a step-wise manner.
  • the gate line driving circuit 30 selects and drives the gate line GL in order based on a predetermined scanning period.
  • the gate line driving circuit 30 is configured by a bi-directional shift register in which the direction of the order of activating the gate line GL can be switched.
  • the gate electrodes of the pixel switch element 26 are connected to the corresponding gate lines GL. While a specific gate line GL is being selected, the pixel switch element 26 is in the electrically conducting state at each pixel connected to the relevant gate line, and the pixel node Np is connected to the corresponding data line DL.
  • the display voltage transmitted to the pixel node Np is held by the capacitor 27 .
  • the pixel switch element 26 is configured by the TFT formed on the same insulation substrate (glass substrate, resin substrate etc.) as the liquid crystal display element 28 .
  • the source driver 40 is provided to output the display voltage set in a step-wise manner by the display signal SIG, which is the digital signal of N bits, to the data line DL.
  • the source driver 40 includes a shift register 50 , data latch circuits 52 , 54 , a tone voltage generation circuit 60 , a decode circuit 70 , and an analog amplifier 80 .
  • the display signal bits DB 0 to DB 5 corresponding to the display luminance of each pixel 25 are serially generated in the display signal SIG. That is, the display signal bits DB 0 to DB 5 at each timing indicate the display luminance at one of the pixels 25 in the liquid crystal array section 20 .
  • the shift register 50 instructs the retrieval of the display signal bits DB 0 to DB 5 to the data latch circuit 52 at a timing synchronized with the period the setting of the display signal SIG is switched.
  • the data latch circuit 52 retrieves the serially generated display signal SIG one by one, and holds the display signal SIG worth of one pixel line.
  • a latch signal LT input to the data latch circuit 54 is activated at a timing the display signal SIG worth of one pixel line is retrieved by the data latch circuit 52 .
  • the data latch circuit 54 retrieves the display signal SIG worth of one pixel line held in the data latch circuit 52 at the relevant time.
  • the tone voltage generation circuit 60 is configured by 63 voltage dividing resistors connected in series between high voltage VDH and low voltage VDL, and generates tone voltages V 1 to V 64 of 64 steps.
  • the decode circuit 70 decodes the display signal SIG held in the data latch circuit 54 , and selects and outputs the voltage to be output to each decode output node Nd 1 , Nd 2 , . . . (collectively referred to as “decode output node Nd”) based on the decoded result from the tone voltages V 1 to V 64 .
  • the display voltage (one of the tone voltages V 1 to V 64 ) corresponding to the display signal SIG worth of one pixel line held in the data latch circuit 54 is simultaneously (in parallel) output to the decode output node Nd.
  • the decode output nodes Nd 1 , Nd 2 corresponding to the data lines DL 1 , DL 2 of the first and second columns are shown by way of example.
  • the analog amplifier 80 outputs the analog voltage corresponding to each display voltage output to the decode output nodes Nd 1 , Nd 2 , from the decode circuit 70 to each data line DL 1 , DL 2 , . . . .
  • the source driver 40 repeatedly outputs the display voltage corresponding to a series of display signal SIG to the data line DL by one pixel line based on the predetermined scanning period, and the gate line driving circuit 30 drives the gate lines GL 1 , GL 2 , . . . in this order or in the reverse order in synchronization with the scanning period, thereby displaying the image or the inverted image based on the display signal SIG on the liquid crystal array section 20 .
  • FIG. 2 shows a view showing a configuration of the gate line driving circuit 30 .
  • the gate line driving circuit 30 is configured by the bi-directional shift register comprising a plurality of stages. That is, the relevant gate line driving circuit 30 includes n cascade connected bi-directional unit shift registers SR 1 , SR 2 , SR 3 , . . . , SR n (the unit shift registers SR 1 , SR 2 , SR 3 , . . . , SR n hereinafter collectively referred to as “unit shift register SR”).
  • One unit shift register SR is arranged for one pixel line, that is, one gate line GL.
  • a clock generator 31 shown in FIG. 2 inputs two phase clock signals CLK, /CLK having phases different from each other to the unit shift register SR of the gate line driving circuit 30 .
  • the clock signals CLK, /CLK are controlled so as to be alternately activated at the timing synchronized with the scanning period of the display apparatus.
  • a voltage signal generator 32 shown in FIG. 2 generates a first voltage signal Vn and a second voltage signal Vr to determine the shift direction of the signal in the bi-directional shift register.
  • the voltage signal generator 32 has the first voltage signal Vn at H level and the second voltage signal Vr at L level when shifting the signal in the direction from the previous stage to the subsequent stage (order of unit shift registers SR 1 , SR 2 , SR 3 , . . . , SR n ) (this direction is defined as “forward direction”).
  • the second voltage signal Vr is at H level and the first voltage signal Vn is at L level when shifting the signal in the direction from the subsequent stage to the previous stage (order of unit shift registers SR n , SR n ⁇ 1 , SR n-2 , . . . ) (this direction is defined as “reverse direction”).
  • Each unit shift register SR includes a first input terminal IN 1 , a second input terminal IN 2 , an output terminal OUT, a clock terminal CK, a first voltage signal terminal T 1 and a second voltage signal terminal T 2 .
  • One of the clock signals CLK, /CLK is input so that the clock signal different from the unit shift register SR adjacent before and after is input to the clock terminal CK of each unit shift register SR, as shown in FIG. 2 .
  • the clock signals CLK, /CLK generated by the clock generator 31 are able to interchange the phase with each other according to the shift direction of the signal by program or by change of connection of the wiring.
  • Interchange by change of connection of the wiring is effective when fixing the shift direction to one direction before manufacturing the display apparatus.
  • Interchange by program is effective when fixing the shift direction to one direction after manufacturing the display apparatus or allowing the shift direction to be changed while using the display apparatus.
  • the gate line GL is connected to the output terminal OUT of the unit shift register SR.
  • the signal (output signal) output to the output terminal OUT becomes a horizontal (or vertical) scanning pulse for activating the gate line GL.
  • a first control pulse STn is input to the first input terminal IN 1 of the unit shift register SR 1 of the first stage, which is the leading stage.
  • the first control pulse STn becomes the start pulse corresponding to the head of each frame period of the image signal in the forward shift, and becomes the end pulse corresponding to the end of each frame period of the image signal in the reverse shift.
  • the first input terminal IN 1 of the unit shift register SR of the second and subsequent stages is connected to the output terminal OUT of the unit shift register SR of the previous stage. That is, the output signal of the previous stage is input to the first input terminal IN 1 of the unit shift register SR for the second and subsequent stages.
  • the second control pulse STr is input to the second input terminal IN 2 of the n th (n th stage) unit shift register SRn, which is the final stage.
  • the second control pulse STr becomes the start pulse in the reverse shift, and becomes the end pulse in the forward shift.
  • the second input terminal IN 2 before n-1 th stage is connected to the output terminal OUT of the subsequent stage. That is, the output signal of the subsequent stage is input to the second input terminal IN 2 of the second and subsequent stages.
  • Each unit shift register SR transmits the input signal (output signal of previous stage) input from the previous stage to the corresponding gate line GL and the unit shift register SR of the next stage while shifting the same in the forward shift in synchronization with the clock signals CLK, /CLK.
  • the input signal (output signal of subsequent stage) input from the subsequent stage is transmitted to the corresponding gate line GL and the unit shift register SR of the previous stage while shifting the same (operation of the unit shift register SR to be hereinafter described in detail).
  • a series of unit shift registers SR function as a so-called gate line driving unit for sequentially activating the gate line GL at the timing based on a predetermined scanning period.
  • FIG. 3 is a circuit diagram showing a configuration of the conventional bi-directional unit shift register SR, similar to that disclosed in Japanese Patent Application Laid-Open No. 2001-350438 (Pages. 13-19, FIGS. 13 to 25).
  • the configuration of each cascade connected unit shift register SR is substantially all the same in the gate line driving circuit 30 , and thus only the configuration of one unit shift register SR will be described below by way of example.
  • the transistors configuring the unit shift register SR are all field effect transistors of the same conductivity type but are assumed to be all N-type TFT in the present embodiment.
  • the conventional bi-directional unit shift register SR includes a first power supply terminal S 1 supplied with low potential side power supply potential VSS and a second power supply terminal S 2 supplied with high potential side power supply potential VDD in addition to the first and second input terminals IN 1 , IN 2 , the output terminal OUT, the clock terminal CK, and first and second voltage signal terminals T 1 , T 2 , as already shown in FIG. 2 .
  • the output stage of the unit shift register SR is configured by a transistor Q 1 connected between the output terminal OUT and the clock terminal CK, and a transistor Q 2 connected between the output terminal OUT and the first power supply terminal S 1 . That is, the transistor Q 1 is an output pull-up transistor for supplying the clock signal input to the clock terminal CK to the output terminal OUT, and the transistor Q 2 is an output pull-down transistor for supplying the potential of the first power supply terminal S 1 to the output terminal OUT.
  • the node connected by the gate (control electrode) of the transistor Q 1 configuring the output stage of the unit shift register SR is defined as node N 1 and the gate node of the transistor Q 2 as node N 2 .
  • a transistor Q 3 is connected between the node N 1 and the first voltage signal terminal T 1 , the gate of which is connected to the first input terminal IN 1 .
  • a transistor Q 4 is connected between the node N 1 and the second voltage signal terminal T 2 , the gate of which is connected to the second input terminal IN 2 .
  • a transistor Q 6 is connected between the node N 2 and the second power supply terminal S 2 , and a transistor Q 7 is connected between the node N 2 and the first power supply terminal S 1 .
  • the gate of the transistor Q 6 is connected to the second power terminal S 2 similar to the drain, or is a so-called diode connected.
  • the gate of the transistor Q 7 is connected to the node N 1 .
  • the transistor Q 7 has a driving ability (ability to flow current) set sufficiently higher than the transistor Q 6 . That is, the on-resistance of the transistor Q 7 is smaller than the on-resistance of the transistor Q 6 .
  • the transistor Q 6 and the transistor Q 7 configure an inverter having the node N 1 as the input end and the node N 2 as the output end.
  • the relevant inverter is a so-called “ratio type inverter”, in which the operation is defined by the ratio of the on-resistance values of the transistor Q 6 and the transistor Q 7 .
  • the inverter functions as a “pull-down driving circuit” for driving the transistor Q 2 to pull-down the output terminal OUT.
  • each unit shift register SR configuring the gate line driving circuit 30 is substantially all the same, and thus the operation of the k th unit shift register SR k will be described herein by way of example.
  • the clock signal CLK is input to the clock terminal CK of the relevant shift register SR k for the sake of simplification (e.g., correspond to unit shift register SR 1 , SR 3 etc. in FIG. 2 ).
  • the output signal of the relevant unit shift register SR k is defined as G k , the output signal of the unit shift register SR k ⁇ 1 of the previous stage (k ⁇ 1 stage) as G k ⁇ 1 , and the output signal of the unit shift register SR k+1 of the next stage (k+1 stage) as G k+1 .
  • the potential of H level of the clock signals CLK, /CLK, the first voltage signal Vn, and the second voltage signal Vr is assumed to be equal to the high potential side power supply potential VDD.
  • the threshold voltage of each transistor configuring the unit shift register SR is assumed to be all the same, where the value thereof is Vth.
  • the voltage signal generator 32 has the first voltage signal Vn at H level (VDD) and the second voltage signal Vr at L level (VSS). That is, the transistor Q 3 functions as a transistor for charging (pulling up) the node N 1 , and the transistor Q 4 functions as a transistor for discharging (pulling down) the node N 1 in the forward shift.
  • the node N 1 is assumed to be at L level (VSS) and the node N 2 at H level (VDD-Vth) in the initial state (this state is hereinafter referred to as “reset state”).
  • the clock terminal CK clock signal CLK
  • the first input terminal IN 1 output signal G k ⁇ 1 of previous stage
  • the second input terminal IN 2 output signal G k+1 of next stage
  • the output terminal OUT output signal Gk is maintained at L level irrespective of the level of the clock terminal CK (clock signal CLK). That is, the gate line GLk to be connected with the relevant unit shift register SR k is in the non-selective state.
  • the clock signal CLK input to the clock terminal CK becomes H level, but since the transistor Q 1 is turned ON and the transistor Q 2 is turned OFF at this point, the level of the output terminal OUT rises therewith.
  • the level of the node N 1 in the floating state is boosted by a predetermined voltage due to coupling via gate-channel capacity of the transistor Q 1 . Therefore, the driving ability of the transistor Q 1 is maintained high even if the level of the output terminal OUT rises, and thus the level of the output signal G k changes following the level of the clock terminal CK.
  • the transistor Q 1 when the gate-source voltage of the transistor Q 1 is sufficiently large, the transistor Q 1 performs the operation in the non-saturated region (non-saturated operation), and thus the loss worth of threshold voltage does not exist, and the output terminal OUT rises to the same level as the clock signal CLK. Therefore, the output signal G k becomes H level by the period the clock signal CLK is at H level, and the gate line GL k is activated and in the selected state.
  • the output signal G k is input to the first input terminal IN 1 of the next stage, and thus the output signal G k+1 of the next stage becomes H level at the timing the clock signal/CLK becomes H level.
  • the transistor Q 4 of the relevant unit shift register SR k is thus turned ON, and the node N 1 becomes L level.
  • the transistor Q 7 is accordingly turned OFF and the node N 2 becomes H level. That is, the state returns to the reset state in which the transistor Q 1 is turned OFF, and the transistor Q 2 is turned ON.
  • the unit shift register SR maintains the reset state while the signal (start pulse or output signal G k ⁇ 1 of the previous stage) is not input to the first input terminal IN 1 . Since the transistor Q 1 is turned OFF and the transistor Q 2 is turned ON in the reset state, the output terminal OUT (gate line GL k ) is maintained at L level (VSS) of low impedance.
  • the unit shift register SR switches to the set state. Since the transistor Q 1 is turned ON and the transistor Q 2 is turned OFF in the set state, the output terminal OUT becomes H level and the output signal G k is output during the period the signal (clock signal CLK) of the clock terminal CK is at H level. Thereafter, when the signal (output signal G k+1 of the next stage or end pulse) is input to the second input terminal IN 2 , the state returns to the original reset state.
  • the first control pulse STn serving as the start pulse input to the first input terminal IN 1 of the unit shift register SR 1 of the first stage is transmitted in the order of unit shift register SR 2 , SR 3 , . . . while being shifted at a timing synchronized with the clock signals CLK, /CLK as shown in the timing chart of FIG. 4 .
  • the gate line driving circuit 30 thereby drives the gate lines GL 1 , GL 2 , GL 3 , . . . in this order at a predetermined scanning period.
  • the second control pulse STr serving as the end pulse must be input to the second input terminal IN 2 of the relevant unit shift register SR n immediately after the unit shift register SR n of the final stage outputs the output signal Gn, as shown in FIG. 4 .
  • the relevant unit shift register SR n is thereby returned to the set state.
  • the voltage signal generator 32 turns the first voltage signal Vn to L level (VSS) and the second voltage signal Vr to H level (VDD). That is, the transistor Q 3 functions as the transistor for discharging (pulling down) the node N 1 and the transistor Q 4 functions as the transistor for charging (pulling up) the node N 1 in the reverse shift, in contradiction to the forward shift.
  • the second control pulse STr is input to the second input terminal IN 2 of the unit shift register SR n of the final stage as start pulse
  • the first control pulse STn is input to the first input terminal IN 1 of the unit shift register SR 1 of the first stage as the end pulse. Therefore, the operation of the transistor Q 3 and the transistor Q 4 is interchanged with each other with respect to the forward shift in the unit shift register SR of each stage.
  • the unit shift register SR maintains the reset state while the signal (start pulse or output signal G k+1 of the next stage) is not input to the second input terminal IN 2 . Since the transistor Q 1 is turned OFF and the transistor Q 2 is turned ON in the reset state, the output terminal OUT (gate line GL k ) is maintained at L level (VSS) of low impedance.
  • the unit shift register SR switches to the set state. Since the transistor Q 1 is turned ON and the transistor Q 2 is turned OFF in the set state, the output terminal OUT becomes H level and the output signal G k is output during the period the signal (clock signal CLK) of the clock terminal CK is at H level. Thereafter, when the signal (output signal G k ⁇ 1 of the previous stage or end pulse) is input to the first input terminal IN 1 , the state returns to the original reset state.
  • the second control pulse STr serving as the start pulse input to the second input terminal IN 2 of the unit shift register SR n of the final stage (n th stage) is transmitted in the order of unit shift register SR n ⁇ 1 , SR n ⁇ 2 , while being shifted at a timing synchronized with the clock signals CLK, /CLK as shown in the timing chart of FIG. 5 .
  • the gate line driving circuit 30 thereby drives the gate lines GL n , GL n ⁇ 1 , GL n ⁇ 2 in this order, that is, the order opposite the forward shift, at a predetermined scanning period.
  • the first control pulse STn serving as the end pulse must be input to the first input terminal IN 1 of the relevant unit shift register SR 1 immediately after the unit shift register SR 1 of the first stage outputs the output signal G 1 , as shown in FIG. 5 .
  • the relevant unit shift register SR 1 is thereby returned to the set state.
  • the gate line driving circuit 30 may be configured as shown in FIG. 6 .
  • the clock generator 31 in this case outputs clock signals CLK 1 , CLK 2 , and CLK 3 , which are three phase clocks having different phases.
  • One of the clock signals CLK 1 , CLK 2 , and CLK 3 is input to the clock terminal CK of each unit shift register SR so that clock signals different to each other are input to unit shift registers SR adjacent before and after.
  • the order of becoming H level can be changed within the clock signals CLK 1 , CLK 2 , and CLK 3 according to the direction of shifting the signal by program or change of connection of the wiring.
  • the signals become H level in the order of CLK 1 , CLK 2 , CLK 3 , CLK 1 , in the forward shift, and become H level in the order of CLK 3 , CLK 2 , CLK 1 , CLK 3 , in the reverse shift.
  • the operation of the individual unit shift register SR is the same for the gate line driving circuit 30 configured as in FIG. 6 as in the case of FIG. 2 described above, and thus the description thereof will be omitted.
  • each unit shift register SR cannot be in the reset state (i.e., initial state) unless after the unit shift register SR of the next stage has operated at least once in the forward shift, for example.
  • each unit shift register SR cannot be in the reset state unless after the unit shift register SR of the previous stage has operated at least once.
  • Each unit shift register SR cannot perform the normal operation unless after the reset state. Therefore, the dummy operation of transmitting a dummy input signal from the first stage to the final stage (or from final stage to first stage) of the unit shift register SR must be performed, prior to the normal operation.
  • a reset transistor may be separately arranged between the node N 2 and the second power supply terminal S 2 (high potential side power supply) of each unit shift register SR, and the reset operation of forcibly charging the node N 2 may be performed before the normal operation. In this case, however, the reset signal line must be separately arranged.
  • FIG. 7 is a circuit diagram showing the configuration of the bi-directional unit shift register SR according to the first embodiment.
  • the output stage of the relevant unit shift register SR is also configured by the transistor Q 1 connected between the output terminal OUT and the clock terminal CK, and the transistor Q 2 connected between the output terminal OUT and the first power supply terminal S 1 . That is, the transistor Q 1 is a first transistor for providing the clock signal input to the clock terminal CK to the output terminal OUT, and the transistor Q 2 is a second transistor for discharging the output terminal OUT.
  • the node (first node) connected with the gate (control electrode) of the transistor Q 1 is defined as node N 1
  • the node (second node) connected with the gate of the transistor Q 2 is defined as node N 2 .
  • the transistor Q 3 which gate is connected to the first input terminal IN 1 , is connected between the node N 1 and the first voltage signal terminal T 1
  • the transistor Q 4 which gate is connected to the second input terminal IN 2 , is connected between the node N 1 and the second voltage signal terminal T 2 . That is, the transistor Q 3 is a third transistor for providing the first voltage signal Vn to the node N 1 based on the signal (first input signal) input to the first input terminal IN 1
  • the transistor Q 4 is the fourth transistor for providing the second voltage signal Vr to the node N 1 based on the signal (second input signal) input to the second input terminal IN 2 .
  • a diode connected transistor Q 6 is connected between the node N 2 and the second power supply terminal S 2 and a transistor Q 7 , which gate is connected to the node N 1 , is connected between the node N 2 and the first power supply terminal S 1 .
  • the transistor Q 7 has the driving ability (ability to flow current) set sufficiently higher than the transistor Q 6 , and the transistors Q 6 , Q 7 configure the ratio type inverters having the node N 1 as the input end and the node N 2 as the output end.
  • the bi-directional unit shift register SR according to the present embodiment further includes a transistor Q 5 , which gate is connected to the node N 1 , connected between the node N 1 and the second voltage signal terminal T 2 .
  • the unit shift register SR k of the k th stage will be described herein by way of example. The following description is given assuming the clock signal CLK is input to the clock terminal CK of the relevant shift register SR k of the k th stage for the sake of simplification. Furthermore, the output signal of the relevant unit shift register SR k is defined as G k , the output signal of the unit shift register SR k ⁇ 1 of the previous stage (k ⁇ 1 stage) as G k ⁇ 1 , and the output signal of the unit shift register SR k+1 of the next stage (k+1 stage) as G k+1 .
  • the potential of H level of the clock signals CLK, /CLK, the first voltage signal Vn, and the second voltage signal Vr is assumed to be equal to the high potential side power supply potential VDD, and the threshold voltage of each transistor configuring the unit shift register SR is assumed to be all the same, where the value thereof is Vth.
  • the voltage signal generator 32 has the first voltage signal Vn at H level (VDD) and the second voltage signal Vr at L level (VSS).
  • the reset state in which the node N 1 is at L level (VSS), and the node N 2 at the H level (VDD-Vth) is assumed as the initial state, and the clock terminal CK (clock signal CLK), the first input terminal IN 1 (output signal G k ⁇ 1 of previous stage) and the second input terminal IN 2 (output signal G k+1 of next stage) are all assumed to be at L level. Since the transistor Q 1 is turned OFF and the transistor Q 2 is turned ON in the reset state, the output terminal OUT (output signal G k ) is maintained at L level irrespective of the level of the clock terminal CK (clock signal CLK).
  • the clock signal CLK becomes L level at time t 0 from the above state, and thereafter, the clock signal /CLK becomes H level and the output signal G k ⁇ 1 (first control pulse STn serving as start pulse for the first stage) of the unit shift register SR k ⁇ 1 of the previous stage becomes H level at time t 1 , it is input to the first input terminal IN 1 of the relevant unit shift register circuit SR k , and the transistor Q 3 is turned ON.
  • the node N 2 is at H level immediately before time t 1 , and the transistor Q 5 is turned ON, since the transistor Q 3 is set to have a driving ability sufficiently higher than the transistor Q 5 , the on-resistance of the transistor Q 3 becomes sufficiently lower than the on-resistance of the transistor Q 5 , and the level of the node N 1 rises.
  • the transistor Q 7 thereby starts to become electrically conductive, and the level of the node N 2 lowers.
  • the resistance of the transistor Q 5 then increases, the level of the node N 1 rapidly rises, and the transistor Q 7 is sufficiently turned ON.
  • the node N 2 becomes L level (VSS)
  • the transistor Q 5 is turned OFF, and the node N 1 becomes H level (VDD-Vth). That is, the state of the relevant unit shift register SRk becomes the set state.
  • the clock signal /CLK becomes L level at time t 2 , at which point the output signal G k ⁇ 1 of the previous stage returns to L level.
  • the transistor Q 3 is then turned OFF, but the set state is maintained since the node N 1 becomes H level of floating state.
  • the level of the output terminal OUT rises following thereto since the transistor Q 1 is turned ON and the transistor Q 2 is turned OFF in the set state.
  • the level of the node N 1 in the floating state is boosted by a specific voltage due to coupling via gate-channel capacity of the transistor Q 1 .
  • the driving ability of the transistor Q 1 thereby increases, and the level of the output signal Gk changes following the level of the clock terminal CK. Therefore, the output signal G k is at H level (VDD), and the gate line GL k is activated and in the selected state during the period the clock signal CLK is at H level.
  • the output signal Gk is input to the first input terminal IN 1 of the next stage, and thus the output signal G k+1 of the next stage becomes H level at time t 5 at when the clock signal /CLK becomes H level.
  • the transistor Q 4 of the unit shift register SR k is then turned ON and the node N 1 become L level, and the transistor Q 7 accordingly is turned OFF and the node N 2 becomes H level. That is, the state returns to the reset state in which the transistor Q 1 is turned OFF and the transistor Q 2 is turned ON. In this case, the transistor Q 5 is turned ON in the unit shift register SR k according to the present embodiment.
  • the node N 1 is at L level in the floating state after the transistor Q 4 is turned OFF, and thus when leakage current is generated at the transistor Q 3 , the charges involved therewith are accumulated at the node N 1 , and the potential of the node N 1 gradually rises in the conventional circuit shown in FIG. 3 .
  • the potential of the node N 1 rises while the clock signal CLK is at H level due to coupling via overlapping capacity between the drain and the gate of the transistor Q 1 .
  • the gate-source voltage of the transistor Q 1 might exceed the threshold voltage due to the potential rise of the node N 1 involved in the leakage current and the potential rise of the node N 1 of when the clock signal CLK becomes H level.
  • the malfunction problem arises in that the transistor Q 1 that is to be turned OFF is turned ON and the gate line is unnecessarily activated (first problem).
  • the voltage signal generator 32 has the first voltage signal Vn at L level (VSS) and the second voltage signal Vr at H level (VDD).
  • the second control pulse STr is input to the second input terminal IN 2 of the unit shift register SR n of the final stage as the start pulse
  • the first control pulse ST n is input to the first input terminal IN 1 of the unit shift register SR 1 of the first stage as the end pulse.
  • the basic operation of the unit shift register SR is the same as in the forward shift even if the operations of the transistor Q 3 and the transistor Q 4 are interchanged, and the transistor Q 5 also functions similar to the forward shift. Therefore, effects similar to the forward shift are obtained even if the unit shift register SR of FIG. 7 performs the operation of the reverse shift.
  • the gate line driving circuit 30 is configured as in FIG. 2 by the bi-directional unit shift register SR, and is driven by the two phase clock signals has been described in the above description, but the application of the present invention is not limited thereto.
  • the present invention is also applicable to when the gate line driving circuit 30 is configured as in FIG. 6 , and is driven by three phase clock signals.
  • FIG. 9 is a circuit diagram of a bi-directional unit shift register SR according to the second embodiment.
  • the unit shift register SR according to the present embodiment has a configuration in which a transistor Q 12 and a transistor Q 13 having a relatively large driving ability are additionally arranged with respect to the conventional circuit of FIG. 3 .
  • the transistor Q 12 is connected between the node N 2 and the first voltage signal terminal T 1 , and the gate is connected to the second input terminal IN 2 . That is, the transistor Q 12 functions to provide the first voltage signal Vn to the node N 2 (second node) based on the signal (second input signal) input to the second input terminal IN 2 .
  • the transistor Q 13 is connected between the node N 2 and the second voltage signal terminal T 2 , and the gate is connected to the first input terminal IN 1 . That is, the transistor Q 13 functions to provide the second voltage signal Vr to the node N 2 based on the signal (first input signal) input to the first input terminal IN 1 .
  • the operation of the unit shift register SR of FIG. 9 is basically similar to the conventional circuit of FIG. 3 but differs in the following aspects.
  • the unit shift register SR k of the k th stage will be described herein by way of example.
  • the first voltage signal Vn is at H level and the second voltage signal Vr is at L level.
  • the transistor Q 3 is turned ON and the node N 1 becomes H level, and the transistor Q 7 is accordingly turned ON and the node N 2 becomes L level.
  • the transistor Q 13 having a large driving ability is turned ON with the operation of the unit shift register SR k , and thus the node N 2 becomes L level (VSS) at high speed.
  • the first voltage signal Vn is at L level and the second voltage signal Vr is at H level. Therefore, in the unit shift register SR k of FIG. 9 , when the output signal G k+1 of the next stage is input to the second input terminal IN 2 , the transistor Q 12 is turned ON, and the node N 2 becomes L level (VSS) at high speed. When the output signal G k ⁇ 1 of the previous stage is input to the first input terminal IN 1 , the transistor Q 13 is turned ON, and the node N 2 becomes H level (VDD-Vth) at high speed.
  • the rise and fall of the level of the node N 2 becomes faster due to the action of the transistors Q 12 , Q 13 .
  • the transistor Q 2 is turned ON at high speed and sufficiently as the level of the node N 2 rapidly becomes H level, whereby the influence of the noise added to the output terminal OUT via the gate line is suppressed, and malfunction caused by noise is resolved (fourth problem).
  • the node N 2 rapidly becomes H level by increasing the size and increasing the driving ability of the transistor Q 6 , thereby suppressing the problem of malfunction caused by noise.
  • the transistors Q 6 , Q 7 configure the ratio type inverter, if the size of the transistor Q 6 is large, the pass through current flowing through the relevant inverter becomes large when the transistor Q 7 is turned ON and the node N 2 becomes L level (correspond to time t 1 to t 5 in FIG. 8 ), thereby increasing the power consumption.
  • the node N 2 rapidly becomes H level without increasing the size of the transistor Q 6 , and thus does not involve increase in power consumption.
  • the larger the driving ability of the transistors Q 12 , Q 13 the more the effect of having the node N 2 to H level at high speed enhances.
  • the increase in power consumption barely occurs since the transistors Q 12 , Q 13 are not simultaneously turned ON and do not form a passage for the pass through current.
  • the driving ability of the transistor Q 6 in the present embodiment only needs to be the driving ability of an extent of maintaining the node N 2 at H level after the node N 2 becomes H level, that is, an extent of at least compensating for the leakage current generated at the node N 2 . That is, advantages of having the driving ability of the transistor Q 6 smaller than the prior art, and reducing the pass through current generated at the inverter comprising transistors Q 6 , Q 7 are also obtained.
  • FIG. 10 is a circuit diagram showing a configuration of a bi-directional unit shift register according to the third embodiment.
  • the unit shift register SR according to the third embodiment has a configuration in which the transistor Q 12 and the transistor Q 13 having a relatively large driving ability shown in the second embodiment are additionally arranged with respect to the unit shift register SR ( FIG. 7 ) of the first embodiment.
  • the circuit of FIG. 7 as described in the first embodiment operates to change the node N 1 from L level to H level when the output signal G k ⁇ 1 of the previous stage is input to the first input terminal IN 1 (time t 1 in FIG. 8 ) in the operation of the forward shift, for example.
  • such operation is performed from a state in which the transistor Q 5 is turned ON, and thus the level of the node N 1 is unlikely to rise. Therefore, the rising speed of the level of the node N 1 may be slow, which inhibits the operation from being performed at high speed.
  • the unit shift register SR when the output signal G k ⁇ 1 of the previous stage is input to the first input terminal IN 1 , the transistor Q 13 having a large driving ability is turned ON, and thus the node N 2 immediately becomes L level and the transistor Q 5 is turned OFF. Thus, the level of the node N 1 rapidly rises, and the above problem does not arise. That is, according to the present embodiment, effects similar to the first embodiment are obtained by arranging the transistor Q 5 in the unit shift register SR, in which case, the rising speed of the level of the node N 1 is suppressed from becoming slow.
  • the transistor Q 12 is turned ON when the output signal G k+1 of the next stage is input to the second input terminal IN 2 , and the node N 2 immediately becomes L level, and the transistor Q 5 is turned OFF. Therefore, effects similar to the forward shift are obtained.
  • FIG. 11 is a circuit diagram of a bi-directional unit shift register SR according to the fourth embodiment.
  • the relevant unit shift register SR has a configuration in which transistors Q 3 A, Q 4 A, Q 8 , Q 9 are additionally arranged with respect to the conventional circuit of FIG. 3 .
  • the transistor Q 3 is connected to the first voltage signal terminal T 1 by way of the transistor Q 3 A
  • the transistor Q 4 is connected to the second voltage signal terminal T 2 by way of the transistor Q 4 A.
  • the gate of the transistor Q 3 A is connected to the first input terminal IN 1 similar to the gate of the transistor Q 3
  • the gate of the transistor Q 4 A is connected to the gate of the transistor Q 4 .
  • the connecting node (third node) between the transistor Q 3 and the transistor Q 3 A is defined as node N 3
  • the connecting node (fourth node) between the transistor Q 4 and the transistor Q 4 A is defined as node N 4 .
  • a diode connected transistor Q 8 (unidirectional first switching element) is connected between the output terminal OUT and the node N 3 so that the direction from the output terminal OUT to the node N 3 becomes the forward direction (direction of flowing current).
  • a diode connected transistor Q 9 (unidirectional first switching element) is connected between the output terminal OUT and the node N 4 so that the direction from the output terminal OUT to the node N 4 becomes the forward direction.
  • the transistor Q 8 flows the current from the output terminal OUT to the node N 3 and charges the node N 3 when the output terminal OUT becomes H level (when activated).
  • the transistor Q 9 flows current from the output terminal OUT to the node N 4 and charges the node N 4 when the output terminal OUT becomes H level. That is, the transistors Q 8 , Q 9 function as charging circuits for charging the nodes N 3 , N 4 .
  • FIG. 12 is a timing chart showing the operation in time of forward shift of the unit shift register SR of FIG. 11 .
  • the unit shift register SR k of the k th stage of when the gate line driving circuit 30 performs the operation of the forward shift will be described herein by way of example. That is, the first voltage signal Vn generated by the voltage signal generator 32 is at H level (VDD) and the second voltage signal Vr is at L level (VSS).
  • the reset state in which the node N 1 is at L level (VSS), and the node N 2 is at H level (VDD-Vth) is assumed as the initial state, and the clock terminal CK (clock signal CLK), the first input terminal IN 1 (output signal G k ⁇ 1 of previous stage) and the second input terminal IN 2 (output signal G k+1 of next stage) are all assumed to be at L level. Since the transistor Q 1 is turned OFF and the transistor Q 2 is turned ON in the reset state, the output terminal OUT (output signal G k ) is at L level.
  • the clock signal CLK becomes L level at time to from the above state, and thereafter, the transistors Q 3 , Q 3 A are both turned ON when the clock signal /CLK becomes H level, and the output signal G k ⁇ 1 (first control pulse STn serving as start pulse for the first stage) of the unit shift register SR k ⁇ 1 of the previous stage becomes H level at time t 1 .
  • the node N 1 thus becomes H level (VDD-Vth), and the transistor Q 7 is accordingly turned ON and the node N 2 becomes L level (VSS). That is, the relevant unit shift register SR k is in the set state.
  • the node N 3 is at H level (VDD-Vth) at this point, but the current does not flow from the node N 3 to the output terminal OUT since the transistor Q 8 functions as the diode having the direction of the output terminal OUT to the node N 3 as the forward direction.
  • the clock signal /CLK becomes L level at time t 2 , at which point the output signal G k ⁇ 1 of the previous stage returns to L level.
  • the transistors Q 3 , Q 3 A are then turned OFF, but the set state is maintained since the node N 1 becomes H level of floating state.
  • the node N 3 also becomes H level of floating state.
  • the level of the output terminal OUT rises following thereto since the transistor Q 1 is turned ON and the transistor Q 2 is turned OFF in the set state.
  • the level of the node N 1 is boosted by a specific voltage.
  • the driving ability of the transistor Q 1 thereby increases, and the level of the output signal G k changes following the level of the clock terminal CK. Therefore, the output signal G k becomes H level (VDD) during the period the clock signal CLK is at H level.
  • the diode connected transistor Q 9 is turned ON and the level of the node N 4 becomes VDD-Vth when the node N 1 is boosted, that is, when the output terminal OUT becomes H level (VDD) in the unit shift register SR of FIG. 11 .
  • the transistor Q 4 has the gate potential at VSS, and the source potential at VDD-Vth, and the gate is in a state negatively biased with respect to the source. Therefore, the leakage current between the drain and the source of the relevant transistor Q 4 is sufficiently suppressed, and the lowering in the level of the node N 1 is suppressed.
  • the output signal G k+1 of the next state becomes H level at time t 5 at when the clock signal /CLK becomes H level.
  • the transistors Q 4 , Q 4 A of the relevant unit shift register SR k are then turned ON and the node N 1 becomes L level, and the transistor Q 7 is accordingly turned OFF and the node N 2 becomes H level. That is, the state returns to the reset state in which the transistor Q 1 is turned OFF and the transistor Q 2 is turned ON.
  • the node N 4 also becomes L level at this point.
  • the first voltage signal Vn is at L level and the second voltage signal Vr is at H level, and thus when the node N 1 is boosted, high voltage is applied between the drain and the source of the transistor Q 3 , and thus the leakage current becomes a concern in the conventional circuit of FIG. 3 .
  • the current flows to the node N 3 via the transistor Q 8 when the node N 1 is boosted, and the level of the node N 3 becomes VDD-Vth.
  • the transistor Q 3 has the gate potential at VSS and the source potential at VDD-Vth, and the gate is in a state negatively biased with respect to the source. Therefore, the leakage current between the drain and the source of the transistor Q 3 is sufficiently suppressed, and lowering in the level of the node N 1 is suppressed. That is, effects similar to the forward shift are obtained.
  • FIG. 11 A configuration in which the transistors Q 3 A, Q 4 A, Q 8 , and Q 9 according to the present embodiment are arranged in the conventional circuit of FIG. 3 has been shown in FIG. 11 , but the present embodiment is also applicable to the bi-directional unit shift register SR of first to third embodiments ( FIGS. 7 , 9 , 10 ) and the like.
  • the shift register of the gate line driving circuit is configured by an amorphous silicon TFT (a-Si TFT)
  • a-Si TFT amorphous silicon TFT
  • increasing the area is facilitated and productivity is higher, and thus is widely used in the screen of a laptop PC, large screen display apparatus etc.
  • the threshold voltage shifts when the gate electrode is continuously biased, thereby affecting the driving ability.
  • the node N 3 is continuously at the positive potential (VDD-Vth), as shown in FIG. 12 , while the bi-directional unit shift register SR ( FIG. 11 ) of the fourth embodiment is performing the operation of the forward shift.
  • VDD-Vth positive potential
  • the bi-directional unit shift register SR FIG. 11
  • the transistor Q 3 A When the shift to the negative direction of the threshold voltage advances, the transistor substantially becomes a normally ON type, where the current flows between the drain and the source even if the voltage between the gate and the source is 0V.
  • the transistor Q 3 becomes normally ON, the following problems arise when the relevant unit shift register SR subsequently performs the operation of the reverse shift.
  • the transistor Q 4 A since the transistor Q 4 A is normally ON, the charges due to the current thereof flows out to the first input terminal IN 1 through the transistor Q 3 A, and the power consumption increases.
  • the effect of the fourth embodiment to suppress the leakage current of the transistor Q 3 cannot be obtained since the node N 3 cannot be sufficiently charged.
  • the bi-directional unit shift register that solves such problem is thereby proposed in the fifth embodiment.
  • FIG. 13 is a circuit diagram showing the configuration of the bi-directional unit shift register according to the fifth embodiment.
  • a transistor Q 10 which gate is connected to the second input terminal IN 2 , is arranged between the node N 3 and the first power supply terminal S 1 (VSS)
  • a transistor Q 11 which gate is connected to the first input terminal IN 1 , is arranged between the node N 4 and the first power supply terminal S 1 with respect to the unit shift register SR ( FIG. 11 ) of the fourth embodiment.
  • the transistor Q 11 is a transistor for discharging the node N 4 (fourth node) based on the signal (first input signal) input to the first input terminal IN 1
  • the transistor Q 10 is a transistor for discharging the node N 3 (third node) based on the signal (second input signal) input to the second input terminal IN 2 .
  • FIG. 14 is as timing chart showing the operation in time of the forward shift of the bi-directional unit shift register according to the fifth embodiment.
  • the relevant operation is substantially the same as that shown in FIG. 12 , and thus the detailed description will be omitted, and only the characteristic features of the present embodiment will be described.
  • the transistor Q 10 since the transistor Q 10 is turned ON when the output signal G k+1 of the next stage becomes H level at time t 5 , the node N 3 is discharged to L level (VSS) at the relevant timing.
  • L level VSS
  • the transistor Q 10 is turned OFF, but the node N 3 is in the floating state, and the node N 3 is maintained at L level until the output signal G k ⁇ 1 of the previous stage becomes H level the next time. That is, the node N 3 is charged only for about one horizontal period of time t 3 to t 5 , and the transistor Q 3 A only has gate-source and gate-drain negatively biased during the relevant period, as shown in FIG. 14 . Therefore, the threshold voltage of the transistor Q 3 A barely shifts, and the above problem is prevented.
  • the transistor Q 11 is turned ON and the node N 4 is discharged to L level (VSS) when the output signal G k ⁇ 1 of the previous stage is at H level.
  • L level VSS
  • gate-source and gate-drain of the transistor Q 4 A are prevented from continuously being negatively biased, and the threshold voltage of the transistor Q 4 barely shifts. That is, effects similar to the forward shift are obtained.
  • FIG. 15 is a circuit diagram of a bi-directional unit shift register SR according to the sixth embodiment.
  • the drains of the transistors Q 8 , Q 9 configuring the charging circuits for charging the nodes N 3 , N 4 are connected to the output terminal OUT, and the relevant transistors Q 8 , Q 9 function as diodes.
  • the drains of the transistors Q 8 , Q 9 are connected to a third power supply terminal S 3 to be supplied with a predetermined high potential side power supply potential VDD 1 .
  • the operation of the unit shift register SR of FIG. 15 is basically the same as the fifth embodiment, and similar effects are obtained.
  • the present embodiment differs from the fifth embodiment in that the supply source of the charges for charging the node N 3 and the node N 4 is not the output signal that appears at the output terminal OUT, but is the power supply for supplying the high potential side power supply potential VDD 1 .
  • the load capacity of the output terminal OUT is alleviated compared to the unit shift register SR of the fifth embodiment, and thus the charging speed of the gate line is increased. Therefore, the operation becomes faster.
  • the high potential side power supply potential VDD 1 supplied to the third power supply terminal S 3 may be the same potential as the high potential side power supply potential VDD supplied to the second power supply terminal S 2 .
  • the second power supply terminal S 2 and the third power supply terminal S 3 may be connected to each other to configure one power supply terminal.
  • the present embodiment has been described as a variant of the fifth embodiment, but is also applicable to the unit shift register SR ( FIG. 11 ) of the fourth embodiment.
  • FIG. 16 is a circuit diagram showing a configuration of a bi-directional unit shift register SR according to the seventh embodiment.
  • the sources of the transistors Q 10 , Q 11 are connected to the first power supply terminal S 1 supplied with the low potential side power supply potential VSS in the fifth embodiment, but the source of the transistor Q 10 may be connected to the second voltage signal terminal T 2 supplied with the second voltage signal Vr, and the source of the transistor Q 11 may be connected to the first voltage signal terminal T 1 supplied with the first voltage signal Vn, as shown in FIG. 16 .
  • the operation of the unit shift register SR of FIG. 16 is basically the same as the fifth embodiment. That is, in the operation of the forward shift, for example, the transistor Q 10 discharges the node N 3 , similar to the fifth embodiment, since the second voltage signal Vr is at L level. In the operation of the reverse shift, the transistor Q 11 discharges the node N 4 , similar to the fifth embodiment, since the first voltage signal Vn is at L level.
  • effects similar to the fifth embodiment are obtained in the present embodiment.
  • effects of the fifth embodiment are obtained even with the configuration of FIG. 13 or the configuration of FIG. 16 , and thus the degree of freedom of the layout of the circuit increases, thereby contributing to reduction in the circuit occupying area.
  • the present embodiment is also applicable to the unit shift register SR ( FIG. 15 ) of the sixth embodiment.
  • FIG. 17 is a circuit combining the second embodiment ( FIG. 9 ) and the fourth embodiment ( FIG. 11 ).
  • FIG. 18 is a circuit combining the first embodiment ( FIG. 7 ) and the fourth embodiment ( FIG. 11 ).
  • the fourth embodiment prevents lowering in level of the node N 1 caused by leakage current, and thus is also effective in suppressing the leakage current of the transistor Q 5 when combining the fourth embodiment and the first embodiment.
  • the source of the transistor Q 5 is connected to the first power supply terminal S 1 (VSS) by way of the transistor Q 5 A, and the connecting node (node N 5 ) between the transistor Q 5 and the transistor Q 5 A is biased with the output signal Gk.
  • the leakage current of the transistor Q 5 is reduced since the gate of the transistor Q 5 is negatively biased with respect to the source when boosting the node N 1 .
  • FIG. 18 A configuration in which the output terminal OUT is connected to the node N 5 is described in FIG. 18 , but the biasing method of the node N 5 is not limited thereto.
  • the technique of the sixth embodiment may be applied, where a transistor Q 5 B connected between the node N 5 and the third power supply terminal S 3 supplied with the predetermined high potential side power supply potential VDD 1 may be arranged, and the gate thereof may be connected to the output terminal OUT, as shown in FIG. 19 .
  • the node N 5 is biased to the potential VDD 1 when boosting of the node N 1 , and effects similar to FIG. 18 are obtained.
  • the load capacity of the output terminal OUT is alleviated compared to the case of FIG. 18 , and thus the charging speed of the gate line increases.
  • FIG. 20 is a circuit combining the first embodiment ( FIG. 7 ) and the fifth embodiment ( FIG. 13 ), and FIG. 21 is a circuit combining the first embodiment ( FIG. 7 ) and the seventh embodiment ( FIG. 16 ).
  • FIG. 22 is a circuit combining the first embodiment ( FIG. 7 ), the second embodiment ( FIG. 9 ) and the fourth embodiment ( FIG. 11 ), and FIG. 23 is a circuit combining the first embodiment ( FIG. 7 ), the second embodiment ( FIG. 9 ) and the seventh embodiment ( FIG. 16 ).
  • the bi-directional unit shift register SR can configure the gate line driving circuit 30 by being cascade connected as in FIG. 2 or FIG. 6 .
  • the first control pulse STn serving as the start pulse must be input to the first input terminal IN 1 of the leading stage (unit shift register SR 1 ) as shown in FIG. 4
  • the second control pulse STr serving as the end pulse must be input to the second input terminal IN 2 of the final stage (unit shift register SR n ) when performing the forward shift, for example.
  • the second control pulse STr serving as the start pulse must be input to the second input terminal IN 2 of the final stage, as shown in FIG. 5
  • the first control pulse STn serving as the end pulse must be input to the first input terminal IN 1 of the leading stage.
  • the drive controlling device for controlling the operation of the gate line driving circuit 30 that is to be adopted is such mounted with the output circuit of the end pulse in addition to the output circuit of the start pulse, which increases the cost (third problem).
  • the bi-directional shift register operable only with the start pulse is proposed in the ninth embodiment.
  • FIGS. 24 to 26 are views showing the configuration of the gate line driving circuit 30 according to the ninth embodiment.
  • the gate line driving circuit 30 according to the present embodiment is also configured by a bi-directional shift register comprising a plurality of stages, but a first dummy shift register SRD 1 acting as the first dummy stage is arranged in a further previous stage of the unit shift register SR 1 of the leading stage for driving the gate line GL 1 in the plurality of stages, and a second dummy shift register SRD 2 serving as the second dummy stage is arranged on the further next stage of the unit shift register SR n of the final stage for driving the gate line GL n .
  • the gate line driving circuit 30 comprises a plurality of stages including the first dummy stage at the beginning and the second dummy stage at the end.
  • Each stage of the relevant gate line driving circuit 30 may be any of the bi-directional unit shift register SR of each embodiment, or that of the prior art shown in FIG. 3 may be applied.
  • the first control pulse STn is input to the first input terminal IN 1 of the unit shift register SR 1 of the leading stage (excluding the first dummy shift register SRD 1 which is the first dummy stage), and the output signal of the previous stage is input to the first input terminal IN 1 of the subsequent stages (unit shift register SR 2 to second dummy shift register SRD 2 ).
  • the second control pulse STr is input to the first input terminal IN 1 of the first dummy shift register SRD 1 .
  • the second control pulse STr is input to the second input terminal IN 2 of the final stage (excluding the second dummy shift register SRD 2 which is the second dummy stage), and the output signal of the next stage is input to the second input terminal IN 2 of the previous stages (unit shift register SR n ⁇ 1 to first dummy shift register SRD 1 ).
  • the first control pulse STn is input to the second input terminal IN 2 of the second dummy shift register SRD 2 .
  • the unit shift register SR 1 of the leading stage, the unit shift register SR n of the final stage, the first dummy shift register SRD 1 , and the second dummy shift register SRD 2 each includes predetermined reset terminals RST 1 , RST 2 , RST 3 , RST 4 .
  • the unit shift register SR 1 of the leading stage, the unit shift register SR n of the final stage, the first dummy shift register SRD 1 , and the second dummy shift register SRD 2 each includes predetermined reset terminals RST 1 , RST 2 , RST 3 , RST 4 .
  • the output signal D 1 of the first dummy shift register SRD 1 is input to the reset terminal RST 1 of the unit shift register SR 1
  • the output signal D 2 of the second dummy shift register SRD 2 is input to the reset terminal RST 2 of the unit shift register SR n
  • the first control pulse STn is input to the reset terminal RST 3 of the first dummy shift register SRD 1
  • the second control pulse STr is input to the reset terminal RST 4 of the second dummy shift register SRD 2 .
  • the unit shift register SR 1 , the unit shift register SR n , the first dummy shift register SRD 1 , and the second dummy shift register SRD 2 are configured so as to be in the reset state (state in which the node N 1 is at L level and the node N 2 is at H level) when the signal is input to the respective reset terminals RST 1 , RST 2 , RST 3 , RST 4 (to be specifically described below).
  • each stage of each bi-directional shift register configuring the gate line driving circuit 30 is assumed to have the configuration of the bi-directional unit shift register SR ( FIG. 7 ) of the first embodiment.
  • the unit shift register SR 1 of the leading stage, the unit shift register SR n of the final stage, the first dummy shift register SRD 1 , and the second dummy shift register SRD 2 have a configuration different from the other stages as is described above, but all have the configuration of the bi-directional unit shift register SR of the first embodiment.
  • FIG. 25 is a specific circuit diagram of the first dummy shift register SRD 1 and the unit shift register SR 1 in the gate line driving circuit 30 of the present embodiment
  • FIG. 26 is a specific circuit diagram of the unit shift register SR n and the second dummy shift register SRD 2 .
  • the relevant unit shift register SR 1 has the same configuration as in FIG. 7 besides the fact that the transistor Q 3 D is connected in parallel to the transistor Q 3 .
  • the gate of the transistor Q 3 D is connected to the reset terminal RST 1 .
  • the first dummy shift register SRD 1 has the same configuration as in FIG. 7 besides the fact that the transistor Q 4 D is connected in parallel to the transistor Q 4 .
  • the gate of the transistor Q 4 D is connected to the reset terminal RST 3 .
  • the relevant unit shift register SRn has the same configuration as in FIG. 7 (i.e., same circuit configuration as first dummy shift register SRD 1 ) besides the fact that the transistor Q 4 D is connected in parallel to the transistor Q 4 .
  • the gate of the transistor Q 4 D is connected to the reset terminal RST 2 .
  • the second dummy shift register SRD 2 has the same configuration as in FIG. 7 (i.e., same circuit configuration as unit shift register SR 1 ) besides the fact that the transistor Q 3 D is connected in parallel to the transistor Q 3 .
  • the gate of the transistor Q 3 D is connected to the reset terminal RST 4 .
  • the gate line driving circuit 30 The operation of the gate line driving circuit 30 according to the present embodiment will now be described. The operation of performing the forward shift will be described first.
  • the first voltage signal Vn supplied by the voltage signal generator 32 is set at H level, and the second voltage signal Vr is set at L level.
  • the transistor Q 4 D of the first dummy shift register SRD 1 and the transistor Q 4 D of the unit shift register SR n operate to discharge the node N 1 .
  • the unit shift registers SR 1 to SR n are assumed to be already in the reset state (state in which the node N 1 is at L level, and node N 2 is at H level) for the sake of simplifying the description.
  • FIG. 27 is a timing chart showing the operation in time of forward shift of the gate line driving circuit 30 according to the present embodiment.
  • the first control pulse STn serving as the start pulse is input to the first input terminal IN 1 of the unit shift register SR 1 of the leading stage at a predetermined timing in the forward shift.
  • the unit shift register SR 1 thereby becomes the set state (state in which the node N 1 is at H level and the node N 2 is at L level).
  • the second control pulse STr is not activated and maintained at L level.
  • the first control pulse STn (start pulse) is input to the reset terminal RST 3 of the first dummy shift register SRD 1 and the second input terminal IN 2 of the second dummy shift register SRD 2 .
  • the transistor Q 4 D is turned ON, the node N 1 becomes L level, and the state of the first dummy shift register SRD 1 becomes the reset state. Therefore, the output signal D 1 of the first dummy shift register SRD 1 becomes L level, and the transistor Q 3 D of the unit shift register SR 1 is turned OFF.
  • the transistor Q 4 is turned ON, the node N 1 becomes L level, and the state of the second dummy shift register SRD 2 also becomes the reset state. Therefore, the output signal D 2 of the second dummy shift register SRD 2 becomes L level and the transistor Q 3 D of unit shift register SR 1 is turned OFF.
  • the signal is sequentially transmitted to the unit shift registers SR 1 to SR n and the second dummy shift register SRD 2 as shown in FIG. 27 in synchronization with the clock signals CLK, /CLK according to the operation of forward shift similar to the first embodiment, and the output signals G 1 , G 2 , G 3 , . . . , G n , D 2 sequentially become H level.
  • the output signal D 2 of the second dummy shift register SRD 2 becomes H level immediately after the unit shift register SR n of the final stage outputs the output signal G n .
  • the output signal D 2 is input to the reset terminal RST 2 of the unit shift register SR n , whereby the relevant transistor Q 3 D is turned ON and the relevant unit shift register SRn becomes the reset state. That is, the output signal D 2 functions as the end pulse of having the unit shift register SR n of the final stage in the reset state.
  • the second dummy shift register SRD 2 becomes the reset state by the first control pulse STn serving as the start pulse of the next frame, and thus is similarly operable in the next frame.
  • the operation of performing the reverse shift will now be described.
  • the first voltage signal Vn is at L level
  • the second voltage signal Vr is H level in the reverse shift.
  • the transistor Q 3 D of the unit shift register SR 1 and the transistor Q 3 D of the second dummy shift register SRD 2 operate to discharge the node N 1 .
  • the unit shift registers SR 1 to SR n are also assumed to be already in the reset state (state in which the node N 1 is at L level, and the node N 2 is at H level).
  • FIG. 28 is a timing chart showing the operation in time of reverse shift of the gate line driving circuit 30 according to the present embodiment.
  • the second control pulse STr serving as the start pulse is input to the second input terminal IN 2 of the unit shift register SRn of the final stage at a predetermined timing in the reverse shift.
  • the unit shift register SRn thereby becomes the set state (state in which the node N 1 is at H level, and the node N 2 is at L level).
  • the first control pulse STn is not activated and maintained at L level.
  • the second control pulse STr (start pulse) is input to the first input terminal IN 1 of the first dummy shift register SRD 1 and the reset terminal RST 4 of the second dummy shift register SRD 2 .
  • the transistor Q 3 is turned ON, and the node N 1 becomes L level, and the state of the relevant first dummy shift register SRD 1 becomes the reset state. Therefore, the output signal D 1 of the first dummy shift register SRD 1 becomes L level, and the transistor Q 3 D of the unit shift register SR 1 is turned OFF.
  • the transistor Q 3 D is turned ON, the node N 1 becomes L level, and the state of the second dummy shift register SRD 2 also becomes the reset state. Therefore, the output signal D 2 of the second dummy shift register SRD 2 becomes at L level, and the transistor Q 4 D of the unit shift register SRn is turned OFF.
  • the signal is sequentially transmitted to the unit shift registers SR 1 to SR n and the first shift register SRD 1 as shown in FIG. 28 in synchronization with the clock signals CLK, /CLK according to the operation of reverse shift similar to the first embodiment, and the output signals G n , G n ⁇ 1 , G n ⁇ 2 , . . . , G 1 , D 1 sequentially become H level.
  • the output signal D 1 of the first dummy shift register SRD 1 becomes H level immediately after the unit shift register SR 1 of the leading stage outputs the output signal G 1 .
  • the output signal D 1 is input to the reset terminal RST 1 of the unit shift register SR 1 , whereby the relevant transistor Q 3 is turned ON and the relevant unit shift register SR 1 becomes the reset state. That is, the output signal D 1 functions as the end pulse of having the unit shift register SR 1 of the leading stage in the reset state.
  • the first dummy shift register SRD 1 becomes the reset state by the second control pulse STr serving as the start pulse of the next frame, and thus is similarly operable in the next frame.
  • the operation of the forward shift and the reverse shift can be performed with only the start pulse without using the end pulse in the bi-directional shift register. That is, the drive controlling device for controlling the operation of the gate line driving circuit 30 only needs to include the output circuit of the start pulse, and the problem of increase in cost (third problem) is resolved.
  • the transistor Q 3 D or the transistor Q 4 D arranged in the unit shift register SR 1 , SR n , and the first and second dummy shift registers SRD 1 , SRD 2 of the bi-directional shift register of the present embodiment function to discharge the corresponding nodes N 1 .
  • the size of the transistors Q 3 D, Q 4 D may be small compared to the transistors Q 3 , Q 4 , and may be about 1/10 and the like.
  • the parasitic capacity of the node N 1 becomes large when the size of the transistors Q 3 D, Q 4 D is large, the action of boosting the node N 1 by the clock signal CLK or /CLK becomes small.
  • the driving ability of the transistor Q 1 becomes lower, and thus it is desirably small to a certain extent.
  • Each stage of the bi-directional shift register has a configuration of the unit shift register SR of the first embodiment in the above description, but the bi-directional unit shift register SR applied to the present embodiment may be the bi-directional unit shift register SR of each embodiment or that of the prior art shown in FIG. 3 may be applied, as described above.
  • the transistor Q 3 D parallel connected to the transistor Q 3 is arranged in the unit shift register SR 1 of the leading stage, the transistor Q 4 D parallel connected to the transistor Q 4 is arranged in the unit shift register SR n of the final stage, the transistor Q 4 D parallel connected to the transistor Q 4 is arranged in the first dummy shift register SRD 1 , and the transistor Q 3 D parallel connected to the transistor Q 3 is arranged in the second dummy shift register SRD 2 .
  • a transistor must be added in parallel to the transistors Q 3 A, Q 4 A when connecting the transistor Q 3 to the first voltage signal terminal T 1 by way of the transistor Q 3 A and connecting the transistor Q 4 to the second voltage signal terminal T 2 by way of the transistor Q 4 A as in the fourth embodiment ( FIG. 11 ) and the fifth embodiment ( FIG. 13 ).
  • FIGS. 29 and 30 show an example in which the unit shift register SR of the fourth embodiment ( FIG. 11 ) is applied to each stage of the gate line driving circuit 30 of the present embodiment.
  • the transistors Q 3 D, Q 3 AD are arranged in parallel to the transistors Q 3 , Q 3 A, respectively, in the unit shift register SR 1 of the leading stage, and the gates thereof are connected to the reset terminal RST 1 .
  • the transistors Q 4 D, Q 4 AD are arranged in parallel to the transistors Q 4 , Q 4 A, respectively, in the first dummy shift register SRD 1 , and the gates thereof are connected to the reset terminal RST 3 .
  • the transistors Q 4 D, Q 4 AD are arranged in parallel to the transistors Q 4 , Q 4 A, respectively, in the unit shift register SR 1 of the final stage, and the gates thereof are connected to the reset terminal RST 2 .
  • the transistors Q 3 D, Q 3 AD are arranged in parallel to the transistors Q 3 , Q 3 A, respectively, in the second dummy shift register SRD 2 , and the gates thereof are connected to the reset terminal RST 4 . According to such configuration, the operation of the forward shift and the reverse shift are possible only with the start pulse similar to the above.
  • the transistors Q 3 D, Q 3 AD, Q 4 D, Q 4 AD respectively function to discharge the level of the node N 1 , and thus the size thereof may be small compared to the transistors Q 3 , Q 3 A, Q 4 , Q 4 A, and may be about 1/10 and the like. Since the parasitic capacity of the node N 1 becomes large when the size of the transistors Q 3 D, Q 3 AD, Q 4 D, Q 4 AD is large, the action of boosting the node N 1 by the clock signal CLK or /CLK becomes small, thereby lowering the driving ability of the transistor Q 1 . Thus, it is desirable to be small to a certain extent.

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CN101064194B (zh) 2010-06-23
KR100847091B1 (ko) 2008-07-18
US20070248204A1 (en) 2007-10-25
TW200746168A (en) 2007-12-16
CN101064194A (zh) 2007-10-31
JP4912023B2 (ja) 2012-04-04
KR20070105242A (ko) 2007-10-30
JP2007293995A (ja) 2007-11-08

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