TWI778223B - 用於處理裝置的技術 - Google Patents

用於處理裝置的技術 Download PDF

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TWI778223B
TWI778223B TW108104470A TW108104470A TWI778223B TW I778223 B TWI778223 B TW I778223B TW 108104470 A TW108104470 A TW 108104470A TW 108104470 A TW108104470 A TW 108104470A TW I778223 B TWI778223 B TW I778223B
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substrate
bonding surface
die
bonding
dies
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TW108104470A
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TW201937584A (zh
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賽普里恩 艾米卡 烏佐
蘿拉 威爾 麥卡雷米
桂蓮 高
蓋烏斯 吉爾曼 方騰二世
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美商英帆薩斯邦德科技有限公司
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

本發明的代表性技術提供用於形成微電子組裝件之製程步驟，其包括製備用於接合之微電子組件，諸如晶粒、晶圓、基板及類似者。該等微電子組件之一或多個表面經形成及製備為接合表面。該等微電子組件在該等所製備接合表面處無黏合劑之情況下經堆疊及接合。

Description

用於處理裝置的技術
以下描述係關於積體電路（「IC（integrated circuits）」）。更特定而言，以下描述係關於製造IC晶粒及晶圓。優先權主張及相關申請案之交叉參考
本申請案主張2019年1月30日申請之美國非臨時申請案第16/262,489號及2018年2月15日申請之美國臨時申請案第62/631,216號之權益，該些申請案以全文引用之方式併入本文中。
微電子元件通常包含半導體材料（諸如，矽或砷化鎵）之較薄厚塊，其通常稱為半導體晶圓。晶圓可經形成為包括晶圓表面上及/或部分嵌入晶圓內之多個積體晶片或晶粒。與晶圓分隔開之晶粒通常經設置為個別經預封裝單元。在一些封裝設計中，晶粒經黏著至基板或晶片載體，該基板或晶片載體繼而經黏著在諸如印刷電路板（printed circuit board；PCB）之電路板上。舉例而言，許多晶粒經設置於適合於表面黏著的封裝中。
經封裝半導體晶粒亦可經設置於「堆疊式（stacked）」配置中，其中一個封裝經設置於（例如）電路板或其他載體上，且另一封裝經黏著在第一封裝之頂部上。此等配置可允許將多個不同晶粒黏著在電路板上之單個覆蓋面積內，且可進一步藉由在封裝之間提供短互連件來促進高速操作。通常，此互連距離可僅略大於晶粒自身之厚度。對於將在晶粒封裝之堆疊內達成的互連，用於機械及電氣連接之互連結構可設置於每一晶粒封裝（除了最頂部封裝）以外之兩側（例如，面）上。
另外，晶粒或晶圓可以三維配置經堆疊作為各種微電子封裝方案之部分。此可包括在較大基板晶粒、裝置、晶圓、基板或類似者上堆疊一或多個晶粒、裝置及/或晶圓之層，以豎直或水平配置堆疊多個晶粒或晶圓，以及兩者之各種組合。晶粒或晶圓可使用各種接合技術以堆疊式配置接合，該等接合技術包括直接介電質接合、無黏合劑技術（諸如ZiBond®）或混合式接合技術（諸如DBI®），兩者可自Invensas接合技術公司（先前是Ziptronix公司）、Xperi公司購得（例如，參見美國專利第6,864,585號及第7,485,968號，其全文併入本文中）。
對於實施堆疊式晶粒及晶圓配置可存在多種挑戰。當使用直接接合或混合接合技術來接合堆疊式晶粒時，通常期望待接合之晶粒的表面為極平坦、平滑且清潔的。舉例而言，大體地，該等表面應在表面拓樸上具有極低偏差且具有低含量之雜質、粒子或其他殘餘物。移除粒子或殘餘物可改善表面之清潔度及平坦度以及層之間的接合之可靠性，然而，粒子及殘餘物之移除有時可能存在問題。
揭示代表性技術及裝置，該等技術包括用於形成新穎微電子組裝件之製程步驟。製程包括製備用於接合之微電子組件，諸如晶粒、晶圓、基板及類似者。在各種實施方案中，微電子組件之一或多個表面經形成及製備為接合表面。微電子組件在所製備接合表面處無黏合劑之情況下經堆疊及接合。
在各種實施方案中，用於形成微電子組裝件之方法包括製備第一基板之接合表面，其包括：使第一基板之接合表面平坦化以具有第一預定最小表面偏差且電漿活化第一基板之接合表面。方法進一步包括製備第二基板之第一接合表面，其包括使第二基板之第一接合表面平坦化以具有第二預定最小表面偏差。
在一實施方案中，方法包括將第二基板安裝至由分割框架保持之分割板或分割帶，且在將第二基板安裝至分割板或分割帶時將第二基板單粒化為複數個晶粒。複數個晶粒中之每一晶粒具有第一接合表面，該第一接合表面包含第二基板之第一接合表面的一部分。
該方法可包括在將複數個晶粒安裝至分割板或分割帶時處理複數個晶粒，使用拾放工具來選擇複數個晶粒中之一晶粒，且在無黏合劑之情況下及在未活化晶粒之第一接合表面之情況下將晶粒之第一接合表面直接接合至第一基板之接合表面。
在額外實施方案中，技術及方法包括製備用於將額外晶粒（或多個額外晶粒）接合至經接合晶粒之第二基板或複數個晶粒（或單個晶粒）之背側。
在一些實施方案中，獨特集合之處理步驟用於清潔第一基板及/或第二基板之接合表面或晶粒之接合表面。舉例而言，在一些具體實例中，一或多個獨特處方集可用於清潔。在其他具體實例中，超高頻音波換能器及/或機械式毛刷可用於幫助清潔。
在一替代實施方案中，基板或晶粒中之一或多者之接合表面在處理期間可塗佈有一或多個保護塗層。舉例而言，在一個具體實例中，個別保護塗層可使接合表面呈現疏水性或親水性。塗層可防止對接合表面之污染，在處理期間保護接合表面免遭損壞，或類似者。在其他製程步驟期間可移除塗層中之一或多者。另外，對組件進行處置之處理工具中之一或多者在處置期間可經塗佈或形成為疏水性的以作為一種用於防止清潔組件之污染的技術。
參考電氣及電子組件以及變化之載體論述各種實施方案及配置。雖然提及具體組件（即，晶粒、晶圓、積體電路（IC）晶片晶粒、基板等），但此不意欲為限制性的，且係為了易於論述及便於說明。參考晶圓、晶粒、基板或類似者論述之技術及裝置適用於任一類型或數目之電氣組件、電路（例如，積體電路（IC）、混合電路、ASIC、記憶體裝置、處理器等）、組件之群組、封裝式組件、結構（例如，晶圓、面板、板、PCB等）及類似者，其可經耦接以彼此介接，與外部電路、系統、載體及類似者介接。此等不同組件、電路、群組、封裝、結構及類似者中之每一者可通常稱作「微電子組件（microelectronic component）」。為簡單起見，除非另外規定，否則接合至另一組件之組件將在本文中稱作「晶粒（die）」，且晶粒所接合之其他組件將在本文中稱作「基板（substrate）」。
在下文使用複數個實例來更詳細地解釋實施方案。儘管在此處且在下文論述各種實施方案及實例，但其他實施方案及實例可藉由組合個別實施方案及實例之特徵及元件來成為可能。
概述
參考圖1A至1C，在各種實例中，揭示用於處理待堆疊且直接或緊密接合之裝置的技術。本發明描述包括將一或多個晶粒102接合至基板104之實例製程。然而，製程亦可用於將晶圓接合至晶圓，將晶粒接合至晶粒，將晶粒接合至晶圓等等。附圖中之圖式展示一些用於形成及製備用於接合之基板104（且特定言之，基板104之接合表面108）的製程，及其他用於形成及製備用於接合至基板104及接合至其他晶粒102之一或多個晶粒102（且特定言之，晶粒102之接合表面106及110）的製程。在此等製程結束時，一或多個晶粒102經接合（直接接合，例如，在無黏合劑之情況下）至基板104或另一晶粒102。當兩個表面（106與108及/或106與110）結合在一起時，接合係在環境條件下進行之自發性製程。
在圖1A至1C處說明展示實例晶粒102及實例基板104之剖面圖。圖1A說明在接合之前的晶粒102及基板104，且圖1B展示在接合後之晶粒102及基板104。圖1C展示在將晶粒102A接合至基板104後，例如藉由將晶粒102B堆疊且接合至晶粒102A來將多個晶粒102接合至基板104。額外晶粒102（C-N）可視需要以類似方式堆疊且接合至晶粒102B。
在各種具體實例中，實例晶粒102或實例基板104可包括由晶粒102之接合表面（106、110）或基板104之接合表面108上之絕緣材料（例如，氧化物）包圍之一或多個導電跡線或互連件（圖中未示）。舉例而言，晶粒102或基板104可包括判定晶粒102或基板104之功能（例如，記憶體、處理程序、可程式化邏輯等）的多個導電及絕緣層（圖中未示）。接合表面（106、108或110）上之經曝露互連件可以電氣方式與各種導電層為連續的，且提供用於晶粒102或基板104之介面。
當使用直接接合或混合接合技術將晶粒102接合至基板104（或將晶粒接合至晶粒，將晶粒接合至晶圓，將晶圓接合至晶圓等）時，通常期望待接合之晶粒102及基板104之表面為極平坦及平滑的。舉例而言，大體上，接合表面（106與108及106與110）在表面拓樸上應具有極低偏差（即，奈米級偏差，例如低於2 nm及較佳地低於0.5 nm），使得接合表面（106與108及106與110）可緊密配合以形成持久接合。通常亦期望接合表面（106與108及106與110）為清潔的且具有大小足夠大以產生接合空隙之低含量之雜質、粒子或其他殘餘物，該等接合空隙會引起電氣連續性故障或其他接合缺陷。
舉例而言，處理步驟中殘存之粒子及殘餘物可引起堆疊式晶粒102與基板104之間的接合介面處之空隙。若空隙大體上小於金屬電互連件大小，則其可為可接受的。然而，通常不能容許引起大小接近或超過電互連件大小之接合缺陷的粒子。此外，由於暫時性載體及基板在經移除時可殘留甚至在清潔後仍存留之接合殘餘物，因此暫時地接合晶粒、晶圓及基板以供處理或處置（例如，使用聚合層或無機層等以供暫時性接合）亦可存在問題。
來自暫時性黏合劑層之可包含高溫聚合物及類似者之殘餘物可為非連續的，其中晶粒表面106及110或基板表面108上之厚度不同（例如，厚度可介於10 nm至50 um範圍內）。電漿清潔（諸如用氧電漿進行灰化）可用於移除薄的殘餘物，但甚至長的氧電漿灰化步驟（例如，超過40分鐘）可能對移除最厚殘餘物為無效的。另外，長的氧灰化製程可易於氧化接合表面（106、110及/或108）上之導電特徵且減小清潔表面之平面度。
舉例而言，接合表面（106、110及/或108）可包括凹入式導電特徵，其中標稱導電層凹部為相鄰介電質層或表面之表面下之約1 nm至20 nm。在晶圓或晶粒表面之長的氧灰化後，先前凹入之導電特徵可大體上變化從而干擾接合或接合後之金屬互連件之形成。舉例而言，先前凹入之導電特徵可現在相鄰介電質區之表面上方突出。在一些情況下，取決於灰化製程參數，導電特徵之突出部可介於3 nm至30 nm範圍。接合表面（106、110及/或108）上方之此等導電突點可妨礙或防止接合層或表面之緊密配合。
在此類情況下，高溫（例如，高於50℃）濕式製程有時用於移除厚殘餘物；然而，此類製程不可與其他晶粒102或基板104層或材料相容。舉例而言，高溫濕式製程可降級晶粒102或基板104之經拋光金屬層，從而降低裝置良率。此外，高溫不可與一些晶粒102或基板104處理組件（例如，塑膠分割帶、夾環等）相容。
在一些習知晶圓清潔製程中，包括侵蝕性清潔溶液之濕式化學清潔溶液可自晶圓之表面有效地移除有機殘餘物。舉例而言，在50℃與80℃之間的溫度下用過氧化氫在氫氧化胺、硫酸或氫氯酸及其各種組合之溶液中之混合物來清潔晶圓可製備原始晶圓表面。然而，由於此等侵蝕性濕式化學物質將不僅清潔聚合殘餘物及粒子，其亦可溶解通常包含諸如銀、銅、鎳及其各種合金之材料的大部分實用導電特徵，因此此類侵蝕性清潔步驟將通常不適宜來清潔晶粒102之接合表面106及110。 代表性製程
圖2至7B說明用於形成及製備用於接合（諸如，用於在無黏合劑之情況下直接接合）之微電子組件（諸如，晶粒102及基板104）之代表性製程200至750。製程200至750包括提供微電子組件上之接合表面（諸如，接合表面106、110及108）或在一些實例中提供兩個接合表面（諸如單個晶粒102上之接合表面106及110），使接合表面平坦化，清潔及活化（在一些實例中）接合表面，及類似者。
描述製程200至750之次序不意欲經理解為限制性，且製程200至750中之任一者中的任何數目之所描述製程區塊可按任何次序組合以實施該等製程或替代製程。另外，可在不脫離本文中所描述之主題之精神及範圍的情況下自製程中之任一者刪除個別區塊。此外，製程200至750可以任何適合之硬體、軟體韌體或其組合實施，而不脫離本文中所描述之主題之範圍。
在替代實施方案中，其他技術可以各種組合包括於製程200至750中，且保持在本發明之範圍內。 用於形成及製備基板之實例技術
在圖2處說明實例基板104形成製程200。在各種具體實例中，基板104可包含矽、鍺、介電質表面、直接或間接帶隙半導體材料或層或另一適合的材料。在區塊202處，製程包括製造基板104。簡要地，形成基板104可包括製造基板104中之裝置（諸如所關注之前端製程（the front end of the line；FEOL）、多層後端製程（backend of the line；BEOL）及其他結構）、清潔基板104之表面等等。
在區塊204處，製程包括在基板104之第一（前方）表面108上形成直接接合層。用於接合層之材料可沉積或形成於第一表面108上，且可包含無機介電質材料層，諸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、氮碳化物、金剛石、金剛石類材料、玻璃、陶瓷、玻璃陶瓷及類似者，或無機介電質層與一或多個金屬特徵之組合。在一些具體實例中，金屬特徵可自介電質表面略微凹入，例如介電質之表面下之1 nm至20 nm。在一些具體實例中，形成直接接合層可併入至晶圓製造製程（諸如，區塊202）中作為最後形成之金屬層。在一個具體實例中，最後一個金屬化介電質層之平坦表面可包含接合表面108，且形成接合層108之額外金屬化介電質塗層可能不為必要的。
形成直接接合層包括對第一表面108（即，接合表面）進行表面處理（finish）以符合介電質粗糙度規格及金屬層（例如，銅等）凹部規格從而製備用於直接接合之表面108。換言之，接合表面108經形成為儘可能平坦及平滑的，且具有極小表面拓樸偏差。諸如化學機械拋光（chemical mechanical polishing；CMP）之各種習知製程可用於達到低表面粗糙度。金屬層可經組態以提供電路徑及/或熱路徑，或可替代地經組態以經由使用所謂的虛設襯墊、軌跡、圖案或類似者來平衡金屬化物。
在區塊206處，基板104之接合表面108經清潔及/或活化以備用於直接接合，如下文所描述。 用於形成及製備晶粒之實例技術
圖3說明用於由晶圓（其亦可稱作「第二基板」，且其可包含類似或相同材料且以與上文參考基板104所描述類似或相同之製程及技術形成）形成單側或雙側晶粒102之實例製程300。在一實施方案中，製造晶圓且形成具有接合表面之表面拓樸要求之（前方）接合表面106的製程步驟302及304實質上與上文在製程200之區塊202及204處參考基板104所描述的相同。
在區塊306處，在使晶圓之接合表面106平坦化（例如，藉由CMP製程）以實現所需拓樸後，保護塗層（諸如抗蝕劑或其他適合的材料）經塗覆至晶圓之接合表面以保護接合表面106免遭污染、保護經曝露金屬層免遭腐蝕且在單粒化操作期間保護接合表面106，該等單粒化操作可易於在晶粒102之前方及側表面上產生殘渣。
另外或替代地，晶圓之背部表面可經處理（例如，貫穿晶粒之導體顯露、平坦化等），從而形成晶粒102上之亦可塗佈有保護塗層之背部接合表面110，或類似者。
在一些具體實例中，超過一個類型之保護層可塗覆至晶圓表面。舉例而言，第一保護層可包含疏水性保護層，且疏水層之上可為親水性保護層。在該實例中，下伏疏水層允許在清潔晶粒102之側表面期間使用侵蝕性蝕刻化學品，且亦增長所製備表面106及110之存放期。在一些情況下，上覆親水層接收或浸漬有在分割製程期間所產生之粒子、殘渣、分割帶、黏合劑等。親水層以及粒子及殘渣經移除。疏水層可暫時地維持完好以在後續處理或儲存期間保護表面106（及/或110）。
在一些情況下，如在區塊308處所展示，自非保護側面薄化晶圓以實現所需厚度。在區塊310處，晶圓安裝至框架上之分割帶且經單粒化（區塊312）以形成晶粒102。可使用鋸、雷射（例如，隱形雷射）、電漿蝕刻製程或其他適合的技術將晶圓單粒化為一定數量之晶粒102。在各種實例中，在晶圓安裝至由框架保持之分割板或分割層或分割帶（或類似者）時，晶粒102經單粒化。
在分割後，分割帶上之經分割晶圓可根據需要擴展且安裝至夾環中。在各種實例中，框架或夾環可包含塑膠部分、金屬部分、其組合及類似者。分割帶可為行業中普遍使用的任何類型之分割帶。一個實例分割帶包括UV釋放帶。在一些實例中，晶粒102可在處於夾環或分割框架上時經運送。 形成及製備晶粒雙側晶粒之實例
圖4說明用於形成雙側晶粒102之實例製程400，其中晶粒102之兩個表面（106及110）將接合至基板104或接合至其他晶粒102，諸如具有多個晶粒對晶粒或晶粒對晶圓應用（例如，如圖1C中所展示）。在區塊402處，製程包括製造用於晶粒102之晶圓，其可包括在貫穿用於未來貫穿裝置連接之晶粒102之所需位置處製造矽穿孔（through-silicon-vias；TSV）。在各種具體實例中，晶圓可由矽、鍺或另一適合的材料製成。
在區塊404處，製程包括在晶粒102之第一（前方）表面106上形成直接接合層。用於接合層之材料可沉積或形成於第一表面106上，且可包含無機介電質材料層或無機介電質層與一或多個金屬特徵之組合，如參考圖2所描述。類似地，如較早所論述，最後一個金屬化介電質層之平坦表面可包含接合表面106，且形成接合層106之額外金屬化介電質塗層可不為必要的。
形成直接接合層包括對第一表面106（即，接合表面）進行表面處理以符合介電質粗糙度規格及金屬層（例如，銅等）凹部規格從而製備用於直接接合之表面106。換言之，接合表面106經形成為儘可能平坦及平滑的，且具有極小表面拓樸偏差。諸如化學機械拋光（CMP）之各種習知製程可用於達到低表面粗糙度。
在一實施方案中，在區塊406處，待單粒化為晶粒102之晶圓之所製備前方表面經直接接合為支援晶圓（例如，在一個實例中，「矽載體（silicon carrier）」，但亦可使用其他材料之載體），以供在第二（背部）接合表面110之製造期間處置晶圓。在一個實例中，使用Zibond直接接合技術將晶圓之第一表面接合至矽晶圓，如上文所描述。
在各種具體實例中，將矽載體直接接合至晶圓具有多個優勢。舉例而言，此技術消除對背側晶圓處理之任何溫度限制。此外，矽載體可具有類似或緊密匹配之熱膨脹係數（coefficient of thermal expansion；CTE），從而在處理期間減少或消除晶圓之翹曲。此可改善與晶圓直接接合之成果及可靠性。此外，直接接合矽載體實現超薄晶圓以直接接合至其他晶粒、晶圓、基板等，其中以其他方式其將不可能實現。
在區塊408處，在形成及拋光第二接合表面110之前，矽基板可經薄化，且TSV經曝露。在晶圓之背側上，晶粒102之第二接合表面110經形成及表面處理（如上文所描述）以符合最大介電質粗糙度規格及金屬層（例如，銅等）凹部規格，且具有極小表面拓樸偏差。另外，保護塗層可塗覆至經拋光之第二接合表面110。
在區塊410處，晶圓之第二表面110可隨後使用黏合劑經接合至暫時性支援晶圓，以處置用於前側106處理之晶圓。在區塊412處，使用一或多種技術自晶圓之第一表面106移除矽支援晶圓，該等技術包括蝕刻、溶解、研磨或類似者。執行移除製程以確保在已移除支撐晶圓後，第一表面106保留用於未來直接或混合接合之介電質層及任何導電層。
在區塊414處，一或多個保護塗層可塗覆至經曝露第一表面106。在一些具體實例中，超過一種類型之保護層可塗覆至第一表面106。舉例而言，第一保護層可包含疏水性保護層，且重疊疏水層可為親水性保護層（如上文所描述）。
在區塊416處，自晶圓之背部表面110移除暫時性載體及暫時性接合黏合劑。在區塊418處，經表面處理之雙側晶圓隨後安裝至框架上之分割帶且經單粒化以形成一定數量之雙側晶粒102（區塊420）。視情況，經分割晶圓可轉移至夾環（區塊422）以備用於接合（區塊424）。
參看圖5，在由製程500所說明之替代具體實例中，，矽載體不使用直接接合技術接合至晶圓。替代地，在參考圖4如上文所描述地製造（區塊502）及形成/表面處理第一接合表面（區塊504）後，使用暫時性接合黏合劑將第一表面106接合至支持載體（區塊506）以用於製造第二（背側）110接合表面。
在區塊508處，晶圓可視需要經薄化，從而曝露TSV。第二接合層110如上文所描述地經形成及表面處理。在區塊510處，一或多個保護塗層可在分割之前塗覆至一或多個所製備接合表面（106及/或110）。在形成及表面處理第二接合表面110後，暫時性載體及暫時性黏合材料經移除（區塊512）。經表面處理之雙側晶圓隨後安裝至框架上之分割帶或分割層（區塊514），例如，且經單粒化（區塊516）以形成一定數量之雙側晶粒102。視情況，經分割晶圓可轉移至夾環（區塊518）以備用於接合（區塊520）。 清潔及製備基板
圖6A及6B之說明分別展示實例製程600及650，從而描述清潔及製備用於接合之基板104（製程600）及晶粒102（製程650）。此外，儘管該等說明（及相關描述）描述將晶粒102接合至基板104，但製程可用於將晶圓接合至晶圓，將晶粒接合至晶粒，將晶粒接合至晶圓等等。另外，此等製程中所描述之基板104亦可指已黏著至另一晶粒102或較大基板（諸如，晶圓）之晶粒102之背側110。
參考圖6A，製程600展示基板104之接合表面108之製備。在一些具體實例中，緊接的為製程600，或該製程概述於圖2處所說明之製程200之區塊206內。舉例而言，在區塊602處，例如藉由濕式製程用溶劑來清潔基板104之接合表面108。緊接的為區塊604，其包括利用氧電漿（通常稱為灰化）或其他電漿化學物質之乾式清潔製程，以移除任何無機及有機污染物。舉例而言，電漿可經由大氣壓、下游或反應性離子蝕刻（reactive ion etching；RIE）製程而提供。
基板104可隨後經再清潔，其包括用去離子或弱鹼性的水或其他適合的溶液洗滌以移除來自灰化製程之任何粒子。在區塊606處，舉例而言，使用氮電漿製程來活化接合表面108，以製備用於接合之基板表面108。在各種實例中，已知該活化製程改善接合晶粒102對基板104之接合強度。類似地，舉例而言，活化步驟可經由大氣壓、下游或反應性離子蝕刻（RIE）製程而提供。亦可用去離子水沖洗基板104以移除來自活化製程之粒子，如區塊608處所展示。 清潔及製備晶粒
參考圖6B，展示用於製備一或多個晶粒102之第一接合表面106之製程650。在一些具體實例中，緊接的為製程650，或該製程分別概述於圖3、4及5之區塊316、424或520或類似者內。舉例而言，在區塊652處，製備晶粒102之第一接合表面106包括自接合表面106移除保護層。在區塊654及656處，一或多個接合表面106經清潔。舉例而言，一或多個替代或視情況選用之製程階段可用於移除任何無機及有機污染物，該等製程階段包括利用溶劑之濕式清潔、利用氧電漿（通常稱為灰化）或使用其他電漿化學物質之之乾式清潔或類似者。乾式清潔可由諸如大氣壓、下游或RIE製程之電漿製程執行。
在一些情況下，在晶粒102藉由框架或夾環（例如，經由濕式製程）保持在分割帶上時，可自晶粒102清除一或多個保護層，其亦清潔由分割製程產生之殘渣。當使用UV釋放帶時，可根據需要在晶粒清潔製程之前或在晶粒清潔製程後執行減小晶粒102與該釋放帶之間的黏合強度以釋放晶粒102之UV曝露。
在各種具體實例中，利用可移除保護塗層而不腐蝕下方金屬層（例如，銅）之化學品（例如，溶劑、蝕刻劑、水等）來清潔晶粒102。舉例而言，清潔化學品可包括過氧化氫在氫氧化胺或酸之溶液中之混合物。金屬鈍化化合物（例如，三唑部分）可用於抑制諸如銀、銅、鎳及其各種合金之導電特徵之金屬蝕刻。可自接合表面106之金屬部分清潔或沖洗此等化學品及鈍化化合物。
在分割製程期間，晶圓之粒子（例如，矽粒子）可藉由分割輪或分割線之機械作用而嵌入於分割帶中。在將晶粒自分割帶直接取放轉移至接合層期間，此等嵌入型粒子可污染清潔晶粒102之邊緣及表面，該等表面包括接合表面106。相應地，自清潔接合表面106減少或消除嵌入型粒子極為重要。在一個實例中，晶粒102可重新安裝至相同或類似材料或另一適合材料之新製分割帶薄板上，從而丟棄原分割帶。此可進行以移除嵌入型污染物或允許使用不與原分割帶相容之化學品。
替代地，可利用更劇烈之晶粒102清潔來移除分割帶中所捕集之污染物，該清潔包括超高頻音波震盪、機械式刷洗及/或高壓洗滌。包括超高頻音波震盪、機械式刷洗及高壓洗滌之劇烈清潔亦清潔晶粒102之邊緣以移除邊緣處之粒子及有機污染物。
晶粒102可藉由諸如氧電漿之電漿製程進行乾式清潔且在處於由框架或夾環保持之分割帶上時藉由濕式製程進行再清潔，以移除一或多個保護層之任何殘存殘餘物或由一些製程步驟產生之額外污染物且改善接合表面106。然而，在一些情況下，分割帶可與電漿製程反應，且可由其反應產物潛在地導致接合表面106之再污染。
在一些情況下，屏蔽晶粒102以外之曝露帶且使晶粒102之間的曝露帶最小化（例如，使用窄切割刀片且不拉伸該帶）且縮短電漿製程持續時間可減少污染。在一些情況下，基於氧之反應性離子蝕刻（RIE）電漿製程對縮短灰化製程係較佳的。在各種實施方案中，RIE電漿腔室中之短灰化製程可比較小功率電漿腔室中之長灰化製程產生更少的表面再污染。再清潔可包含用去離子水沖洗晶粒102，其可與機械式刷洗、超高頻音波震盪及/或高壓洗滌組合。
在區塊658處，晶粒102可經活化。基於氮之RIE製程或下游電漿方法或其他包括電漿清潔步驟之原子層清潔方法可用於活化晶粒表面106及/或清潔來自所關注表面之任何殘存殘餘物或非所要材料。在區塊660處，作為選擇方案，可用去離子水沖洗晶粒102以進行最終清潔。
在晶粒102形成及製備方法結束時，晶粒102可接合至基板104之所製備接合表面108（如圖1B中所說明）。對於如圖1C中所展示之多個晶粒102堆疊配置，在將每一晶粒102A放置在基板104（或前一晶粒102N）上後，所置放晶粒102A之第二接合表面110（背側）可在將下一晶粒102B之接合表面106直接接合至先前晶粒102A之背側表面110之前經平坦化、清潔及活化（在一些具體實例中，視需要且如上文所論述）。任何所添加之晶粒102N可具有製備好的接合表面106及/或110，其中之一或兩者可或可不經活化。
在一些情況下，基於氮之電漿製程可與分割帶極具反應性且導致接合表面污染，其可抵消電漿活化之益處。電漿製程（如灰化及活化中所使用）亦可與晶粒102或基板104上之金屬裝置層反應且改變金屬層自介電質表面之凹入。形成為氮電漿與聚合分割帶之相互作用之產物的化合物中之一些可吸附在所關注之接合表面上且污染該等接合表面（106、108，且在一些具體實例中，110）。
因此，在一些具體實例中，接合表面106及/或110中之至少一者可不經活化。在一些具體實例中，當分割帶存在或緊密接近時，各種組合之較溫和氧或氮電漿對修改表面（106、108，且在一些具體實例中，110）而言係較佳的。類似地，活化表面（106、108，且在一些具體實例中，110）可經進一步清潔。清潔步驟可包含利用去離子水之沖洗，其可與機械式刷洗、超高頻音波清潔及/或高壓洗滌組合。
在各種具體實例中，相較於本文中所描述之製程步驟，一些晶粒製程步驟可經修改或消除。 清潔及活化拾放工具上之晶粒
在一具體實例中，晶粒102由拾放工具（其通常包含選取工具及接合或放置工具）選擇，其可使晶粒102在將晶粒102放置在所製備基板104上以用於接合的路徑上經歷清潔製程。在一實施方案中，晶粒102在處於選取及/或放置工具上時經活化。在晶粒102處於工具上時執行之此類清潔及活化步驟可為以上描述之某些製程之添加或作為替代方案，但以上描述之步驟之某些細節可以類似方式執行。
作為一實例，晶粒102可由拾放工具攜載經過路徑上之濕式清潔台、大氣電漿、雷射爆炸或類似者達至基板104。在一些具體實例中，晶粒102在活化後及在接合之前不進行沖洗。在其他具體實例中，可在接合之前的製程步驟處用去離子水、所製備處方集或類似者來沖洗晶粒102。在一些具體實例中，自分割帶選取晶粒102，且藉由選取工具將該等晶粒翻轉至將晶粒102之背部表面110呈現至接合工具。選取工具之面部可與待接合之表面106直接接觸。接合工具頭耦接至晶粒102之背側110，且使晶粒102之所製備表面106與基板104之所製備表面108在一起以供接合。
在另其他具體實例中，自分割帶選取良裸晶粒（known good dies）102之所製備表面106，且藉由選取工具將該表面翻轉至將晶粒102之背側110呈現至接合工具。選取工具之面部可與待接合之表面106直接接觸。接合工具頭耦接至晶粒102之背側110，且使晶粒102（諸如圖1C處之晶粒102B）之所製備面部106與堆疊及接合至基板104之良裸晶粒102（諸如圖1C處之晶粒102A）的經曝露之所製備表面110在一起以供接合。
舉例而言，在清潔且活化第一晶粒102A之第二表面110及基板104之第一表面108後，可類似地自分割層選取第二良裸晶粒102B之所製備第一表面106，且將該所製備第一表面接合至第一晶粒102A之所製備第二表面110。多個良裸晶粒102（A至N）可堆疊在基板104上方或彼此上方，或其組合。
在另一個具體實例中，自分割帶選取所製備晶粒102，且藉由選取工具將該等晶粒翻轉至將晶粒102之背側110呈現至接合工具。接合工具頭耦接至晶粒102之背側110，且靜電裝置可用於在將晶粒102之所製備面部106附接至基板104之所製備表面108以用於接合之前自接合表面106移除微粒。另外，拾放工具可具有多孔性表面以接觸接合表面。
在其他實例中，可以掠射角將二氧化碳粒子或壓縮氣體（例如，氮氣）施加至所製備表面106以在接合之前自所製備表面106移除雜散微粒。在一些應用中，可施加熱壓縮氣體（例如，熱氮氣）以恰好在接合操作之前自所製備表面106移除雜散粒子或過量濕氣。壓縮氮之壓力可在20 psi至300 psi之間且較佳地在50 psi與150 psi之間的範圍。類似地，壓縮氣體（例如，氮氣）之溫度可在25℃至100℃之間且較佳地在50℃與90℃之間的範圍。流體表面清潔時間可在2毫秒至1000毫秒之間的範圍且較佳地低於200毫秒。 活化一個接合表面
在大部分上述實例中，在將晶粒102接合至基板104之前，基板104之所製備表面108及晶粒102之所製備表面106各自經電漿清潔（利用氧電漿之灰化係最常見製程）且活化。在某些具體實例中，然而，在將晶粒102接合至基板104之前，此等接合表面中之僅一者（例如，基板104之所製備表面108或晶粒102之所製備表面106）經電漿清潔及/或活化。
在具體實例中，消除晶粒102上或基板104上之表面灰化及活化製程可減少製程相關缺陷且提高良率，以及減小用於形成接合表面之成本。舉例而言，消除該等製程步驟可使得消除接合表面106由分割帶/電漿相互作用產物所致之污染物且減少或消除來自配線層之金屬損耗。另外，可使分割框架或夾環之損壞最小化，因此可延長框架或夾環之使用壽命。此外，當活化一個表面（106、108）而非兩個表面（106、108）時，在採用較少製程步驟之情況下且在接合能量不減少之情況下可提高處理量。隨著用於晶粒102清潔之電漿腔室之消除，總體擁有成本同樣減少。 清潔及製備基板替代具體實例
圖7A及7B之說明分別展示實例製程700及750，從而描述用於清潔及製備用於接合之基板104（製程700）及晶粒102（製程750）之替代製程。此外，儘管該等說明（及相關描述）描述將晶粒102接合至基板104，但製程可用於將晶圓接合至晶圓，將晶粒接合至晶粒，將晶粒接合至晶圓等等。另外，此等製程中描述之基板104亦可指已黏著至另一晶粒102或較大基板（諸如，晶圓）之晶粒102之背側。
參考圖7A，展示用於製備基板104之接合表面108之製程700。在區塊702處，基板104經製造，且在區塊704處，接合表面108以與關於圖2處之製程200所描述類似之方式形成於基板104上。舉例而言，製備接合表面108以用於在無黏合劑之情況下直接接合。在一些具體實例中，如較早所揭示，基板104之製造亦可包括形成接合表面108。
在區塊706處，基板104之接合表面108例如藉由利用溶劑之濕式製程或類似者進行清潔。緊接的為區塊708，其包括利用氧電漿（通常稱為灰化）或其他電漿化學物質之乾式清潔製程，以移除任何無機及有機污染物。舉例而言，電漿可經由大氣壓、下游或反應性離子蝕刻（RIE）製程而提供。基板104可經再清潔，其包括用去離子或弱鹼性的水或其他適合的溶液洗滌以移除來自灰化製程之任何粒子。在一些具體實例中，在儲存用於後續使用之基板104之前或在活化步驟之前，基板104之接合表面108可藉由清潔方法呈現為疏水性的。在區塊710處，舉例而言，使用氮電漿製程來活化接合表面108，以製備用於接合之基板表面108。在各種實例中，已知該活化製程改善接合強度。必要時，亦可用去離子水沖洗基板104以移除來自活化製程之潛在污染粒子。 清潔及製備晶粒替代具體實例
參考圖7B，展示用於製備一或多個晶粒102之一或多個接合表面106及/或110的製程750。在區塊752處，在晶圓上製造晶粒102，且在區塊754處，接合表面106形成及製備於晶粒102之表面上，如先前關於圖3處之製程300所描述。舉例而言，製備用於在無黏合劑之情況下直接接合之接合表面106。在區塊756處，亦如以上所描述，一或多個保護層可添加至接合表面106，且在區塊758處，晶圓經單粒化為複數個晶粒102。
在區塊760處，製程包括自接合表面106移除一或多個保護層。在區塊762處，使用化學處方集來清潔一或多個接合表面106，如下文進一步所描述。在一些情況下，可在晶粒102由框架或夾環保持在分割帶上時自晶粒102清除一或多個保護層，其亦清除由分割製程產生之殘渣。當使用UV釋放帶時，可根據需要在晶粒清潔製程之前或在晶粒清潔製程後執行減小晶粒102與該釋放帶之間的黏合強度以釋放晶粒102之UV曝露。
製程750（其包括在晶粒102處於框架或夾環上或處於聚合薄板上時清潔（或其他處理）該等晶粒）之優勢包括：消除來自氧及氮電漿步驟之聚合殘餘物；減少用於製造之處理步驟及循環次數；當已活化基板104時，可能不需要活化晶粒102；製程（其包括未活化晶粒之情況）之接合能量與類似製程相當，在該類似製程中晶粒102隨著基板104活化而經活化；及更高之所製造裝置處理量。 實例化學處方集
參考圖7B，在自單粒化晶粒102清除保護層後（且視情況在藉由電漿製程清潔晶粒102後），晶粒102可曝露於化學處方集一預定時間以清潔及製備用於接合之一或多個晶粒表面106及/或110。在該具體實例中，在有或沒有穩定添加劑之情況下，所製備處方集包含用甘油酸酯處理之經稀釋氫氟酸或經緩衝氫氟酸或氟化銨、有機酸及去離子水。在一些具體實例中，處方集可包含含有氟離子之無機或有機酸。較佳地，氟離子之含量小於2%且較佳地小於0.5%，且在一些情況下，較佳地小於0.1%。氟離子源之實例可包括氫氟酸、經緩衝氧化蝕刻劑、氟化銨或氟化四丁基銨。
處方集亦可包含脂族或非脂族有機酸，且超過一種有機酸可用於處方集中。處方集之有機酸含量可通常小於2%且較佳地小於1%，且較佳地小於0.1%。有機酸之實例可包括甲酸、乙酸、甲基磺酸及其類似物。在一些具體實例中，可使用礦物酸（例如，極少量之硫酸）。然而，所使用之量不應使接合表面106處之金屬層之表面粗糙化。
在各種具體實例中，甘油併入至處方集中，其中甘油之含量可在處方集之0.5%至25%之間變化，且較佳地低於10%。在其他應用中，極少量之醯胺、胺、丁基化羥基甲氧苯（butylated hydroxyanisole；BHA）、丁基化羥基甲苯或有機碳酸酯可添加至處方集。在其他具體實例中，處方集可為pH值較佳地小於9.5且較佳地小於8.5之弱鹼性。較佳地，此等額外添加劑之總含量小於5%且較佳地小於1%。
亦期望將抑制接合表面106處之金屬層之表面之移除或蝕刻或粗糙化的錯合劑併入至處方集中。在銅之情況下，例如，可使用具有一或多個三唑部分之適合的銅錯合劑。錯合劑之濃度可小於2%，且較佳地小於1%、0.2%，且小於100 ppm且在一些情況下小於5 ppm。在曝露至處方集後，晶粒102藉由選取工具放置且在未活化之情況下（及視情況在無灰化之情況下）接合至基板104。
在藉由處方集清潔後，晶粒102可經沖洗（例如，用去離子水），且可經活化。基於氮之RIE製程或下游電漿方法或其他包括電漿清潔步驟之原子層清潔方法可用於活化晶粒表面106及/或清潔來自所關注表面之任何殘存殘餘物或非所要材料。作為選擇方案，可在活化後用去離子水沖洗晶粒102。
在晶粒102形成及製備方法結束時，晶粒102可接合至基板104之所製備接合表面108（如圖1B中所說明）。對於如圖1C中所展示之多個晶粒堆疊配置，在將每一晶粒102A放置在基板104（或另一晶粒102N）上後，所放置晶粒102A之第二接合表面110（背側）可在將下一晶粒102B直接接合至先前晶粒102A之背側表面110之前經平坦化、清潔及活化（視需要且如上文所論述）。任何所添加之晶粒102（A至N）可具有製備好的接合表面106及/或110，其可或可不經活化。 形成疏水性接合表面
在另一個具體實例中，晶粒102或基板104或兩者之表面可藉由以上描述之清潔步驟中之一或多者呈現為疏水性。表面（106、108及/或110）自身呈現疏水性之一個優勢係疏水性表面可較不易沾染粒子污染物，且易於用諸如氮之壓縮液體、二氧化碳或二氧化碳粒子清潔。晶粒102（例如，在處於分割框架中時）之接合表面106或110或基板104之接合表面108可藉由將其非活化表面（106、108及/或110）曝露於以上描述之含有極稀氟離子之處方集、隨後沖洗並乾燥經曝露表面（106、108及/或110）而呈現為疏水性的。根據此技術，具有疏水性表面106及/或110之經清潔、未活化晶粒102可附接到所製備之經活化基板104（或另一晶粒102）之表面108以供接合。類似地，具有疏水性表面108之經清潔、未活化基板104可接合至一或多個經活化晶粒102之表面106。通常，表面（106、108及/或110）之氮活化往往會使表面（106、108及/或110）呈現親水性。將經配合表面（106、108及/或110）退火改善經配合材料之間的接合能量。通常，接合溫度越高，分離經配合材料所需之能量更高。 額外製程步驟減少
在另一具體實例中，在自單粒化晶粒102清除保護層後，晶粒102藉由拾放工具放置且在未曝露至處方集、灰化或活化之情況下接合至基板104。在各種具體實例中，在基板104經活化且晶粒102不經活化之情況下，所引起之直接接合之接合能量（或接合強度）對於DBI形成製程而言足夠。舉例而言，在一些具體實例中，接合能量為大致1000 mJ/m2 ，其根據一些規格滿足用於適合的直接接合之最小接合能量要求。此外，消除某些氧及氮RIE步驟會消除可沉積在晶粒102表面上之分割帶/電漿反應副產物，以及額外製程步驟之成本及時間。 退火
作為用於全部所論述具體實例之接合製程中之最終步驟，晶粒102及基板104可加熱至高於環境溫度（經退火）以形成金屬對金屬接合。在此等具體實例中，退火製程之高溫使得接合層（106、108及/或110）中之金屬（例如，Cu）比包圍金屬之介電質材料（例如，氧化物）擴展更多。CTE之差異允許在室溫下可凹入在接合表面（106、108及/或110）以下之一或多個金屬層擴展以橋接介電質材料之兩個配合表面之間的間隙且在退火期間形成導電接合部。
在一個具體實例中，在每一晶粒102經放置後，多晶粒堆疊不經退火，而在堆疊之全部晶粒102經放置後，全部堆疊經退火。替代地，在每一晶粒102經放置後，可使用低溫退火。此外，清潔且製備經接合晶粒102之背部表面110以接受額外經清潔晶粒102或晶粒堆疊。具有多晶粒堆疊之基板104可在對各種接合介面處之相對金屬特徵而言之較高溫度下經熱退火以緊密配合。
在一些具體實例中，在所揭示製程後，基板104可藉由已知方法單粒化以形成包含直接接合至較小單粒化基板104（圖中未示）之晶粒102之新結構。在一個具體實例中，晶粒102之接合表面面積小於單粒化基板104之接合表面。 拾放工具製備
在各種實施方案中，拾放工具經設計或處理為使污染晶粒102之機會最小化。拾放工具（或其部分）可由經選擇用於所需疏水特性之材料形成（或塗佈有材料）。舉例而言，該等工具可塗佈有諸如聚四氟乙烯（polytetrafluoroethylene ； PTFE）之材料或另一疏水性材料。
此外，工具可經製備（例如，具有結構設計、具有預定處理等）為抗污染的或避免傳遞污染物至晶粒102。如此，在自待接合之晶粒表面106及/或110選取時，面部選取製程（例如，選取所製備接合表面106及/或110處之晶粒102）並不降低接合品質。替代地，可以化學方式處理晶粒102之表面106及/或110從而具有疏水特性，以使來自選取工具之黏附至表面106及/或110之粒子減至最少。此外，在所需間距處，可清潔該拾放工具之表面以移除潛在晶粒表面污染物源。工具之一或多個表面可為多孔性的。
本文中所描述之技術、組件及裝置不限於圖1A至7B之說明，且可在不脫離本發明之範圍的情況下應用於包括其他電氣組件之其他設計、類型、配置及構造。在一些情況下，額外或替代組件、技術、序列或製程可用於實施本文中所描述之技術。此外，組件及/或技術可以各種組合配置及/或組合，同時引起類似或大致相同之結果。 結論
儘管已以特定針對於結構特徵及/或方法動作之語言描述了本發明之實施方案，但應理解，實施方案不一定限於所描述特定特徵或動作。確切而言，將特定特徵及動作揭示為實施實例裝置及技術之代表性形式。
102‧‧‧晶粒 102A‧‧‧晶粒 102B‧‧‧晶粒 102A-N‧‧‧晶粒 104‧‧‧基板 106‧‧‧接合表面 108‧‧‧接合表面 110‧‧‧接合表面 200‧‧‧代表性製程 202‧‧‧區塊 204‧‧‧區塊 206‧‧‧區塊 300‧‧‧代表性製程 302‧‧‧製程步驟 304‧‧‧製程步驟 306‧‧‧區塊 308‧‧‧區塊 310‧‧‧區塊 312‧‧‧區塊 316‧‧‧區塊 400‧‧‧代表性製程 402‧‧‧區塊 404‧‧‧區塊 406‧‧‧區塊 408‧‧‧區塊 410‧‧‧區塊 412‧‧‧區塊 414‧‧‧區塊 416‧‧‧區塊 418‧‧‧區塊 420‧‧‧區塊 422‧‧‧區塊 424‧‧‧區塊 500‧‧‧代表性製程 502‧‧‧區塊 504‧‧‧區塊 506‧‧‧區塊 508‧‧‧區塊 510‧‧‧區塊 512‧‧‧區塊 514‧‧‧區塊 516‧‧‧區塊 518‧‧‧區塊 520‧‧‧區塊 600‧‧‧代表性製程 602‧‧‧區塊 604‧‧‧區塊 606‧‧‧區塊 608‧‧‧區塊 650‧‧‧代表性製程 652‧‧‧區塊 654‧‧‧區塊 656‧‧‧區塊 658‧‧‧區塊 660‧‧‧區塊 700‧‧‧代表性製程 702‧‧‧區塊 704‧‧‧區塊 706‧‧‧區塊 708‧‧‧區塊 710‧‧‧區塊 750‧‧‧代表性製程 752‧‧‧區塊 754‧‧‧區塊 756‧‧‧區塊 758‧‧‧區塊 760‧‧‧區塊 762‧‧‧區塊
參考隨附圖式闡述詳細描述。在圖式中，元件符號之一或多個最左側數字識別首次出現該元件符號之圖式。在不同圖式中使用相同附圖標號指示類似或相同物件。
對此論述，在圖式中所說明之裝置及系統展示為具有大量組件。如本文中所描述，裝置及/或系統之各種實施方案可包括較少組件且保持在本發明之範圍內。替代地，裝置及/或系統之其他實施方案可包括額外組件或所描述組件之各種組合，且保持在本發明之範圍內。
圖1A展示在將晶粒接合至基板之前的基板及兩個晶粒之實例剖面圖。
圖1B展示在將晶粒接合至基板後的基板及兩個晶粒之實例剖面圖。
圖1C展示基板及將多個晶粒接合至該基板之實例剖面圖。
圖2係說明根據一具體實例之用於製備用於接合之基板的實例製程之流程圖。
圖3係說明根據一具體實例之用於製備用於接合之晶粒的實例製程之流程圖。
圖4係說明根據一具體實例之用於製備用於接合之晶粒的另一實例製程之流程圖。
圖5係說明根據一具體實例之用於製備用於接合之晶粒的另一實例製程之流程圖。
圖6A係說明根據一具體實例之用於製備用於接合之基板的實例製程之流程圖。
圖6B係說明根據一具體實例之用於製備用於接合之晶粒的實例製程之流程圖。
圖7A係說明根據一具體實例之用於製備用於接合之基板的另一實例製程之流程圖。
圖7B係說明根據一具體實例之用於製備用於接合之晶粒的另一實例製程之流程圖。
102A‧‧‧晶粒
102B‧‧‧晶粒
102A-N‧‧‧晶粒
104‧‧‧基板
106‧‧‧接合表面
108‧‧‧接合表面
110‧‧‧接合表面

Claims (29)

  1. 一種形成微電子組裝件之方法，包括：製備第一基板之接合表面，其包括基於第一氣體以第一電漿活化所述第一基板之所述接合表面；形成第二基板之接合表面；將所述第二基板安裝至分割層；在所述第二基板被安裝至所述分割層時將所述第二基板單粒化為多個晶粒，所述多個晶粒中的每一個晶粒的接合表面包括所述第二基板的所述接合表面的一部分；在所述多個晶粒被安裝至所述分割層時處理所述多個晶粒，其包括基於第二氣體以第二電漿清潔所述多個晶粒的所述接合表面，所述第二氣體與所述第一氣體不同；選擇所述多個晶粒中的晶粒；以及在無黏合劑之情況下，並且在所述晶粒被安裝至所述分割層時沒有活化所述晶粒的所述接合表面之情況下，將所述晶粒的所述接合表面直接接合至所述第一基板的所述接合表面。
  2. 如請求項1的方法，進一步包括：在單粒化所述第二基板之前，將保護塗層施加至所述第二基板的所述接合表面。
  3. 如請求項1的方法，進一步包括：使用化學試劑、超高頻音波換能器及/或機械式毛刷來清潔所述多個晶粒或所述第一基板之一或多個表面。
  4. 如請求項1的方法，進一步包括：在所述晶粒由拾放工具保持時處理所述晶粒，所述處理包括原位清潔所述晶粒的所述接合表面。
  5. 如請求項1的方法，進一步包括：通過由疏水性材料形成或塗佈有疏水性材料的拾放工具接觸所述晶粒的所述接合表面，以拾取所述晶粒。
  6. 如請求項1的方法，其中所述第一電漿包括氮電漿。
  7. 如請求項1的方法，其中所述第二電漿包括氧電漿。
  8. 一種形成微電子組裝件之方法，包括：製備第一基板之接合表面；製備第二基板之接合表面；將所述第二基板安裝至分割層；在所述第二基板被安裝至所述分割層時，將所述第二基板單粒化成多個晶粒，所述多個晶粒中的每一個晶粒的接合表面包括所述第二基板的所述接合表面的一部分；在所述多個晶粒被安裝至所述分割層時，處理所述多個晶粒；選擇所述多個晶粒中的晶粒，並且從所述分割層移除所述晶粒；活化所述第一基板的所述接合表面或所述晶粒的所述接合表面之一者；以及在無黏合劑之情況下，並且在沒有活化所述第一基板的所述接合表面或所述晶粒的所述接合表面之另一者之情況下，將所述晶粒的所述接合表面直接接合至所述第一基板的所述接合表面。
  9. 如請求項8的方法，進一步包括：以氧電漿清潔所述第一基板的所述接合表面或所述晶粒的所述接合表面之所述另一者。
  10. 如請求項8的方法，其中所述第一基板的所述接合表面或所述晶粒的所述接合表面是藉由氮電漿活化。
  11. 如請求項8的方法，其中所述晶粒的所述接合表面是所述晶粒的第一接合表面，以及其中所述晶粒包括與所述晶粒的所述第一接合表面相對的第二接合表面，所述方法進一步包括：以氮電漿活化所述晶粒的所述第二接合表面、以氮電漿活化另一晶粒的第 一接合表面、或是以氮電漿活化所述晶粒的所述第二接合表面和所述另一晶粒的所述第一接合表面；以及在無黏合劑之情況下，將所述另一晶粒的所述第一接合表面直接接合至所述晶粒的所述第二接合表面。
  12. 一種形成微電子組裝件之方法，包括：製備第一基板之接合表面；製備第二基板之接合表面；將所述第二基板安裝至分割層；在所述第二基板安裝至所述分割層時，將所述第二基板單粒化成多個晶粒，所述多個晶粒中的每一個晶粒的接合表面包括所述第二基板的所述接合表面的一部分；基於第一氣體以第一電漿清潔所述第一基板的所述接合表面或所述多個晶粒中的一或多個晶粒的所述接合表面中的一者；基於第二氣體以第二電漿活化所述第一基板的所述接合表面或所述多個晶粒中的一或多個晶粒的所述接合表面中的另一者；以及在無黏合劑之情況下，將所述一或多個晶粒的所述接合表面直接接合至所述第一基板的所述接合表面。
  13. 如請求項12的方法，進一步包括：在所述多個晶粒被安裝至所述分割層時清潔所述多個晶粒，其中活化所述多個晶粒中的所述一或多個晶粒的所述接合表面是在所述一或多個晶粒被安裝至所述分割層時或是在從所述分割層移除所述一或多個晶粒之後執行。
  14. 如請求項12的方法，進一步包括：在將所述晶粒之所述接合表面直接接合至所述第一基板之所述接合表面之前，使所述晶粒之所述接合表面呈現疏水性。
  15. 如請求項12的方法，進一步包括：應用超高頻音波清潔器來清潔所述多個晶粒、應用超高頻音波清潔器來清潔所述第一基板、或是應用超高頻音波清潔器來清潔所述多個晶粒及所述第一基板。
  16. 如請求項12的方法，其中所述第一基板和所述晶粒的所述接合表面包括相應的導電特徵，相應的所述導電特徵在所述第一基板和所述晶粒的所述接合表面直接接合時會合。
  17. 如請求項16的方法，進一步包括：在直接接合之後在高溫下使所述第一基板和所述晶粒退火，使得會合的所述導電特徵永久結合。
  18. 如請求項12的方法，其中所述微電子組裝件包含所述多個晶粒之多個直接接合晶粒之堆疊，且其中在放置多個晶粒在所述堆疊上之後，所述微電子組裝件被退火。
  19. 如請求項12的方法，其中所述第一電漿包括氧電漿。
  20. 如請求項12的方法，其中所述第二電漿包括氮電漿。
  21. 一種形成微電子組裝件之方法，包括：形成第一基板之接合表面；形成第二基板之接合表面，所述第二基板的覆蓋面積小於所述第一基板的覆蓋面積，其中形成所述第二基板的所述接合表面包括在所述第二基板被安裝至一層時清潔所述第二基板的所述接合表面；活化所述第一基板的所述接合表面、活化所述第二基板的所述接合表面、或是活化所述第一基板和所述第二基板的所述接合表面；以及在無黏合劑之情況下，將所述第二基板的所述接合表面直接接合至所述第一基板的所述接合表面。
  22. 如請求項21的方法，其中所述活化步驟包括：在所述第二基板被安裝至所述層時或在從所述層移除所述第二基板之後，使所述第一基板的 所述接合表面暴露至電漿或離子化氣體、使所述第二基板的所述接合表面暴露至電漿或離子化氣體、或是使所述第一基板和所述第二基板的所述接合表面暴露至電漿或離子化氣體。
  23. 如請求項22的方法，其中所述電漿或所述離子化氣體包括氧或氮電漿。
  24. 如請求項21的方法，其中所述層包括夾環、分割板或分割層。
  25. 如請求項21的方法，進一步包括：在直接接合之後在高溫下使所述第一基板和所述第二基板退火，使得在所述第一基板和所述第二基板的所述接合表面處匹配的導電特徵永久結合。
  26. 如請求項21的方法，其中所述第二基板的所述接合表面是所述第二基板的第一接合表面，並且所述第二基板包括與所述第二基板的所述第一接合表面相對的第二接合表面，所述方法進一步包括：活化所述第二基板的所述第二接合表面或另一基板的第一接合表面的一者；以及在無黏合劑之情況下，將所述另一基板的所述第一接合表面直接接合至所述第二基板的所述第二接合表面。
  27. 一種形成微電子組裝件之方法，包括：形成第一基板之接合表面；形成第二基板之第一接合表面，所述第二基板的覆蓋面積小於所述第一基板的覆蓋面積，其中形成所述第二基板的所述第一接合表面包括在所述第二基板被安裝至一層時清潔所述第二基板的所述第一接合表面；從所述層移除所述第二基板並且形成所述第二基板的第二接合表面，所述第二接合表面與所述第二基板的所述第一接合表面相對； 活化所述第一基板的所述接合表面或所述第二基板的所述第一接合表面和所述第二接合表面；在無黏合劑之情況下，將所述第二基板的所述第一接合表面直接接合至所述第一基板的所述接合表面；以及將另一基板的第一接合表面接合至所述第二基板的所述第二接合表面。
  28. 如請求項27的方法，其中在無黏合劑之情況下，所述另一基板使用直接接合方法被接合至所述第二基板的所述第二接合表面。
  29. 如請求項27的方法，進一步包括：在高於所述微電子組裝件的環境溫度的溫度下使所述微電子組裝件退火，使得在所述第一基板的所述接合表面和所述第二基板的所述第一接合表面處匹配的導電特徵永久結合。
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US20210375850A1 (en) 2021-12-02
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