FR2938202B1 - Traitement de surface pour adhesion moleculaire - Google Patents
Traitement de surface pour adhesion moleculaireInfo
- Publication number
- FR2938202B1 FR2938202B1 FR0857586A FR0857586A FR2938202B1 FR 2938202 B1 FR2938202 B1 FR 2938202B1 FR 0857586 A FR0857586 A FR 0857586A FR 0857586 A FR0857586 A FR 0857586A FR 2938202 B1 FR2938202 B1 FR 2938202B1
- Authority
- FR
- France
- Prior art keywords
- surface treatment
- molecular adhesion
- adhesion
- molecular
- treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Element Separation (AREA)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0857586A FR2938202B1 (fr) | 2008-11-07 | 2008-11-07 | Traitement de surface pour adhesion moleculaire |
PCT/EP2009/064121 WO2010052151A1 (fr) | 2008-11-07 | 2009-10-27 | Traitement de surface pour liaison moléculaire |
KR1020117008780A KR20110085990A (ko) | 2008-11-07 | 2009-10-27 | 분자 결합을 위한 표면 처리 |
US13/122,717 US8202785B2 (en) | 2008-11-07 | 2009-10-27 | Surface treatment for molecular bonding |
EP09740335A EP2362860A1 (fr) | 2008-11-07 | 2009-10-27 | Traitement de surface pour liaison moléculaire |
CN2009801445160A CN102209692A (zh) | 2008-11-07 | 2009-10-27 | 用于分子结合的表面处理 |
TW098137770A TW201023253A (en) | 2008-11-07 | 2009-11-06 | Surface treatment for molecular bonding |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0857586A FR2938202B1 (fr) | 2008-11-07 | 2008-11-07 | Traitement de surface pour adhesion moleculaire |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2938202A1 FR2938202A1 (fr) | 2010-05-14 |
FR2938202B1 true FR2938202B1 (fr) | 2010-12-31 |
Family
ID=40941355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0857586A Expired - Fee Related FR2938202B1 (fr) | 2008-11-07 | 2008-11-07 | Traitement de surface pour adhesion moleculaire |
Country Status (7)
Country | Link |
---|---|
US (1) | US8202785B2 (fr) |
EP (1) | EP2362860A1 (fr) |
KR (1) | KR20110085990A (fr) |
CN (1) | CN102209692A (fr) |
FR (1) | FR2938202B1 (fr) |
TW (1) | TW201023253A (fr) |
WO (1) | WO2010052151A1 (fr) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2965974B1 (fr) * | 2010-10-12 | 2013-11-29 | Soitec Silicon On Insulator | Procédé de collage moléculaire de substrats en silicium et en verre |
US9540545B2 (en) | 2011-09-02 | 2017-01-10 | Schlumberger Technology Corporation | Plasma treatment in fabricating directional drilling assemblies |
FR2987166B1 (fr) | 2012-02-16 | 2017-05-12 | Soitec Silicon On Insulator | Procede de transfert d'une couche |
FR3002078B1 (fr) | 2013-02-11 | 2015-03-27 | Commissariat Energie Atomique | Procede de realisation d'une couche semi-conductrice presentant au moins deux epaisseurs differentes |
FR3002079B1 (fr) | 2013-02-11 | 2016-09-09 | Commissariat Energie Atomique | Procede de fabrication d'un transistor |
FR3002080B1 (fr) | 2013-02-11 | 2015-03-27 | Commissariat Energie Atomique | Procede de fabrication d'un transistor |
FR3007576B1 (fr) * | 2013-06-19 | 2015-07-10 | Soitec Silicon On Insulator | Procede de transfert d'une couche de circuits. |
US9786633B2 (en) | 2014-04-23 | 2017-10-10 | Massachusetts Institute Of Technology | Interconnect structures for fine pitch assembly of semiconductor structures and related techniques |
US10079224B2 (en) | 2014-08-11 | 2018-09-18 | Massachusetts Institute Of Technology | Interconnect structures for assembly of semiconductor structures including at least one integrated circuit structure |
WO2016118209A2 (fr) | 2014-11-05 | 2016-07-28 | Massachusetts Institute Of Technology | Dispositifs à semi-conducteur multicouche fabriqués à l'aide d'une combinaison d'un substrat et de structures de trou d'interconnexion, et techniques de fabrication |
FR3028664B1 (fr) * | 2014-11-14 | 2016-11-25 | Soitec Silicon On Insulator | Procede de separation et de transfert de couches |
WO2017015432A1 (fr) | 2015-07-23 | 2017-01-26 | Massachusetts Institute Of Technology | Circuit intégré supraconducteur |
US10134972B2 (en) | 2015-07-23 | 2018-11-20 | Massachusetts Institute Of Technology | Qubit and coupler circuit structures and coupling techniques |
CN106409650B (zh) * | 2015-08-03 | 2019-01-29 | 沈阳硅基科技有限公司 | 一种硅片直接键合方法 |
US10121754B2 (en) | 2015-11-05 | 2018-11-06 | Massachusetts Institute Of Technology | Interconnect structures and methods for fabricating interconnect structures |
US10242968B2 (en) | 2015-11-05 | 2019-03-26 | Massachusetts Institute Of Technology | Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages |
WO2018056965A1 (fr) * | 2016-09-21 | 2018-03-29 | Massachusetts Institute Of Technology | Structure semi-conductrice multicouche et procédés de fabrication de structures semi-conductrices multicouches |
US10586909B2 (en) | 2016-10-11 | 2020-03-10 | Massachusetts Institute Of Technology | Cryogenic electronic packages and assemblies |
US10727219B2 (en) * | 2018-02-15 | 2020-07-28 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
US20210238087A1 (en) * | 2018-08-02 | 2021-08-05 | Byd Company Limited | Glass composite, casing, display device and terminal device |
US10978508B2 (en) | 2018-10-16 | 2021-04-13 | L3 Cincinnati Electronics Corporation | Infrared detector having a directly bonded silicon substrate present on top thereof |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6500694B1 (en) | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6902987B1 (en) * | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
TW473942B (en) * | 2000-07-14 | 2002-01-21 | Slight Opto Eletronics Co Ltd | Structural integration of image sensor |
FR2817395B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
US6995430B2 (en) * | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
JP2004186226A (ja) | 2002-11-29 | 2004-07-02 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法 |
US7250114B2 (en) | 2003-05-30 | 2007-07-31 | Lam Research Corporation | Methods of finishing quartz glass surfaces and components made by the methods |
DE10355728B4 (de) * | 2003-11-28 | 2006-04-13 | X-Fab Semiconductor Foundries Ag | Verbinden von Halbleiterscheiben gleichen Durchmessers zum Erhalt einer gebondeten Scheibenanordnung |
WO2006035864A1 (fr) * | 2004-09-30 | 2006-04-06 | Shin-Etsu Handotai Co., Ltd. | Méthode de nettoyage d’une tranche soi |
US7232759B2 (en) * | 2004-10-04 | 2007-06-19 | Applied Materials, Inc. | Ammonium hydroxide treatments for semiconductor substrates |
WO2006082751A2 (fr) | 2005-02-02 | 2006-08-10 | Asahi Glass Company, Limited | Procede de polissage de substrat en verre |
US7601271B2 (en) * | 2005-11-28 | 2009-10-13 | S.O.I.Tec Silicon On Insulator Technologies | Process and equipment for bonding by molecular adhesion |
EP2200077B1 (fr) * | 2008-12-22 | 2012-12-05 | Soitec | Procédé pour la liaison de deux substrats |
-
2008
- 2008-11-07 FR FR0857586A patent/FR2938202B1/fr not_active Expired - Fee Related
-
2009
- 2009-10-27 CN CN2009801445160A patent/CN102209692A/zh active Pending
- 2009-10-27 KR KR1020117008780A patent/KR20110085990A/ko not_active Application Discontinuation
- 2009-10-27 WO PCT/EP2009/064121 patent/WO2010052151A1/fr active Application Filing
- 2009-10-27 US US13/122,717 patent/US8202785B2/en not_active Expired - Fee Related
- 2009-10-27 EP EP09740335A patent/EP2362860A1/fr not_active Withdrawn
- 2009-11-06 TW TW098137770A patent/TW201023253A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
KR20110085990A (ko) | 2011-07-27 |
CN102209692A (zh) | 2011-10-05 |
TW201023253A (en) | 2010-06-16 |
FR2938202A1 (fr) | 2010-05-14 |
EP2362860A1 (fr) | 2011-09-07 |
US20110189834A1 (en) | 2011-08-04 |
WO2010052151A1 (fr) | 2010-05-14 |
US8202785B2 (en) | 2012-06-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120907 |
|
ST | Notification of lapse |
Effective date: 20140731 |