CN113410133A - 用于处理器件的技术 - Google Patents
用于处理器件的技术 Download PDFInfo
- Publication number
- CN113410133A CN113410133A CN202110686074.5A CN202110686074A CN113410133A CN 113410133 A CN113410133 A CN 113410133A CN 202110686074 A CN202110686074 A CN 202110686074A CN 113410133 A CN113410133 A CN 113410133A
- Authority
- CN
- China
- Prior art keywords
- substrate
- bonding surface
- bonding
- die
- dies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 219
- 239000000758 substrate Substances 0.000 claims abstract description 234
- 239000000853 adhesive Substances 0.000 claims abstract description 26
- 230000001070 adhesive effect Effects 0.000 claims abstract description 26
- 238000004377 microelectronic Methods 0.000 claims abstract description 25
- 238000004140 cleaning Methods 0.000 claims description 66
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 46
- 230000003213 activating effect Effects 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 23
- 229910052757 nitrogen Inorganic materials 0.000 claims description 23
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 19
- 239000001301 oxygen Substances 0.000 claims description 19
- 229910052760 oxygen Inorganic materials 0.000 claims description 19
- 230000002209 hydrophobic effect Effects 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 16
- 239000011253 protective coating Substances 0.000 claims description 13
- 230000004913 activation Effects 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 5
- 239000013043 chemical agent Substances 0.000 claims 1
- 238000011065 in-situ storage Methods 0.000 claims 1
- 238000009877 rendering Methods 0.000 claims 1
- 230000008569 process Effects 0.000 description 112
- 235000012431 wafers Nutrition 0.000 description 78
- 239000010410 layer Substances 0.000 description 57
- 210000002381 plasma Anatomy 0.000 description 40
- 239000002184 metal Substances 0.000 description 27
- 229910052751 metal Inorganic materials 0.000 description 27
- 239000002245 particle Substances 0.000 description 23
- 239000000203 mixture Substances 0.000 description 20
- 238000004380 ashing Methods 0.000 description 18
- 238000009472 formulation Methods 0.000 description 18
- 239000011241 protective layer Substances 0.000 description 16
- 238000001994 activation Methods 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 238000001020 plasma etching Methods 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 239000000356 contaminant Substances 0.000 description 10
- 239000010949 copper Substances 0.000 description 9
- 239000008367 deionised water Substances 0.000 description 9
- 229910021641 deionized water Inorganic materials 0.000 description 9
- 239000000126 substance Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 7
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 229920000642 polymer Polymers 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000011109 contamination Methods 0.000 description 5
- -1 etchant Substances 0.000 description 5
- 150000007524 organic acids Chemical class 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 230000001680 brushing effect Effects 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000003379 elimination reaction Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000013011 mating Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 3
- 238000013019 agitation Methods 0.000 description 3
- 239000001569 carbon dioxide Substances 0.000 description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 239000008139 complexing agent Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005108 dry cleaning Methods 0.000 description 3
- 230000008030 elimination Effects 0.000 description 3
- 235000011187 glycerol Nutrition 0.000 description 3
- 230000005661 hydrophobic surface Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- AFVFQIVMOAPDHO-UHFFFAOYSA-N Methanesulfonic acid Chemical compound CS(O)(=O)=O AFVFQIVMOAPDHO-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000000908 ammonium hydroxide Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- FPGGTKZVZWFYPV-UHFFFAOYSA-M tetrabutylammonium fluoride Chemical compound [F-].CCCC[N+](CCCC)(CCCC)CCCC FPGGTKZVZWFYPV-UHFFFAOYSA-M 0.000 description 2
- 150000003852 triazoles Chemical class 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 239000004322 Butylated hydroxytoluene Substances 0.000 description 1
- NLZUEZXRPGMBCV-UHFFFAOYSA-N Butylhydroxytoluene Chemical compound CC1=CC(C(C)(C)C)=C(O)C(C(C)(C)C)=C1 NLZUEZXRPGMBCV-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 208000034809 Product contamination Diseases 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 125000001931 aliphatic group Chemical group 0.000 description 1
- 150000001408 amides Chemical class 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 235000019282 butylated hydroxyanisole Nutrition 0.000 description 1
- 235000010354 butylated hydroxytoluene Nutrition 0.000 description 1
- 229940095259 butylated hydroxytoluene Drugs 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052500 inorganic mineral Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229940098779 methanesulfonic acid Drugs 0.000 description 1
- 239000011707 mineral Substances 0.000 description 1
- 150000007522 mineralic acids Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 235000005985 organic acids Nutrition 0.000 description 1
- 150000005677 organic carbonates Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000678 plasma activation Methods 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 238000005201 scrubbing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/03009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/0383—Reworking, e.g. shaping
- H01L2224/03845—Chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
- H01L2224/091—Disposition
- H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/09181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
- H01L2224/75312—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
- H01L2224/80011—Chemical cleaning, e.g. etching, flux
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
- H01L2224/80012—Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
- H01L2224/80013—Plasma cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
- H01L2224/80019—Combinations of two or more cleaning methods provided for in at least two different groups from H01L2224/8001 - H01L2224/80014
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80905—Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80909—Post-treatment of the bonding area
- H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/8301—Cleaning the layer connector, e.g. oxide removal step, desmearing
- H01L2224/83011—Chemical cleaning, e.g. etching, flux
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/8301—Cleaning the layer connector, e.g. oxide removal step, desmearing
- H01L2224/83013—Plasma cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Dicing (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Treatment Of Water By Ion Exchange (AREA)
- Multi Processors (AREA)
- Multi-Process Working Machines And Systems (AREA)
Abstract
本申请的各实施例涉及用于处理器件的技术。代表性技术提供用于形成微电子组件的过程步骤,包括准备用于结合的微电子部件,诸如管芯、晶圆、衬底等。该微电子部件的一个或多个表面被形成和准备为结合表面。该微电子部件在该准备的结合表面处堆叠并结合而无需粘合剂。
Description
分案申请说明
本申请是国际申请日为2019年1月31日、于2020年8月14日进入中国国家阶段、国家申请号为201980013695.8、名称为“用于处理器件的技术”的中国发明专利申请的分案申请。
优先权要求和相关申请的交叉引用
本申请根据35 U.S.C.§119(e)(1)要求2019年1月30日提交的美国非临时专利申请16/262,489和2018年2月15日提交的美国临时专利申请62/631,216的权益,这些申请据此全文以引用方式并入。
技术领域
以下描述涉及集成电路(“IC”)。更具体地讲,以下描述涉及制造IC管芯和晶圆。
背景技术
微电子元件通常包括半导体材料诸如硅或砷化镓的薄板,该薄板通常被称为半导体晶圆。晶圆可被形成为包括在晶圆表面上和/或部分嵌入晶圆内的多个集成芯片或管芯。与晶圆分离的管芯通常作为单独的预封装单元提供。在一些封装设计中,将管芯安装到衬底或芯片载体,该衬底或芯片载体继而安装在电路面板诸如印刷电路板(PCB)上。例如,在适于进行表面安装的封装中提供许多管芯。
封装式半导体管芯还可以以“堆叠”布置提供,其中例如在电路板或其他载体上提供一个封装,并且在第一封装的顶部上安装另一个封装。这些布置可允许多个不同管芯安装在电路板上的单个占有面积内,并且可通过在封装之间提供短互连来进一步促进高速度操作。通常,该互连距离可能仅略大于管芯自身的厚度。为了在管芯封装叠堆内实现互连,可在每个管芯封装(最顶部封装除外)的两侧(例如,面)上提供用于机械连接和电连接的互连结构。
另外,管芯或晶圆可以作为各种微电子封装方案的一部分以三维布置堆叠。这可以包括在较大的基础管芯、器件、晶圆、衬底等上堆叠一个或多个管芯、器件和/或晶圆的层、以竖直或水平布置堆叠多个管芯或晶圆以及两者的各种组合。管芯或晶圆可以使用各种结合技术以堆叠布置来结合,包括直接电介质结合、非粘合技术,诸如或混合结合技术诸如这两种技术均可从Invensas Bonding Technologies,Inc.(以前的Ziptronix,Inc.),Xperi公司获得(参见例如美国专利6,864,585和7,485,968,其全文以引用方式并入本文)。
实现堆叠管芯和晶圆布置可能存在多种挑战。当使用直接结合或混合结合技术结合堆叠的管芯时,通常期望待结合管芯的表面极其平坦、平滑和清洁。例如,一般来讲,表面应具有非常低的表面拓扑方差,并且具有低含量的杂质、颗粒或其他残余物。颗粒或残余物的移除可改善表面的清洁度和平坦度以及层之间结合的可靠性,然而,颗粒和残余物的移除有时可能是有问题的。
附图说明
参考附图阐述了详细描述。在这些图中,参考标号的一个或多个最左边的数字标识首次出现参考标号的图。在不同图中使用相同的附图标记表示相似或相同的项目。
对于该讨论,图中所示的装置和系统被示出为具有多个部件。如本文所述,装置和/或系统的各种实施方式可以包括较少的部件并且仍然在本公开的范围内。另选地,装置和/或系统的其他实施方式可以包括附加部件或所描述部件的各种组合,并且仍然在本公开的范围内。
图1A示出了在将管芯结合到衬底之前衬底和两个管芯的示例性剖面图。
图1B示出了在将管芯结合到衬底之后衬底和两个管芯的示例性剖面图。
图1C示出了衬底以及将多个管芯结合到衬底的示例性剖面图。
图2是示出根据实施方案的用于准备用于结合的衬底的示例性过程的流程图。
图3是示出根据实施方案的用于准备用于结合的管芯的示例性过程的流程图。
图4是示出根据实施方案的用于准备用于结合的管芯的另一个示例性过程的流程图。
图5是示出根据实施方案的用于准备用于结合的管芯的另一个示例性过程的流程图。
图6A是示出根据实施方案的用于准备用于结合的衬底的示例性过程的流程图。
图6B是示出根据实施方案的用于准备用于结合的管芯的示例性过程的流程图。
图7A是示出根据实施方案的用于准备用于结合的衬底的另一个示例性过程的流程图。
图7B是示出根据实施方案的用于准备用于结合的管芯的另一个示例性过程的流程图。
发明内容
公开了代表性的技术和器件,包括用于形成新型微电子组件的过程步骤。过程包括准备用于结合的微电子部件,诸如管芯、晶圆、衬底等。在各种实施方式中,微电子部件的一个或多个表面被形成和准备为结合表面。微电子部件可在准备的结合表面处堆叠并结合而无需粘合剂。
在各种实施方式中,用于形成微电子组件的方法包括准备第一衬底的结合表面,包括:使第一衬底的结合表面平面化以具有第一预先确定的最小表面方差,以及等离子体激活第一衬底的结合表面。该方法还包括准备第二衬底的第一结合表面,包括将第二衬底的第一结合表面平面化以具有第二预先确定的最小表面方差。
在实施方式中,该方法包括将第二衬底安装到由切割框架保持的切割片或切割带,以及在将第二衬底安装到切割片或切割带的同时将第二衬底分割成多个管芯。多个管芯中的每个管芯具有由第二衬底的第一结合表面的一部分构成的第一结合表面。
该方法可包括在将多个管芯安装到切割片或切割带的同时处理多个管芯,使用拾取和放置工具选择多个管芯中的管芯,以及在没有粘合剂并且不激活管芯的第一结合表面的情况下将管芯的第一结合表面直接结合到第一衬底的结合表面。
在附加实施方式中,技术和方法包括准备第二衬底或多个管芯(或单个管芯)的背侧以用于将附加管芯(或多个附加管芯)结合到结合的管芯。
在一些实施方式中,使用独特组的处理步骤来清洁第一衬底和/或第二衬底或管芯的结合表面。例如,在一些实施方案中,可使用一种或多种独特的配方进行清洁。在其他实施方案中,可使用兆频超声波换能器和/或机械刷来帮助清洁。
在另选实施方式中,衬底或管芯中的一者或多者的结合表面可在处理期间涂覆有一个或多个保护性涂层。例如,在一个实施方案中,单独的保护性涂层可使结合表面疏水或亲水。涂层可防止对结合表面的污染,防止在处理期间对结合表面的损坏等。涂层中的一个或多个涂层可在其他过程步骤期间被移除。另外,处理部件的处理工具中的一个或多个处理工具可被涂覆或形成为疏水的,作为防止清洁部件在处理期间被污染的技术。
本发明参考电气和电子部件以及变化的载体讨论了各种具体实施和布置。虽然提到了特定部件(即,管芯、晶圆、集成电路(IC)、芯片管芯、衬底等),但这并非旨在进行限制,而是为了便于讨论和说明方便。参考晶圆、管芯、衬底等讨论的技术和器件适用于任何类型或数量的电子部件、电路(例如,集成电路(IC)、混合电路、ASIC、存储器器件、处理器等)、部件组、封装部件、结构(例如,晶圆、面板、板、PCB等)等,它们可耦接以彼此交接,与外部电路、系统、载体等交接。这些不同部件、电路、组、封装、结构等中的每一者可以统称为“微电子部件”。为简单起见,除非另外指明,否则结合到另一个部件的部件在本文中将被称为“管芯”,并且管芯所结合的另一个部件在本文中将被称为“衬底”。
下面使用多个示例更详细地解释实施方式。尽管在此处和下文讨论了各种实施方式和示例,但是通过组合各个实施方式和示例的特征和元素,其他实施方式和示例也是可能的。
具体实施方式
概述
参见图1A-图1C,在各种示例中,公开了用于处理待堆叠并直接或紧密结合的器件的技术。本公开描述了包括将一个或多个管芯102结合到衬底104的示例性过程。然而,该过程也可用于将晶圆结合到晶圆、将管芯结合到管芯、将管芯结合到晶圆等。附图中的示意图示出了用于形成和准备用于结合的衬底104(以及特别是衬底104的结合表面108)的一些过程,以及用于形成和准备用于结合到衬底104并且结合到其他管芯102的一个或多个管芯102(以及特别是管芯102的结合表面106和110)的其他过程。在这些过程结束时,将一个或多个管芯102结合(例如,在没有粘合剂的情况下直接结合)到衬底104或另一个管芯102。结合是当两个表面(106和108和/或106和110)放在一起时在环境条件下发生的自发过程。
示出示例性管芯102和示例性衬底104的剖面图在图1A-图1C处示出。图1A示出了结合之前的管芯102和衬底104,并且图1B示出了结合之后的管芯102和衬底104。图1C示出了在将管芯102A结合到衬底104之后,例如通过将管芯102B堆叠并结合到管芯102A,将多个管芯102结合到衬底104。附加管芯102(C-N)可根据需要以类似方式堆叠并结合到管芯102B。
在各种实施方案中,示例性管芯102或示例性衬底104可包括由管芯102的结合表面(106,110)或衬底104的结合表面108上的绝缘材料(例如,氧化物)围绕的一个或多个导电迹线或互连件(未示出)。例如,管芯102或衬底104可包括多个导电层和绝缘层(未示出)以确定管芯102或衬底104的功能(例如,存储器、处理、可编程逻辑等)。结合表面(106、108或110)上的暴露互连件可与各种导电层电连续,并为管芯102或衬底104提供界面。
当使用直接结合或混合结合技术将管芯102结合到衬底104(或将管芯结合到管芯、将管芯结合到晶圆、将晶圆结合到晶圆等)时,通常期望要结合的管芯102和衬底104的表面极其平坦和平滑。例如,一般来讲,结合表面(106和108,以及106和110)应具有非常低的表面拓扑方差(即,纳米级方差,例如低于2nm,并且优选地低于0.5nm),使得结合表面(106和108,以及106和110)可紧密配合以形成持久结合。通常还期望结合表面(106和108,以及106和110)是清洁的并且具有低含量的杂质、颗粒或其他残余物,这些杂质、颗粒或其他残余物的尺寸足够大以导致结合空隙,该结合空隙可导致电连续性故障或其他结合缺陷。
例如,处理步骤中剩余的颗粒和残余物可在堆叠管芯102与衬底104之间的结合界面处产生空隙。如果空隙显著小于金属电互连尺寸,它们可能是可接受的。然而,通常无法容忍导致尺寸接近或超过电互连尺寸的结合缺陷的颗粒。另外,由于临时载体和衬底在移除时可留下结合残余物(其甚至在清洁之后也可持续存在),因此临时结合管芯、晶圆和衬底以用于处理或操作(例如,使用聚合物层或无机层等用于临时结合)也可能是有问题的。
来自临时粘合剂层的残余物(其可由高温聚合物等构成)可为不连续的,在管芯表面106和110或衬底表面108上具有不同的厚度(例如,厚度可在10nm至50um的范围内)。等离子体清洁(诸如用氧等离子体灰化)可用于移除薄的残余物,但即使是长的氧等离子体灰化步骤(例如,超过40分钟)也可能对移除最厚的残余物无效。另外,长的氧灰化过程往往可氧化结合表面(106、110和/或108)上的导电特征结构并降低清洁的表面的平面性。
例如,结合表面(106、110和/或108)可包括凹陷导电特征结构,其中标称导电层凹陷部低于相邻介电层或表面的表面约1nm至20nm。在对晶圆或管芯表面进行长时间的氧灰化之后,先前凹陷的导电特征结构可显著改变以干扰结合或结合后金属互连件的形成。例如,先前凹陷的导电特征结构现在可在相邻介电区域的表面上方突出。在一些情况下,根据灰化过程参数,导电特征结构的突出部可从3nm变为30nm。结合表面(106、110和/或108)上方的这些导电凸体可阻碍或防止结合层或表面的紧密配合。
在此类情况下,有时使用高温(例如,超过50℃)湿法来移除厚残余物;然而,这样的过程可能与其他管芯102或衬底104层或材料不相容。例如,高温湿法可使管芯102或衬底104的抛光金属层劣化,从而降低器件产率。此外,高温可能与一些管芯102或衬底104处理部件(例如,塑料切割带、夹持环等)不相容。
在一些常规晶圆清洁过程中,湿化学清洁溶液(包括侵蚀性清洁溶液)可有效地从晶圆表面移除有机残余物。例如,在介于50℃和80℃之间的温度下,用氢氧化铵、硫酸或盐酸以及它们的各种组合的溶液中的过氧化氢混合物清洁晶圆可产生原始晶圆表面。然而,此类侵蚀性清洁步骤对于清洁管芯102的结合表面106和110通常是不切实际的,因为这些侵蚀性的湿化学品将不仅清洁聚合物残余物和颗粒,它们还可溶解大部分的实际导电特征结构,这些导电特征结构通常由诸如银、铜、镍以及它们的各种合金之类的材料构成。
代表性过程
图2-图7B示出了用于形成和准备用于结合(诸如用于在没有粘合剂的情况下的直接结合)的微电子部件(诸如管芯102和衬底104)的代表性过程200-750。过程200-750包括在微电子部件上提供结合表面(诸如结合表面106、110和108),或者在一些示例中提供两个结合表面(诸如单个管芯102上的结合表面106和110),使结合表面平面化,清洁和激活(在一些示例中)结合表面等。
描述过程200-750的顺序不旨在被解释为限制,并且可以以任何顺序组合过程200-750中的任一个过程中的任何数量的所描述的过程框以实现该过程或另选过程。另外,在不脱离本文描述的主题的实质和范围的情况下,可以从过程中的任一个过程删除各个框。此外,可以在任何合适的硬件、软件、固件或它们的组合中实现过程200-750,而不脱离本文描述的主题的范围。
在另选实施方式中,其他技术可以以各种组合包括在过程200-750中,并且仍然在本公开的范围内。
用于形成和准备衬底的示例性技术
示例性衬底104形成过程200在图2中示出。在各种实施方案中,衬底104可由硅、锗、介电表面、直接或间接间隙半导体材料或层或者另一种合适的材料构成。在框202处,该过程包括制造衬底104。简而言之,形成衬底104可包括在衬底104中制造器件,诸如线的前端(FEOL)、线的多层后端(BEOL)和其他所关注的结构,清洁衬底104的表面等。
在框204处,该过程包括在衬底104的第一(前)表面108上形成直接结合层。用于结合层的材料可沉积或形成在第一表面108上,并且可由无机介电材料层诸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、氮碳化物、金刚石、类金刚石材料、玻璃、陶瓷、玻璃陶瓷等或无机介电层与一个或多个金属特征结构的组合构成。在一些实施方案中,金属特征结构可从介电表面略微凹陷,例如在介电表面下方1nm至20nm。在一些实施方案中,形成直接结合层可作为最后形成的金属层结合到晶圆制造过程(诸如框202)中。在一个实施方案中,最后金属化介电层的平面表面可包括结合表面108,并且形成结合层108的附加金属化介电涂层可为不必要的。
形成直接结合层包括修整第一表面108(即,结合表面)以满足电介质粗糙度规格和金属层(例如,铜等)凹陷规格以准备用于直接结合的表面108。换句话讲,结合表面108被形成为尽可能平坦且平滑的,具有非常小的表面拓扑方差。可使用各种常规过程诸如化学机械抛光(CMP)来实现低表面粗糙度。金属层可被配置为提供电路径和/或热路径,或者可替代地被配置为通过使用所谓的虚设焊盘、迹线、图案等来平衡金属化。
在框206处,清洁和/或激活衬底104的结合表面108以准备直接结合,如下所述。
用于形成和准备管芯的示例性技术
图3示出了用于由晶圆(其也可被称为“第二衬底”,并且其可由类似或相同的材料构成,并且以与上文参考衬底104所述类似或相同的过程和技术形成)形成单面或双面管芯102的示例性过程300。在实施方式中,在过程200的框202和框204处,根据结合表面的表面拓扑要求,制造晶圆并形成(前)结合表面106的过程步骤302和304与上文参考衬底104所述的基本上相同。
在框306处,在(例如,通过CMP过程)平面化晶圆的结合表面106以实现期望的拓扑之后,将保护性涂层(诸如抗蚀剂或其他合适的材料)施加到晶圆的结合表面以保护结合表面106免受污染,保护暴露的金属层免受腐蚀,并且在分割操作期间保护结合表面106,该分割操作往往可在管芯102的前表面和侧表面上生成碎屑。
除此之外或作为另外一种选择,可对晶圆的背表面进行处理(例如,穿管芯导体显露、平面化等),从而在管芯102上形成背结合表面110,该背结合表面也可涂覆有保护性涂层等。
在一些实施方案中,可将多于一种类型的保护层施加到晶圆表面。例如,第一保护层可包括疏水性保护层,并且覆盖在疏水层上的可以是亲水性保护层。在该示例中,下面的疏水层允许在清洁管芯102的侧表面期间使用侵蚀性蚀刻化学品,并且还增加准备的表面106和110的保存期限。在一些情况下,上覆亲水层接收或浸渍有在切割处理期间产生的颗粒、碎屑、切割带、粘合剂等。移除亲水层连同颗粒和碎屑。疏水层可暂时保持完整,以在后续处理或储存期间保护表面106(和/或110)。
在一些情况下,如在框308处所示,从未保护侧减薄晶圆以实现期望的厚度。在框310处,将晶圆安装到框架上的切割带上并分割(框312)以形成管芯102。可使用锯、激光(例如,隐形激光)、等离子体蚀刻工艺或其他合适的技术将晶圆分割成一定量的管芯102。在各种示例中,在将晶圆安装到由框架保持的切割片或切割层或切割带(等)的同时分割管芯102。
在切割之后,如果需要,可使切割带上的切割的晶圆膨胀并将其安装到夹持环中。在各种示例中,框架或夹持环可由塑料部件、金属部件、它们的组合等构成。切割带可为工业中常用的任何类型的切割带。一个示例性切割带包括UV剥离带。在一些示例中,管芯102可在处于夹持环或切割框架上时被运送。
形成和准备管芯–双面管芯示例
图4示出了用于形成双面管芯102的示例性过程400,其中管芯102的两个表面(106和110)将结合到衬底104或其他管芯102,诸如利用多个管芯到管芯或管芯到晶圆应用(例如,如图1C所示)。在框402处,该过程包括制造用于管芯102的晶圆,这可包括在整个管芯102的期望位置处制造硅通孔(TSV),以用于未来的贯穿器件连接。在各种实施方案中,晶圆可由硅、锗或另一种合适的材料制成。
在框404处,该过程包括在管芯102的第一(前)表面106上形成直接结合层。用于结合层的材料可沉积或形成在第一表面106上,并且可由无机介电材料层或无机介电层与一个或多个金属特征结构的组合构成,如参考图2所述。类似地,如前所讨论的,最后金属化介电层的平面表面可包括结合表面106,并且形成结合层106的附加金属化介电涂层可为不必要的。
形成直接结合层包括修整第一表面106(即,结合表面)以满足电介质粗糙度规格和金属层(例如,铜等)凹陷规格以准备用于直接结合的表面106。换句话讲,结合表面106被形成为尽可能平坦且平滑的,具有非常小的表面拓扑方差。可使用各种常规过程诸如化学机械抛光(CMP)来实现低表面粗糙度。
在实施方式中,在框406处,将待分割成管芯102的晶圆的准备的前表面直接结合到支撑晶圆(例如,在一个示例中为“硅载体”,但也可使用其他材料的载体),以用于在制造第二(后)结合表面110期间处理晶圆。在一个示例中,使用如上所述的Zibond直接结合技术将晶圆的第一表面结合到硅晶圆。
在各种实施方案中,将硅载体直接结合到晶圆具有多个优点。例如,该技术移除了背侧晶圆处理的任何温度限制。此外,硅载体可具有相似或紧密匹配的热膨胀系数(CTE),从而减少或消除处理期间晶圆的翘曲。这可改善与晶圆的直接结合的成功和可靠性。另外,直接结合硅载体使超薄晶圆能够直接结合到其他管芯、晶圆、衬底等,否则将是不可能的。
在框408处,在形成和抛光第二结合表面110之前,可减薄硅衬底,并暴露TSV。形成并修整(如上所述)晶圆背侧上的管芯102的第二结合表面110,以便以最小表面拓扑方差满足最大电介质粗糙度规格和金属层(例如,铜等)凹陷规格。此外,可将保护性涂层施加到抛光的第二结合表面110。
在框410处,然后可使用粘合剂将晶圆的第二表面110结合到临时支撑晶圆,以处理晶圆以进行前侧106处理。在框412处,使用一种或多种技术(包括蚀刻、溶解、磨削等)从晶圆的第一表面106移除硅支撑晶圆。执行移除过程以确保第一表面106保持介电层和任何导电层,以用于在支撑晶圆已被移除之后进行未来的直接结合或混合结合。
在框414处,可将一个或多个保护性涂层施加到暴露的第一表面106。在一些实施方案中,可将多于一种类型的保护层施加到第一表面106。例如,第一保护层可包括疏水性保护层,并且覆盖在疏水层上的可以是亲水性保护层(如上所述)。
在框416处,从晶圆的背表面110移除临时载体和临时结合粘合剂。在框418处,然后将完成的双面晶圆安装到框架上的切割带上并分割以形成一定量的双面管芯102(框420)。任选地,可将切割的晶圆转移到夹持环(框422)以准备结合(框424)。
参见图5,在过程500所示的另选实施方案中,不使用直接结合技术将硅载体结合至晶圆。相反,在如上文参考图4所述制造(框502)和形成/修整第一结合表面(框504)之后,使用临时结合粘合剂将第一表面106结合到支撑载体(框506)以用于制造第二(背侧)110结合表面。
在框508处,可根据需要减薄晶圆,从而暴露TSV。如上所述形成并修整第二结合层110。在框510处,可在切割之前将一个或多个保护性涂层施加到准备的结合表面(106和/或110)。在形成和修整第二结合表面110之后,移除临时载体和临时粘合剂材料(框512)。然后将完成的双面晶圆安装到例如框架上的切割带或切割层(框514),并且分割(框516)以形成一定量的双面管芯102。任选地,可将切割的晶圆转移到夹持环(框518)以准备结合(框520)。
清洁和准备衬底
图6A和图6B的图示分别示出了示例性过程600和650,描述了清洁和准备衬底104(过程600)和管芯102(过程650)以用于结合。同样,尽管图示(以及相关联的描述)描述了将管芯102结合到衬底104,但该过程可用于将晶圆结合到晶圆、将管芯结合到管芯、将管芯结合到晶圆等。此外,这些过程中所述的衬底104还可指已经安装到另一个管芯102或安装到较大衬底(诸如晶圆)的管芯102的背侧110。
参见图6A,示出了用于准备衬底104的结合表面108的过程600。在一些实施方案中,过程600遵循图2所示的过程200的框206或在该框内汇总。例如,在框602处,例如用溶剂通过湿法来清洁衬底104的结合表面108。接着是框604,包括用氧等离子体(通常称为灰化)或其他等离子体化学品进行干清洁过程,以移除任何无机和有机污染物。等离子体可通过例如大气、下游或反应离子蚀刻(RIE)工艺提供。
然后可以重新清洁衬底104,包括用去离子或适度碱性水或其他合适的溶液擦洗,以从灰化过程中移除任何颗粒。在框606处,使用氮等离子体过程激活结合表面108,例如以准备用于结合的衬底表面108。在各种示例中,已知激活过程改善结合管芯102与衬底104的结合强度。类似地,激活步骤可通过例如大气、下游或反应离子蚀刻(RIE)工艺提供。衬底104也可用去离子水冲洗以从激活过程中移除颗粒,如在框608处所示。
清洁和准备管芯
参见图6B,示出了用于准备管芯102的第一结合表面106的过程650。在一些实施方案中,过程650遵循分别来自图3、图4和图5的框316、424或520等或在这些框内汇总。例如,在框652处,准备管芯102的第一结合表面106包括从结合表面106移除保护层。在框654和656处,清洁结合表面106。例如,可使用一个或多个另选或任选的过程阶段(包括用溶剂进行湿清洁、用氧等离子体进行干清洁(通常称为灰化)或使用其他等离子体化学品等)来移除任何无机和有机污染物。干清洁可通过等离子体过程诸如大气、下游或RIE工艺来执行。
在一些情况下,可在通过框架或夹持环(例如,经由湿法)将管芯102保持在切割带上的同时从管芯102清洁保护层,这也清洁了由切割过程产生的碎屑。当使用UV剥离带时,如果需要,可在管芯清洁过程之前或在管芯清洁过程之后执行UV暴露以降低管芯102与带之间的粘附强度以剥离管芯102。
在各种实施方案中,管芯102用化学品(例如,溶剂、蚀刻剂、水等)清洁,该化学品可移除保护性涂层而不腐蚀下面的金属层(例如,铜)。例如,清洁用化学品可包括氢氧化铵或酸的溶液中的过氧化氢混合物。金属钝化化合物(例如,三唑部分)可用于抑制导电特征结构(诸如银、铜、镍以及它们的各种合金)的金属蚀刻。这些化学品和钝化化合物可从结合表面106的金属部分清洁或冲洗掉。
在切割过程期间,可通过切割轮或导线的机械作用将晶圆颗粒(例如硅颗粒)嵌入切割带中。在拾取和放置从切割带到结合层的直接管芯转移期间,这些嵌入的颗粒可能污染清洁的管芯102的边缘和表面,包括结合表面106。因此,从清洁的结合表面106减少或消除嵌入的颗粒是非常重要的。在一个示例中,可将管芯102重新安装到相同或相似材料或另一种合适材料的新切割带的片材上,从而丢弃初始切割带。这样做可以移除嵌入的污染物或使得能够使用与初始切割带不相容的化学品。
作为另外一种选择,捕集在切割带中的污染物可通过更有力地清洁管芯102来移除,包括兆频超声波摇动、机械刷洗和/或高压清洗。有力的清洁(包括兆频超声波摇动、机械刷洗和高压清洗)也清洁管芯102的边缘以移除边缘处的颗粒和有机污染物。
当在由框架或夹持环保持的切割带上时,可利用等离子体过程(诸如氧等离子体)对管芯102进行干清洁,并利用湿法重新清洁该管芯,以移除由一些过程步骤产生的保护层的任何剩余残余物或附加污染物,并改善结合表面106。然而,在一些情况下,切割带可与等离子体过程反应并且可潜在地导致结合表面106被其反应产物再污染。
在一些情况下,屏蔽超出管芯102的暴露带并且使管芯102之间的暴露带最小化(例如,使用窄切割刀片并且不拉伸带)并且缩短等离子体过程持续时间可减少污染。在一些情况下,优选基于氧的反应离子蚀刻(RIE)等离子体过程来缩短灰化过程。在各种实施方式中,RIE等离子体室中的短灰化过程可以比不太强的等离子体室中的长灰化过程引起更少的表面再污染。重新清洁可包括用去离子水冲洗管芯102,这可与机械刷洗、兆频超声波摇动和/或高压清洗组合。
在框658处,可激活管芯102。可使用基于氮的RIE工艺或下游等离子体方法或其他等离子体清洁步骤(包括原子层清洁方法)来激活管芯表面106和/或从所关注的表面清洁任何剩余的残余物或不期望的材料。在框660处,作为选择,可用去离子水冲洗管芯102以进行最终清洁。
在管芯102形成和准备过程结束时,可将管芯102结合到衬底104的准备的结合表面108(如图1B所示)。对于如图1C所示的多管芯102堆叠布置而言,在将每个管芯102A放置在衬底104(或前一个管芯102N)上之后,可在将下一个管芯102B的结合表面106直接结合到前一个管芯102A的背侧表面110之前,对放置的管芯102A的第二结合表面110(背侧)进行平面化、清洁和激活(在一些实施方案中,根据需要和如上所讨论)。任何添加的管芯102N可具有准备的结合表面106和/或110,该结合表面中的一个或两者可被激活或可不被激活。
在一些情况下,基于氮的等离子体过程可与切割带非常有反应性并且引起结合表面污染,这可抵消等离子体激活的益处。等离子体过程(如用于灰化和激活)还可与管芯102或衬底104上的金属器件层反应,并从介电表面改变金属层的凹陷部。由于氮等离子体与聚合物切割带的相互作用而形成的化合物中的一些化合物可吸附在所关注的结合表面上并且污染结合表面(106、108,并且在一些实施方案中为110)。
因此,在一些实施方案中,结合表面106和/或110中的至少一个结合表面可不被激活。在一些实施方案中,当切割带存在或紧邻时,优选各种组合的更温和的氧或氮等离子体来对表面(106、108,在一些实施方案中为110)进行修改。类似地,激活的表面(106、108,并且在一些实施方案中为110)可被进一步清洁。清洁步骤可包括用去离子水冲洗,这可与机械刷洗、兆频超声波清洁和/或高压清洗组合。
在各种实施方案中,与本文所述的过程步骤相比,可修改或消除一些管芯过程步骤。
在拾取和放置工具上清洁和激活管芯
在实施方案中,通过拾取和放置工具(通常包括拾取工具以及结合或放置工具)来选择管芯102,该工具可在将管芯102放置在准备的衬底104上以用于结合的过程中使管芯102通过清洁过程。在实施方式中,管芯102在拾取和/或放置工具上时被激活。当管芯102在工具上时执行的此类清洁和激活步骤可以是上述过程中的某些过程的补充或替代,但上述步骤的某些细节可以以类似的方式执行。
例如,管芯102可由拾取和放置工具承载,通过湿清洁站、大气等离子体、激光爆炸等到达衬底104。在一些实施方案中,管芯102在激活之后且在结合之前不被冲洗。在其他实施方案中,可在结合之前的过程步骤处用去离子水、准备的配方等冲洗管芯102。在一些实施方案中,从切割带拾取管芯102并通过拾取工具使该管芯翻转以将管芯102的背表面110呈现给结合工具。拾取工具的面可与要结合的表面106直接接触。结合工具头部耦接到管芯102的背侧110,并且将管芯102的准备的表面106带到衬底104的准备的表面108以用于结合。
在另外的其他实施方案中,从切割带拾取已知良好管芯102的准备的表面106并通过拾取工具使该表面翻转以将管芯102的背侧110呈现给结合工具。拾取工具的面可与要结合的表面106直接接触。结合工具头部耦接到管芯102的背侧110,并且将管芯102的准备的面106(诸如图1C处的管芯102B)带到堆叠并结合到衬底104的已知良好管芯102(诸如图1C处的管芯102A)的暴露的准备的面110以用于结合。
例如,在清洁和激活第一管芯102A的第二表面110和衬底104的第一表面108之后,可类似地从切割层拾取第二已知良好管芯102B的准备的第一表面106,并将其结合到第一管芯102A的准备的第二表面110。多个已知良好管芯102(A-N)可堆叠在衬底104上方或彼此上方,或它们的组合。
在另一个实施方案中,从切割带拾取准备的管芯102并通过拾取工具使该管芯翻转以将管芯102的背侧110呈现给结合工具。结合工具头部耦接到管芯102的背侧110,并且静电器件可用于在将管芯102的准备的面106附接到衬底104的准备的表面108以进行结合之前从结合表面106移除颗粒。此外,拾取和放置工具可具有用于接触结合表面的多孔表面。
在其他示例中,二氧化碳颗粒或压缩气体(例如氮气)可以以掠射角施加到准备的表面106,以在结合之前从准备的表面106移除伪颗粒。在一些应用中,可在即将进行结合操作之前施加热压缩气体(例如,热氮气)以从准备的表面106移除伪颗粒或过量的水分。压缩氮气的压力可在20psi至300psi之间的范围内,并且优选地在50psi至150psi之间的范围内。相似地,压缩气体(例如氮气)的温度可在25℃至100℃之间的范围内,并且优选地在50℃至90℃之间的范围内。流体表面清洁时间可在2毫秒至1000毫秒之间的范围内,并且优选地在200毫秒以下。
激活一个结合表面
在上述大多数示例中,在将管芯102结合到衬底104之前,对衬底104的准备的表面108和管芯102的准备的表面106各自进行等离子体清洁(用氧等离子体进行灰化是最常见的过程)并激活。然而,在某些实施方案中,在将管芯102结合到衬底104之前,等离子体清洁和/或激活这些结合表面中的仅一个结合表面(例如,衬底104的准备的表面108或管芯102的准备的表面106)。
在实施方案中,消除管芯102上或衬底104上的表面灰化和激活过程可减少过程相关缺陷并提高产率,以及降低形成结合表面的成本。例如,消除过程步骤可导致消除切割带/等离子体相互作用产物对结合表面106的污染,并减少或消除布线层的金属损耗。另外,可使对切割框架或夹持环的损坏最小化,从而可延长框架或夹持环寿命。此外,当激活一个表面(106,108)而不是两个表面(106,108)时,可以用较少的过程步骤来提高吞吐量,并且不降低结合能量。通过消除用于管芯102清洁的等离子体室也降低了所有权总成本。
清洁和准备衬底–另选的实施方案
图7A和图7B的图示分别示出了示例性过程700和750,描述了用于清洁和准备衬底104(过程700)和管芯102(过程750)以用于结合的另选过程。同样,尽管图示(以及相关联的描述)描述了将管芯102结合到衬底104,但该过程可用于将晶圆结合到晶圆、将管芯结合到管芯、将管芯结合到晶圆等。此外,这些过程中所述的衬底104还可指已经安装到另一个管芯102或较大衬底(诸如晶圆)的管芯102的背侧。
参见图7A,示出了用于准备衬底104的结合表面108的过程700。在框702处,制造衬底104,并且在框704处以与关于图2处的过程200所述类似的方式在衬底104上形成结合表面108。例如,准备结合表面108以在没有粘合剂的情况下进行直接结合。在如先前所公开的一些实施方案中,衬底104的制造还可包括形成结合表面108。
在框706处,例如用溶剂通过湿法等来清洁衬底104的结合表面108。接着是框708,包括用氧等离子体(通常称为灰化)或其他等离子体化学品进行干清洁过程,以移除任何无机和有机污染物。等离子体可通过例如大气、下游或反应离子蚀刻(RIE)工艺提供。可以重新清洁衬底104,包括用去离子或适度碱性水或其他合适的溶液擦洗,以从灰化过程中移除任何颗粒。在一些实施方案中,在储存衬底104以供后续使用之前或在激活步骤之前,可通过清洁方法使衬底104的结合表面108疏水。在框710处,使用氮等离子体过程激活结合表面108,例如以准备用于结合的衬底表面108。在各种示例中,已知激活过程会提高结合强度。如果需要,衬底104也可用去离子水冲洗以从激活过程中移除潜在的污染颗粒。
清洁和准备管芯–另选的实施方案
参见图7B,示出了用于准备管芯102的结合表面106和/或110的过程750。在框752处,在晶圆上制造管芯102,并且在框754处,在管芯102的表面上形成并准备结合表面106,如先前关于图3处的过程300所述。例如,准备结合表面106以在没有粘合剂的情况下进行直接结合。在框756处,可将一个或多个保护层添加到结合表面106,也如上所述,并且在框758处,将晶圆分割成多个管芯102。
在框760处,该过程包括从结合表面106移除保护层。在框762处,使用化学配方清洁结合表面106,如下文进一步所述。在一些情况下,可在通过框架或夹持环将管芯102保持在切割带上的同时从管芯102清洁保护层,这也清洁了由切割过程产生的碎屑。当使用UV剥离带时,如果需要,可在管芯清洁过程之前或在管芯清洁过程之后执行UV暴露以降低管芯102与带之间的粘附强度以剥离管芯102。
过程750的优点(包括当在框架或夹持环上或在聚合物片材上时清洁(或其他处理)管芯102)包括:从氧和氮等离子体步骤中消除聚合物残余物;减少用于制造的处理步骤和循环时间;当衬底104已被激活时,管芯102可能不需要被激活;该过程(包括管芯未激活的情况)的结合能量与管芯102被激活连同衬底104激活的类似过程相当;以及所制造的器件的更高吞吐量。
示例性化学配方
参见图7B,在从分割的管芯102清洁保护层之后(并且任选地在用等离子体过程清洁管芯102之后),管芯102可暴露于化学配方持续预先确定的时间以清洁和准备管芯表面106和/或110以用于结合。在该实施方案中,准备的配方包含甘油稀释的氢氟酸或缓冲的氢氟酸或氟化铵、有机酸和去离子水,具有或不具有稳定添加剂。在一些实施方案中,配方可包含含有氟离子的无机酸或有机酸。氟离子的含量优选地小于2%,并且优选地小于0.5%,并且在一些情况下优选地小于0.1%。氟离子源的示例可包括氢氟酸、缓冲氧化物蚀刻、氟化铵或四丁基氟化铵。
配方也可包含脂族或非脂族有机酸,并且在配方中可使用一种以上的有机酸。配方中的有机酸含量通常可小于2%,并且优选地小于1%,并且优选地小于0.1%。有机酸的示例可包括甲酸、乙酸、甲基磺酸等。在一些实施方案中,可使用矿物酸(例如,非常少量的硫酸)。然而,所用的量不应使结合表面106处的金属层的表面粗糙化。
在各种实施方案中,将甘油掺入配方中,其中甘油的含量可在配方的0.5%至25%之间改变,并且优选地低于10%。在其他应用中,可将非常少量的酰胺、胺、丁基羟基茴香醚(BHA)、丁基羟基甲苯、或有机碳酸盐加入到配方中。在其他实施方案中,配方可为适度碱性的,pH优选地小于9.5,并且优选地小于8.5。这些附加添加剂的总含量优选地小于5%,并且优选地小于1%。
还期望将抑制结合表面106处金属层的表面的移除或蚀刻或粗糙化的络合剂掺入到配方中。就铜而言,例如,可使用具有一个或多个三唑部分的合适的铜络合剂。在一些情况下,络合剂的浓度可小于2%,并且优选地小于1%、0.2%,并且小于100ppm和小于5ppm。在暴露于配方之后,管芯102由拾取工具放置并且结合到衬底104,而无需激活(并且任选地无需灰化)。
在用配方清洁之后,管芯102可被冲洗(例如用去离子水),并且可被激活。可使用基于氮的RIE工艺或下游等离子体方法或其他等离子体清洁步骤(包括原子层清洁方法)来激活管芯表面106和/或从所关注的表面清洁任何剩余的残余物或不期望的材料。作为选择,可在激活之后用去离子水冲洗管芯102。
在管芯102形成和准备过程结束时,可将管芯102结合到衬底104的准备的结合表面108(如图1B所示)。对于如图1C所示的多管芯堆叠布置而言,在将每个管芯102A放置在衬底104(或另一个管芯102N)上之后,可在将下一个管芯102B直接结合到前一个管芯102A的背侧表面110之前,对放置的管芯102A的第二结合表面110(背侧)进行平面化、清洁和激活(根据需要和如上所讨论)。任何添加的管芯102(A-N)可具有准备的结合表面106和/或110,该结合表面可被激活或可不被激活。
形成疏水性结合表面
在另一个实施方案中,可通过上述清洁步骤中的一个或多个清洁步骤使管芯102或衬底104或两者的表面疏水。使表面(106、108和/或110)本身疏水的一个优点是疏水性表面可能不太容易受到颗粒污染,并且易于用压缩流体诸如氮气、二氧化碳或二氧化碳颗粒进行清洁。可通过以下方式使管芯102的结合表面106或110(例如,当在切割框架中时)或衬底104的结合表面108疏水:将其未激活的表面(106、108和/或110)暴露于上述含非常稀的氟化物的配方,然后冲洗并干燥暴露的表面(106、108和/或110)。根据该技术,具有疏水性表面106和/或110的清洁、未激活的管芯102可附接到准备的激活衬底104的表面108(或附接到另一个管芯102)以用于结合。类似地,具有疏水性表面108的清洁、未激活的衬底104可结合到一个或多个激活管芯102的表面106。通常,表面(106、108和/或110)的氮激活往往使表面(106、108和/或110)亲水。使配合的表面(106、108和/或110)退火改善了配合的材料之间的结合能量。通常,结合温度越高,分离配合的材料所需的能量越高。
附加过程步骤减少
在另外的实施方案中,在从分割的管芯102清洁保护层之后,管芯102由拾取和放置工具放置并且结合到衬底104,而不暴露于配方、灰化或激活。在各种实施方案中,在衬底104被激活并且管芯102未被激活的情况下,所得直接结合的结合能量(或结合强度)足以用于DBI形成过程。例如,在一些实施方案中,结合能量为约1000mJ/m2,其满足根据一些规格的用于合适的直接结合的最小结合能量要求。另外,消除某些氧和氮RIE步骤消除了可沉积在管芯102表面上的切割带/等离子体反应副产物,以及附加过程步骤的成本和时间。
退火
作为所讨论的所有实施方案的结合过程中的最后步骤,可将管芯102和衬底104加热至高于环境温度(退火)以形成金属-金属接头。在这些实施方案中,退火过程的高温导致结合层(106、108和/或110)中的金属(例如,Cu)比包围金属的介电材料(例如,氧化物)膨胀更多。CTE的差异允许在室温下可凹陷到结合表面(106,108和/或110)以下的金属层膨胀以桥接介电材料的两个配合表面之间的间隙并在退火期间形成导电接头。
在一个实施方案中,多管芯叠堆在每个管芯102被放置之后不退火,而是一旦叠堆的所有管芯102被放置,整个叠堆就被退火。作为另外一种选择,可在放置每个管芯102之后使用低温退火。另外,清洁并准备结合管芯102的背表面110以接受附加清洁的管芯102或管芯叠堆。具有多管芯叠堆的衬底104可在较高温度下热退火,以用于各种结合界面处的相对金属特征结构紧密配合。
在一些实施方案中,在所公开的过程之后,可通过已知方法对衬底104进行分割以形成由管芯102构成的新结构,该新结构直接结合到较小分割的衬底104(未示出)。在一个实施方案中,管芯102的结合表面积小于分割的衬底104的结合表面。
拾取和放置工具准备
在各种实施方式中,拾取和放置工具被设计或处理以使污染管芯102的机会最小化。拾取和放置工具(或它们的部分)可由对于期望的疏水特性而选择的材料形成(或涂覆有该材料)。例如,工具可涂覆有诸如聚四氟乙烯(PTFE)之类的材料或另一种疏水性材料。
另外,工具可被准备(例如,用结构设计,用预先确定的处理等)成耐受污染物或避免污染物传递到管芯102。因此,面拾取过程(例如,在准备的结合表面106和/或110处拾取管芯102)在从待结合的管芯表面106和/或110拾取时不会降低结合质量。作为另外一种选择,可对管芯102的表面106和/或110进行化学处理以具有疏水特性,从而使从拾取工具粘附到表面106和/或110的颗粒最小化。另外,可以以期望的间隔清洁拾取和放置工具的表面以移除潜在管芯表面污染物源。工具的一个或多个表面可以是多孔的。
本文所述的技术、部件和器件不限于图1A-图7B的图示,并且在不脱离本公开的范围的情况下可应用于包括具有其他电子部件的其他设计、类型、布置和构造。在一些情况下,可使用附加或另选的部件、技术、序列或过程来实现本文所述的技术。此外,部件和/或技术可以各种组合布置和/或组合,同时产生类似或大致相同的结果。
结论
尽管已经用结构特征和/或方法动作专用的语言描述了本公开的实施方式,但是应当理解,这些实施方式不必限于所描述的特定特征或动作。相反,公开了特定特征和动作作为实现示例性装置和技术的代表性形式。
Claims (50)
1.一种形成微电子组件的方法,包括:
准备第一衬底的结合表面,包括基于第一气体、利用第一等离子体激活所述第一衬底的所述结合表面;
形成第二衬底的结合表面;
将所述第二衬底安装到切割层;
在所述第二衬底被安装到所述切割层的同时将所述第二衬底分割成多个管芯,所述多个管芯中的每个管芯具有包括所述第二衬底的所述结合表面的一部分的结合表面;
在所述多个管芯被安装到所述切割层的同时处理所述多个管芯,包括基于与所述第一气体不同的第二气体、利用第二等离子体清洁所述管芯的所述结合表面;
选择所述多个管芯中的管芯;以及
在没有粘合剂并且在所述管芯被安装到所述切割层的同时不激活所述管芯的所述结合表面的情况下,将所述管芯的所述结合表面直接结合到所述第一衬底的所述结合表面。
2.根据权利要求1所述的方法,还包括在分割所述第二衬底之前,将保护性涂层施加到所述第二衬底的所述结合表面。
3.根据权利要求1所述的方法,还包括使用化学试剂、兆频超声波换能器和/或机械刷来清洁所述多个管芯或所述第一衬底的一个或多个表面。
4.根据权利要求1所述的方法,还包括在所述管芯由拾取和放置工具保持的同时处理所述管芯,所述处理包括所述管芯的所述结合表面的原位清洁。
5.根据权利要求1所述的方法,还包括通过使所述管芯的所述结合表面与由疏水材料形成或涂覆有疏水材料的拾取和放置工具接触来拾取所述管芯。
6.根据权利要求1所述的方法,其中所述第一等离子体包括氮等离子体。
7.根据权利要求1所述的方法,其中所述第二等离子体包括氧等离子体。
8.一种形成微电子组件的方法,包括:
准备第一衬底的结合表面;
准备第二衬底的结合表面;
将所述第二衬底安装到切割层;
在所述第二衬底被安装到所述切割层的同时将所述第二衬底分割成多个管芯,所述多个管芯中的每个管芯具有包括所述第二衬底的所述结合表面的一部分的结合表面;
在所述多个管芯被安装到所述切割带的同时处理所述多个管芯;
选择所述多个管芯中的管芯并且从所述切割带移除所述管芯;
激活所述第一衬底的所述结合表面或所述管芯的所述结合表面中的一个;以及
在没有粘合剂并且在不激活所述第一衬底的所述结合表面或所述管芯的所述结合表面中的另一个的情况下,将所述管芯的所述结合表面直接结合到所述第一衬底的所述结合表面。
9.根据权利要求8所述的方法,还包括利用氧等离子体清洁所述第一衬底的所述结合表面或所述管芯的所述结合表面中的另一个。
10.根据权利要求8所述的方法,其中所述第一衬底的所述结合表面或所述管芯的所述结合表面利用氮等离子体被激活。
11.根据权利要求8所述的方法,其中所述管芯的所述结合表面是所述管芯的第一结合表面,并且其中所述管芯包括与所述管芯的所述第一结合表面相对的第二结合表面,所述方法还包括:
利用氮等离子体激活所述管芯的所述第二结合表面、附加管芯的第一结合表面,或所述管芯的所述第二结合表面和所述附加管芯的所述第一结合表面;以及
在没有粘合剂的情况下,将所述附加管芯的所述第一结合表面直接结合到所述管芯的所述第二结合表面。
12.一种形成微电子组件的方法,包括:
准备第一衬底的结合表面;
准备第二衬底的结合表面;
将所述第二衬底安装到切割层;
在所述第二衬底被安装到所述切割层的同时将所述第二衬底分割成多个管芯,所述多个管芯中的每个管芯具有包括所述第二衬底的所述结合表面的一部分的结合表面;
基于第一气体、利用第一等离子体清洁所述第一衬底的所述结合表面或所述多个管芯中的一个或多个管芯的所述结合表面中的一个;
基于第二气体、利用第二等离子体激活所述第一衬底的所述结合表面或所述多个管芯中的所述一个或多个管芯的所述结合表面中的另一个;以及
在没有粘合剂的情况下,将所述一个或多个管芯的所述结合表面直接结合到所述第一衬底的所述结合表面。
13.根据权利要求12所述的方法,还包括在所述多个管芯被安装到所述切割层的同时清洁所述多个管芯,其中在所述一个或多个管芯被安装到所述切割层的同时或者在从所述切割层移除所述一个或多个管芯之后,激活所述多个管芯中的所述一个或多个管芯的所述结合表面被执行。
14.根据权利要求12所述的方法,还包括在将所述管芯的所述结合表面直接结合到所述第一衬底的所述结合表面之前,使所述管芯的所述结合表面疏水。
15.根据权利要求12所述的方法,还包括施加兆频超声波清洁器以清洁所述多个管芯或所述第一衬底或者所述多个管芯和所述第一衬底。
16.根据权利要求12所述的方法,其中所述第一衬底和所述管芯的所述结合表面包括对应的导电特征结构,所述导电特征结构在所述第一衬底和所述管芯的所述结合表面被直接结合时接触。
17.根据权利要求16所述的方法,还包括在所述直接结合之后在高温下使所述第一衬底和所述管芯退火,以使接触的所述导电特征结构永久接合。
18.根据权利要求12所述的方法,其中所述微电子组件包括所述多个管芯中的多个直接结合的管芯的叠堆,并且其中在将所述多个管芯放置在所述叠堆上之后,所述微电子组件被退火。
19.根据权利要求12所述的方法,其中所述第一等离子体包括氧等离子体。
20.根据权利要求12所述的方法,其中所述第二等离子体包括氮等离子体。
21.一种形成微电子组件的方法,包括:
形成第一衬底的结合表面;
形成第二衬底的结合表面,所述第二衬底具有比所述第一衬底的占有面积小的占有面积,其中形成所述第二衬底的所述结合表面包括在所述第二衬底被安装到层上的同时清洁所述第二衬底的所述结合表面;
激活所述第一衬底的所述结合表面、所述第二衬底的所述结合表面,或所述第一衬底和所述第二衬底的所述结合表面;以及
在没有粘合剂的情况下,将所述第二衬底的所述结合表面直接结合到所述第一衬底的所述结合表面。
22.根据权利要求21所述的方法,其中所述激活包括在所述第二衬底被安装到所述层的同时或者在从所述层移除所述第二衬底之后,向等离子体或者电离气体暴露所述第一衬底的所述结合表面、所述第二衬底的所述结合表面,或所述第一衬底和所述第二衬底的所述结合表面。
23.根据权利要求22所述的方法,其中所述等离子体或者电离气体包括氧或氮等离子体。
24.根据权利要求21所述的方法,其中所述层包括夹持环、切割片或切割层。
25.根据权利要求21所述的方法,还包括在所述直接结合之后在高温下使所述第一衬底和所述第二衬底退火,以使所述第一衬底和所述第二衬底的所述结合表面处的导电特征结构配合以永久接合。
26.根据权利要求21所述的方法,其中所述第二衬底的所述结合表面是所述第二衬底的第一结合表面,并且其中所述第二衬底包括与所述第二衬底的所述第一结合表面相对的第二结合表面,所述方法还包括:
激活所述第二衬底的所述第二结合表面或附加衬底的第一结合表面中的一个;以及
在没有粘合剂的情况下,将所述附加衬底的所述第一结合表面直接结合到所述第二衬底的所述第二结合表面。
27.一种形成微电子组件的方法,包括:
形成第一衬底的结合表面;
形成第二衬底的第一结合表面,所述第二衬底具有比所述第一衬底的占有面积小的占有面积,其中形成所述第二衬底的所述第一结合表面包括在所述第二衬底被安装到层上的同时清洁所述第二衬底的所述第一结合表面;
从所述层移除所述第二衬底,并且形成与所述第二衬底的所述第一结合表面相对的、所述第二衬底的第二结合表面;
激活所述第一衬底的所述结合表面或所述第二衬底的所述第一结合表面和所述第二结合表面;
在没有粘合剂的情况下,将所述第二衬底的所述第一结合表面直接结合到所述第一衬底的所述结合表面;以及
将附加衬底的所述第一结合表面结合到所述第二衬底的所述第二结合表面。
28.根据权利要求27所述的方法,其中在没有粘合剂的情况下,所述附加衬底使用直接结合方法被结合到所述第二衬底的所述第二结合表面。
29.根据权利要求27所述的方法,还包括在比所述微电子组件的环境温度高的温度下使所述微电子组件退火,以使所述第一衬底和所述第二衬底的所述结合表面处的导电特征结构配合以永久接合。
30.一种形成微电子组件的方法,所述方法包括:
准备第一衬底的结合表面;
准备第二衬底的结合表面;
激活所述第一衬底的所述结合表面;以及
在没有粘合剂并且在不激活所述第二衬底的所述结合表面的情况下,将所述第二衬底的所述结合表面直接结合到所述第一衬底的所述结合表面。
31.根据权利要求30所述的方法,还包括在所述直接结合之前,将晶圆安装到切割层并且将所述晶圆分割成多个管芯,所述第二衬底包括所述多个管芯中的管芯。
32.根据权利要求31所述的方法,还包括在所述多个管芯被安装到所述切割层的同时处理所述多个管芯,包括清洁所述管芯的所述结合表面。
33.根据权利要求30所述的方法,其中激活所述第一衬底的所述结合表面包括基于第一气体、利用第一等离子体激活所述第一衬底的所述结合表面。
34.根据权利要求33所述的方法,其中处理所述多个管芯包括基于与所述第一气体不同的第二气体、利用未激活第二等离子体清洁所述管芯的所述结合表面。
35.根据权利要求34所述的方法,其中所述第一等离子体包括氮等离子体。
36.根据权利要求35所述的方法,其中所述第二等离子体包括氧等离子体。
37.根据权利要求32所述的方法,还包括在分割所述晶圆之前,将保护性涂层施加到所述晶圆的所述结合表面。
38.根据权利要求37所述的方法,其中清洁所述管芯的所述结合表面包括从所述管芯的所述结合表面移除所述保护性涂层。
39.根据权利要求37所述的方法,还包括将保护性涂层施加到所述第一衬底的所述结合表面。
40.根据权利要求31所述的方法,还包括通过使所述管芯的所述结合表面与拾取和放置工具接触来拾取所述管芯。
41.根据权利要求40所述的方法,还包括使所述管芯的背表面与结合工具接触,以及利用所述结合工具将所述第二衬底的至少一部分的所述结合表面直接结合到所述第一衬底的所述结合表面,所述背表面与所述第二衬底的所述至少一部分的所述结合表面相对。
42.根据权利要求30所述的方法,其中将所述第二衬底的所述结合表面直接结合到所述第一衬底的所述结合表面包括将第一晶圆的所述结合表面直接结合到第二晶圆的所述结合表面。
43.一种形成微电子组件的方法,所述方法包括:
准备第一衬底的第一结合表面;
使管芯的第二集合表面与拾取和放置工具接触,并且从支撑移除所述管芯;
使所述管芯的背表面与结合工具接触,所述背表面与所述第二结合表面相对;
激活所述第一结合表面和所述第二结合表面中的仅一个;以及
在没有粘合剂并且在不激活所述第一结合表面和所述第二结合表面中的另一个的情况下,使用所述结合工具将所述第一衬底的所述第一结合表面直接结合到所述管芯的所述第二结合表面。
44.根据权利要求43所述的方法,还包括准备第二衬底的结合表面,以及在准备所述第二衬底的所述结合表面之后,将所述第二衬底安装到所述支撑,并且将所述第二衬底分割成多个管芯,所述多个管芯包括所述管芯。
45.根据权利要求44所述的方法,还包括在所述多个管芯被安装到所述支撑的同时处理所述多个管芯,包括清洁所述管芯的所述结合表面。
46.根据权利要求45所述的方法,其中激活包括基于第一气体、利用第一等离子体激活,并且其中处理所述多个管芯包括基于与所述第一气体不同的第二气体、利用未激活第二等离子体清洁所述管芯的所述结合表面。
47.根据权利要求46所述的方法,其中所述第一等离子体包括氮等离子体,并且其中所述第二等离子体包括氧等离子体。
48.根据权利要求44所述的方法,还包括在分割所述第二衬底之前,将保护性涂层施加到所述第二衬底的所述结合表面。
49.一种结合结构,包括:
第一衬底,所述第一衬底在没有居间粘合剂的情况下,沿着结合界面被直接结合到管芯,所述管芯具有比所述第一衬底的占有面积小的占有面积,
其中所述管芯和所述第一衬底中的一个包括在结合之前已利用激活种而被激活的特性剖面,并且所述管芯和所述第一衬底中的另一个缺少在结合之前已利用所述激活种而被激活的所述特性剖面。
50.根据权利要求49所述的结合结构,其中所述激活种包括氮。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862631216P | 2018-02-15 | 2018-02-15 | |
US62/631,216 | 2018-02-15 | ||
US16/262,489 | 2019-01-30 | ||
US16/262,489 US10727219B2 (en) | 2018-02-15 | 2019-01-30 | Techniques for processing devices |
CN201980013695.8A CN111742398B (zh) | 2018-02-15 | 2019-01-31 | 用于处理器件的技术 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980013695.8A Division CN111742398B (zh) | 2018-02-15 | 2019-01-31 | 用于处理器件的技术 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113410133A true CN113410133A (zh) | 2021-09-17 |
Family
ID=67541023
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110686074.5A Pending CN113410133A (zh) | 2018-02-15 | 2019-01-31 | 用于处理器件的技术 |
CN201980013695.8A Active CN111742398B (zh) | 2018-02-15 | 2019-01-31 | 用于处理器件的技术 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980013695.8A Active CN111742398B (zh) | 2018-02-15 | 2019-01-31 | 用于处理器件的技术 |
Country Status (4)
Country | Link |
---|---|
US (3) | US10727219B2 (zh) |
CN (2) | CN113410133A (zh) |
TW (2) | TWI836575B (zh) |
WO (1) | WO2019160690A1 (zh) |
Families Citing this family (82)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7109092B2 (en) | 2003-05-19 | 2006-09-19 | Ziptronix, Inc. | Method of room temperature covalent bonding |
US7485968B2 (en) | 2005-08-11 | 2009-02-03 | Ziptronix, Inc. | 3D IC method and device |
US8735219B2 (en) | 2012-08-30 | 2014-05-27 | Ziptronix, Inc. | Heterogeneous annealing method and device |
US20150262902A1 (en) | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
US11069734B2 (en) | 2014-12-11 | 2021-07-20 | Invensas Corporation | Image sensor device |
US9741620B2 (en) | 2015-06-24 | 2017-08-22 | Invensas Corporation | Structures and methods for reliable packages |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
US10446487B2 (en) | 2016-09-30 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
US11176450B2 (en) | 2017-08-03 | 2021-11-16 | Xcelsis Corporation | Three dimensional circuit implementing machine trained network |
US10580735B2 (en) | 2016-10-07 | 2020-03-03 | Xcelsis Corporation | Stacked IC structure with system level wiring on multiple sides of the IC die |
TWI822659B (zh) | 2016-10-27 | 2023-11-21 | 美商艾德亞半導體科技有限責任公司 | 用於低溫接合的結構和方法 |
US10002844B1 (en) | 2016-12-21 | 2018-06-19 | Invensas Bonding Technologies, Inc. | Bonded structures |
US20180182665A1 (en) | 2016-12-28 | 2018-06-28 | Invensas Bonding Technologies, Inc. | Processed Substrate |
KR20230156179A (ko) | 2016-12-29 | 2023-11-13 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 집적된 수동 컴포넌트를 구비한 접합된 구조체 |
WO2018169968A1 (en) | 2017-03-16 | 2018-09-20 | Invensas Corporation | Direct-bonded led arrays and applications |
US10515913B2 (en) | 2017-03-17 | 2019-12-24 | Invensas Bonding Technologies, Inc. | Multi-metal contact structure |
US10508030B2 (en) | 2017-03-21 | 2019-12-17 | Invensas Bonding Technologies, Inc. | Seal for microelectronic assembly |
US10269756B2 (en) | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
US10879212B2 (en) | 2017-05-11 | 2020-12-29 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
US10446441B2 (en) | 2017-06-05 | 2019-10-15 | Invensas Corporation | Flat metal features for microelectronics applications |
US10217720B2 (en) | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
US11195748B2 (en) | 2017-09-27 | 2021-12-07 | Invensas Corporation | Interconnect structures and methods for forming same |
US11031285B2 (en) | 2017-10-06 | 2021-06-08 | Invensas Bonding Technologies, Inc. | Diffusion barrier collar for interconnects |
US10923408B2 (en) | 2017-12-22 | 2021-02-16 | Invensas Bonding Technologies, Inc. | Cavity packages |
US11380597B2 (en) | 2017-12-22 | 2022-07-05 | Invensas Bonding Technologies, Inc. | Bonded structures |
US10727219B2 (en) * | 2018-02-15 | 2020-07-28 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
US11169326B2 (en) | 2018-02-26 | 2021-11-09 | Invensas Bonding Technologies, Inc. | Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects |
US11056348B2 (en) | 2018-04-05 | 2021-07-06 | Invensas Bonding Technologies, Inc. | Bonding surfaces for microelectronics |
US10790262B2 (en) | 2018-04-11 | 2020-09-29 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
US10964664B2 (en) | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
JP7130323B2 (ja) * | 2018-05-14 | 2022-09-05 | 株式会社ディスコ | ウェーハの加工方法 |
US11004757B2 (en) | 2018-05-14 | 2021-05-11 | Invensas Bonding Technologies, Inc. | Bonded structures |
JP7281873B2 (ja) | 2018-05-14 | 2023-05-26 | 株式会社ディスコ | ウェーハの加工方法 |
US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
US10923413B2 (en) | 2018-05-30 | 2021-02-16 | Xcelsis Corporation | Hard IP blocks with physically bidirectional passageways |
KR20210009426A (ko) | 2018-06-13 | 2021-01-26 | 인벤사스 본딩 테크놀로지스 인코포레이티드 | 패드로서의 tsv |
US11393779B2 (en) | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
US10910344B2 (en) | 2018-06-22 | 2021-02-02 | Xcelsis Corporation | Systems and methods for releveled bump planes for chiplets |
WO2020010056A1 (en) | 2018-07-03 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Techniques for joining dissimilar materials in microelectronics |
WO2020010136A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
US11462419B2 (en) | 2018-07-06 | 2022-10-04 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
US11515291B2 (en) | 2018-08-28 | 2022-11-29 | Adeia Semiconductor Inc. | Integrated voltage regulator and passive components |
US20200075533A1 (en) | 2018-08-29 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes |
US11011494B2 (en) | 2018-08-31 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
US11158573B2 (en) | 2018-10-22 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Interconnect structures |
US11244920B2 (en) | 2018-12-18 | 2022-02-08 | Invensas Bonding Technologies, Inc. | Method and structures for low temperature device bonding |
CN113330557A (zh) | 2019-01-14 | 2021-08-31 | 伊文萨思粘合技术公司 | 键合结构 |
US11901281B2 (en) | 2019-03-11 | 2024-02-13 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with integrated passive component |
US10854578B2 (en) | 2019-03-29 | 2020-12-01 | Invensas Corporation | Diffused bitline replacement in stacked wafer memory |
US11205625B2 (en) | 2019-04-12 | 2021-12-21 | Invensas Bonding Technologies, Inc. | Wafer-level bonding of obstructive elements |
US11610846B2 (en) | 2019-04-12 | 2023-03-21 | Adeia Semiconductor Bonding Technologies Inc. | Protective elements for bonded structures including an obstructive element |
US11373963B2 (en) | 2019-04-12 | 2022-06-28 | Invensas Bonding Technologies, Inc. | Protective elements for bonded structures |
US11355404B2 (en) | 2019-04-22 | 2022-06-07 | Invensas Bonding Technologies, Inc. | Mitigating surface damage of probe pads in preparation for direct bonding of a substrate |
US11385278B2 (en) | 2019-05-23 | 2022-07-12 | Invensas Bonding Technologies, Inc. | Security circuitry for bonded structures |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US12080672B2 (en) | 2019-09-26 | 2024-09-03 | Adeia Semiconductor Bonding Technologies Inc. | Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive |
US11862602B2 (en) | 2019-11-07 | 2024-01-02 | Adeia Semiconductor Technologies Llc | Scalable architecture for reduced cycles across SOC |
US11762200B2 (en) | 2019-12-17 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded optical devices |
US11876076B2 (en) | 2019-12-20 | 2024-01-16 | Adeia Semiconductor Technologies Llc | Apparatus for non-volatile random access memory stacks |
US11842894B2 (en) | 2019-12-23 | 2023-12-12 | Adeia Semiconductor Bonding Technologies Inc. | Electrical redundancy for bonded structures |
US11721653B2 (en) | 2019-12-23 | 2023-08-08 | Adeia Semiconductor Bonding Technologies Inc. | Circuitry for electrical redundancy in bonded structures |
US11817304B2 (en) * | 2019-12-30 | 2023-11-14 | Micron Technology, Inc. | Method of manufacturing microelectronic devices, related devices, systems, and apparatus |
KR20230003471A (ko) | 2020-03-19 | 2023-01-06 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 직접 결합된 구조체들을 위한 치수 보상 제어 |
US11742314B2 (en) | 2020-03-31 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Reliable hybrid bonded apparatus |
US11735523B2 (en) | 2020-05-19 | 2023-08-22 | Adeia Semiconductor Bonding Technologies Inc. | Laterally unconfined structure |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
WO2022000385A1 (zh) | 2020-07-01 | 2022-01-06 | 重庆康佳光电技术研究院有限公司 | 显示面板的制作方法、显示面板及显示装置 |
US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11264357B1 (en) | 2020-10-20 | 2022-03-01 | Invensas Corporation | Mixed exposure for large die |
KR20230095110A (ko) * | 2020-10-29 | 2023-06-28 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 직접 접합 방법 및 구조체 |
WO2022094587A1 (en) * | 2020-10-29 | 2022-05-05 | Invensas Bonding Technologies, Inc. | Direct bonding methods and structures |
EP4315411A1 (en) * | 2021-03-31 | 2024-02-07 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding methods and structures |
CN113385989B (zh) * | 2021-06-10 | 2022-08-30 | 安徽光智科技有限公司 | 一种非粘接性的多片磨边滚圆方法 |
US20230045597A1 (en) * | 2021-08-04 | 2023-02-09 | Applied Materials, Inc. | Methods and apparatus for minimizing voids for chip on wafer components |
US20230115122A1 (en) * | 2021-09-14 | 2023-04-13 | Adeia Semiconductor Bonding Technologies Inc. | Method of bonding thin substrates |
FR3131469A1 (fr) * | 2021-12-23 | 2023-06-30 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procédé d’assemblage par collage direct de composants électroniques |
US20230268300A1 (en) * | 2022-02-24 | 2023-08-24 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures |
US20240194635A1 (en) * | 2022-12-09 | 2024-06-13 | Applied Materials, Inc. | Integrated process sequence for hybrid bonding applications |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080315351A1 (en) * | 2007-06-20 | 2008-12-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor substrate and maehtod for manufacturing the same |
CN101552281A (zh) * | 2002-07-29 | 2009-10-07 | 富士胶片株式会社 | 固态成像设备及制造所述固态成像设备的方法 |
CN101558483A (zh) * | 2005-08-11 | 2009-10-14 | 齐普特洛尼克斯公司 | 三维ic方法和器件 |
CN102034687A (zh) * | 2009-09-28 | 2011-04-27 | S.O.I.Tec绝缘体上硅技术公司 | 键合和转移层的工艺 |
CN102209692A (zh) * | 2008-11-07 | 2011-10-05 | S.O.I.技术(硅绝缘体技术)公司 | 用于分子结合的表面处理 |
US20120112347A1 (en) * | 2010-06-11 | 2012-05-10 | Helmut Eckhardt | Flexible electronic devices and related methods |
CN105589587A (zh) * | 2014-10-21 | 2016-05-18 | 宸鸿科技(厦门)有限公司 | 透明复合基板与其制备方法及触控面板 |
CN106082108A (zh) * | 2015-04-29 | 2016-11-09 | 台湾积体电路制造股份有限公司 | 用于减少背侧硅损坏的结构 |
US20170045749A1 (en) * | 2015-08-10 | 2017-02-16 | Corning Incorporated | Methods for making optical devices |
JP2017124586A (ja) * | 2016-01-15 | 2017-07-20 | 東洋紡株式会社 | フレキシブル電子デバイスの製造方法 |
Family Cites Families (266)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2626408B1 (fr) | 1988-01-22 | 1990-05-11 | Thomson Csf | Capteur d'image a faible encombrement |
DE69429848T2 (de) | 1993-11-01 | 2002-09-26 | Matsushita Electric Industrial Co., Ltd. | Elektronische Anordnung und Verfahren zur Herstellung |
KR960009074A (ko) | 1994-08-29 | 1996-03-22 | 모리시다 요이치 | 반도체 장치 및 그 제조방법 |
US6097096A (en) | 1997-07-11 | 2000-08-01 | Advanced Micro Devices | Metal attachment method and structure for attaching substrates at low temperatures |
FR2787241B1 (fr) | 1998-12-14 | 2003-01-31 | Ela Medical Sa | Composant microelectronique cms enrobe, notamment pour un dispositif medical implantable actif, et son procede de fabrication |
KR20010052451A (ko) | 1999-03-30 | 2001-06-25 | 롤페스 요하네스 게라투스 알베르투스 | 반도체 웨이퍼 세척 장치 및 방법 |
JP3532788B2 (ja) | 1999-04-13 | 2004-05-31 | 唯知 須賀 | 半導体装置及びその製造方法 |
US6984571B1 (en) | 1999-10-01 | 2006-01-10 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6902987B1 (en) | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
JP3440057B2 (ja) | 2000-07-05 | 2003-08-25 | 唯知 須賀 | 半導体装置およびその製造方法 |
US6423640B1 (en) | 2000-08-09 | 2002-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Headless CMP process for oxide planarization |
TW522531B (en) | 2000-10-20 | 2003-03-01 | Matsushita Electric Ind Co Ltd | Semiconductor device, method of manufacturing the device and mehtod of mounting the device |
JP2002134658A (ja) * | 2000-10-24 | 2002-05-10 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2002353416A (ja) | 2001-05-25 | 2002-12-06 | Sony Corp | 半導体記憶装置およびその製造方法 |
US6793759B2 (en) | 2001-10-09 | 2004-09-21 | Dow Corning Corporation | Method for creating adhesion during fabrication of electronic devices |
US6887769B2 (en) | 2002-02-06 | 2005-05-03 | Intel Corporation | Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same |
US6762076B2 (en) | 2002-02-20 | 2004-07-13 | Intel Corporation | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices |
US7105980B2 (en) | 2002-07-03 | 2006-09-12 | Sawtek, Inc. | Saw filter device and method employing normal temperature bonding for producing desirable filter production and performance characteristics |
JP4083502B2 (ja) | 2002-08-19 | 2008-04-30 | 株式会社フジミインコーポレーテッド | 研磨方法及びそれに用いられる研磨用組成物 |
US6822326B2 (en) | 2002-09-25 | 2004-11-23 | Ziptronix | Wafer bonding hermetic encapsulation |
US7023093B2 (en) | 2002-10-24 | 2006-04-04 | International Business Machines Corporation | Very low effective dielectric constant interconnect Structures and methods for fabricating the same |
US6962835B2 (en) | 2003-02-07 | 2005-11-08 | Ziptronix, Inc. | Method for room temperature metal direct bonding |
US6908027B2 (en) | 2003-03-31 | 2005-06-21 | Intel Corporation | Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process |
US7109092B2 (en) | 2003-05-19 | 2006-09-19 | Ziptronix, Inc. | Method of room temperature covalent bonding |
GB2404280B (en) | 2003-07-03 | 2006-09-27 | Xsil Technology Ltd | Die bonding |
JP3980539B2 (ja) | 2003-08-29 | 2007-09-26 | 唯知 須賀 | 基板接合方法、照射方法、および基板接合装置 |
US6867073B1 (en) | 2003-10-21 | 2005-03-15 | Ziptronix, Inc. | Single mask via method and device |
US20060057945A1 (en) | 2004-09-16 | 2006-03-16 | Chia-Lin Hsu | Chemical mechanical polishing process |
TWI303864B (en) | 2004-10-26 | 2008-12-01 | Sanyo Electric Co | Semiconductor device and method for making the same |
JP2007081037A (ja) | 2005-09-13 | 2007-03-29 | Disco Abrasive Syst Ltd | デバイスおよびその製造方法 |
US20070075417A1 (en) | 2005-10-05 | 2007-04-05 | Samsung Electro-Mechanics Co., Ltd. | MEMS module package using sealing cap having heat releasing capability and manufacturing method thereof |
US7550366B2 (en) | 2005-12-02 | 2009-06-23 | Ayumi Industry | Method for bonding substrates and device for bonding substrates |
US7193423B1 (en) | 2005-12-12 | 2007-03-20 | International Business Machines Corporation | Wafer-to-wafer alignments |
JP4160083B2 (ja) | 2006-04-11 | 2008-10-01 | シャープ株式会社 | 光学装置用モジュール及び光学装置用モジュールの製造方法 |
US7750488B2 (en) | 2006-07-10 | 2010-07-06 | Tezzaron Semiconductor, Inc. | Method for bonding wafers to produce stacked integrated circuits |
JP2008130603A (ja) | 2006-11-16 | 2008-06-05 | Toshiba Corp | イメージセンサ用ウェハレベルパッケージ及びその製造方法 |
JP4840174B2 (ja) | 2007-02-08 | 2011-12-21 | パナソニック株式会社 | 半導体チップの製造方法 |
US7803693B2 (en) | 2007-02-15 | 2010-09-28 | John Trezza | Bowed wafer hybridization compensation |
US7919410B2 (en) | 2007-03-14 | 2011-04-05 | Aptina Imaging Corporation | Packaging methods for imager devices |
JP2008244080A (ja) | 2007-03-27 | 2008-10-09 | Sharp Corp | 半導体素子の製造方法 |
TWI332790B (en) | 2007-06-13 | 2010-11-01 | Ind Tech Res Inst | Image sensor module with a three-dimensional dies-stacking structure |
KR101413380B1 (ko) * | 2007-08-28 | 2014-06-30 | 쓰리엠 이노베이티브 프로퍼티즈 캄파니 | 반도체 다이의 제조방법, 상기 방법으로 제조된 반도체다이를 포함하는 반도체 소자 |
US20090127667A1 (en) | 2007-11-21 | 2009-05-21 | Powertech Technology Inc. | Semiconductor chip device having through-silicon-via (TSV) and its fabrication method |
KR20100122110A (ko) * | 2008-03-07 | 2010-11-19 | 쓰리엠 이노베이티브 프로퍼티즈 컴파니 | 패턴화된 배킹이 있는 다이싱 테이프 및 다이 부착 접착제 |
KR20090106822A (ko) | 2008-04-07 | 2009-10-12 | 삼성전자주식회사 | 웨이퍼 본딩 방법 및 그 방법에 의해 본딩된 웨이퍼 구조체 |
US8349635B1 (en) | 2008-05-20 | 2013-01-08 | Silicon Laboratories Inc. | Encapsulated MEMS device and method to form the same |
FR2931585B1 (fr) | 2008-05-26 | 2010-09-03 | Commissariat Energie Atomique | Traitement de surface par plasma d'azote dans un procede de collage direct |
US20090320875A1 (en) | 2008-06-25 | 2009-12-31 | Applied Materials, Inc. | Dual chamber megasonic cleaner |
US8193632B2 (en) | 2008-08-06 | 2012-06-05 | Industrial Technology Research Institute | Three-dimensional conducting structure and method of fabricating the same |
US9893004B2 (en) | 2011-07-27 | 2018-02-13 | Broadpak Corporation | Semiconductor interposer integration |
US8168458B2 (en) | 2008-12-08 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices |
US8476165B2 (en) | 2009-04-01 | 2013-07-02 | Tokyo Electron Limited | Method for thinning a bonding wafer |
US8263434B2 (en) | 2009-07-31 | 2012-09-11 | Stats Chippac, Ltd. | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
US8482132B2 (en) | 2009-10-08 | 2013-07-09 | International Business Machines Corporation | Pad bonding employing a self-aligned plated liner for adhesion enhancement |
JP2011128140A (ja) | 2009-11-19 | 2011-06-30 | Dainippon Printing Co Ltd | センサデバイス及びその製造方法 |
JP2011104633A (ja) | 2009-11-19 | 2011-06-02 | Stanley Electric Co Ltd | スクライブ方法 |
JP5807221B2 (ja) | 2010-06-28 | 2015-11-10 | アユミ工業株式会社 | 接合構造体製造方法および加熱溶融処理方法ならびにこれらのシステム |
JP5517800B2 (ja) | 2010-07-09 | 2014-06-11 | キヤノン株式会社 | 固体撮像装置用の部材および固体撮像装置の製造方法 |
US8481406B2 (en) | 2010-07-15 | 2013-07-09 | Soitec | Methods of forming bonded semiconductor structures |
SG177816A1 (en) * | 2010-07-15 | 2012-02-28 | Soitec Silicon On Insulator | Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods |
FR2963158B1 (fr) | 2010-07-21 | 2013-05-17 | Commissariat Energie Atomique | Procede d'assemblage par collage direct entre deux elements comprenant des portions de cuivre et de materiaux dielectriques |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
FR2966283B1 (fr) | 2010-10-14 | 2012-11-30 | Soi Tec Silicon On Insulator Tech Sa | Procede pour realiser une structure de collage |
US8377798B2 (en) | 2010-11-10 | 2013-02-19 | Taiwan Semiconductor Manufacturing Co., Ltd | Method and structure for wafer to wafer bonding in semiconductor packaging |
US8620164B2 (en) | 2011-01-20 | 2013-12-31 | Intel Corporation | Hybrid III-V silicon laser formed by direct bonding |
JP5682327B2 (ja) | 2011-01-25 | 2015-03-11 | ソニー株式会社 | 固体撮像素子、固体撮像素子の製造方法、及び電子機器 |
US20120194719A1 (en) | 2011-02-01 | 2012-08-02 | Scott Churchwell | Image sensor units with stacked image sensors and image processors |
WO2012133760A1 (ja) | 2011-03-30 | 2012-10-04 | ボンドテック株式会社 | 電子部品実装方法、電子部品実装システムおよび基板 |
US8501537B2 (en) | 2011-03-31 | 2013-08-06 | Soitec | Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods |
US8716105B2 (en) | 2011-03-31 | 2014-05-06 | Soitec | Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
EP3534399A1 (en) | 2011-05-24 | 2019-09-04 | Sony Corporation | Semiconductor device |
US9252172B2 (en) | 2011-05-31 | 2016-02-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region |
JP5982748B2 (ja) | 2011-08-01 | 2016-08-31 | ソニー株式会社 | 半導体装置、半導体装置の製造方法、および電子機器 |
US8697493B2 (en) | 2011-07-18 | 2014-04-15 | Soitec | Bonding surfaces for direct bonding of semiconductor structures |
US8552567B2 (en) | 2011-07-27 | 2013-10-08 | Micron Technology, Inc. | Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication |
US8441131B2 (en) | 2011-09-12 | 2013-05-14 | Globalfoundries Inc. | Strain-compensating fill patterns for controlling semiconductor chip package interactions |
JP5780228B2 (ja) * | 2011-11-11 | 2015-09-16 | 住友ベークライト株式会社 | 半導体装置の製造方法 |
FR2987626B1 (fr) | 2012-03-05 | 2015-04-03 | Commissariat Energie Atomique | Procede de collage direct utilisant une couche poreuse compressible |
CN104254927B (zh) | 2012-04-16 | 2018-06-01 | 亮锐控股有限公司 | 用于产生w-台面管芯间隔的方法和装置 |
CN103377911B (zh) | 2012-04-16 | 2016-09-21 | 中国科学院微电子研究所 | 提高化学机械平坦化工艺均匀性的方法 |
JP5664592B2 (ja) | 2012-04-26 | 2015-02-04 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
US9142517B2 (en) | 2012-06-05 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding mechanisms for semiconductor wafers |
US8809123B2 (en) | 2012-06-05 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers |
US9048283B2 (en) | 2012-06-05 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding systems and methods for semiconductor wafers |
US20140001949A1 (en) | 2012-06-29 | 2014-01-02 | Nitto Denko Corporation | Phosphor layer-covered led, producing method thereof, and led device |
US8735219B2 (en) | 2012-08-30 | 2014-05-27 | Ziptronix, Inc. | Heterogeneous annealing method and device |
US9136293B2 (en) | 2012-09-07 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for sensor module |
TW201423873A (zh) * | 2012-12-03 | 2014-06-16 | Powertech Technology Inc | 包含晶圓級撿晶之覆晶接合方法 |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US20140175655A1 (en) | 2012-12-22 | 2014-06-26 | Industrial Technology Research Institute | Chip bonding structure and manufacturing method thereof |
US8946784B2 (en) | 2013-02-18 | 2015-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for image sensor packaging |
US9443796B2 (en) | 2013-03-15 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Air trench in packages incorporating hybrid bonding |
US8802538B1 (en) | 2013-03-15 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for hybrid wafer bonding |
JP6157911B2 (ja) | 2013-04-17 | 2017-07-05 | 富士通株式会社 | 光半導体装置 |
JP6224509B2 (ja) * | 2013-05-14 | 2017-11-01 | 信越化学工業株式会社 | ウエハ用仮接着材料、それらを用いた仮接着用フィルム、及びウエハ加工体並びにそれらを使用した薄型ウエハの製造方法 |
US9064937B2 (en) | 2013-05-30 | 2015-06-23 | International Business Machines Corporation | Substrate bonding with diffusion barrier structures |
US8860229B1 (en) | 2013-07-16 | 2014-10-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonding with through substrate via (TSV) |
US9929050B2 (en) | 2013-07-16 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure |
US9723716B2 (en) | 2013-09-27 | 2017-08-01 | Infineon Technologies Ag | Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure |
US9257399B2 (en) | 2013-10-17 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D integrated circuit and methods of forming the same |
JP2015115446A (ja) | 2013-12-11 | 2015-06-22 | 株式会社東芝 | 半導体装置の製造方法 |
US9887162B2 (en) * | 2013-12-18 | 2018-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Molding structure for wafer level package |
US9437572B2 (en) | 2013-12-18 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pad structure for hybrid bonding and methods of forming same |
US9018079B1 (en) | 2014-01-29 | 2015-04-28 | Applied Materials, Inc. | Wafer dicing using hybrid laser scribing and plasma etch approach with intermediate reactive post mask-opening clean |
US20150255349A1 (en) | 2014-03-07 | 2015-09-10 | JAMES Matthew HOLDEN | Approaches for cleaning a wafer during hybrid laser scribing and plasma etching wafer dicing processes |
US20150262902A1 (en) | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
US9299736B2 (en) | 2014-03-28 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding with uniform pattern density |
US9230941B2 (en) | 2014-03-28 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding structure for stacked semiconductor devices |
US9472458B2 (en) | 2014-06-04 | 2016-10-18 | Semiconductor Components Industries, Llc | Method of reducing residual contamination in singulated semiconductor die |
US9142459B1 (en) | 2014-06-30 | 2015-09-22 | Applied Materials, Inc. | Wafer dicing using hybrid laser scribing and plasma etch approach with mask application by vacuum lamination |
KR102275705B1 (ko) | 2014-07-11 | 2021-07-09 | 삼성전자주식회사 | 웨이퍼 대 웨이퍼 접합 구조 |
JP2016072316A (ja) | 2014-09-29 | 2016-05-09 | 日立オートモティブシステムズ株式会社 | 半導体装置の製造方法 |
US9536848B2 (en) | 2014-10-16 | 2017-01-03 | Globalfoundries Inc. | Bond pad structure for low temperature flip chip bonding |
JP6367084B2 (ja) | 2014-10-30 | 2018-08-01 | 株式会社東芝 | 半導体チップの接合方法及び半導体チップの接合装置 |
US9394161B2 (en) | 2014-11-14 | 2016-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | MEMS and CMOS integration with low-temperature bonding |
US11069734B2 (en) | 2014-12-11 | 2021-07-20 | Invensas Corporation | Image sensor device |
US9899442B2 (en) | 2014-12-11 | 2018-02-20 | Invensas Corporation | Image sensor device |
US9971777B2 (en) | 2014-12-18 | 2018-05-15 | International Business Machines Corporation | Smart archiving of real-time performance monitoring data |
JP6738591B2 (ja) | 2015-03-13 | 2020-08-12 | 古河電気工業株式会社 | 半導体ウェハの処理方法、半導体チップおよび表面保護テープ |
US9741620B2 (en) | 2015-06-24 | 2017-08-22 | Invensas Corporation | Structures and methods for reliable packages |
US9656852B2 (en) | 2015-07-06 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company Ltd. | CMOS-MEMS device structure, bonding mesa structure and associated method |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US10075657B2 (en) | 2015-07-21 | 2018-09-11 | Fermi Research Alliance, Llc | Edgeless large area camera system |
US9728521B2 (en) | 2015-07-23 | 2017-08-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bond using a copper alloy for yield improvement |
CN106409650B (zh) | 2015-08-03 | 2019-01-29 | 沈阳硅基科技有限公司 | 一种硅片直接键合方法 |
US9559081B1 (en) | 2015-08-21 | 2017-01-31 | Apple Inc. | Independent 3D stacking |
US9953941B2 (en) | 2015-08-25 | 2018-04-24 | Invensas Bonding Technologies, Inc. | Conductive barrier direct hybrid bonding |
US9496239B1 (en) | 2015-12-11 | 2016-11-15 | International Business Machines Corporation | Nitride-enriched oxide-to-oxide 3D wafer bonding |
US9852988B2 (en) | 2015-12-18 | 2017-12-26 | Invensas Bonding Technologies, Inc. | Increased contact alignment tolerance for direct bonding |
US9923011B2 (en) | 2016-01-12 | 2018-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure with stacked semiconductor dies |
US10446532B2 (en) | 2016-01-13 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Systems and methods for efficient transfer of semiconductor elements |
US10026716B2 (en) | 2016-04-15 | 2018-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC formation with dies bonded to formed RDLs |
US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
KR102505856B1 (ko) | 2016-06-09 | 2023-03-03 | 삼성전자 주식회사 | 웨이퍼 대 웨이퍼 접합 구조체 |
US9941241B2 (en) | 2016-06-30 | 2018-04-10 | International Business Machines Corporation | Method for wafer-wafer bonding |
US9892961B1 (en) | 2016-08-09 | 2018-02-13 | International Business Machines Corporation | Air gap spacer formation for nano-scale semiconductor devices |
US10446487B2 (en) | 2016-09-30 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
US10672663B2 (en) | 2016-10-07 | 2020-06-02 | Xcelsis Corporation | 3D chip sharing power circuit |
US10580735B2 (en) | 2016-10-07 | 2020-03-03 | Xcelsis Corporation | Stacked IC structure with system level wiring on multiple sides of the IC die |
US11176450B2 (en) | 2017-08-03 | 2021-11-16 | Xcelsis Corporation | Three dimensional circuit implementing machine trained network |
US10163750B2 (en) | 2016-12-05 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure for heat dissipation |
US10453832B2 (en) | 2016-12-15 | 2019-10-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seal ring structures and methods of forming same |
US10002844B1 (en) | 2016-12-21 | 2018-06-19 | Invensas Bonding Technologies, Inc. | Bonded structures |
US20180182665A1 (en) | 2016-12-28 | 2018-06-28 | Invensas Bonding Technologies, Inc. | Processed Substrate |
CN117878055A (zh) | 2016-12-28 | 2024-04-12 | 艾德亚半导体接合科技有限公司 | 堆栈基板的处理 |
KR20230156179A (ko) | 2016-12-29 | 2023-11-13 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 집적된 수동 컴포넌트를 구비한 접합된 구조체 |
US20180190583A1 (en) | 2016-12-29 | 2018-07-05 | Invensas Bonding Technologies, Inc. | Bonded structures with integrated passive component |
US10276909B2 (en) | 2016-12-30 | 2019-04-30 | Invensas Bonding Technologies, Inc. | Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein |
US10431614B2 (en) | 2017-02-01 | 2019-10-01 | Semiconductor Components Industries, Llc | Edge seals for semiconductor packages |
JP7030825B2 (ja) | 2017-02-09 | 2022-03-07 | インヴェンサス ボンディング テクノロジーズ インコーポレイテッド | 接合構造物 |
WO2018169968A1 (en) | 2017-03-16 | 2018-09-20 | Invensas Corporation | Direct-bonded led arrays and applications |
US10515913B2 (en) | 2017-03-17 | 2019-12-24 | Invensas Bonding Technologies, Inc. | Multi-metal contact structure |
US10508030B2 (en) | 2017-03-21 | 2019-12-17 | Invensas Bonding Technologies, Inc. | Seal for microelectronic assembly |
JP6640780B2 (ja) | 2017-03-22 | 2020-02-05 | キオクシア株式会社 | 半導体装置の製造方法および半導体装置 |
US10784191B2 (en) | 2017-03-31 | 2020-09-22 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
US10269756B2 (en) | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
US10580823B2 (en) | 2017-05-03 | 2020-03-03 | United Microelectronics Corp. | Wafer level packaging method |
US10879212B2 (en) | 2017-05-11 | 2020-12-29 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
US10446441B2 (en) | 2017-06-05 | 2019-10-15 | Invensas Corporation | Flat metal features for microelectronics applications |
US10217720B2 (en) | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
CN107331759A (zh) * | 2017-08-21 | 2017-11-07 | 厦门华联电子股份有限公司 | 免有机胶的晶圆级封装方法和led倒装芯片封装体 |
US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
US11195748B2 (en) | 2017-09-27 | 2021-12-07 | Invensas Corporation | Interconnect structures and methods for forming same |
US11031285B2 (en) | 2017-10-06 | 2021-06-08 | Invensas Bonding Technologies, Inc. | Diffusion barrier collar for interconnects |
US11251157B2 (en) | 2017-11-01 | 2022-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die stack structure with hybrid bonding structure and method of fabricating the same and package |
US10672820B2 (en) | 2017-11-23 | 2020-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybrid bonded structure |
US10571703B2 (en) | 2017-12-11 | 2020-02-25 | North Inc. | Wavelength combiner method using photonic integrated circuit with respective input facets for corresponding lasers |
US11011503B2 (en) | 2017-12-15 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Direct-bonded optoelectronic interconnect for high-density integrated photonics |
US10923408B2 (en) | 2017-12-22 | 2021-02-16 | Invensas Bonding Technologies, Inc. | Cavity packages |
US11380597B2 (en) | 2017-12-22 | 2022-07-05 | Invensas Bonding Technologies, Inc. | Bonded structures |
US11127738B2 (en) | 2018-02-09 | 2021-09-21 | Xcelsis Corporation | Back biasing of FD-SOI circuit blocks |
JP6900006B2 (ja) | 2018-02-14 | 2021-07-07 | 東芝デバイス&ストレージ株式会社 | チップ移載部材、チップ移載装置、およびチップ移載方法 |
US10727219B2 (en) * | 2018-02-15 | 2020-07-28 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
US11169326B2 (en) | 2018-02-26 | 2021-11-09 | Invensas Bonding Technologies, Inc. | Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects |
US11256004B2 (en) | 2018-03-20 | 2022-02-22 | Invensas Bonding Technologies, Inc. | Direct-bonded lamination for improved image clarity in optical devices |
US10991804B2 (en) | 2018-03-29 | 2021-04-27 | Xcelsis Corporation | Transistor level interconnection methodologies utilizing 3D interconnects |
US11056348B2 (en) | 2018-04-05 | 2021-07-06 | Invensas Bonding Technologies, Inc. | Bonding surfaces for microelectronics |
US10790262B2 (en) | 2018-04-11 | 2020-09-29 | Invensas Bonding Technologies, Inc. | Low temperature bonded structures |
US10964664B2 (en) | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
US11398258B2 (en) | 2018-04-30 | 2022-07-26 | Invensas Llc | Multi-die module with low power operation |
US10403577B1 (en) | 2018-05-03 | 2019-09-03 | Invensas Corporation | Dielets on flexible and stretchable packaging for microelectronics |
US11004757B2 (en) | 2018-05-14 | 2021-05-11 | Invensas Bonding Technologies, Inc. | Bonded structures |
US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
IT201800005778A1 (it) | 2018-05-28 | 2019-11-28 | Dispositivo microfluidico per l'espulsione di fluidi, in particolare per la stampa con inchiostri, e relativo procedimento di fabbricazione | |
US10923413B2 (en) | 2018-05-30 | 2021-02-16 | Xcelsis Corporation | Hard IP blocks with physically bidirectional passageways |
WO2019241367A1 (en) | 2018-06-12 | 2019-12-19 | Invensas Bonding Technologies, Inc. | Interlayer connection of stacked microelectronic components |
KR20210009426A (ko) | 2018-06-13 | 2021-01-26 | 인벤사스 본딩 테크놀로지스 인코포레이티드 | 패드로서의 tsv |
US11393779B2 (en) | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
US10910344B2 (en) | 2018-06-22 | 2021-02-02 | Xcelsis Corporation | Systems and methods for releveled bump planes for chiplets |
US10937755B2 (en) | 2018-06-29 | 2021-03-02 | Advanced Micro Devices, Inc. | Bond pads for low temperature hybrid bonding |
WO2020010056A1 (en) | 2018-07-03 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Techniques for joining dissimilar materials in microelectronics |
WO2020010136A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
US11462419B2 (en) | 2018-07-06 | 2022-10-04 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
US20200035641A1 (en) | 2018-07-26 | 2020-01-30 | Invensas Bonding Technologies, Inc. | Post cmp processing for hybrid bonding |
US11515291B2 (en) | 2018-08-28 | 2022-11-29 | Adeia Semiconductor Inc. | Integrated voltage regulator and passive components |
US20200075533A1 (en) | 2018-08-29 | 2020-03-05 | Invensas Bonding Technologies, Inc. | Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes |
US11011494B2 (en) | 2018-08-31 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
US11158573B2 (en) | 2018-10-22 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Interconnect structures |
US11244920B2 (en) | 2018-12-18 | 2022-02-08 | Invensas Bonding Technologies, Inc. | Method and structures for low temperature device bonding |
CN113330557A (zh) | 2019-01-14 | 2021-08-31 | 伊文萨思粘合技术公司 | 键合结构 |
US11387202B2 (en) | 2019-03-01 | 2022-07-12 | Invensas Llc | Nanowire bonding interconnect for fine-pitch microelectronics |
US11901281B2 (en) | 2019-03-11 | 2024-02-13 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with integrated passive component |
GB2582388A (en) | 2019-03-22 | 2020-09-23 | Cirrus Logic Int Semiconductor Ltd | Composite structures |
US10854578B2 (en) | 2019-03-29 | 2020-12-01 | Invensas Corporation | Diffused bitline replacement in stacked wafer memory |
US11205625B2 (en) | 2019-04-12 | 2021-12-21 | Invensas Bonding Technologies, Inc. | Wafer-level bonding of obstructive elements |
US11373963B2 (en) | 2019-04-12 | 2022-06-28 | Invensas Bonding Technologies, Inc. | Protective elements for bonded structures |
US11610846B2 (en) | 2019-04-12 | 2023-03-21 | Adeia Semiconductor Bonding Technologies Inc. | Protective elements for bonded structures including an obstructive element |
US11355404B2 (en) | 2019-04-22 | 2022-06-07 | Invensas Bonding Technologies, Inc. | Mitigating surface damage of probe pads in preparation for direct bonding of a substrate |
US11385278B2 (en) | 2019-05-23 | 2022-07-12 | Invensas Bonding Technologies, Inc. | Security circuitry for bonded structures |
US20200395321A1 (en) | 2019-06-12 | 2020-12-17 | Invensas Bonding Technologies, Inc. | Sealed bonded structures and methods for forming the same |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US12080672B2 (en) | 2019-09-26 | 2024-09-03 | Adeia Semiconductor Bonding Technologies Inc. | Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive |
US20210118864A1 (en) | 2019-10-21 | 2021-04-22 | Invensas Corporation | Non-Volatile Dynamic Random Access Memory |
US11862602B2 (en) | 2019-11-07 | 2024-01-02 | Adeia Semiconductor Technologies Llc | Scalable architecture for reduced cycles across SOC |
US11762200B2 (en) | 2019-12-17 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded optical devices |
US11876076B2 (en) | 2019-12-20 | 2024-01-16 | Adeia Semiconductor Technologies Llc | Apparatus for non-volatile random access memory stacks |
US11721653B2 (en) | 2019-12-23 | 2023-08-08 | Adeia Semiconductor Bonding Technologies Inc. | Circuitry for electrical redundancy in bonded structures |
US11842894B2 (en) | 2019-12-23 | 2023-12-12 | Adeia Semiconductor Bonding Technologies Inc. | Electrical redundancy for bonded structures |
US20210242152A1 (en) | 2020-02-05 | 2021-08-05 | Invensas Bonding Technologies, Inc. | Selective alteration of interconnect pads for direct bonding |
KR20230003471A (ko) | 2020-03-19 | 2023-01-06 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 직접 결합된 구조체들을 위한 치수 보상 제어 |
US11742314B2 (en) | 2020-03-31 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Reliable hybrid bonded apparatus |
US11735523B2 (en) | 2020-05-19 | 2023-08-22 | Adeia Semiconductor Bonding Technologies Inc. | Laterally unconfined structure |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11264357B1 (en) | 2020-10-20 | 2022-03-01 | Invensas Corporation | Mixed exposure for large die |
KR20230095110A (ko) | 2020-10-29 | 2023-06-28 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 직접 접합 방법 및 구조체 |
WO2022094587A1 (en) | 2020-10-29 | 2022-05-05 | Invensas Bonding Technologies, Inc. | Direct bonding methods and structures |
JP2024501017A (ja) | 2020-12-28 | 2024-01-10 | アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド | 基板貫通ビアを有する構造体及びそれを形成する方法 |
KR20230125309A (ko) | 2020-12-28 | 2023-08-29 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 기판-관통 비아를 가지는 구조체 및 이를 형성하기위한 방법 |
EP4272249A1 (en) | 2020-12-30 | 2023-11-08 | Adeia Semiconductor Bonding Technologies Inc. | Structure with conductive feature and method of forming same |
US20220208723A1 (en) | 2020-12-30 | 2022-06-30 | Invensas Bonding Technologies, Inc. | Directly bonded structures |
EP4302325A1 (en) | 2021-03-03 | 2024-01-10 | Adeia Semiconductor Bonding Technologies Inc. | Contact structures for direct bonding |
EP4315411A1 (en) | 2021-03-31 | 2024-02-07 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding methods and structures |
WO2022212595A1 (en) | 2021-03-31 | 2022-10-06 | Invensas Bonding Technologies, Inc. | Direct bonding and debonding of carrier |
US20220320036A1 (en) | 2021-03-31 | 2022-10-06 | Invensas Bonding Technologies, Inc. | Direct bonding and debonding of carrier |
WO2023278605A1 (en) | 2021-06-30 | 2023-01-05 | Invensas Bonding Technologies, Inc. | Element with routing structure in bonding layer |
EP4371153A1 (en) | 2021-07-16 | 2024-05-22 | Adeia Semiconductor Bonding Technologies Inc. | Optically obstructive protective element for bonded structures |
JP2024528964A (ja) | 2021-08-02 | 2024-08-01 | アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド | ボンデッド構造体用の保護半導体素子 |
KR20240052815A (ko) | 2021-09-01 | 2024-04-23 | 아데이아 세미컨덕터 테크놀로지스 엘엘씨 | 인터포저를 갖는 적층 구조체 |
US20230067677A1 (en) | 2021-09-01 | 2023-03-02 | Invensas Bonding Technologies, Inc. | Sequences and equipment for direct bonding |
US20230115122A1 (en) | 2021-09-14 | 2023-04-13 | Adeia Semiconductor Bonding Technologies Inc. | Method of bonding thin substrates |
EP4406020A1 (en) | 2021-09-24 | 2024-07-31 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with active interposer |
WO2023069323A1 (en) | 2021-10-18 | 2023-04-27 | Adeia Semiconductor Technologies Llc | Reduced parasitic capacitance in bonded structures |
WO2023069912A1 (en) | 2021-10-19 | 2023-04-27 | Adeia Semiconductor Bonding Technologies Inc. | Stacked inductors in multi-die stacking |
EP4420197A1 (en) | 2021-10-22 | 2024-08-28 | Adeia Semiconductor Technologies LLC | Radio frequency device packages |
CN118355491A (zh) | 2021-10-25 | 2024-07-16 | 美商艾德亚半导体接合科技有限公司 | 堆叠电子器件的功率分配 |
US20230125395A1 (en) | 2021-10-27 | 2023-04-27 | Adeia Semiconductor Bonding Technologies Inc. | Stacked structures with capacitive coupling connections |
WO2023076495A1 (en) | 2021-10-28 | 2023-05-04 | Adeia Semiconductor Bonding Technologies Inc. | Diffusion barriers and method of forming same |
US20230140107A1 (en) | 2021-10-28 | 2023-05-04 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding methods and structures |
US20230142680A1 (en) | 2021-10-28 | 2023-05-11 | Adeia Semiconductor Bonding Technologies Inc. | Stacked electronic devices |
WO2023081273A1 (en) | 2021-11-05 | 2023-05-11 | Adeia Semiconductor Bonding Technologies Inc. | Multi-channel device stacking |
US20230154816A1 (en) | 2021-11-17 | 2023-05-18 | Adeia Semiconductor Bonding Technologies Inc. | Thermal bypass for stacked dies |
CN118613910A (zh) | 2021-11-18 | 2024-09-06 | 美商艾德亚半导体接合科技有限公司 | 用于裸片堆叠的流体冷却 |
US20230187264A1 (en) | 2021-12-13 | 2023-06-15 | Adeia Semiconductor Technologies Llc | Methods for bonding semiconductor elements |
CN118613904A (zh) | 2021-12-13 | 2024-09-06 | 美商艾德亚半导体接合科技有限公司 | 互连结构 |
KR20240118874A (ko) | 2021-12-17 | 2024-08-05 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 직접 접합을 위한 전도성 특징부를 갖는 구조체 및 그 형성 방법 |
WO2023122509A1 (en) | 2021-12-20 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Thermoelectric cooling for die packages |
US20230197496A1 (en) | 2021-12-20 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Direct bonding and debonding of elements |
US20230197560A1 (en) | 2021-12-20 | 2023-06-22 | Adeia Semiconductor Bonding Technologies Inc. | Thermoelectric cooling in microelectronics |
KR20240126868A (ko) | 2021-12-22 | 2024-08-21 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 낮은 스트레스 직접 하이브리드 접합 |
KR20240119164A (ko) | 2021-12-23 | 2024-08-06 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 패키지 기판 상의 직접 결합 |
WO2023122687A1 (en) | 2021-12-23 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Apparatuses and methods for die bond control |
CN118648105A (zh) | 2021-12-23 | 2024-09-13 | 美商艾德亚半导体接合科技有限公司 | 具有互连组件的键合结构 |
US20230207402A1 (en) | 2021-12-27 | 2023-06-29 | Adeia Semiconductor Bonding Technologies Inc. | Directly bonded frame wafers |
-
2019
- 2019-01-30 US US16/262,489 patent/US10727219B2/en active Active
- 2019-01-31 WO PCT/US2019/015985 patent/WO2019160690A1/en active Application Filing
- 2019-01-31 CN CN202110686074.5A patent/CN113410133A/zh active Pending
- 2019-01-31 CN CN201980013695.8A patent/CN111742398B/zh active Active
- 2019-02-11 TW TW111132285A patent/TWI836575B/zh active
- 2019-02-11 TW TW108104470A patent/TWI778223B/zh active
-
2020
- 2020-07-02 US US16/919,989 patent/US11037919B2/en active Active
-
2021
- 2021-06-10 US US17/344,100 patent/US11855064B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101552281A (zh) * | 2002-07-29 | 2009-10-07 | 富士胶片株式会社 | 固态成像设备及制造所述固态成像设备的方法 |
CN101558483A (zh) * | 2005-08-11 | 2009-10-14 | 齐普特洛尼克斯公司 | 三维ic方法和器件 |
US20080315351A1 (en) * | 2007-06-20 | 2008-12-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor substrate and maehtod for manufacturing the same |
CN102209692A (zh) * | 2008-11-07 | 2011-10-05 | S.O.I.技术(硅绝缘体技术)公司 | 用于分子结合的表面处理 |
CN102034687A (zh) * | 2009-09-28 | 2011-04-27 | S.O.I.Tec绝缘体上硅技术公司 | 键合和转移层的工艺 |
US20120112347A1 (en) * | 2010-06-11 | 2012-05-10 | Helmut Eckhardt | Flexible electronic devices and related methods |
CN105589587A (zh) * | 2014-10-21 | 2016-05-18 | 宸鸿科技(厦门)有限公司 | 透明复合基板与其制备方法及触控面板 |
CN106082108A (zh) * | 2015-04-29 | 2016-11-09 | 台湾积体电路制造股份有限公司 | 用于减少背侧硅损坏的结构 |
US20170045749A1 (en) * | 2015-08-10 | 2017-02-16 | Corning Incorporated | Methods for making optical devices |
JP2017124586A (ja) * | 2016-01-15 | 2017-07-20 | 東洋紡株式会社 | フレキシブル電子デバイスの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN111742398A (zh) | 2020-10-02 |
US20210375850A1 (en) | 2021-12-02 |
US20190252364A1 (en) | 2019-08-15 |
US20200365575A1 (en) | 2020-11-19 |
TWI778223B (zh) | 2022-09-21 |
WO2019160690A1 (en) | 2019-08-22 |
TWI836575B (zh) | 2024-03-21 |
US11855064B2 (en) | 2023-12-26 |
CN111742398B (zh) | 2021-07-09 |
US11037919B2 (en) | 2021-06-15 |
US10727219B2 (en) | 2020-07-28 |
TW201937584A (zh) | 2019-09-16 |
TW202249073A (zh) | 2022-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111742398B (zh) | 用于处理器件的技术 | |
US12068278B2 (en) | Processed stacked dies | |
US11348801B2 (en) | Processing stacked substrates | |
US11742315B2 (en) | Die processing | |
US20230140107A1 (en) | Direct bonding methods and structures | |
TW202429529A (zh) | 用於處理裝置的技術 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: California, USA Applicant after: Insulation Semiconductor Bonding Technology Co. Address before: California, USA Applicant before: Evanss Adhesive Technologies |