TWI495101B - 藉由使用包含具有高共價半徑之原子的嵌入半導體層之用於矽基電晶體中工程應變之技術 - Google Patents

藉由使用包含具有高共價半徑之原子的嵌入半導體層之用於矽基電晶體中工程應變之技術 Download PDF

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TWI495101B
TWI495101B TW095139687A TW95139687A TWI495101B TW I495101 B TWI495101 B TW I495101B TW 095139687 A TW095139687 A TW 095139687A TW 95139687 A TW95139687 A TW 95139687A TW I495101 B TWI495101 B TW I495101B
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strain
tin
region
semiconductor layer
crystalline
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Christof Streck
Volker Kahlert
Alexnader Hanke
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Globalfoundries Us Inc
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Description

藉由使用包含具有高共價半徑之原子的嵌入半導體層之用於矽基電晶體中工程應變之技術
本發明大致關於形成積體電路，且更詳言之，關於藉由使用嵌入矽/鍺而形成具有應變通道區(strained channel region)之不同電晶體類型，以提高電荷載體於電晶體之通道區中之移動性(mobility)。
積體電路之製造，需於給定之晶片區域上，依據特定電路佈局形成大量電路元件。大抵上，目前應用許多製程技術，其中，對於複雜電路諸如微處理器、儲存晶片等，CMOS技術由於在操作速度及/或電力消耗及/或成本效率方面有極佳之性能，而為目前最有前景之方法。使用CMOS技術製造複雜積體電路時，數百萬之電晶體，亦即N－通道電晶體與P－通道電晶體形成於包含結晶半導體層之基板上。MOS電晶體，不管其為N－通道電晶體或P－通道電晶體，包含所謂PN接面(junction)，係由高度摻雜之汲極與源極區介面所形成，於該汲極與源極區之間設有相反摻雜之通道區。
通道區之導電度，亦即導電通道之驅動電流能力，係由形成於該通道區上且以薄絕緣層分隔之閘極所控制。導電通道一旦形成，由於施加適當控制電壓於閘電極(gate electrode)，通道區導電度取決於摻雜物濃度、多數電荷載體移動性、以及電晶體寬度方向上通道區給定延伸時源極與汲極區間距離(亦稱為通道長度)。因此，施加適當控制電壓於閘電極，並結合於絕緣層下快速產生導電通道之能力，整個通道區導電性實質上決定了MOS電晶體之性能。所以，縮短通道長度使通道電阻係數降低，對達成提高積體電路操作速度提供了通道長度之主要設計標準。
然而，電晶體尺寸持續縮小，許多與此有關之問題必須提出，以便不會過度抵消穩定地縮短MOS電晶體通道長度所得之優點。此方面之一主要課題為發展增進之光微影技術(photolithography)與蝕刻策略，以便為新一代裝置可靠而再現性地製出具關鍵尺寸之電路元件，例如電晶體之閘電極。再者，汲極與源極區要求於垂直方向與側邊方向具有高精細摻雜物分佈(profile)，以提供低的片和接觸電阻係數(sheet and contact resistivity)，以及所欲通道控制能力。此外，考量漏電流控制，關於閘極絕緣層之PN接面垂直位置亦為關鍵設計標準。所以，縮短通道長度通常亦需要減小關於由閘極絕緣層與通道區所形成介面之汲極與源極區深度，因而需要精巧植入技術。依據其他方法，磊晶生長區(稱為升高汲極與源極區)形成有對閘電極的特定偏移(offset)，以增加該升高汲極與源極區之導電性，同時維持關於閘極絕緣層之淺PN接面。
因為關鍵尺寸，亦即電晶體閘極長度持續縮小，所以必須順應與可能地新開發關於以上所述製程步驟之高複雜製程技術，有人提出對給定通道長度，藉由增加通道區中電荷載體移動性而亦提高電晶體元件之通道導電性，藉以提供達成改善性能之可能性，使與未來技術節點之進步可相匹配，並避免或至少延遲許多與裝置尺寸縮放(scaling)有關之上述製程之調適。增加電荷載體移動性之一有效機制為修改通道區之晶格結構，例如藉於通道區附近產生拉伸或壓縮應力而於通道區產生相應應變，使電子與電洞之移動性分別受到修改。例如，於通道區產生拉伸應變增加電子移動性，而可獲得50%或更高之移動性增加，視拉伸應變大小與方向而定，此移動性增加依序可直接轉化成相應導電性提高。另一方面，通道區之壓縮應變可增加電洞移動性，因而提供改善P型電晶體性能之可能性。對更進一步世代之裝置而言，將應力或應變工程導入積體電路製造中，係極有前景之方法，因為，例如經應變矽(strained silicon)可視為「新」類型半導體材料，其可使快速強大之半導體裝置製造成為可能而無需使用昂貴半導體材料，同時許多已建立完備之製造技術仍可使用。
因此，有人提出於通道區中或於其下導入例如矽/鍺層或矽/碳層，以產生拉伸或壓縮應力，而可導致相應應變。藉由於通道區中或於其下導入應力產生層，可相當程度地提高電晶體性能，所以投入相當大努力將形成相應應力層實施於習知與眾所公認之MOS技術中。例如，發展其他磊晶生長技術並加入製造流程中，以於通道區中或於其下適當位置形成含鍺或含碳應力層。
其他方法係應用例如藉由覆蓋層(overlaying layer)、間隔件元件等來產生外部應力，以於通道區內產生所欲應變。然而，藉施加特定外部應力來產生通道區中應變之製程，可能遇到外部應力無效率地轉化成通道區中應變之問題。所以，雖然以上所述於通道區內需要額外應力層之方法，於製程複雜性方面具有優勢，但是應力轉移機制之效率可能受該製程與裝置特性所影響，而可能造成減小一種電晶體類型之性能改善。
另一方法係藉由於電晶體汲極與源極區中形成應變矽/鍺層，提高PMOS電晶體中電洞移動性，其中，經壓縮應變之汲極區與源極區於鄰接矽通道區中產生單軸應變。為此目的，PMOS電晶體之汲極與源極區選擇性地凹陷，而NMOS電晶體係經遮蔽，然後藉由磊晶生長使矽/鍺層選擇性地形成於PMOS電晶體中。此技術對PMOS電晶體以及因此整個CMOS裝置之性能提高，提供顯著好處。
所以，利用嵌入式半導體材料尤其是矽/鍺之工程應變，視所欲功效提供作為應變或鬆弛層，已證明是種增加高階矽基電晶體之裝置性能之有力方法。然而，結果，個別通道區所引發之應變程度，取決於基本矽與嵌入半導體化合物間之晶格不匹配量。對矽/鍺而言，目前建立之磊晶生長技術，鍺最大濃度限制為約25%，否則可能發生鍺聚集，轉而可能導致於相應嵌入半導體化合物材料中不希望之應力解除，由此亦降低個別通道區之應變。
綜觀上述情況，對利用嵌入半導體材料來有效增加應變之改善技術，同時實質上避免或至少減少一或多個以上所述問題，實有其需求。
以下提出本發明之簡單概述，用來初步瞭解本發明之一些態樣。此概述並非本發明之詳盡綜論，其無意用來驗證本發明之關鍵或重要元件，或用來描繪本發明之範圍。其唯一目的是以簡化形式呈現一些觀念作為稍後更詳細說明之引言。
大抵而言，本發明係關於一種用於在結晶半導體層之特定區中產生應變之技術，為達此目的，於此技術中採用矽基(silicon－based)晶格(亦即具有似鑽石晶格結構之晶格)與本身具增大晶格間隙之半導體化合物間的晶格不匹配(lattice mismatch)。對應技術慣用於相當高階矽基MOS電晶體元件中產生應變矽通道，其中，如前所述，由此機制所得應變量尤其顯著受限於可成功使用於目前所建立磊晶生長技術之有限鍺濃度。所以，本發明中，除鍺之外可額外使用或是與鍺選一使用的方式，可使用於似矽結晶結構中，對鍵結(bonding)特性具有顯著增加共價半徑之其他原子種類，藉以使於個別矽基結晶結構中有大幅減少非矽原子數及高度晶體畸變(distortion)成為可能。本發明之例釋實施例中，由於相較於矽與鍺，錫原子具有相同的原子價(valence)，而且亦展現顯著較大共價半徑，所以錫(Sn)可作為鍺之額外添加物或替代物。
依據本發明之一例釋實施例，一種電晶體裝置包括基板，該基板上形成有具有似鑽石結晶結構之結晶半導體層。該結晶半導體層包括應力引發區(stress－inducing region)，該應力引發區包含矽與具有與該結晶結構中之矽相同的原子價之其他原子種類，該其他原子種類具有共價半徑大於鍺之共價半徑。此外，該電晶體裝置包括形成於該結晶半導體層之上之閘電極(gate electrode)，以及應變通道區。
依據本發明之另一例釋實施例，一種半導體裝置包括結晶半導體層，該結晶半導體層具有包含矽與錫之第一部份，以於該結晶半導體層中形成第一應變區。
依據本發明之又一例釋實施例，一種方法包括於結晶半導體層中形成以矽與至少一種具有共價半徑大於鍺之共價半徑之其他原子種類為基礎之結晶結構。此外，該方法包括使用該結晶結構以於該半導體層之第一特定區中產生應變。
本發明可很容易做各種修改與變化，其特定實施例以附圖舉例之方式顯示，並於本文中做詳細闡述。然而，應明瞭，本文中特定實施例之闡述並無意用來限制本發明於所揭示之特定型式，反而是意圖用來涵蓋所有落於如後附申請專利範圍所界定本發明精神與範圍內之修改、等同與變化。
以下說明本發明之例釋實施例。為清楚起見，並非所有實際施行之特徵皆描述於本說明書中。當然，應可理解，於任何此等實際施行之開發中，必須決定許多特定實施例以達成開發者特定目的，諸如依從與系統有關及商業有關之限制，該些目的從一個實施例至另一實施例會有不同。此外，將可理解，此等開發可能複雜且耗時，但對該些了解本發明揭示內容之熟悉此項技術者而言，此等開發實為例行性之工作。
現將參照附圖對本發明進行說明。圖中各種結構、系統與裝置為概要性敘述，僅用於解釋，以便不會因熟悉此項技術者所週知之細節而模糊本發明。儘管如此，本說明書仍包含附圖，以便用來說明與解釋本發明之例釋實施例。應明瞭本文所使用之字與片語，並將該些字與片語解釋成具有符合該些字與片語為熟悉該相關領域者所理解之意義。無特別之術語或片語定義，亦即，異於該些熟悉本領域者所理解之通常與習慣意義之定義，隱含於本文術語或片語之一致用法中。當術語或片語意含特殊意義時，亦即，除熟悉本領域者所理解外之其他意義時，此特殊定義將以直接且明確提供該術語或片語特殊定義之下定義方式於本說明書中進行說明。
大抵上，本發明專注於利用相較於非應變矽晶體而具有不同晶格間隙之鑽石型晶格結構之應變或鬆弛半導體結構來增進應變引發機制。如前所述，於矽基半導體裝置之適當位置內設應變或鬆弛矽/鍺層之機制，提供了有效率工程應變技術，以相應提高電荷載體移動性，尤其是於相當高階MOS電晶體裝置之通道區內。該些技術依賴於磊晶生長製程，於此製程中可形成應變或鬆弛矽/鍺層，視裝置需求而定。
此外，最近發展局部選擇性磊晶生長技術，可有效抑制顯著材料沉積於介電質表面，然卻有效率地沉積矽、矽/鍺等於暴露之矽或似矽表面。例如，若矽/鍺層沉積於結晶矽層上，則可沉積矽/鍺材料，以使具有實質上如底層結晶「模板(template)」一樣之晶格間隙，而形成應變矽/鍺層，因為相較於純矽晶體，未受擾亂之矽/鍺晶體可有稍微增大之晶格間隙。矽/鍺層與矽層之晶格間隙差異取決於鍺濃度。所以，產生於矽/鍺層之應變量亦取決於鍺濃度。然而，如前所述，依目前所用磊晶生長技術，最大鍺濃度可高達約25至30%，但較高之濃度實際上可能導致鍺聚集，轉而可能導致缺陷率增加，使得初始應變矽/鍺層鬆弛化。
依據本發明，所欲晶格不匹配程度以及因此應變，可於具有比鍺顯著較大共價半徑之原子種類基礎上予以調整，其中，於一些例釋實施例中，關於似鑽石結晶結構中之共價鍵結結構，所考慮使用之原子種類其原子價實質上與矽或鍺相同。於一例釋實施例中，具有共價半徑1.04埃()之錫可作為適當之原子種類。例如，具有共價半徑1.17埃之矽可與具有共價半徑1.22埃之鍺組合使用，其中，另外可使用一定量之錫以產生顯著增大之晶格不匹配。因為矽與錫間共價半徑差異顯著大於矽與鍺間共價半徑差異，所以利用減少非矽原子數目可達成對整個晶格結構較顯著之作用。如此一來，鍺濃度可維持於臨界值約25%以下，且藉由加入一定量錫仍可得到晶格不匹配提高。
再者，於一些例釋實施例中，矽可與錫組合使用而無需添加任何鍺，藉此提供適度高程度之晶格修改(lattice modification)有顯著減少非矽原子數目。例如，於一些實施例中，除了以磊晶生長方式引入錫之外，亦考慮利用其他技術例如植入來引入一定量錫，或此二方式擇一使用。儘管如此，但因減少錫原子數目可對晶格畸變產生顯著貢獻，甚至利用目前植入技術所能達到之原子濃度可充分產生特定應變或至少細調晶格不匹配，所以藉此達到該應變程度。因為離子植入為建立完備之技術，以光微影技術所形成之阻劑罩(resist mask)為基礎，可於室溫進行離子植入，因此錫之相應引入可用高度有效率與甚至高度局部方式來達成，藉此提供製程技術及裝置設計額外彈性。例如，可利用目前施行之植入技術來達成濃度約為102 0 錫原子/立方公分，使可進行相應矽/錫或矽/鍺/錫結晶結構中應變之有效率調整或控制。
以下詳細說明可參考為本發明原理之特定應用，亦即，引入具有增大共價半徑之原子種類以於特定結晶半導體區產生應變。然而，應明瞭，並無意對特定電晶體結構例如似SOI電晶體、本體式(bulk)裝置、具有升高汲極與源極區之電晶體等做任何限制，除非於實施方式與申請專利範圍中對此特別限制有做說明。
參照第1a至1d圖、第2a至2d圖與第3圖，本發明進一步之例釋實施例現將作更詳細闡述。
第1a圖概要顯示於初期製造階段時，半導體裝置100之截面圖。半導體裝置100包括基板101，該基板101可表任何帶有半導體層102之適當基板，於基板101中或其上可形成電路元件例如電晶體、電容器、電阻器等。例如，基板101可表本體式半導體基板如矽基板，或可表任何絕緣基板如似SOI基板，其中，半導體層102可形成於埋入式絕緣層(未圖示)上。應明瞭，雖然本發明結合如典型上以高階CMOS技術，包括具50奈米(nm)和甚至更小閘極長度之電晶體所製造之高度縮小化MOS電晶體，其具有相當大之優點，但本發明原理亦可應用至較非關鍵應用上，以便使現有設計可達到顯著之性能增加。
半導體層102可為矽基結晶半導體層，其中矽基一詞係理解成包含矽濃度至少為原子50%之材料層。於例釋實施例中，半導體層102可表摻雜矽層，如典型上用於高度複雜積體電路，而該積體電路具有閘極長度於上述特定範圍內之電晶體元件之摻雜矽層。於層102上可進一步形成實質上結晶層103，該結晶層103可表所謂之緩衝層，於此結晶層中，結晶不匹配以及因此特定原子種類諸如鍺、錫等之濃度可逐漸增加，以使於其上形成實質上鬆弛之應力引發結晶層104，此應力引發結晶層可包含至少一個具有共價半徑大於鍺共價半徑之原子種類與矽相組合。於一例釋實施例中，應力引發結晶層104可包含矽、鍺與錫，其中，鍺濃度範圍可從低於1%至約25%，而錫濃度範圍可為約0.1至25%。於一些實施例中，可選擇鍺含量遠低於25%，例如1至10%，而錫含量可選擇於約0.1至10%範圍內。於又一實施例中，應力引發結晶層104可包含矽與錫而實質上無任何鍺。
層104可表實質上鬆弛層，具有依層102所提供結晶模板之鑽石似結構，該結晶模板係經緩衝層103轉移至層104，然而，其中層104晶格間隙可異於層102晶格間隙，端視鍺與錫濃度而定。
如第1a圖所示，可依據下列製程形成半導體裝置100。提供基板101後，基板101可表其上形成有層102之本體式矽基板或絕緣層上矽基板，層102厚度可適於磊晶生長製程，緩衝層103可藉由磊晶生長製程105予以形成，於此磊晶製程105中，一或多個非矽種類可用不同濃度進行沉積以形成緩衝層103。例如，於氫化鍺(GeH4 )基礎上形成矽/鍺緩衝層之技術已建立完備，並且當認為於緩衝層103中無另外原子種類例如錫係適當時，可用來形成層103。於其他實施例中，可於其他原子種類例如錫之基礎上形成緩衝層103，緩衝層103可藉由以氫化錫(SnH4 )作為磊晶生長製程105之前驅物來製成，其中，氫化錫可以如氫化鍺之相同方式處理。
藉由適當沉積緩衝層103之材料，就晶格間隙而言，相應晶格結構可逐漸地自層102之基本結晶模板中衍生出來，使得層104最後可沉積成相較於層102之原始晶格間隙，具有增大晶格間隙而實質上無應變之半導體層，亦即鬆弛之半導體層。為達此目的，於磊晶生長製程105中，若有需要，則可提供所欲量之錫及個別量之鍺與矽組合，而矽仍為層104之主要材料。達成所欲層厚度後，可中斷磊晶生長製程105，然後可進行其他磊晶生長製程以於層104上沉積實質上結晶矽層。於其他實施例中，可修改磊晶生長製程105以利後續沉積摻雜矽或未摻雜矽，視需求而定，其中，實質上鬆弛層104係作為結晶模板。如此一來，沉積於其上之矽可具有實質上相同之結晶結構，該結晶結構相較於自然結晶矽層例如層102，係為應變結晶結構。因此，可產生特定程度之拉伸應變。
第1b圖概要顯示於進一步製造階段時之半導體裝置100。如圖中所示，依據上述磊晶生長技術於層104中形成另一結晶矽層106。如此一來，層106呈現本質拉伸應變，表示為107，藉以有效率地修改層106中電荷載體移動性。此外，層106上形成有閘電極108，並且以閘極絕緣層109分隔。閘電極108組合閘極絕緣層109於層106中界定出通道區110，如前所述，層106呈現拉伸應變107，藉以增加例如通道區110中電子移動性。結果，相應電晶體元件包括閘電極108與通道區110之性能可顯著提高，其中於磊晶生長製程105基礎上，拉伸應變107程度可有效率地予以調整與控制。因此，利用應力引發結晶層104之方式，可提供產生矽基層106中拉伸應變之有效率應變產生機制。
第1c圖概要顯示依據另一例釋實施例之半導體裝置100，於此裝置中，於結晶半導體層之特定區域中可產生壓縮應變。該實施例中，應力引發結晶層104可直接形成於結晶層102上，層102於磊晶生長製程105中再次作為結晶模板，因為層102之結晶結構於層104中實質上維持著，所以該結晶模板現可已組態過，使得層104本身生長成實質上應變層，藉以降低其自然晶格間隙，使得通道區110可為壓縮應變區，藉以修改電洞移動性，而可利於於通道區110與閘電極108基礎上形成P－通道電晶體。
之後，自如第1b圖或第1c圖中裝置100開始，於建立完備之形成金氧半電晶體技術基礎上，可繼續進一步之製造程序，稍後將參照第2a至2d圖作更詳細之說明。
如前所說明，具有增加共價半徑原子種類之適度低濃度，可充分修改產生壓縮或拉伸應變所需之相應晶格不匹配，如第1a至1c圖所述者。所以，於一些例釋實施例中，可使用除磊晶生長製程105外之額外或可與磊晶生長製程105擇一使用之其他引入原子種類技術，例如擴散或植入。例如，可實施植入製程以引入例如錫原子進入層104，藉以增加相應濃度，以及因此引入應變。
第1d圖概要顯示包括第一裝置區150與第二裝置區160之半導體裝置100例釋實施例，於裝置區150中可形成有閘電極108，而於裝置區160中可於第二閘極絕緣層119上形成第二閘電極118，其中，第二裝置區160可用植入遮罩121予以覆蓋，遮罩121可為阻劑型遮罩。此外，半導體裝置100進行離子植入120以局部方式引入錫。例如，於所示實施例中，可假設利用磊晶生長製程105已形成層104(參照第1c圖所說明)，藉以提供具有本質應變107之層104。藉由於閘電極108附近進一步植入錫離子，相應錫濃度可予以增加，其中，可使用高劑量例如101 6 至101 7 離子/平方公分，以於層104內提供適度高之額外錫原子濃度。為了獲得於層104內實質上沉積錫離子之植入能量，而不過度損害「模板層」102，可依據已建立完備之模擬模型來選擇製程120之植入參數。
植入製程120完成後，可除去阻劑遮罩121，然後裝置100可接著進行回火製程，以使層104中受損部份再結晶及實質上置該植入種類於晶格位置，以重建層104中應變晶格。由於通道區110附近錫濃度增加，因而於其內可產生均勻增加之壓縮應變，亦藉而造成更有效率地修改電荷載體移動性。
應明瞭，上述實施例只具有例釋性質，可考慮進行許多之修改。例如，以遮罩121為基礎於形成閘電極108與118之前，可進行植入製程120，使得層104整個曝光部份可接收增加之錫含量。又一例釋實施例中，當以植入製程120引入之錫濃度足夠產生所欲應變107之程度時，可省略磊晶生長製程105。又一其他例釋實施例中，可於矽與鍺基礎上進行磊晶生長製程105，而植入製程120可用來局部引入錫原子，藉以提供細調最後所得應變之方法。例如，第一與第二裝置區150、160可表不同電晶體類型之區域，或可表不同晶粒區域，該些裝置區有不同應變程度需求。例如，於複雜微處理器之高靈敏度裝置區，例如靜態RAM區，希望沒有應變或有相當小之應變；然而於邏輯區，例如CPU核心，較佳為應力增加，以提高CPU核心之運作速度。結果，由於結晶結構上具有增加共價半徑之原子種類例如錫之效果提高，植入技術可達到適當之濃度，以便局部調整應變。
參照第2a至2d圖，本發明之其他例釋實施例現將作更詳細說明，於該些實施例中，嵌入應變半導體材料係形成於電晶體元件之汲極與源極區中，以於鄰接通道區中引發相應應變。
第2a圖概要顯示包括基板201且基板201上形成有結晶半導體層202之半導體裝置200截面圖。基板201可表本體式矽基板或似SOI基板，亦即，基板201可形成於理入式絕緣層(未圖示)上，於基板201上形成有結晶半導體層202。結晶半導體層202可表矽基層，亦即，層202可包含至少約50%矽。此外，於初期製造階段，電晶體元件250可形成於結晶半導體層202中或之上。於該階段，閘電極208可形成於層202上，並可包含摻雜多晶矽或任何其他可設於層202上之適當材料，可用閘極絕緣層209分隔。應明瞭，亦可使用其他方法或電晶體結構與本發明相組合，其中，例如閘電極208可表示取代品或假閘電極，該取代品或假閘電極可於製程稍後階段移除，以提供具提高電氣特性之導電性材料。閘電極208可由封蓋層230與個別間隔件元件231所「包覆(encapsulated)」，而間隔件元件231可用個別襯墊232而與閘電極208分隔。例如，封蓋層230與間隔件231可包含任何適當介電材料例如氮化矽、氧氮化矽與二氧化矽，可作為蝕刻製程與磊晶生長製程之蝕刻與生長遮罩，以形成嵌入應變半導體區。襯墊232典型上由對間隔件231具有高蝕刻選擇性之材料所形成。例如，於建立完備之蝕刻程序上，二氧化矽與氮化矽之組合可有效率地用於襯墊232與間隔件231。
如第2a圖所示之半導體裝置200可依據下列步驟予以形成。製造基板201後(若考慮似SOI基板，基板201可包括以高階晶圓鍵結技術或其他方法來形成埋入式絕緣層)，閘電極208與閘極絕緣層209之形成，可利用沉積法及/或氧化法形成適當閘極絕緣材料，接著進行適當閘電極材料之沉積。然後，依據建立完備之程序，可應用高階微影技術及蝕刻技術來圖案化相應之層，藉以形成閘電極208與閘極絕緣層209，其中，於進行圖案化製程時，封蓋層230亦可進行圖案化，該封蓋層230可作為抗反射塗層(ARC)、硬質遮罩層等。下一步，藉由電漿輔助化學氣相沉積(PECVD)可共形地沉積襯墊材料，接著沉積間隔件層，然後以非等向性蝕刻製程進行間隔件層圖案化，因而得到間隔件231。之後，可移除襯墊232經暴露之殘留部份，然後裝置200可進行非等向性蝕刻製程233，以形成個別孔洞或凹陷鄰接密封閘電極208。
第2b圖概要顯示於進一步製造階段中之半導體裝置200，其中，於非等向性蝕刻製程233完成後形成凹陷或孔洞234。下一步，裝置200可進行任何製備裝置200之預處理，以便進行後續選擇性磊晶生長製程。例如，可實施適當清洗製程以從裝置200之暴露表面移除污染物與蝕刻副產物。之後，可進行選擇性磊晶生長製程246，其中，於一個例釋實施例中，於含矽前驅物、含鍺前驅物以及包括具有如矽與鍺相同原子價並比鍺共價半徑大之原子種類之前驅物基礎上，可建立適當沉積環境。於一個例釋實施例中，於氫化錫(SnH4 )基礎上可產生沉積，以於製程246沉積環境中提供所欲錫濃度。如前所述，典型上，於選擇性磊晶生長製程中，製程參數例如壓力、溫度、載氣種類等係經選擇，以使實質上無材料沉積於介電層表面例如封蓋層230與間隔件231之表面，而是於結晶層202之暴露表面上產生沉積，藉而利用此沉積層作為結晶模板，該模板實質上決定了磊晶生長材料之結晶結構。於該例釋實施例中，於凹陷234至少一部份中生長之材料係供作為應變材料，亦即，該材料應具有如層202基本模板一樣之結晶結構以及因此實質上一樣之晶格間隙，由於鍺與其他具有增加共價半徑之原子種類例如錫之存在，因而產生高度應變材料區。如此一來，由於應變結晶材料存在，於鄰接凹陷234處之通道區235中亦產生相應之應變。
如前所述，對矽與鍺而言由於錫共價半徑增加，非矽原子之顯著減少可足夠獲得於磊晶生長製程246時之相應應變半導體材料。因此，對產生所需應變而言，沉積環境中濃度範圍約0.1至10%之例如錫之適度低濃度，可視為適當。其他實施例中，於矽與至少一個其他具有增加共價半徑之原子種類例如錫基礎上，可建立製程246之沉積環境，而實質上無加入任何鍺，藉此當對其他電氣特性例如PN接面漏電流等而言，鍺實質數量之影響也許認為不適當時，提供增加之設計彈性。於磊晶生長製程236中，可用任何適當方法控制錫及/或鍺濃度以及因此矽濃度。例如，一些情況中，因為於裝置200進一步製程之後續高溫製程中，錫不同於鍺之擴散行為，使錫原子更靠近汲極與源極區上表面，可認為適當。其他例釋實施例中，可於後續形成金屬矽化物之區域附近提供錫，其中相較於需要顯著增加鍺含量以產生相同應變量然而對後續矽化製程可造成顯著限制而言，顯著減少之錫原子數可增加產生金屬矽化物之彈性。又於其他實施例中，可於由磊晶生長製程246所形成之應變矽/鍺/錫層或矽/錫層頂部上形成最終矽層。
第2c圖概要顯示磊晶生長製程236完成後之半導體裝置200。所以，裝置200包括具有對應於矽基層202之鑽石結構之結晶結構之凹陷應變半導體區236。由於晶格不匹配，因區236中結晶結構之自然晶格間隙大於規則矽間隙，因此通道區235中產生壓縮應變207，藉以提高電晶體250操作時之電洞移動性。此外，當使用高鍺含量時，由於鍺被具有增加共價半徑之原子種類例如錫所部份或完全取代，因此於區236中非矽原子濃度(該濃度遠低於習知裝置中先前所遭遇聚積之限制值)之基礎上，可得到顯著增加之應變207數值。然而，如前所述，區236中鍺及/或錫濃度於深度方向可變化以符合各種裝置需求。例如，於所示實施例中，可形成特定「過度生長」以提高後續矽化製程，藉以降低產生之接觸電阻。此外，可提供磊晶生長材料236之上部區，標示為236A，藉由相應增加錫濃度，該上部區可具有降低之鍺濃度但仍提供高度之應變，然而，該上部區可仍具有比產生相同應變207量之矽/鍺區顯著低之濃度，藉以提高於選擇後續矽化製程之適當耐火金屬時之彈性。應明瞭，於磊晶生長製程進行中，可產生區236中鍺及/或錫濃度之任何其他適當變化。
然後，能於形成汲極與源極區，至少一部份汲極與源極區之任何植入製程之後，當間隔件231具有適當尺寸以得到所欲側邊外形(lateral profile)時，可將間隔件231與封蓋層230移除。其他情況中，可移除間隔件231與封蓋層230，以及可進行習知製程序列以與中間之植入製程形成間隔件元件，而得到以設計規則所界定汲極與源極區所需之複雜側邊外形。
第2d圖概要顯示於進一步製造階段時之半導體裝置200，其中實質上完成電晶體250。所以，裝置200包括側壁間隔件結構237，該結構可包括複數個個別之間隔件元件用個別襯墊分隔。此外，依據裝置需求，汲極與源極區239具有特定側邊摻雜外形。此外，金屬矽化物區238可形成於汲極與源極區239上，而相應金屬矽化物區239可形成於閘電極208中。結果，由於區236所產生之應變207，通道區235可予以壓縮地應變，藉以顯著增加電晶體250(可為P－通道電晶體)之驅動電流能力。由於於區236中提供具有增加共價半徑之原子種類，相較於包括埋入式矽/鍺區之習知裝置，可達成應變207之顯著增加。
此外，藉由適當設計區236中之鍺及/或錫濃度設計，可提供形成金屬矽化物區238之增加彈性。例如，藉由降低至少上部區236A中鍺含量但同時藉由相應地提高錫濃度來增加應變，則高導電性鎳矽化物可形成於區238中。如此一來，可獲得性能顯著增加，但同時可維持與形成嵌入矽/鍺半導體結構之習知製程之高度相容性，並可獲得於設計方面之額外自由度。為了此目的，於可達成適當與所欲非矽原子之引入基礎上，可使相應磊晶生長製程適合於包括提供適當前驅材料例如氫化錫(SnH4 )，此情況藉由應變半導體區236內之相分離與晶體滑移而使有效率地控制產生之應變，實質上未產生任何應力釋放。
第3圖概要顯示依據其他實施例之半導體裝置300之截面圖。半導體裝置300包括形成於基板301上，以結晶半導體層302為基礎之第一電晶體350與第二電晶體360。關於基板302與半導體層302，應用如前參照組件101、102、201與202所述之相同標準。此外，於所述實施例中，電晶體350、360可具有密封閘電極308，並鄰接相應升高半導體區336、336A而形成。於其他例釋實施例中(未圖示)，可不設升高半導體區336、336A，並可僅表結晶半導體層302之一部份。
如第3圖所示之裝置300，可依據如前參照第2a至2b圖所述之製程策略予以形成，然而，其中，電晶體350、360可表示為可接收不同應變大小之電晶體，因為該些電晶體可表於不同晶粒區之電晶體或可表不同導電性類型之電晶體。例如，第一電晶體350可表P－通道電晶體而電晶體360可表N－通道電晶體。因此，於形成個別孔洞或凹陷以容設半導體區336、336A之相應蝕刻製程中，可達成製程均勻性提高，此是由於當暴露一型電晶體時，該蝕刻製程可不需任何硬質遮罩來完全覆蓋另一型電晶體。類似情況，於後續磊晶生長製程中，由於任何負載作用減少(其亦可能為習知技術之課題)，可達成跨越基板301之均勻性之提高，於該製程中，一型電晶體係完全受到覆蓋，而另一型電晶體則受到暴露。於形成升高半導體區336、336A相應磊晶生長製程中，可引入少量鍺及/或錫以提供例如與第二電晶體360性能相容之「基本」應變307。其他例釋實施例中，當認為基本應變307不適當時，可省略相應孔洞蝕刻與後續磊晶生長製程。於其他情況中，電晶體360可表於關鍵裝置區中例如靜態RAM區中之P－通道電晶體，該區可接收減少之應變307量，而電晶體350可能需要增加應變量。
於一例釋實施例中，可進行植入製程320，於此製程中，暴露第一電晶體350而第二電晶體360可用阻劑遮罩321覆蓋。於植入製程320中，可將錫植入至區336，藉以增加區336中錫濃度，由於錫增加之共價半徑產生更有效率晶格畸變，而可導致所欲之應變增加。因為植入誘發濃度可能需要高濃度例如約102 0 原子/立方公分或更高，所以進行植入製程320時，區336可實質上無晶形化。因此，可進行回火製程以再結晶基於結晶模板302之該實質上無晶形化區336，藉此於區336中形成高度應變晶體結構。結果，可增加初始呈現之應變307至值307A，藉以獲得電晶體350所需之移動性增加。之後，可繼續實施如前參照第2a至2d圖所述之進一步製程以完成電晶體350與360。
其他例釋實施例中，當利用植入製程320所達成濃度去產生應變307A係適當時，可進行植入製程320而無需先形成區336、336A。例如，於高靈敏裝置區，基於應變半導體材料上之應變工程對N－通道電晶體而言可能不適當，然而可能需要PMOS電晶體之通道區中之「溫和」應變。於此情況，可於形成任何汲極與源極區之前應用植入製程320，其中，於一實施例中，植入製程320另外可施行為預先非晶形化植入製程以便促進後續引入摻雜形成汲極與源極區。如此一來，可達到高選擇性效能改善，且對現今製程技術具有高度相容性，實質上未大幅地影響N－通道電晶體。
因此，本發明藉由經應變或鬆弛之半導體材料方式來提供形成應變之改善技術，於此技術中，係將比鍺具有更大共價半徑之原子種類，例如錫，引入至個別結晶矽基半導體層，藉以顯著減少因聚集與晶格缺陷所引起之應力釋放風險。於例釋實施例中，可利用於適當前驅物材料例如氫化錫(SnH4 )上之磊晶生長製程來引入具有增加共價半徑之原子種類。此外，利用其他技術例如植入來引入原子種類，可達到高度定位化之應變工程，藉以提供高彈性之製程與產品設計。
以上所揭示之特定實施例只用於例釋，對該些嫻熟本說明書所教示優點之技藝者而言，顯然可以不同但均等之方式對本發明進行修改與實踐。例如，以上所提出之製程步驟可以不同之次序予以進行。此外，除如下文申請專利範圍中所述者外，並無意去限制本說明書所示之結構或設計細節。所以顯然地，以上所揭示之特定實施例可加以變化或修改，而所有該些變化係落於本發明之範圍與精神內。因此，本說明書所尋求之保護係如以下申請專利範圍中所提出者。
100、200、300．．．半導體裝置
101、201、301．．．基板
102、202．．．半導體層
103．．．緩衝層
104．．．應力引發層
105、246．．．磊晶生長製程
106．．．結晶矽層
107、207、307、307A．．．應變
108、118、208、308．．．閘電極
109、119、209．．．絕緣層
110、235．．．通道區
120、320．．．植入製程
121、321．．．遮罩
150、160．．．裝置區
230．．．封蓋層
231．．．間隔件
232．．．襯墊
233．．．蝕刻製程
234．．．凹陷
236．．．應變半導體區
236A．．．上部區
237．．．間隔結構
238．．．金屬矽化物區
239．．．汲極與源極區
250、350、360．．．電晶體
302．．．半導體層；結晶模板
336、336A．．．升高半導體區
參照附圖與以下說明可瞭解本發明，其中，相似元件符號代表相似元件，且其中：第1a至1d圖概要顯示依據本發明之例釋實施例，於以矽與以可內建於矽鑽石結構中且相較於鍺具有增大共價半徑之其他原子種類為基礎之結晶半導體層中，形成應變區之不同製造階段期間之半導體裝置之截面圖；第2a至2d圖概要顯示依據本發明之又一些例釋實施例，於形成接收嵌入應變半導體區之電晶體裝置以於個別通道區中產生壓縮應變之不同製造階段期間之截面圖；以及第3圖為依據本發明之另一例釋實施例，概要顯示半導體裝置之截面圖，該半導體裝置包括接收不同錫量以產生不同應變大小之不同電晶體元件。
100．．．半導體裝置
101．．．基板
102．．．半導體層
103．．．緩衝層
104．．．應力引發層
106．．．結晶矽層
107．．．應變
108．．．閘電極
109．．．絕緣層
110．．．通道區

Claims (19)

  1. 一種電晶體裝置，包括：基板，其上形成有具有似鑽石結晶結構之結晶半導體層，該結晶半導體層包括應力引發區，該應力引發區包括矽及具有與該結晶結構中之矽相同的原子價之其他原子種類，該其他原子種類具有共價半徑大於鍺之共價半徑；閘電極，形成於該結晶半導體層之上；以及應變通道區，其中，該結晶結構以對該閘電極橫向偏移(lateral offset)而形成。
  2. 如申請專利範圍第1項之電晶體裝置，其中，該應力引發區係形成於汲極與源極區中。
  3. 如申請專利範圍第1項之電晶體裝置，其中，該應力引發區係該應變半導體材料，以於該通道區中產生壓縮應變。
  4. 如申請專利範圍第1項之電晶體裝置，其中，該應力引發區包括錫。
  5. 如申請專利範圍第4項之電晶體裝置，其中，該應力引發區包括鍺。
  6. 一種半導體裝置，包括：結晶半導體層，具有包括矽與錫之第一部份，以於該結晶半導體層中形成第一應變區；以及該第二部份包括矽與錫，以於該結晶半導體層中 形成第二應變區，其中，該第一部份與該第二部份中之錫濃度不同。
  7. 如申請專利範圍第6項之半導體裝置，其中，該第一應變區代表場效電晶體之通道區。
  8. 如申請專利範圍第7項之半導體裝置，其中，該錫係設於該場效電晶體之汲極與源極區中，該錫與該矽組合形成應變汲極與源極區。
  9. 如申請專利範圍第6項之半導體裝置，其中，該部份中之錫含量係在約0.1至25原子%之範圍。
  10. 如申請專利範圍第6項之半導體裝置，其中，該第一部份復包括鍺。
  11. 一種形成積體電路之方法，包括：於結晶半導體層中形成以矽與至少一種具有共價半徑大於鍺之共價半徑之其他原子種類為基礎之結晶結構；使用該結晶結構以於該半導體層之第一特定區中產生應變；以及於該結晶半導體層之上形成閘電極，其中，該結晶結構以對該閘電極橫向偏移(lateral offset)而形成。
  12. 如申請專利範圍第11項之方法，其中，形成該結晶結構包括使用該結晶半導體層作為生長模板而磊晶生長該矽與該至少一種其他原子種類。
  13. 如申請專利範圍第11項之方法，其中，形成該結晶結構包括沉積該矽與該至少一種其他原子種類成實質上 非晶形形態，以及使用該結晶半導體層作為結晶模板而再結晶該矽與該至少一種其他原子種類。
  14. 如申請專利範圍第11項之方法，其中，形成該結晶結構包括植入該至少一種其他原子種類至該結晶半導體層之第一部份中，以及使用該結晶半導體層作為結晶模板而再結晶該部份。
  15. 如申請專利範圍第14項之方法，復包括於該結構中形成矽/鍺晶體，以及植入該至少一種其他原子種類以調整該第一區中之應變量。
  16. 如申請專利範圍第14項之方法，復包括植入該至少一種其他原子種類至第二部份中，以於該結晶半導體層之第二特定區中產生第二應變，該第二應變與該第一應變不同。
  17. 如申請專利範圍第11項之方法，復包括形成鄰接該閘電極之凹陷，以及於該凹陷內形成至少部份之該結晶結構。
  18. 如申請專利範圍第11項之方法，其中，磊晶生長該矽與該至少一種其他原子種類係以包括錫與氫之前驅物為基礎。
  19. 如申請專利範圍第18項之方法，其中，該前驅物包括氫化錫。
TW095139687A 2005-10-31 2006-10-27 藉由使用包含具有高共價半徑之原子的嵌入半導體層之用於矽基電晶體中工程應變之技術 TWI495101B (zh)

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US7544551B2 (en) 2009-06-09
TW200802861A (en) 2008-01-01
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