TWI420602B - 用於形成nmos與pmos電晶體中之凹陷之受應變之汲極/源極區之技術 - Google Patents
用於形成nmos與pmos電晶體中之凹陷之受應變之汲極/源極區之技術 Download PDFInfo
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Description
本發明大致係有關積體電路的形成,且詳言之,係有關藉由使用,例如,矽/鍺而形成不同電晶體類型的源極/汲極區以增進MOS電晶體之通道區域中的電荷載體移動性。
積體電路的製造必需根據指定的電路配置圖在給定的晶片區域上形成大量的電路元件。一般而言,現在實施的係複數製程技術,其中,就複雜電路而言,例如微處理器及儲存晶片等,由於就操作速度及/或電源消耗及/或成本效率的觀點來看的優異特性,使得CMOS技術為現今最有希望的方法。在使用CMOS技術製造複雜積體電路的期間,數百萬的電晶體,亦即,N-通道電晶體與P-通道電晶體,係形成於包括結晶性半導體層的基材(substrate)上。MOS電晶體,不論是考慮N-通道電晶體或P-通道電晶體,包含由汲極與源極區之間配置經反向摻雜的通道區之經高度摻雜的汲極與源極區界面所形成之所謂的PN接面(junction)。
該通道區的導電性,亦即,該導電通道的驅動電流能力,係藉由在該通道區上方形成並且藉由薄絕緣層與該通道區隔開的閘極電極(gate electrode)予以控制。該通道區的導電性,在形成導電通道時,由於適當控制電壓施於該閘極電極,取決於該摻雜物濃度、大多數電荷載體的移動性、及就該電晶體寬度方向的給定通道區延伸程度來說,取決於該源極與汲極區之間的距離,該距離亦稱為通道長度。因此,結合憑藉對該閘極電極施加控制電壓而使該絕緣層下方迅速地產生導電通道的能力,該通道區的總體導電性實質上決定了該MOS電晶體的效能。由此,該通道長度的減短,及與彼相關的通道電阻率降低,使該通道長度成為完成該等積體電路的操作速度提升的主要設計基準。
然而,該等電晶體尺寸的持續縮小涉及複數與彼相關的議題,該等議題有必要加以處理以便不致過度抵銷穩定地降低MOS電晶體的通道長度所獲得的優點。在此形態中之一個主要問題為研發加強的光蝕刻顯影(photolitho graphy)技術及蝕刻策略以便可靠地並且再現地產生新一代裝置的臨界尺寸之電路元件,例如該等電晶體的閘極電極。再者,該等汲極與源極區中需要高度先進的摻雜劑外廓,在垂直方向及側方向,以提供低片材(sheet)及接觸電阻率並結合預期的通道控制性。此外,就洩漏電流控制(leakage current control)的觀點來看,與該閘極絕緣層有關的PN接面之垂直位置亦代表臨界的設計基準。因此,降低該通道長度也可能需要降低與該閘極絕緣層及該通道區所形成的界面有關之汲極與源極區的深度,因而需要先進的植入技術。根據其他的方法,配合與該閘極電極的指定偏移量而形成磊晶生長區,該等磊晶生長(epitaxially grown)區被稱為提高的汲極與源極區,以提供該等提高的汲極與源極區提高的導電性,同時維持與該閘極絕緣層有關的淺PN接面。
因為該等臨界尺寸的持續尺寸減小,亦即,該等電晶體的閘極長度,需要順應並且可能地有關以上界定的製程步驟之高度複雜的製程技術的新開發,所以已提出藉由提高給定通道長度的通道區中的電荷載體移動性而同樣地增進該電晶體元件的通道導電性,藉以提供達成與朝向未來技術節點行進相容的效能改良之潛能,同時避免或至少延後許多與裝置按比例縮放有關的上述製程順應性。用於增加該電荷載體移動性之一個有效機制為在該通道區中的晶格結構修飾,例如藉由產生抗張(tensile)或壓縮應力(compressive stress)而在該通道區中產生對應的應變,該應變分別地造成電子與電洞經改變的移動性。例如,產生該通道區中的抗張應變將提高電子的移動性,其中,取決於該抗張應變的量級及方向,可獲得50%或更大的移動性增量,該移動性增量可依序地直接地轉變成該導電性的對應增量。另一方面,該通道區中的壓縮應變可提高電洞的移動性,藉以提供增進P-型電晶體效能的潛力。將該應力或應變工程導入積體電路製造就更進一代的裝置而言係為非常有希望的方法,因為,例如,受應變之矽可視為半導體材料的「新」類型,彼可使得快速有效力的半導體能夠製造而不需昂貴的半導體材料及製造技術。
因此,已提出將,例如,矽/鍺層或矽/碳層導入該通道區中或下方以產生抗張或壓縮應力,該應力可導致對應的應變。儘管該電晶體效能可藉由將應力產生層導入該通道區中或下方而增進相當多,但是必須耗費相當多的精力以便在傳統及經完善驗證的MOS技術中實施對應的應力層之形成。例如,必須開發額外的磊晶生長技術並且實施至該製程流程中而在該通道區中或下方的適當位置處形成鍺或含碳的應力層。因而,製程複雜度係顯著地提高,藉以也增加製造成本及降低生產量的潛在可能性。
由此,在其他方法中,試圖使用由例如,覆蓋層及間隔元件等,所產生的外部應力而在該通道區內產生預期的應變。然而,藉由施加指定的外部應力而使該通道區中產生應變的製程將遭遇到該外部應力非常無效率的轉換成該通道區中應變,因為該通道區會牢固地黏到絕緣體上矽(SOI)裝置中的埋入式絕緣層或塊狀(bulk)裝置中的剩餘塊狀矽。因而,儘管提供於以上討論方法的顯著優點需要在該通道區內有額外應力層,但所獲得的適度低之應變使後面的方法較不具吸收力。
在另一方法中,藉由在該等電晶體的汲極與源極區中形成受應變之矽/鍺層而增進PMOS電晶體的電洞移動性,其中該受壓縮應變的汲極與源極區將使相鄰矽通道區中產生非軸向的應變。最後,將該PMOS電晶體的汲極與源極區選擇性地置於凹部,同時罩蓋該等NMOS電晶體並且後繼地藉由磊晶生長在該PMOS電晶體中選擇性地形成該矽/鍺層。儘管就該PMOS電晶體並且因此整個CMOS裝置的效能增益來看,此技術可提供顯著的優點,但若使用能平衡該PMOS電晶體的效能增益的適當設計,而為了將該PMOS汲極與源極區置於凹部並且生長該矽/鍺區同時罩蓋該NMOS電晶體,需要複雜的製程技術,則可能提高製程的不均勻性。
有鑑於以上說明的情況,存在一種需求能有效地提高PMOS電晶體中的電荷載體移動性,同時實質上避免或至少減少以上界定的問題之一個或更多個的改良技術。
以下提出本發明的簡單概要以提供本發明的某些形態之基本了解。本概要並非本發明毫無遺漏的概觀。其並非意欲確認本發明的關鍵或重要元件或敘述本發明的範圍。其唯一的目的在於以簡化形態提出某些概念當作以下討論的更詳細說明之開頭。
一般而言,本發明係有關能形成不同類型的電晶體(例如PMOS及NMOS電晶體)的技術,其中至少該PMOS電晶體包含受應變之汲極與源極區以便有效地提高在對應通道區中的電荷載體移動性,同時在該等電晶體元件形成的期間可提供增進的彈性及製程均勻性。為達此目的,可對該二種類型的電晶體元件共通地(commonly)執行用於形成毗鄰閘極電極之凹部的蝕刻製程及後繼磊晶生長製程,藉以顯著地改良製程均勻性,同時也採取一些手段以改變該二電晶體之一者中的應變,例如在該NMOS電晶體中的應變,以便藉由利用例如提高的接面洩漏及改變的能帶間隙等此等效應而同時地增進其效能。在本發明的例示性實施例中,該等電晶體可以SOI裝置的形式提供,其中可顯著地降低不利的效應,例如浮體效應,特別是在部分耗盡的SOI裝置中。
根據本發明之一例示性實施例,一種方法包含形成毗鄰第一類型之第一電晶體之閘極電極的第一凹部,及形成毗鄰第二類型之第二電晶體之閘極電極的第二凹部,其中該第二類型與該第一類型不相同。該方法復包含在該第一與第二凹部中選擇性地形成受應變之半導體層,及選擇性地改變該第二凹部中之該受應變之半導體層以降低其中的應變。
根據本發明之另一例示性實施例,一種方法包含形成毗鄰第一類型之第一電晶體之閘極電極的第一凹部,其中該第一電晶體的閘極電極形成在半導體的第一主體上方。再者,形成毗鄰第二類型之第二電晶體之第二閘極電極的第二凹部,其中該第二類型與該第一類型不相同,而且其中該第二電晶體的閘極電極形成在半導體的第二主體上方。再者,該方法包含共通地形成在該第一凹部中之第一半導體層及在該第二凹部中之第二半導體層,其中至少該第一半導體層為受應變之半導體層。
根據本發明又另一例示性實施例,一種半導體裝置包含形成於半導體的第一主體中及上的第一導電性類型之第一電晶體,其中該第一電晶體的延伸區及源極與汲極區中包含指定半導體材料之受應變之層。該半導體裝置復包含形成於半導體的第二主體中及上的第二導電性類型之第二電晶體,其中該第二電晶體的延伸區及源極與汲極區中包含該指定半導體材料之實質上鬆弛之層。
以下說明本發明的例示性實施例。為求清晰起見,本說明書中並未說明實際實施方式的所有特徵。應當明白在任何此實際實施例的發展過程中,都必須做許多特定實施的決定以達到開發者的指定目標,例如遵守系統相關及商業相關的限制,彼等都將隨一個個實施方式而改變。再者,應明白此開發的努力成果可能複雜並且耗時,儘管如此,也都是獲得本揭示內容的助益之普通熟悉此技藝者的日常工作。
現在本發明將參照隨附的圖式加以說明。該等圖式中概略地描述各種不同的結構、系統及裝置僅為了達到解釋的目的,而且以便不致混淆本發明與熟於此藝者眾所周知的細節。儘管如此,包括隨附的圖形係為了說明並且解釋本發明的例示性範例。本文所用的單字及片語應理解並且解釋為具有與熟悉相關技藝者所理解的那些單字及片語相同的意義。本文中的術語及片語前後一致的用途意欲暗示該術語或片語沒有特殊定義,亦即,與熟於此藝者所了解的普通及慣用意義不同的定義。只要是術語或片語意欲具有特殊的意義,亦即,熟於此藝者所了解以外的意義,此特殊的意義將以直接地且明確地提供該術語或片語的特殊意義的限定方式在本說明書中做明確地說明。
大致上,本發明預期用於不同類型導電性的電晶體元件(例如,NMOS電晶體及PMOS電晶體)的製造之技術,其中藉由在該PMOS電晶體的汲極與源極區及延伸區中提供受壓縮應變之半導體層而增進該PMOS電晶體中電洞之電荷載體移動性。同時,本發明提供高效率且彈性的製造程序,其中用於該汲極與源極及延伸區中形成凹部區域的蝕刻製程,以及後繼的選擇性磊晶生長製程,對於兩種類型的電晶體均可同時地執行,因此“平緩(smoothing)”這些製程的負載效應。此外,該NMOS電晶體中的任何應變,其可能在該PMOS電晶體中的受應變之半導體層形成的期間產生,都可適當地予以調整以降低對該電子移動性的任何不利效應,因此助於CMOS電路的總體效能。在該NMOS電晶體內的應變改變可能導致該汲極與源極區及該延伸區內實質上鬆弛的半導體材料,造成實質上未受應變之接觸區。再者,該實質上鬆弛的半導體層也可能導致改變的能帶間隙並且進而該NMOS電晶體中的汲極與源極及該延伸區之電阻率。因此,在電流驅動能力的方面之效能增益也可在該NMOS電晶體中獲得,因此提供實質上維持顧及經常會遇到與PMOS及NMOS電晶體的電流驅動能力相關的非對稱性之電路設計的潛在可能性,因為由於增進的電洞移動性造成之該PMOS電晶體的效能增益可能額外地造成降低該NMOS電晶體的源極與源極接面電阻所引致的對應或實質上對應的驅動能力之提高。因而,即使現有的設計考慮到以上說明的非對稱性也可顯著地提升該總體效能。
再者,本發明可結合部分耗盡的絕緣體上矽(SOI)裝置而有益地應用,因為提高的洩漏電流,其本質上可能被視為不利的效應,而且其可能與相較於摻雜矽經改變的能帶間隙的存在有關,可能造成增進的電荷載體放電及電荷能力以顯著地降低該浮體效應,該效應被視為部分耗盡的SOI電晶體中最主要的關注事項。因此,可能顯著地增進遲滯性質(hysteresis behavior),也就是說,在部分耗盡的SOI電晶體中之與歷史相關的訊號傳送延遲,藉以提供更大的設計彈性,如在傳統部分耗盡的SOI裝置中經常都必須增加額外的邊界以考慮到部分耗盡的SOI裝置相當大的遲滯所造成延遲變化的最壞情況。然而,應明白儘管本發明與SOI裝置結合係相當有益,特別是與部分耗盡的電晶體元件,但是本發明也可與其他電晶體結構結合而有益地應用,例如形成於塊狀矽基材或任何其他適當載體上的電晶體。因此,本發明不得限制於SOI裝置,除非此等限制在詳細說明及後附的申請專利範圍中明確地敘明。
參照第1a至1g圖及第2a至2c圖,現在將更詳細地說明本發明另外的例示性實施例。第1a圖概略地舉例說明包含第一電晶體110與第二電晶體120的半導體裝置100之截面圖。在基材101上面形成該第一與第二電晶體110、120,彼等可能不同於其導電性類型使得,例如,該第一電晶體110可代表PMOS電晶體而該第二電晶體120可代表NMOS電晶體。如以上的解釋,該基材101可代表彼上面形成能夠形成該第一與第二電晶體110、120之實質上結晶性半導體層的任何適當基材。在一個例示性實施例中,該基材101可代表彼上面形成絕緣層102接著結晶性半導體層的適當載體材料,該結晶性半導體層內可能已經界定半導體第一活性區或主體111,對應於該第一電晶體元件110,及半導體第二活性區或主體121,對應於該第二電晶體120。應明白包括該絕緣層102的基材101,其可包含二氧化矽、氮化矽或任何其他適當的絕緣材料,可代表任何SOI型基材,其中此術語係視為至少具有絕緣部分的任何基材之通稱,該絕緣部分上面有形成適合於彼內形成電晶體元件的結晶性半導體層。
該等活性區111及121可具有適合該等電晶體110、120的指定設計規則的厚度。在一個例示性實施例中,該等活性區111及121係設計而能形成部分耗盡的電晶體元件,同時,在其他的實施例中,該厚度可能適合於形成完全耗盡的裝置。再者,可分開該等活性區111及121並且進而藉由對應的絕緣結構103相互電性絕緣,該絕緣結構103可依淺溝槽絕緣(STI)或任何其他適當絕緣結構的形式提供。該絕緣結構103可由任何適當的材料構成,例如二氧化矽及氮化矽等。
在第1a圖所示的製造階段中,該第一與第二電晶體110、120分別地包含個別的閘極電極112及122,彼等各自藉由對應的閘極絕緣層113及123與個別的活性區111、121分別地隔開。再者,該閘極電極112上面已經形成頂蓋層(capping layer)114而且相似地該閘極電極122上面已經形成頂蓋層124,該等頂蓋層可包含適當的材料,例如氮化矽及氧氮化矽等。再者,以高度保形的方式(highly conformal manner)在該等活性區111、121及該等閘極電極112及122上形成間隔物層104。該間隔物層104的厚度可根據裝置的要求而選擇,例如在大約50至300埃()的範圍內,或毗鄰該等閘極電極112、122形成的凹部偏移量所欲的任何其他適當值。
用於形成如第1a圖所示的半導體裝置100之典型製程可包含下列製程。包括該絕緣層102的基材101,當考慮SOI結構時,可接收例如未摻雜或預摻雜的結晶性矽層的適當半導體層,其中該矽層可藉由晶圓黏合技術或用於提供SOI基材之任何其他已被接受的技術來形成。之後,該絕緣結構103可根據已被接受的調製法形成,例如標準光蝕刻顯影及各向異性(anisotropic)蝕刻技術接著適當的沈積及研磨技術,同時該絕緣結構103係依溝槽絕緣的形式提供。然而,其他的技術都可用於定義該等活性區111及121。接下來,可藉由氧化法及/或沈積法接著閘極電極材料(例如多晶矽或預摻雜多晶矽)的沈積而形成適當的介電層,該閘極電極材料的沈積可藉由已被接受的低壓化學氣相沈積(LPCVD)技術來完成。
之後,可在該閘極電極材料頂面上形成頂蓋層,其中該頂蓋層也可扮演後繼執行的光蝕刻顯影法用的抗反射塗佈(anti-reflective coating,ARC)層的角色。再者,該頂蓋層可額外地或選擇性地扮演該閘極電極材料後繼圖案化期間的硬質遮罩(hard mask)。又在其他的實施例中,該頂蓋層可經設計而與該閘極電極材料一起圖案化以便在最終形成個別的頂蓋層114、124而在前述光蝕刻微影及蝕刻製程的期間沒有任何另外的功能。
在該等閘極電極112、122及該等閘極絕緣層113、123圖案化之後,該間隔物層104可根據,例如,已被接受的電漿加強化學氣相沈積(PECVD)技術沈積所需的厚度,該所需的厚度實質上決定該活性區111、121內要被形成的預期凹部偏移量以在彼內形成用於獲得該等活性區111及121之一中的預期應變之適當半導體材料。在該間隔物層104的沈積之後,可對該半導體裝置100進行選擇性各向異性蝕刻製程102,藉以從該裝置100的水平部分移除該間隔物層。對應的適當各向異性蝕刻調製法在此技藝中已被接受而且也經常用於側壁間隔物的形成,同樣地可用於本實施方式並且進而用於電晶體元件的適當側向摻雜劑外廓之形成。
第1b圖概略地顯示該各向異性蝕刻製程102完成之後的半導體裝置100,藉以分別地留下該等閘極電極112及122側壁上的間隔物元件115、125。如以上的解釋,該等間隔物115、125的對應寬度115a、125a實質上一致而且實質上由該層104的厚度並且進而由用於形成該間隔物層104的對應沈積調製法決定。因此,藉由介電材料包覆該等閘極電極112、122以便在用於該電晶體110中形成嵌入之受應變之半導體層的後繼蝕刻及磊晶生長製程的期間實質上保護該等閘極電極112、122。
第1c圖概略地顯示在各向異性蝕刻製程(如106所示)期間的半導體裝置100,在該製程的期間分別地毗鄰該等閘極電極112及122形成對應的凹部116及126。該各向異性蝕刻製程106可經設計以顯示該活性區111及121的材料(例如矽)與該等間隔物115、125、該等頂蓋層114、124及該絕緣結構103的材料之間的高度選擇性。例如,在矽、二氧化矽及氮化矽之間具有適度選擇性的高度選擇性各向異性蝕刻製程係在此技藝中已被接受。藉此,當以溝槽絕緣的形式提供時,可以像在該絕緣結構103形成的期間運用般地使用類似的蝕刻技術。然而,應明白,就給定的蝕刻化學而固定的製程參數而言,該蝕刻製程106在該製程可控制的情況下可能為重要的,然而該蝕刻時間沒有任何終點偵測,所以製程不均勻性可能橫跨該基材101而直接地造成不同的凹部116、126之蝕刻深度。再者,該蝕刻製程106可能對圖案密度及圖案結構顯示特定的依賴性,其可能導致在傳統技術中經常藉由對應的蝕刻遮罩覆蓋一個電晶體元件,而有降低的可控制性。因此,由於避免蝕刻遮罩就像用於覆蓋該類型電晶體同時使另一類型暴露出來的傳統技術中經常遇到的情況,所以可達到增進的圖案均勻性並且進而達到蝕刻均勻性,藉以增進所得凹部116、126的均勻性。
接下來,可準備該裝置100以供後繼磊晶生長製程之用,其中可沈積適當的半導體化合物以至少在該等電晶體110、120之一中形成在個別閘極電極(例如閘極電極112)以下的受應變區域。由此,可執行適當之已被接受的清潔製程以移除該等凹部116、126內的暴露矽表面上之任何污染物。之後,根據已被接受的調製法提供適當的沈積氣氛,其中,在一個實施例中,該沈積氣氛可經設計以引發矽/鍺材料的沈積。可理解的是,當適當的摻雜物材料連同該半導體化合物同時地被沈積時,選擇性磊晶生長製程也可能遇到各種不同負載效應,彼等會改變局部的生長速率以及該局部摻雜物摻入量。相似地對該蝕刻製程106而言,缺乏任何磊晶生長遮罩,如同傳統策略中經常提供的,可顯著地增進該選擇性磊晶生長製程的均勻性。因此,在該磊晶生長的期間也可能達到增進的製程均勻性。
第1d圖概略地顯示該選擇性磊晶生長製程完成以便使對應的磊晶生長半導體層117及127分別地沈積在該等凹部116及126中之後的半導體裝置100。在一個例示性實施例中,該等半導體層117、127代表受壓縮應變之半導體材料,例如矽/鍺。例如,可將約10至20原子百分比的鍺供入該矽/鍺材料中,藉以在該等層117、127中形成受壓縮應變之晶格,其也將引致該等個別通道區中的對應非軸向壓縮應變,該等通道區以111a與121a來表示並且位在該等個別閘極電極112及122下方。應明白矽/鍺的提供關於PMOS電晶體中提供壓縮應變而言可能非常有益,同時附帶地被改變的能帶間隙可提供降低的接面電阻率,而且當對應的壓縮應變至少部分地被鬆弛時,個別PN接面的二極體洩漏最後也可能導致NMOS電晶體的增進效能,這將在後面作說明。然而,在其他實施例中,當實質上抗張應變如預期時,就可沈積其他的半導體化合物,例如矽/碳。
第1e圖概略地顯示在更進一步的製造階段中之半導體裝置100,其中該等間隔物115、125及對應的頂蓋層114、124都被移除。最後,當該等間隔物115、125及該等頂蓋層114、124實質上包含氮化矽時,就可執行已被接受的高度選擇性蝕刻製程,例如以熱磷酸為基礎。在一些實施例中,可藉由離子植入形成用於後繼汲極與源極延伸區形成的適當偏移間隔物(第1e圖中未顯示)而繼續進行進一步的製程。為了達到此目的,可形成對應的植入遮罩(未顯示),例如覆蓋該電晶體120同時暴露出該電晶體110。之後,可移除該植入遮罩並且可形成另外的植入遮罩以覆蓋該電晶體110同時暴露出該電晶體120。
第1f圖概略地顯示具有覆蓋該電晶體110的對應植入遮罩108之半導體裝置100。然而,應明白根據另一個例示性實施例,在此製造階段中可能未提供任何偏移間隔物,因此該第一電晶體110中可能尚未形成任何延伸區並且在第1f圖中說明此情況。然而,不管是否對應的偏移間隔物已經形成並且該電晶體110中可形成對應的延伸區,都可執行離子植入107以改變形成於該電晶體120中的半導體層127之應變。在一個例示性實施例中,該植入107可包含以包含氙、碳及氟其中之一的離子物種為基礎的植入步驟,其中可選擇對應的植入參數,例如植入能量及劑量,以有效地改變至少在該半導體層127之有意義部分內的結晶性結構。為了達到此目的,可使用已被接受的模擬技術以決定用於在該半導體層127內產生預期鬆弛效應的適當植入能量值及劑量值。例如,就大約l0至50奈米(nm)的範圍之半導體層127的厚度而言,在大約20至200千伏特的範圍之植入能量可能適合於以上指定的離子物種。在有些實施例中,可設計該離子植入107以產生複數結晶性缺陷,其最後導致顯著的鬆弛使得該半導體層127,其可包含矽/鍺,可代表實質上鬆弛的晶體,藉以也顯著地降低在該通道區121a內的任何壓縮應變,要不然可能對於彼內的電子移動性具有不利的影響。
在另外的例示性實施例中,當尚未提供偏移間隔物時,該植入製程107係經設計以實質上非晶化(amorphize)至少該半導體層127有意義的部分,以及該活性區121的暴露區域,如第1f圖所示。例如,在101 5
至101 6
離子/平方公分範圍內的高劑量配合重質離子物種,例如氙,可能導致暴露部分的實質非晶化,藉以實質上完全地移除該通道區121a內的任何壓縮應變。在一個例示性實施例中,當該閘極電極122的側壁上已經形成偏移間隔物(未顯示)時,在該等植入107設計成非晶化植入之後,就可利用經預先非晶化的結晶性結構引起的顯著降低通道效應非常有效地執行用於形成延伸區的對應植入。在其他的實施例中,可對如第1f圖所示的裝置,也就是說,該第一電晶體110不需經歷任何前述的間隔物形成及/或延伸植入,而進行另外的電晶體形成製程以完成該第一與第二電晶體110、120。
第1g圖概略地顯示更進一步的製造階段中之半導體裝置100。因此,該第一電晶體110包含汲極與源極區119及對應的延伸區119e,其至少部分地形成於該受應變之半導體層127內,藉以在通道區111a內產生非軸向的壓縮應變130。再者,在該閘極電極112的側壁上形成間隔物結構118,包含,例如,第一間隔物118a及第二間隔物118b。相似地,該電晶體120可包含汲極與源極區129及對應的延伸區129e,其實質上在實質上鬆弛的半導體層127內形成。因此,實質上移除該通道區121a中的任何壓縮應變,例如在該電晶體110中的應變130,然而另一方面,當包含矽/鍺時,該鬆弛的半導體層127的改變能帶間隙結構可提供降低的電阻,此外,然而該PN接面可提供提高的洩漏電流,藉以促成操作期間的電荷載體放電與充電以便降低該等電晶體120與110中的不利浮體效應。
如第1g圖所示之用於形成該半導體裝置100的典型製程流程可包含下列製程。如同以上的解釋,經過該鬆弛或非晶化植入107之後,就可移除該遮罩108並且可形成該等間隔物118a及128a,除非這些間隔物已經事先形成。為了達到此目的,可執行已被接受的間隔物形成技術,該技術包括適當材料及蝕刻阻擋層的沈積,接著適當的各向異性蝕刻製程。之後,可執行經適當設計的植入製程以形成該等延伸區119e及129e,其中可形成對應的植入遮罩以便將P-型摻雜物導入該電晶體110並且將N-型摻雜物導入該電晶體120。之後,可藉由已被接受的技術形成一個或更多個間隔物,例如間隔物元件118b及128b,接著後繼的深汲極與源極植入,其中再度地,可運用對應的罩蓋制度(regime)以便一方面提供經高度P-摻雜的汲極與源極區119並且另一方面經高度N-摻雜的汲極與源極區129。之後,可執行適當的退火製程以活化該等對應的摻雜物並且再結晶該等汲極與源極區及該等對應的延伸區。應明白,在有些實施例中,經過該植入107之後,若被設計成非晶化植入,可在用於形成該等汲極與源極區129及該等對應的延伸區129e之前,先執行對應的退火循環以便使該半導體層127重新長成實質上鬆弛的半導體層。在其他的具體例中,維持該層127實質上非晶化的結構並且以實質上非晶化的晶體為基礎執行用於形成該等延伸區129e及該等汲極與源極區129可能係有益的,藉以允許任何通道效應所引起的增進摻雜物外廓,同時可在用於活化該等摻雜物的後繼退火循環期間達到改良的再結晶效應。
結果,該半導體裝置100可包含呈PMOS電晶體形式的第一電晶體110,該PMOS電晶體內有壓縮應變130形成於該通道區111a中,藉以顯著地改良該電洞移動性,同時附帶地在可顯示提高的洩漏電流之活性區111中產生PN接面,藉以提供用於在該裝置100操作期間,降低主體電位增進之有效機制。相似地,該電晶體120可包含該實質上應變鬆弛的通道區121a,然而,同時由於該等汲極與源極區及該等延伸區129、129e中降低的矽/鍺之能帶間隙而能達到顯著降低的電阻,藉以也增進該電晶體120的電流驅動能力。再者,由於該等電晶體110、120提高的洩漏電流,所以能提供用於降低該不利主體電壓(亦即,該浮體效應)的有效機制。依此方式,可獲得該裝置100的效能之顯著提升,尤其是當以部分耗盡的SOI裝置的形式提供的情況時。
參照第2a至2c圖,現在將更詳細地說明本發明另外的例示性實施例。第2a圖概略地顯示可類似於第1a圖所示的裝置之半導體裝置200。也就是說,該半導體裝置200可包含彼上面形成絕緣層202的基材201,該絕緣層202上方可形成半導體的第一活性區或主體211及半導體的第二活性區或第二主體221。有關該基材201、該絕緣層202及該個別活性區211及221的特徵,適用如先前參照零件101、102、111及121所解釋的相同標準。再者,在該第一活性區211中及上面形成的第一電晶體210在此製造階段中可包含藉由個別頂蓋層214覆蓋並且藉由閘極絕緣層213與該活性區211分開的閘極電極212。相似地,第二電晶體220可包含形成在閘極電極222上的頂蓋層224並且藉由個別的閘極絕緣層223與該活性區221分開的閘極電極222。如第2a圖所示的半導體裝置200可根據如參照第1a圖所示的半導體裝置100所說明之實質上相同的製程形成,除了該間隔物層104的形成以外。再者,可對該半導體裝置200進行植入製程207,其中可形成對應的植入遮罩208以便實質上防止該第一電晶體210受到對應的離子轟擊(bombardment)所影響,同時該電晶體220暴露於該植入207。該植入207可以離子物種為主,例如氙、碳及氟等,並且可利用在該活性區221內提供實質上完全的非晶化之製程參數來執行。該活性區221的對應實質上非晶化部分如221a所示,其中該實質上非晶化部分221a的垂直延伸可藉以適當地選擇或改變該植入能量而調整。對應的能量參數可由已被接受的模擬計算輕易地獲得。因此,該植入207可被控制以維持原始結晶性活性區221的至少一部分,其可表示成垂直距離221b,其中應明白,由於離子植入製程的特定本質,非晶化與結晶區之間的邊界可能為非陡峭的邊界而且實質上可能代表連續的轉變。接下來,可移除該植入遮罩208並且後繼地可保形地沈積間隔物層,例如層104(第1a圖)並且可後繼地圖案化以形成對應的間隔物元件。
第2b圖概略地顯示以上說明的製程完成之後的半導體裝置200,藉以分別地提供間隔物215及225,以便實質上包覆該等個別的閘極電極212及222。接下來,可執行各向異性蝕刻製程,如206所示,以形成毗鄰該等個別的閘極電極212及222之凹部216及226。藉此,由於事實上該活性區221的暴露部分實質上被非晶化,所以在第一電晶體210與第二電晶體220中的蝕刻速率可不相同,藉以如同在第一電晶體210中遭遇到的,相對於實質上結晶性材料經常地提供增進的蝕刻速率。因此,該凹部226相較於該凹部216可具有提高的深度。之後,可在磊晶選擇性生長製程之前執行任何預清潔製程,並且之後可沈積適當的半導體化合物,例如用於形成該第一電晶體210的凹部216中的受應變層之矽/鍺。因為沈積在該第二電晶體220上的半導體化合物可能遇到實質上非晶化的半導體材料,所以喪失適當的結晶性模板並且因此以實質上非晶化或多結晶的方式沈積該半導體化合物。
在另一個實施例中,由於預先非晶化的部分221a之提高的蝕刻速率,可執行先前的非晶化植入207以便在後繼的各向異性蝕刻製程206期間實質上完全地移除實質上非晶化的部分221a以保留實質上結晶性部分,其相較於該凹部216係顯著地較薄。因此,在該選擇性磊晶生長製程的期間,該材料可沈積在該凹部226底部之實質上結晶性材料上面,其中,相對於該凹部216,因為該凹部226剩餘的厚度可能相應地變形,所以可形成實質上鬆弛的半導體層,藉以當以磊晶方式生長的晶體實質上被鬆弛時,該其餘的部分中將產生抗張應變。
第2c圖概略地顯示該磊晶生長製程完成之後的半導體裝置200,其中當該凹部226形成之後仍留下實質上非晶化的部分時,就在該閘極電極212之後形成受應變之半導體層217,同時在該閘極電極222之後形成實質上非晶化的半導體層227。在以上說明的其他例示性實施例中,該半導體層227可,至少部分地,包含非晶化部分鄰接該通道區221之實質上鬆弛的半導體晶體。應明白,由於該等凹部216及226的不同深度,所以也可獲得該等層217及227高度的對應差異。之後,可執行退火製程以有效地再結晶或進一步結晶化該半導體層227,其中當該層227在先前選擇性磊晶生長製程的期間已經依實質上鬆弛層之形態產生時,該半導體層227可變成實質上鬆弛或可維持實質上鬆弛層的狀態。在此例中,因為可形成在該層227底下的凹部之其餘結晶性材料而顯示抗張應變,所以該通道區221中也可產生一定程度的抗張應變,藉以增進彼內的電子移動性。
之後,可依參照第1f至1g圖說明的方式繼續進行進一步的製程,也就是說,可在該等電晶體210及220中形成源極與汲極區及對應的延伸區。在該半導體層227依實質上非晶化層的形態沈積之一實施例中,先前說明的退火製程可能沒執行並且可能延到直到該等電晶體210及220中形成個別的汲極與源極區及延伸區時,所以可依普通的退火製程完成再結晶,其對於有限的熱預算而言可能係有益的,同樣地鍺原子傾向在提高的溫度下更輕易地擴散,藉以潛在地犧牲該等閘極絕緣層213及223的特性,及該通道導電性。
因此,利用參照第2a至2c圖所說明的實施例,就先前對照第1a至1g圖所說明的製程來說,可提供增進的製程及設計彈性而不會添加任何製程複雜度。舉例來說,在該選擇性磊晶生長製程之前及該蝕刻製程206之前執行該鬆弛或非晶化植入207,可局部地調整蝕刻速率而不會顯著地影響改良的蝕刻均勻性,該改良的蝕刻均勻性係藉由避免對應的蝕刻遮罩而完成。例如,從第2a圖所示的裝置開始之類似方法中,可在該電晶體220上面形成植入遮罩208以便非晶化該活性區211至指定的深度而在後繼蝕刻製程206的期間提供提高的蝕刻速率。因此,利用減短的蝕刻時間,該凹部216可獲得實質上相同的深度,然而另一方面,該對應的凹部226具有顯著降低的厚度。因此,在後繼的選擇性磊晶生長製程中,可形成具有提高高度的對應半導體層227,藉以顯著地減低後繼執行的鬆弛非晶化植入之侷限,因為個別的通道區221中產生顯著較小的應變因此可更有效地鬆弛,同時可降低任何植入引發的損害之產生。再者,藉由局部地改變該蝕刻速率,至可調整最後獲得之個別半導體層217及227的高度差異之特定程度,藉以也可提供調整金屬矽化物的高度之可能性,該金屬矽化物經常都在該等電晶體元件210及220完成之後形成。再者,在某些例示性實施例中,該選擇性磊晶生長製程可按照摻入特定量的摻雜物(例如,P-型摻雜物)而執行,其中由於依實質上單獨的方式,選擇性地控制該蝕刻速率進而控制該等對應凹部216、226的深度之可能性,而能相應地設置清楚定義的PN接面。例如,可形成適當淺凹部226,其中適當高度的P-型摻雜不可能過度地影響該活性區211內更深處形成的對應PN接面,然而該凹部216中可配置適當高度的P-型摻雜以便可獲得,至少部分地,明確的PN接面。
結果,藉著增進該PMOS電晶體中的電洞移動性同時附帶地在該NMOS電晶體中提供降低的接面電阻,可達成PMOS與NMOS電晶體的增進效能。在特定的實施例中,提供部分耗盡的電晶體裝置,其中在該裝置操作的期間,該提高的洩漏電流額外地提供用於降低該主體電壓的有效機制,藉以顯著地改良部分耗盡的SOI裝置的遲滯性質。
以上所揭示的特定實施例僅為例示性,因為本發明可依獲得本文教導的助益之熟於此藝者顯而易見之不同但等效的方式變更。例如,以上說明的製程步驟可依不同的順序而執行。再者,除了以下申請專利範圍所說明的以外,不欲限制本文所示的結構或設計之細節。因此很顯然地以上所揭示的特定實施例可加以改變或修飾,而且所有此等變化都視為在本發明的範圍與精神的範疇以內。因此,本文尋求保護的部分係如以下申請專利範圍所說明。
100...半導體裝置
101...基材
102...絕緣層
102...各向異性蝕刻製程
103...絕緣結構
104...間隔物層
106...各向異性蝕刻製程
107...離子植入
108...植入遮罩
110...第一電晶體;第一電晶體元件
111...半導體第一活性區
111a...通道區
112...閘極電極
113...閘極絕緣層
114...頂蓋層
115...各間隔物元件
115a...間隔物的對應寬度
116...凹部
117...磊晶生長半導體層
118...間隔物結構
118a...第一間隔物
118b...第二間隔物
119...汲極與源極區
119e...延伸區
120...第二電晶體
121...半導體第二活性區
121a...通道區
122...閘極電極
123...閘極絕緣層
124...頂蓋層
125...間隔物元件
125a...間隔物的對應寬度
126...凹部
127...磊晶生長半導體層
128a...第一間隔物
128b...間隔物元件
129...汲極與源極區
129e...延伸區
130...非軸向的壓縮應變
200...半導體裝置
201...基材
202...絕緣層
206...各向異性蝕刻製程
207...植入製程
208...植入遮罩
210...第一電晶體
211...半導體第一活性區
212...閘極電極
213...閘極絕緣層
214...頂蓋層
215...間隔物
216...凹部
217...受應變之半導體層
220...第二電晶體
221...半導體第二活性區
221a...實質上非晶化部分
221b...垂直距離
222...閘極電極
223...閘極絕緣層
224...頂蓋層
225...間隔物
226...凹部
227...受應變之半導體層
參照以下的說明結合隨附的圖式就可了解本發明,其中類似的元件符號視為類似的元件,而其中:第1a至1g圖概略地顯示在根據本發明的例示性實施例之在各種不同製造階段的期間包括PMOS與NMOS電晶體的半導體裝置之截面圖,其中形成該PMOS電晶體使受壓縮應變之半導體層內含於該PMOS電晶體的汲極與源極區並且局部地在其延伸區,同時該NMOS電晶體的汲極/源極與延伸區中包含實質上鬆弛的半導體層;以及第2a至2c圖概略地顯示根據本發明另外的例示性實施例,在第二電晶體接受實質上未受應變之半導體層的情況下彼內形成受應變之半導體層的第一電晶體形成的期間之截面圖。
儘管本發明容易進行各種不同的修飾及替代性形式,但是彼等的指定實施例已藉由圖式中的例子顯示並且在此詳細地加以說明。無論如何,應了解指定實施例在本文中的說明並非意欲將本發明限於所揭示的特定形式,相對而言,本發明意欲涵蓋落在後附申請專利範圍所界定之發明精神與範圍以內的所的修飾例、等效例及替代例。
100...半導體裝置
101...基材
102...絕緣層
103...絕緣結構
110...第一電晶體
111...半導體第一活性區
111a...通道區
112...閘極電極
117...磊晶生長半導體層
118...間隔物結構
118a...第一間隔物
118b...第二間隔物
119...汲極與源極區
119e...延伸區
120...第二電晶體
121...半導體第二活性區
121a...通道區
122...閘極電極
123...閘極絕緣層
127...磊晶生長半導體層
128a...第一間隔物
128b...間隔物元件
129...汲極與源極區
129e...延伸區
130...非軸向的壓縮應變
Claims (21)
- 一種用於形成積體電路之方法,包含:形成毗鄰第一類型之第一電晶體之閘極電極的第一凹部;形成毗鄰第二類型之第二電晶體之閘極電極的第二凹部,該第二類型與該第一類型不相同;在該第一與第二凹部中選擇性地形成受應變之半導體層;以及選擇性地改變該第二凹部中之該受應變之半導體層以降低其中的應變。
- 如申請專利範圍第1項之方法,其中改變該受應變之半導體層包含藉由離子植入而鬆弛該第二凹部中的該應變。
- 如申請專利範圍第2項之方法,其中該離子植入係藉由使用包含氙、碳及氟之至少一者的離子物種而執行。
- 如申請專利範圍第1項之方法,其中改變該受應變之半導體層包含非晶化該第二凹部內的該半導體層以及執行退火製程以用於實質上再結晶該非晶化的半導體層。
- 如申請專利範圍第1項之方法,復包含在絕緣層上所形成的半導體之結晶主體上方形成該第一電晶體的該閘極電極及該第二電晶體的該閘極電極。
- 如申請專利範圍第5項之方法,其中該第一電晶體代表PMOS電晶體而且該第二電晶體代表NMOS電晶體。
- 如申請專利範圍第1項之方法,復包含在形成該第一與 第二凹部之前先在該第一與第二電晶體的該閘極電極上形成頂蓋層。
- 如申請專利範圍第7項之方法,復包含在形成該第一與第二凹部之前先在該第一與第二閘極電極的側壁處形成間隔物。
- 如申請專利範圍第1項之方法,復包含在填充該第一與第二凹部的該半導體層中至少局部地形成用於該第一與第二電晶體之汲極與源極區及延伸區。
- 一種用於形成積體電路之方法,包含:形成毗鄰第一類型之第一電晶體之第一閘極電極的第一凹部;形成毗鄰第二類型之第二電晶體之第二閘極電極的第二凹部,該第二類型與該第一類型不相同;共通地形成在該第一凹部中之第一半導體層及在該第二凹部中之第二半導體層;以及在形成該第一與第二半導體層之前先實質上非晶化毗鄰該第二閘極電極的半導體主體的部分,其中該第一半導體層在該第一凹部中係受應變以及該第二半導體層在該第二凹部中係實質上鬆弛。
- 如申請專利範圍第10項之方法,其中該第一與第二半導體層皆係受應變之層,該方法復包含選擇性地改變該第二凹部中之該受應變之半導體層以降低其中的應變。
- 如申請專利範圍第10項之方法,其中該第二凹部係形成在該非晶化的部分中。
- 如申請專利範圍第10項之方法,其中在形成該第一與第二凹部之後非晶化該部分。
- 如申請專利範圍第10項之方法,復包含執行退火製程以實質上再結晶該部分及該第二半導體層。
- 如申請專利範圍第10項之方法,復包含在形成該第一與第二凹部之前先利用蝕刻阻擋層包覆該第一與第二電晶體的該閘極電極。
- 如申請專利範圍第10項之方法,其中在絕緣層上方所形成的半導體層上形成該第一與第二電晶體。
- 如申請專利範圍第10項之方法,復包含形成毗鄰該第一與第二閘極電極之汲極與源極區及延伸區。
- 如申請專利範圍第10項之方法,其中該第一電晶體代表P-通道電晶體而且該半導體層係受壓縮應變之層。
- 一種半導體裝置,包含:第一導電性類型之第一電晶體,該第一電晶體的延伸區及源極與汲極區中包含指定半導體材料之受應變之層;以及第二導電性類型之第二電晶體,該第二電晶體的延伸區及源極與汲極區中包含該指定半導體材料之實質上鬆弛之層。
- 如申請專利範圍第19項之半導體裝置,復包含埋入式絕緣層,在該埋入式絕緣層上形成該第一與第二電晶體。
- 如申請專利範圍第20項之半導體裝置,其中該第一與第二電晶體代表部分耗盡的電晶體。
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