TWI464802B - 藉由化學氣相沉積之低溫介電膜形成 - Google Patents

藉由化學氣相沉積之低溫介電膜形成 Download PDF

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TWI464802B
TWI464802B TW100134827A TW100134827A TWI464802B TW I464802 B TWI464802 B TW I464802B TW 100134827 A TW100134827 A TW 100134827A TW 100134827 A TW100134827 A TW 100134827A TW I464802 B TWI464802 B TW I464802B
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Anthony Dip
Kimberly G Reid
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Description

藉由化學氣相沉積之低溫介電膜形成
本發明係關於半導體基板處理，尤有關於使用氯化之矽烷與水蒸氣之低溫介電膜沉積之方法。
在半導體基板表面上之積體電路之形成過程中，氧化物或氮氧化物膜頻繁地生長或沉積在晶體基板(例如：矽)之表面上方。舉例來說，用在半導體快閃記憶體與微特徵側壁應用(micro-feature sidewall applications)之高品質氧化矽(SiOx ，x≦2)膜之化學氣相沉積(CVD)之工業標準製程係以二氯矽烷(DCS)與一氧化二氮(N2 O)之高溫反應為基礎。此製程之主要優點包含在批次製程中同時處理多個基板之能力；氧化矽膜之良好電氣性能；以及相較於其他CVD膜，膜之濕蝕刻速率相對低，該CVD膜例如：使用矽酸四乙酯(TEOS，tetraethyl orthosilicate)、雙(叔丁胺基)矽烷(BTBAS，bis(tertiary-butylamino) silane)、與其他前導物所沉積之膜。
然而，有一些關於使用DCS與N2 O來執行氧化矽膜之CVD之缺點。當使氧化矽膜與需要低的熱預算之先進材料結合時，此CVD製程需要可能會限制其使用之相當高之基板溫度(例如：約800℃)。並且，已發現使用N2 O氣體作為氧化氣體會導致不良與普遍不可控制之氮(N)結合到氧化矽膜中。低的膜沉積率被認為是由於氧化膜上之速率限制DCS成核步驟所造成，其因DCS與N2 O間缺乏氣相反應所引起。
高K介電質之需求使製造業者必須藉由將氮結合至氧化物膜中來加強現存之氧化物膜(例如：矽與鍺上之氧化物膜)。在此技藝中眾所皆知，氮結合至氧化物膜會增加所產生氮氧化物膜之介電常數，並且允許薄閘極介電質生長在這些半導體基板材料上。氮氧化矽(SiOx Ny )膜可以有良好的電氣特性，包含半導體應用中之裝置運作所期望之高電子遷移率(electron mobility)與低電子陷阱密度(electron trap density)。氮結合至薄氧化矽膜之更多優點包含：減少硼穿透P摻雜多晶矽閘極、改善之介面平坦度、氮氧化矽膜之介電常數之增加、以及改善之障壁特性以避免金屬氧化物或金屬閘極材料擴散至下方基板。
由於半導體裝置之微型化與先進材料之使用(需要減少之半導體處理方法之熱預算)，有新處理方法之需求，該新處理方法提供於控制之深度具高氮結合之低溫氧化矽與氮氧化矽膜沉積作用，同時提供氧化物生長之控制速率。
本發明之一實施例提供藉由使用二氯矽烷(DCS)與水蒸氣在批次式處理系統中之數個基板上低溫CVD氧化矽膜之方法。該方法包含：將數個基板安置在製程腔室中；將製程腔室加熱至400℃與少於650℃間之沉積溫度；將包含水蒸氣之第一製程氣體流動到製程腔室中；將包含二氯矽烷(DCS)之第二製程氣體流動到製程腔室中；在製程腔室中建立少於2 Torr之氣體壓力；以及使第一與第二製程氣體反應，以在數個基板上熱沉積氧化矽膜。另一實施例更包含：在流動第一製程氣體與第二製程氣體時將包含一氧化氮(NO)氣體之第三製程氣體流動到製程腔室中；以及使氧化物膜與第三製程氣體反應，以在基板上形成氮氧化矽膜。
本發明之實施例提供用來形成半導體裝置之介電膜之低溫沉積製程。在一實施例中，提供使用二氯矽烷(DCS)與水蒸氣之氧化矽膜之非電漿CVD方法。在另一實施例中，提供使用DCS、水蒸氣、與一氧化氮(NO，nitric oxide)氣體之氮氧化矽膜之非電漿CVD方法。本發明之實施例達到具有良好材料與電氣特性之二氧化矽與氮氧化矽膜之高沉積速率，同時使用比工業標準高溫氧化物(HTO)製程(依賴基板上之DCS與一氧化二氮(N2 O，nitrous oxide)之反應)更低之沉積溫度。
本發明者了解，以水蒸氣氧化劑與非必要之NO氣體取代N2 O氧化劑來形成氮氧化矽膜，允許沉積溫度降低大於100℃、大於200℃、或甚至大於300℃(例如：高達350℃)，同時提供有良好材料特性之氧化矽膜，該良好材料特性包含相較於基線HTO製程之低濕蝕刻速率。此沉積溫度之降低提供先進積體電路所需之熱預算之必要降低，因為受限制之熱預算不會允許基板溫度之增加，而且更長之處理時間在半導體裝置之高量製造中會不符合成本效益。
水蒸氣氧化劑之使用比在相同低沉積溫度下使用N2 O提供更高之沉積速率，同時提供相當之氧化矽與氮氧化矽膜之電氣性能。不像使用N2 O之HTO製程，本發明之實施例提供用來精確控制氮氧化矽膜之N結合之機構。而且，可以選擇性地在高於沉積溫度之溫度下執行後沉積(post-deposition)熱處理，以進一步改善氧化矽與氮氧化矽膜之材料與電氣特性。
雖然不希望受理論拘束，本發明者相信，不像被認為專門發生在基板表面上之DCS與N2 O間之反應，DCS與水蒸氣間之氣相反應(在與基板表面互相作用之前)能使基板表面上發生因DSC裂解或聚合物之形成所產生之DCS物種之改善核化作用。
圖1係橫剖面圖，顯示具有製程腔室12之批次式處理系統10，而數個基板20安置在製程腔室12內。熟悉本技藝者將觀察到，雖然顯示與描述批次式處理系統10，本發明亦可應用於一次處理一個基板之單一式基板處理。圖2A與2B描述在圖1中之基板20上個別形成氧化矽與氮氧化矽膜之製程流程圖。
現在參考圖1與圖2兩者，在方法200之一實施例中，在步驟202中，將數個基板20安置在製程腔室12中。基板20可以安置在可旋轉基板支撐器13上。熟悉本技藝者將觀察到，將基板20安置或裝載到批次式處理系統10內可以包含在基板20插入後透過排氣口15使製程腔室12排氣、以及透過真空口14來排空製程腔室12。此外，將基板20安置於批次式處理系統10內也可以包含使用惰性氣體(例如：氮)來洗滌製程腔室12，以稀釋或減少製程腔室12內之有機污染物之濃度。
在步驟204中，將製程腔室12加熱到400℃與少於650℃之間之沉積溫度。在製程腔室12之加熱期間，加熱速率可以從每分鐘數度C到每分鐘100度C以上。
在加熱之後，在步驟206中，將包含水蒸氣之第一製程氣體透過進氣口16而導引到製程腔室12中。第一製程氣體包含水蒸氣但不是氮化氣體。在步驟208中，將包含DCS與非必要之稀釋氣體之第二製程氣體透過進氣口17而導引到製程腔室12中。在步驟210中，在製程腔室中建立低於2 Torr之製程氣體壓力。在步驟212中，來自水蒸氣之氧與DCS於氣相中反應，並在各基板20上沉積氧化矽膜。
現在參考圖1與圖3兩者，在方法300之另一實施例中，在步驟302中，將數個基板20安置在製程腔室12中。基板20可以安置在可旋轉基板支撐器13上。熟悉本技藝者將觀察到，將基板20安置或裝載到批次式處理系統10內可以包含在基板20插入之後透過排氣口15來使製程腔室12排氣、以及透過真空口14來排空製程腔室12。此外，將基板20安置於批次式處理系統10內也可以包含使用惰性氣體(例如：氮)來洗滌製程腔室12，以稀釋或減少製程腔室12內之有機污染物之濃度。
在步驟304中，接著將製程腔室12加熱到400℃與少於650℃之間之處理溫度。在製程腔室12之加熱期間，加熱速率可以從每分鐘數度C到每分鐘100度C以上。
在加熱之後，在步驟306中，將包含水蒸氣之第一製程氣體透過進氣口16而導引到製程腔室12中。在步驟308中，將包含DCS與非必要之稀釋氣體之第二製程氣體透過進氣口17而導引到製程腔室12中。在步驟310中，將包含NO與非必要之稀釋氣體之第三製程氣體導引到製程腔室中。在步驟312中，在製程腔室中建立低於2 Torr之製程氣體壓力。在步驟314中，來自水蒸氣之氧在氣相中與DCS和NO反應，如此來自NO之氮會結合至氧化矽膜中，藉此在各基板20上形成氮氧化矽膜。
配合可以產生處理環境之第一、第二、與非必要之第三製程氣體之流速，處理環境有一處理壓力。本發明者了解處理壓力可低於2 Torr，以沉積具有良好均勻度與半導體裝置之所需材料與電氣特性之氧化矽與氮氧化矽膜。根據一實施例，處理壓力可以在100 mTorr與少於2 Torr之間、100 mTorr與1 Torr之間、1 Torr與少於2 Torr之間、1 Torr與1.5 Torr之間、或1.5 Torr與少於2 Torr之間。根據本發明之實施例，沉積製程可以使用在400℃與少於650℃之間、400℃與450℃之間、400℃與500℃之間、500℃與550℃之間、500℃與600℃之間、550℃與600℃之間、550℃與少於650℃之間、或600℃與少於650℃之間之沉積溫度。在一實施例中，配合處理溫度來設定處理壓力，以控制氧化矽或氮氧化矽膜之沉積速率。熟悉本技藝者將觀察到，在膜沉積期間，處理壓力與氣體流速隨時會變化。因此，「設定」一詞並不限制於設定處理壓力、氣體流速、或處理溫度之單一動作。更確切地說，設定可以代表任何數目之設定或調整動作，如此係依據來自內部控制、來自產業、或者由客戶所決定之任何品質標準來沉積氧化矽膜或氮氧化矽膜。第一、第二、以及非必要之第三製程氣體之流速可以在從10 sccm(每分鐘標準立方米)到20 slm(每分鐘標準公升)之範圍內，對NO氮化氣體而言為1到5000 sccm，而對稀釋氣體而言為100 sccm到20 slm。
根據本發明之一實施例，在將包含水蒸氣之第一製程氣體流動到製程腔室12中之前，如圖1所顯示，藉由氫氣(H2 )與氧氣(O2 )之燃燒作用以在製程腔室12外部產生水蒸氣。如圖1所描述，產生第一濕製程氣體之一範例為使用Tokyo Electron Ltd.,Nirasaki,Tamanashi,Japan所發展之高稀釋致熱炬18(high-dilution pyrogenic torch)。高稀釋致熱炬燃燒小流量之氫氣與氧氣。致熱炬18因此在製程腔室12外部產生水蒸氣(即蒸氣形式之水蒸氣)。
在本發明之另一實施例中，在處理環境中使用稀釋氣體來稀釋第一與第二製程氣體。稀釋氣體之濃度與第一和第二製程氣體之濃度之比率會影響氧化矽或氮氧化矽膜之沉積速率。因此，可以使用稀釋氣體來控制氧化矽膜生長速率與氮氧化矽膜生長速率。在一實施例中，如圖1所顯示，稀釋氣體包含氮氣(N2 )。然而，可以使用其他非反應性氣體，例如：氬(Ar)。仍舊參考圖1，熟悉本技藝者將容易地了解，可以使用氮稀釋氣體來稀釋包含水蒸氣之第一製程氣體，而不需將NO氣體流動到製程腔室中。
在方法之另一實施例中，一旦氧化矽膜或氮氧化矽膜沉積在各基板20上，便以高於沉積溫度之熱處理溫度來熱處理其上有膜之基板20。在此技藝中眾所皆知，熱處理基板20上之二氧化矽或氮氧化矽膜會更改膜之特性，尤其是膜之電氣特性，因此會變更含膜裝置之電氣特性。根據本發明之實施例，在熱處理期間，可以更改處理環境與處理壓力。舉例來說，在製程腔室12中之膜沉積作用之後，在熱處理前製程腔室12會被真空洗滌一或更多次，以去除包含第一、第二、與非必要之第三製程氣體之處理環境以及稀釋氣體(若有的話)。處理環境一經洗滌，熱處理氣體會被導引並且處理腔室12內會建立熱處理溫度與熱處理壓力，其會需要從沉積壓力提升或降低壓力。或者，其上有氧化矽或氮氧化矽膜之基板20會傳送到不同處理系統以進行熱處理。熱處理壓力可以相似於沉積壓力之範圍。根據一實施例，熱處理氣體包含氮氣(N2 )、一氧化氮(NO)、一氧化二氮(N2 O)、氧氣(O2 )、或水(H2 O)、或其混合物之至少一者。
圖4係顯示根據本發明實施例之為DCS流速的函數之氧化矽沉積速率。膜沉積條件包含100 sccm之H2 氣體流速度與100 sccm之O2 氣體流速度通過致熱炬18、水蒸氣產生器，因此產生水蒸氣。使用200 sccm之N2 稀釋氣體流速來稀釋包含水蒸氣之第一製程氣體。在氧化矽膜之沉積期間建立0.2 Torr之處理壓力，而沉積溫度可以變化於450℃到600℃間。氧化矽膜之厚度小於約100。DCS氣體流速可以變化於10 sccm到20 sccm之間。圖4顯示增加DCS流速會導致增加之氧化矽沉積速率，在450℃與500℃之沉積溫度下從約3-4/min增加到約9-10/min、以及在600℃下從6/min增加到約11/min。此外，為了作比較，圖4顯示在基板表面上使用將DCS與N2 O反應之習知HTO製程於810℃之沉積溫度下之氧化矽膜之沉積速率僅為約2/min，而且沉積速率實質上與DCS流速無關。
圖5係顯示根據本發明實施例之為N2 後沉積熱處理溫度的函數之不同氧化矽膜之濕蝕刻速率。濕蝕刻速率為氧化矽膜之材料品質之量測，其中高品質氧化矽膜濕蝕刻慢於低品質氧化矽膜。在存在N2 氣體之0.5 Torr之處理壓力與不同溫度之(沉積)製程腔室中，經沉積之氧化矽膜接著被熱處理1小時。在熱處理之後，二氧化矽膜接著在稀釋HF(200：1，N2 O：HF)中經歷2.5分鐘之濕蝕刻製程，而且將蝕刻速率對基線HTO氧化矽膜之蝕刻速率正規化，該基線HTO氧化矽膜係於800℃下使用50 sccm之DCS氣體流速與100 sccm之N2 O氣體流速沉積而成。圖5顯示對於相同方式沉積之氧化矽膜而言，更高之沉積溫度或更高之DCS氣體流速會導致更高之濕蝕刻速率。此外，後沉積熱處理溫度越高，使用10 sccm之DCS氣體流速所沉積之氧化矽膜之濕蝕刻速率越低。在一範例中，於600℃之基板溫度下使用低DCS氣體流速(10 sccm)所沉積並接著在N2 氣體中、800℃之基板溫度下經熱處理之氧化矽膜之濕蝕刻速率小於基線HTO氧化矽膜之濕蝕刻速率。
圖6係顯示藉由本發明實施例所形成之氧化矽與氮氧化矽膜之電容-電壓曲線。藉由使用DCS與水蒸氣來沉積氧化矽膜，並且藉由將50 sccm與100 sccm之NO氣體添加到DCS與水蒸氣製程氣體中來沉積氮氧化矽膜。表1與圖6之結果說明NO氣體之添加會增加TOX 、沉積速率、等效氧化物厚度(EOT)、以及介電常數(K)。此外，雖然未顯示於表1中，對於在0到50 sccm間之NO氣體流速而言，介面陷阱密度(Dit )預期會減少至基線氧化矽之介面陷阱密度之約1/100(即從約E12eV-1 cm-2 降低到E10eV-1 cm-2 )。這樣的Dit 之減少會提供具有相對地無電荷陷阱之介面之氮氧化矽膜，並且其本身可以有利地使用作為具有大幅改善之電子/電動遷移率與最高通道驅動電流之金氧半導體場效電晶體(MOSFET，metal oxide semiconductor field effect transistor)裝置之閘介電質。而且'當NO氣體流速增加到大於50 sccm，而氮氧化矽膜中之N濃度進一步增加時，不管Dit 值之增加，預期將改善包含氮氧化矽膜(例如：非揮發性記憶體(NVM，non-volatile memory)應用，如快閃記憶體隧道閘極)之半導體裝置之可靠度。雖然增加之Dit 值表示介面電荷捕獲與MOSFET起始電壓(Vth )之可能偏移之可能性提高，NVM應用之可靠度之改善被認為比因Dit 增加所帶來之任何缺點重要。增加之N濃度被認為有利於將膜內之鬆(懸浮)原子鍵結結合得更緊密。此外，增加之N濃度會提高膜之密度，而且導致對於在上升電壓之電子衝擊(electron bombardment)(常使用於半導體處理期間)之阻力增加。總體而言，結果顯示，不像使用DCS與N2 O之先前技術反應，在使用DCS與H2 O之膜沉積期間添加NO有效於將N結合至氧化矽膜，以形成半導體裝置之氮氧化矽膜。
雖然已藉由其一或多個實施例之描述來說明本發明，以及雖然已相當詳細地說明本實施例，其並不意圖將隨附申請專利範圍限定或以任何方式限制於這些詳述。額外優點與修改將容易地顯露給熟悉本技藝者。本發明因此不限制於顯示與描述之特定細節、代表設備與方法、以及說明範例。因此，在不離開一般發明概念之範圍內，可以變更這些細節。
10．．．批次式處理系統
12．．．製程腔室
13．．．基板支撐器
14．．．真空口
15．．．排氣口
16、17．．．進氣口
18．．．致熱炬
20．．．基板
200、300．．．方法
202、204、206、208、210、212．．．步驟
302、304、306、308、310、312、314．．．步驟
隨附之圖示，包含於說明書內且構成說明書的一部分，闡明本發明之實施例，並且連同上述發明之一般說明與上面之詳細說明，得以解釋本發明。
圖1係橫剖面圖，概略地顯示根據本發明一實施例之用來處理數個基板之批次式處理系統；
圖2係在基板上沉積氧化物膜之方法之一實施例之製程流程圖；
圖3係在基板上沉積氮氧化物膜之方法之一實施例之製程流程圖；
圖4係顯示根據本發明實施例之為DCS流速的函數之氧化矽沉積速率；
圖5係顯示根據本發明實施例之為N2 後沉積熱處理溫度的函數之不同氧化矽膜之濕蝕刻速率；
圖6係藉由本發明實施例所形成之氧化矽與氮氧化矽膜之電容-電壓曲線。
10．．．批次式處理系統
12．．．製程腔室
13．．．基板支撐器
14．．．真空口
15．．．排氣口
16、17．．．進氣口
18．．．致熱炬
20．．．基板

Claims (16)

  1. 一種在基板上形成介電膜之方法，該方法包含：將數個基板安置在製程腔室中；將該製程腔室加熱至400℃與少於650℃間之沉積溫度；將包含水蒸氣之第一製程氣體流動到該製程腔室中；將包含二氯矽烷(DCS)之第二製程氣體流動到該製程腔室中；在該製程腔室中建立少於2Torr之氣體壓力；以及使該第一與該第二製程氣體反應，以藉由非電漿化學氣相沉積，在該數個基板上熱沉積氧化矽膜。
  2. 如申請專利範圍第1項之在基板上形成介電膜之方法，更包含藉由燃燒氫氣(H2 )與氧氣(O2 )以在該製程腔室外部產生該水蒸氣。
  3. 如申請專利範圍第1項之在基板上形成介電膜之方法，更包含，在形成該氧化矽膜後，在熱處理氣體中熱處理其上有該氧化矽膜之該基板，該熱處理氣體包含氮氣(N2 )、一氧化氮(NO)、一氧化二氮(N2 O)、氧氣(O2 )、或水(H2 O)、或其混合物之至少一者。
  4. 如申請專利範圍第3項之在基板上形成介電膜之方法，其中該熱處理係執行於高於該沉積溫度之溫度下。
  5. 如申請專利範圍第1項之在基板上形成介電膜之方法，更包含在流動該第一製程氣體與該第二製程氣體時將第一稀釋氣體流動到該製程腔室中，以控制該氧化矽膜之生長速率。
  6. 如申請專利範圍第1項之在基板上形成介電膜之方法，更包含在流動該第一製程氣體與該第二製程氣體時將包含一氧化氮(NO)氣體之第三製程氣體流動到該製程腔室中；以及使該氧化矽膜與該第三製程氣體反應，以在該基板上形成氮氧化矽膜。
  7. 如申請專利範圍第6項之在基板上形成介電膜之方法，其中將包含NO氣體之該第三製程氣體在該製程腔室外面添加到該第一製程氣體。
  8. 如申請專利範圍第6項之在基板上形成介電膜之方法，更包含在流動該第一製程氣體與該第二製程氣體時將第一稀釋氣體流動到該製程腔室中，以控制該氧化矽膜之生長速率；以及在流動該第三製程氣體時將第二稀釋氣體流動到該製程腔室中，以控制氮結合到該氧化矽膜。
  9. 如申請專利範圍第6項之在基板上形成介電膜之方法，更包含在形成該氮氧化矽膜後，在熱處理氣體中熱處理其上有該氮氧化矽膜之該基板，該熱處理氣體包含氮氣(N2 )、一氧化氮(NO)、一氧化二氮(N2 O)、氧氣(O2 )、或水(H2 O)、或其混合物之至少一者。
  10. 如申請專利範圍第9項之在基板上形成介電膜之方法，其中該熱處理係執行於高於該沉積溫度之溫度下。
  11. 如申請專利範圍第6項之在基板上形成介電膜之方法，其中該氮氧化矽膜具有比該氧化矽膜更低之介面陷阱密度(Dit )。
  12. 一種在基板上形成介電膜之方法，該方法包含：將數個基板安置在製程腔室中；將該製程腔室加熱至400℃與少於650℃間之沉積溫度；將包含水蒸氣之第一製程氣體流動到該製程腔室中，其中藉由燃燒氫氣(H2 )與氧氣(O2 )以在該製程腔室外面產生該水蒸氣；將包含二氯矽烷(DCS)之第二製程氣體流動到該製程腔室中；在該製程腔室中建立少於2Torr之氣體壓力；使該第一與該第二製程氣體反應，以藉由非電漿化學氣相沉 積，在該數個基板上熱沉積氧化矽膜；以及在形成該氧化矽膜後，在熱處理氣體中熱處理其上有該氧化矽膜之該基板，該熱處理氣體包含氮氣(N2 )、一氧化氮(NO)、一氧化二氮(N2 O)、氧氣(O2 )、或水(H2 O)、或其混合物之至少一者，其中該熱處理係執行於高於該沉積溫度之溫度下。
  13. 如申請專利範圍第12項之在基板上形成介電膜之方法，更包含在流動該第一製程氣體與該第二製程氣體時將第一稀釋氣體流動到該製程腔室中，以控制該氧化矽膜之生長速率。
  14. 一種在基板上形成介電膜之方法，該方法包含：將數個基板安置在製程腔室中；將該製程腔室加熱至400℃與少於650℃間之沉積溫度；將包含水蒸氣之第一製程氣體流動到該製程腔室中；將包含二氯矽烷(DCS)之第二製程氣體流動到該製程腔室中；將包含一氧化氮(NO)之第三製程氣體流動到該製程腔室中；在該製程腔室中建立少於2Torr之氣體壓力；使該第一、該第二、與該第三製程氣體反應，以在該數個基板上熱沉積氮氧化矽膜；以及在形成該氮氧化矽膜後，在熱處理氣體中熱處理其上有該氮氧化矽膜之該基板，該熱處理氣體包含氮氣(N2 )、一氧化氮(NO)、一氧化二氮(N2 O)、氧氣(O2 )、或水(H2 O)、或其混合物之至少一者。
  15. 如申請專利範圍第14項之在基板上形成介電膜之方法，其中該熱處理係執行於高於該沉積溫度之溫度下。
  16. 如申請專利範圍第14項之在基板上形成介電膜之方法，更包含藉由燃燒氫氣(H2 )與氧氣(O2 )以在該製程腔室外面產生該水蒸氣。
TW100134827A 2010-09-30 2011-09-27 藉由化學氣相沉積之低溫介電膜形成 TWI464802B (zh)

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