TWI427781B - 具有奈米線結構光偵測器之主動像素感測器 - Google Patents

具有奈米線結構光偵測器之主動像素感測器 Download PDF

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TWI427781B
TWI427781B TW099142973A TW99142973A TWI427781B TW I427781 B TWI427781 B TW I427781B TW 099142973 A TW099142973 A TW 099142973A TW 99142973 A TW99142973 A TW 99142973A TW I427781 B TWI427781 B TW I427781B
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nanowire
substrate
photodiode
pixel
nanowires
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TW201138084A (en
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Young-June Yu
Munib Wober
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Zena Technologies Inc
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Description

具有奈米線結構光偵測器之主動像素感測器
本發明一般而言係關於半導體成像裝置之領域，該等半導體成像裝置可係使用標準CMOS製程加一奈米線製作製程而製作的。
本申請案係關於　　　　　　　 提出申請、代理人檔案號碼為095035-0381955、標題為「NANOWIRE CORE-SHELL LIGHT PIPES」之美國申請案號　　　　　　　 ，該申請案以全文引用之方式併入本文中。
實施於互補金屬氧化物半導體(CMOS)中之成像裝置係眾所周知且與CCD影像感測器一起廣泛地使用。CMOS成像裝置具有若干優點：(1)其等可降低成本及電力消耗、(2)其等易於製造，從而採用所開發之高標準化製程來大量生產消費者積體電路(IC)(包含記憶體晶片及微處理器以及其他數位及類比IC)及(3)其等將多個功能整合於一單個晶片上，從而允許按比例縮小裝置之大小及電力消耗。CMOS成像裝置亦允許採用藉由新發展CMOS製程所提供之較小幾何形狀製程。
成像裝置通常係由包含光偵測裝置及支援電路之像素之列及行形成。該等光偵測裝置通常包含光電二極體、光導體及光電容器，其中之每一者可產生與照射於光偵測器上之光子成比例之光電荷。一CMOS像素通常包含一光電二極體及將光電荷轉換成電壓信號以供像素輸出之三個或四個電晶體。
通常，像素陣列中之一個或多個光偵測器僅接收落到整個像素區域上之光通量之一分率。此乃因該像素包含阻擋傳入光且通常不用作一光偵測器之支援電路。光偵測器區域與像素區域之百分比通常稱為光學填充因數。通常，一小像素之填充因數小於30%。此意指像素中之一個或多個光偵測器偵測由像素接收之光能量之小於30%。
通常將需要額外製作處理之一微透鏡系統放置於像素陣列中之每一像素上方以藉由使光束聚焦於光偵測器上來增強填充因數。此方法通常因製作要求而需要每一微透鏡之間的(通常)0.7微米之一間隙。對於約為2微米×2微米之一小像素，該微透鏡具有一圓形形狀，其具有約1.3微米之一直徑。在此情形下，一微透鏡僅能夠覆蓋像素區域之約33%。因此，藉由使用一微透鏡增強填充因數對於小CMOS像素情形而言係可忽略地小。
此外，光需要透過多個厚電介質層直至其一直到達光偵測器之表面。(圖1)。在毗鄰層之間的每一界面處，某些光因折射率變化及存在一界面而被反射。此外，光能量在傳輸穿過該等厚層期間被損失。此光傳輸損失與層之數目及層之厚度成比例。此外，因CMOS製作要求而形成多個電介質層。最新CMOS製程通常採用5至6個金屬層來進行影像感測器製作。此導致在每一電介質層及金屬層係厚約1.0微米時沈積5微米至6微米厚電介質層。此外，在光偵測器之頂部上，當不存在金屬層時，用一平坦化層塗佈該等電介質層以用於平坦化表面層。
因此，因傳輸損失而造成之光能量損失可變得顯著。另外，當像素大小係小至2.0微米×2.0微米或甚至更小時，光偵測器上方之金屬層之窗開口之高度與大小之縱橫比大於6。在此情形下，當光係以除垂直於成像平面以外之一角度入射時，光束被金屬層阻擋。若採用一微透鏡，則該縱橫比變得甚至更高且導致一更壞光陰影效應。隨著像素大小變小，此光陰影變得更壞。因此，嚴重減少像素信號，從而導致一不可接受之信號雜訊比SNR。
因此，需要藉由引入一新類型之像素架構來克服此等問題。較佳地，為便於製造及電子器件整合，該新架構應係CMOS相容。
一般而言，本發明之實施例組合主動像素電路與奈米線光偵測器以形成具有一奈米線結構光偵測器之一主動像素感測器(APS)。一主動元件係具有電控制電子及/或電洞流動(電控制電或光，或反之亦然)之能力之任一類型之電路組件。不能夠憑藉另一電信號控制電流之組件稱作被動元件。電阻器、電容器、電感器、變壓器及二極體皆被視為被動元件。在本文中所揭示之實施例中，主動元件包含(但不限於)一主動波導、電晶體、矽控整流器(SCR)、發光二極體及光電二極體。一波導係經設計以沿由其實體邊界判定之一方向侷限及引導選擇性波長之電磁輻射之一系統或材料。較佳地，該選擇性波長係該波導之直徑之一函數。一主動波導係具有電控制電子及/或電洞流動(電控制電或光，或反之亦然)之能力之一波導。舉例而言，該主動波導之此能力係可將該主動波導視為係「主動」且屬於一主動元件類之一個原因。
根據本發明之一例示性實施例，採用一工業標準CMOS製程形成一成像裝置作為一單體式CMOS積體電路。此實施例包含具有一像素陣列之一聚焦平面，該等像素中之每一者皆包含一主動像素讀出電路。該主動像素讀出電路可包含一放大場效電晶體(FET)、一重設FET、一輸出切換FET及一轉移閘極，轉移閘極係用於將電荷自光偵測器轉移至該放大FET之一切換FET。此實施例通常包括一像素中之四個FET，其形成為4-T組態。在其他實施例中，該像素讀出電路藉由移除該轉移閘極而包括3-T組態。除讀出電路之外，每一像素通常包含一光偵測器，其形成為一極窄及長圓柱形形狀半導體條棒(亦即，一奈米線)。
根據另一實施例，一額外轉移閘極係形成為操作地連接至該奈米線結構光偵測器以使得產生於該奈米線中之光電荷可與產生於體光電二極體中之光電荷分離。
根據一系列另外實施例，奈米線結構光偵測器形成為呈諸多變化形式之二極體，包含：一p摻雜奈米線、一n摻雜奈米線、一軸向p-n二極體、一軸向p-i-n二極體、一同軸p-n二極體、一同軸p-i-n二極體、在基板之背側處之一p摻雜奈米線及在基板之背側處之具有p+摻雜外殼之一p摻雜奈米線。
一實施例係關於一種裝置，該裝置包括：一基板；一奈米線光偵測器，其位於該基板上，奈米線光電二極體包括具有一表面及一核心之一奈米線，其中該奈米線之軸向方向垂直於該基板；及一主動像素讀出電路，其位於該基板中。在一項態樣中，該奈米線光偵測器包括一光導體、一光電二極體或一光閘極。在另一態樣中，該裝置進一步包括環繞該奈米線光電二極體之至少一個垂直光閘極。在另一態樣中，該垂直光閘極經組態以電鈍化該奈米線之表面，從而抑制暗電流。在另一態樣中，光載子壽命係相對於一未鈍化之奈米線光電二極體增加。
在另一態樣中，該裝置相對於一未鈍化之奈米線光電二極體具有較大量子效率。在另一態樣中，該奈米線包括一n型半導體。在另一態樣中，施加至該奈米線之一負偏壓致使該奈米線中之電荷載子空乏。在另一態樣中，該奈米線包括一p型半導體。在另一態樣中，施加至該奈米線之一正偏壓致使該奈米線中之電荷載子空乏。在另一態樣中，該主動像素讀出電路包括呈3-T組態之三個電晶體。在另一態樣中，該主動像素讀出電路包括呈4-T組態之四個電晶體。
在另一態樣中，該裝置進一步包括以操作方式附接至該奈米線之一微透鏡耦合器。在另一態樣中，該微透鏡耦合器係球形球透鏡或二元微透鏡。在另一態樣中，高於一臨限值之負偏壓之一增加使奈米線之表面反轉。在另一態樣中，高於一臨限值之負偏壓之增加使奈米線之表面及核心之移動電荷空乏。在另一態樣中，該裝置進一步包括在該光閘極與該奈米線之間的一電介質包覆層。在另一態樣中，該電介質包覆層之厚度沿奈米線在軸向方向上變化。在另一態樣中，該裝置3進一步包括一基板光電二極體。在另一態樣中，該奈米線位於基板之一第一側上且該基板光電二極體位於基板之一第二側上。在另一態樣中，該奈米線與該基板光電二極體位於基板之同一側上。
一實施例係關於一種裝置，其包括一像素陣列，該等像素包括：一基板；一奈米線光偵測器，其位於該基板上，奈米線光電二極體包括具有一表面及一核心之一奈米線，其中該奈米線之軸向方向垂直於該基板；及一主動像素讀出電路，其位於該基板中。在一項態樣中，該裝置包括一單體式CMOS電路。
現將參考所附示意圖、僅以實例之方式揭示本發明之實施例，該等圖中，對應參考符號指示對應部件。
在以下詳細說明中，參考形成本發明之一部分之附圖。在圖式中，除非上下文另有規定，否則相同符號通常識別相同組件。在詳細說明、圖式及申請專利範圍中所闡述之圖解說明性實施例並非意在限制本發明。在不背離本文所呈現標的物之精神或範疇之情況下可利用其他實施例且可做出其他改變。
以下之表中概括圖中所圖解說明之元件之符號。下文更詳細地闡述該等元件。
術語奈米線係指具有約為數奈米(舉例而言，幾百奈米或更少)之一厚度或直徑及一不受約束之長度之一結構。奈米線可包含金屬(例如，Ni、Pt、Au)、半導電(例如，Si、InP、GaN等)及絕緣(例如，SiO2 ，TiO2 )材料。奈米線可展現100或更大之縱橫比(長度與寬度比)。因此，其等可稱為1維材料。奈米線可具有在塊狀或3維(3-D)材料中看不到之諸多引起關注之性質。此乃因奈米線中之電子可橫向地受量子侷限且因此佔用可不同於在塊狀材料中所發現之傳統連續能級或能帶之能級。因此，奈米線可具有電及光學傳導之離散值。
該奈米線係自基板豎立(垂直於基板)及伸出。該豎立奈米線可係在基板之前側上或在基板之背側處。本文中實施例之基板通常具有電子組件及奈米線光電二極體。在前側奈米線結構中，該豎立奈米線係在基板之使該等電子組件位於其中之同一側上，而在背側奈米線結構中，該豎立奈米線係位於基板之與其中使該等電子組件位於基板中或基板上之側相反之側上。
可藉由使用不同材料分別形成CMOS像素及奈米線。舉例而言，可使用矽來製作一CMOS影像裝置。然而，可藉由使用III-V族或II-VI族材料(例如，GaAS、GaN、GaP、InP、InN、InAs、CdTe、CdSe、ZnS、ZnSe等)來在所製作之CMOS裝置上形成奈米線。
一轉移閘極係用於一像素中之一開關之一電晶體。該轉移閘極之作用係將電荷自一裝置之一個側轉移至另一側。在某些實施例中，該轉移閘極用以將電荷自光電二極體轉移至感測節點(或浮動擴散部)。一重設閘極係用於重設一裝置之一閘極開關。在某些實施例中，該裝置係由一n+區形成之感測節點。重設意指恢復至藉由某一電壓設定之原始電壓位準。在某些實施例中，重設汲極(RD)之電壓係用作一重設位準之電壓。
一釘紮光電二極體係包含不具有一電壓變化之一狀態之一光電二極體。一習用釘紮光電二極體包含在該光電二極體之主動層之表面處之一經摻雜釘紮層，其使該光電二極體中之移動電荷空乏。該釘紮層通常將該光電二極體之主動層之表面之電位釘紮至基板之電位(通常係接地位準或零伏特)。以此方式，該釘紮層減少來自該光電二極體之主動層之表面之暗電流。
在某些實施例中，使用氣-液-固(VLS)生長方法來生長矽奈米線(SiNW)。在此方法中，一金屬熔滴催化含Si之源氣體分解。來自該氣體之矽原子溶解成形成一共晶液體之熔滴。該共晶液體用作Si儲槽。隨著更多矽原子進入至溶液中，該共晶液體變成矽過飽和，從而最終造成Si原子之沈澱。通常，Si自該滴之底部沈澱出，從而在金屬催化劑滴在頂部上之情況下導致矽奈米線之由底向上生長。
在某些實施例中，將金用作用於生長矽奈米線之金屬催化劑。然而，可使用其他金屬，包含但不限於Al、GA、In、Pt、Pd、Cu、Ni、Ag及其組合。可使用諸如濺鍍、化學氣相沈積(CVD)、電漿增強型化學氣相沈積(PECVD)、蒸鍍等習用CMOS技術來將固態金沈積及圖案化於矽晶圓上。舉例而言，可憑藉光學微影、電子束微影或任一其他適合技術來執行圖案化。然後，可加熱該矽晶圓，從而致使金在該矽晶圓上形成熔滴。矽及金形成具有363℃之一熔化溫度之19%Au之一共晶。亦即，Si-Au共晶體之一液滴在363℃(適合於處理矽裝置之一適中溫度)下形成。
在某些實施例中，基板具有一(111)定向。然而，亦可使用其他定向，包含但不限於(100)。用於奈米線產生之一常見矽源氣體係SiH4 。然而，可使用其他氣體，包含但不限於SiCl4 。在某些實施例中，舉例而言，可在80毫托至400毫托之壓力及450℃至600℃之範圍內之溫度下用SiH4 來進行奈米線生長。在某些實施例中，溫度係在470至540℃之一範圍內。通常，SiH4 之較低分壓力導致產生垂直奈米線(NW)之一較高百分比。舉例而言，在80毫托分壓力及470℃下，矽奈米線之高達60%沿垂直<111>方向生長。在某些實施例中，可生長基本上圓環形之奈米線。在其他實施例中，奈米線係六邊形。
在一項實施例中，奈米線生長係在一熱壁低壓CVD反應器中進行。在憑藉丙酮及異丙醇清潔Si基板之後，可將樣品浸入一緩衝HF溶液中以移除任何自然氧化物。可藉由熱蒸鍍來將接連之薄Ga及Au金屬層(標稱厚1奈米至4奈米)沈積於基板上。通常，Ga層係在Au層之前沈積。在一實施例中，在將CVD室抽空降至約10-7 托之後，可在真空中將該等基板加熱高達600℃以形成金屬熔滴。舉例而言，可使用100 sccm之SiH4 流(He混合物中之2%)在自500℃至700℃之一溫度範圍內在3毫巴之一總壓力下生長矽奈米線。
憑藉Au-Ga催化劑生長之矽奈米線之大小及長度係相對同質的，其中大多數該等線沿四個<111>方向定向。為進行比較，憑藉一純Au催化劑生長之矽奈米線成核且生長有更隨機散佈之奈米線之長度及直徑。此外，憑藉Au-Ga催化劑生長之奈米線往往具有沿軸向方向之一錐形。生長達一長時間之奈米線之尖端直徑係與生長達一短時間之彼等奈米線之尖端直徑相同且由催化劑直徑判定。然而，奈米線之佔用面積往往在生長過程期間增加。此指示奈米線漸細主要係由矽之側壁沈積(徑向生長)所造成。奈米線可經生長而在底部(基底)處具有1500奈米之一直徑，而尖端之直徑可在15微米之一長度上小於70奈米。此外，奈米線直徑係生長溫度之一函數。較高生長溫度導致具有較小直徑之奈米線。舉例而言，憑藉Ga/Au催化劑在600℃下生長之奈米線之平均直徑係約60奈米，但對於500℃下之生長而言，平均直徑減小降至約30奈米。另外，直徑之變化往往隨降低沈積溫度而變窄。
使用VLS製程，可生長垂直奈米線。亦即，基本上垂直於基板表面之奈米線。通常，並非所有奈米線皆將係完全地垂直。亦即，奈米線可以除90度之外的一角度傾斜於該表面。通常觀測傾斜之奈米線包含(但不限於)三個70.5°-斜向<111>磊晶生長方向及旋轉60°之三個額外70.5°-斜向方向。
除生長垂直奈米線之外，該VLS製程亦可用以生長經摻雜之奈米線。實際上，藉由改變源氣體之組合物，可產生生長線之一摻雜分佈。舉例而言，奈米線可係藉由將乙硼烷(B2 H2 )或三甲基硼烷(TMB)添加至源氣體而製成為p型。亦可使用將受體原子添加至矽奈米線之其他氣體。奈米線可係藉由將PH3 或AsH3 添加至源氣體而製成為n型。亦可使用將供體原子施加至矽奈米線之其他氣體。可產生之摻雜分佈包含(但不限於)n-p-n、p-n-p及p-i-n。
另外，可使用其他方法或VLS方法之變化形式來生長奈米線。其他方法或變化形式包含(但不限於)(1)CVD、(2)反應性氛圍、(3)蒸鍍、(4)分子束磊晶(MBE)、(5)雷射燒蝕及(6)溶液方法。在CVD製程中，提供一揮發性氣態矽前體。實例性矽前體氣體包含SiH4 及SiCl4 。CVD可用於磊晶生長。此外，可藉由將揮發性摻雜前體添加至矽前體來達成摻雜。在反應性氛圍中退火包括在與基板反應之一氣體中加熱基板。舉例而言，若在包含氫之一氛圍中將矽退火，則該氫與矽基板局部地反應，從而形成SiH4 。然後，SiH4 可與催化劑金屬滴反應，藉此起始奈米線生長。此生長製程可用於非CMOS製程。
在蒸鍍方法中，在導致產生SiO氣體之條件下加熱SiO2 源。當SiO氣體吸收於金屬催化劑熔滴上時，其形成Si及SiO2 。亦可在不具有一金屬催化劑滴之情況下執行此方法，不存在一金屬催化劑，觀測到SiO2 催化矽奈米線生長。在MBE方法中，加熱一高純度矽源直至Si原子蒸鍍。朝向該基板引導一氣態Si束。該氣態矽原子吸收至金屬熔滴上且溶解成金屬熔滴，藉此起始奈米線之生長。
在雷射燒蝕方法中，一雷射束瞄準包含矽及催化劑原子兩者之源。經燒蝕之原子藉由與惰性氣體分子衝突而冷卻及凝結以形成具有與原始目標相同組合物之熔滴。亦即，具有矽及催化劑原子兩者之熔滴。亦可憑藉基本上由純矽組成之目標來執行該雷射燒蝕方法。基於溶液之技術通常使用有機液體。具體而言，該等有機液體通常包括富含有矽源及催化劑顆粒之高壓超臨界有機液體。在高於金屬-矽共晶之一反應溫度下，該矽前體分解，從而形成具有該金屬之一合金。在超飽和之後，矽沈澱出來，從而生長奈米線。
以上奈米線生長技術皆係由底向上技術。然而，亦可憑藉由頂向下技術來製作奈米線。由頂向下技術通常涉及圖案化及蝕刻一適合基板，舉例而言，矽。可經由微影(舉例而言，電子束微影、奈米球微影及奈米印刷微影)來達成圖案化。可執行乾式或濕式蝕刻。乾式蝕刻技術包含(但不限於)反應性離子蝕刻。可憑藉標準蝕刻或經由金屬輔助之蝕刻製程來執行濕式蝕刻。在金屬輔助之蝕刻製程中，濕式化學蝕刻Si，其中藉由存在作為一鹽添加至蝕刻溶液之一貴金屬來催化該Si溶解反應。
一奈米線吸收某一選擇性帶寬之光能量，此取決於該奈米線之尺寸及該奈米線之設計參數(諸如，一直徑、長度及其核心及包覆層之折射率)。未吸收之光能量如在一波導中一樣沿奈米線行進。藉由使用此等特性，該奈米線可用作一成像裝置中之一色彩選擇性濾光器裝置。此外，奈米線結構光偵測器可建構為一色彩敏感性光感測器。藉由延伸此特徵，可形成一色彩資訊蒐集像素陣列。
圖2展示形成於一成像裝置中之諸多此等單元之一聚焦平面陣列之一個像素之一經簡化剖視圖。每一像素包含形成於一半導體基板101上之一讀出電路100與在該基板上面之若干金屬線103。作為一光敏元件，一奈米線結構光偵測器102係形成為自該基板豎立。光吸收沿奈米線結構光偵測器102發生。奈米線結構光偵測器102之輸出端可連接至位於基板中之讀出電路100。由於奈米線結構光偵測器102之佔用面積較小，因此可在一像素中形成一個以上奈米線結構光偵測器102。奈米線結構光偵測器102之長垂直結構之作用係吸收某一帶寬之光能量且產生一對應電信號及/或在具有最小損失之情況下將未吸收之光能量導引至基板二極體，因此執行為一波導。在奈米線之頂部處，可形成一光學耦合器(例如，一透鏡)105以在具有最小能量損失或反射之情況下將入射光耦合至奈米線。在此實施例中，一微透鏡可用作一耦合器。該微透鏡可係，但不限於一球形球透鏡。一球形球透鏡之耦合效率通常高於90%。在另一態樣中，如圖2b中所示，可使用二元微透鏡。
圖3展示在一經薄化半導體基板之背側處具有一奈米線結構光偵測器之一像素之一經簡化剖視圖。奈米線109藉由吸收某一帶寬之光能量來產生光電荷且將電荷轉儲至經薄化基板中。然後，由讀出電路100使用一電場將電荷收集於經薄化基板中。此外，奈米線將未吸收之光導引且耦合至基板108中。在基板108之背側處採用一奈米線結構光偵測器之一優點係易於製作奈米線。當在前側處形成奈米線時，必需移除其中認為應該建構奈米線之一區中之圖2中所圖解說明之厚電介質層104。相比之下，可在無此移除步驟之情況下製成圖3中所揭示之實施例。此外，可在不修改CMOS裝置之前側結構之情況下製作奈米線。此實施例包含前側金屬及絕緣層106及背側金屬及絕緣層107兩者。此外，如在前側實施例中，可將一光學耦合器105之一微透鏡耦合至奈米線109。
一奈米線結構半導體可組態為各種光偵測器組態。此等組態包含：一光導體、一光電二極體或一光閘極裝置。一光導體係其電阻率依據入射光改變之一光敏裝置。一光電二極體係產生電子-電洞對作為一光電荷之一p-n二極體或一p-i-n二極體。一光閘極裝置係具有一受偏壓閘極之一MOS(金屬氧化物半導體)裝置，該偏壓閘極在該半導體中形成一電位井且在該電位井中累積光電荷。在以下實施例中，將光電二極體、光閘極裝置或一光電二極體與一光閘極偵測器之組合之各種組態實施為光偵測元件。
圖4展示具有一奈米線結構光閘極裝置之一CMOS像素之一剖視圖。在此實施例中，存在每像素兩個光偵測器、一奈米線(NW)光閘極偵測器及一基板二極體。奈米線由具有一電介質包覆層及一垂直閘極之一n型半導體形成。環繞奈米線之垂直閘極之作用係藉由將一微小負偏壓電壓施加至奈米線光閘極來使奈米線空乏且在奈米線核心處形成一電位井，如圖5b中所示。進一步增加負偏壓電壓將使奈米線之表面區反轉至p+，此乃因電洞因負光閘極偏壓而在該表面區中累積。然而，因此在無雜質摻雜之情況下奈米線類似於一釘紮光電二極體地起作用。對於一p型奈米線，可施加一正偏壓電壓以使該奈米線空乏。在一純質奈米線之情形下，不需要一光閘極偏壓以供空乏。然而，可施加一負偏壓以產生一表面釘紮效應。
環繞該奈米線結構光偵測器之一垂直光閘極可產生數個益處。眾所周知，一半導體(包含矽)之表面因界面原子之懸掛鍵而具有缺陷。此等缺陷形成一半導體中之能帶間隙內之缺陷狀態且經由熱產生製程導致洩漏或暗電流。在無光閘極偏壓之情況下，奈米線可具有自其表面區產生之一極大暗電流。此乃因奈米線之表面體積比與一習用基板裝置相比係極大。因此，一光閘極偏壓電壓可藉由電鈍化奈米線表面來幫助抑制暗電流。亦可藉由化學地處理奈米線之表面以移除所有懸掛鍵來鈍化奈米線之表面。舉例而言，可藉由使用諸如LaAlO3 、GdScO3 、LaScO3 等材料之一極薄層之原子層沈積(ALD)來針對矽奈米線實施此一方法。另一選擇係，可經由使用MOCVD或濺鍍來用HfO2 化學地處理該表面。
可由奈米線表面引起之另一問題係光產生之載子可因在奈米線表面處之缺陷狀態下發生之重組製程而具有一短壽命。因此，藉由將偏壓電壓施加至環繞光閘極來鈍化奈米線表面係有益的，此乃因其幫助減少暗電流且增強光載子壽命，從而導致較佳量子效率。
奈米線核心之電位沿奈米線之軸向方向C1-C2不係恆定的。此乃因奈米線之頂部端係開放的且最受負閘極偏壓影響，而奈米線之底部端連接至在重設期間具有正偏壓電壓且在重設之後保持該偏壓之N-井。因此，越接近於該奈米線之頂部，該偏壓越具負性。越接近於奈米線之底部，奈米線中所創建之偏壓越具正性。因此，沿奈米線之軸向方向創建一電位梯度，如圖6中所示。此梯度致使產生於奈米線中之光電荷漂移至基板二極體中之電位井中。
在另一態樣中，使用一p型奈米線。在此態樣中，可將一正偏壓電壓施加至環繞奈米線之光閘極，如圖5c中所示。在此情形下，在一微小正光閘極偏壓下p型奈米線之表面變成被空乏。進一步增加光閘極偏壓將空乏奈米線之整個區，亦即，自表面至奈米線之核心。圖5d中展示針對奈米線之此態樣之一電位分佈。
在基板中，可在p型基板與n-井區之間形成一p-n接面二極體。一p+層覆蓋除奈米線接面以外之n-井表面。此p+形狀允許接收來自奈米線之光電荷且抑制歸因於基板之表面狀態之暗電流。由於行進穿過奈米線之光可照明基板二極體，因此電荷產生於基板二極體中且收集於電位井中。因此，電位井收集來自奈米線及基板二極體兩者之電荷。與僅利用入射光子之一分率之習用CMOS像素相比，此實施例可藉由利用大多數入射光子來增強量子效率。
基板光電二極體之n-井經輕摻雜以使得n區可在一低偏壓電壓之情況下而容易地空乏。對於在接通轉移閘極時自基板二極體至感測節點之一完全電荷轉移而言，空乏之n-井係最佳。類似於CCD裝置，完全電荷轉移允許光電荷之一低雜訊讀出。
感測節點係用基板中之n+擴散部形成。感測節點連接至一放大電晶體，例如，組態為一源極隨耦器電晶體之一電晶體。一選擇開關電晶體可用以控制放大器輸出至一輸出節點之連接。一重設電晶體亦可連接至感測節點以使得當啟動重設閘極時加偏壓於感測節點至VDD。當啟動轉移閘極時，n-井電連接至感測節點。然後，n-井變為受正偏壓且在n-井電位與垂直光閘極偏壓電壓之間創建奈米線中之一電位梯度。對於一給定負光閘極偏壓電壓，可藉由分別逐漸或逐階梯改變電介質包覆層之厚度來獲得沿軸向方向之另外電位梯度，如圖7a及圖7b中所示。由於跨越電介質層之電位下降與層之厚度成比例，因此奈米線之電位沿軸向方向逐漸改變。此電位梯度有利於高效收集光產生之載子及增強載子壽命。此乃因軸向電場幫助自奈米線區移除熱產生之載子且因此降低電子-電洞重組機率。
在另一態樣中，使用一p型奈米線。對於一給定正光閘極偏壓電壓，可藉由分別逐漸或逐階梯改變包覆層之厚度來創建沿軸向奈米線方向之一電位梯度，如圖7c及圖7d中所示。
圖8展示其中用一n+磊晶層塗佈p摻雜奈米線以形成一p-n接面之雙光電二極體結構之一剖視圖。在一替代實施例(圖中未展示)中，奈米線可係經摻雜且該包覆層可係一磊晶p+層以形成一p-n接面。
在圖8中，存在每像素兩個光電二極體、一個光電二極體係一奈米線二極體且另一個光電二極體係一基板二極體。奈米線光電二極體係用一p、n或純質型半導體形成。一n+層覆蓋奈米線表面，從而形成一p-n二極體或一p-i-n二極體。在基板中，一n-二極體經輕摻雜以使得n-區可在一低偏壓電壓之情況下而容易地空乏。光電荷係同時地但於分開電位井中整合於光電二極體之兩者中。此乃因該等光電二極體由一p+層分離以避免兩個光電二極體之間的相互作用。在此實施例中，存在兩個分離之讀出電路。用於奈米線之讀出電路具有3-T組態，例如，一重設電晶體、一源極隨耦器放大器及一選擇開關(圖8中未展示)。用於基板二極體之第二讀出電路係基於4-T組態，例如，一轉移閘極、一重設電晶體、一源極隨耦器電晶體及一選擇開關。亦可藉由移除轉移閘極來用3-T組態替換該4-T組態。此等兩個光電二極體可用以收集由不同波長之輻射所形成之電荷。
圖9展示具有一奈米線結構光閘極偵測器之一CMOS像素之一實施例。此實施例包含在奈米線周圍之兩個垂直光閘極(VP閘極1、VP閘極2)、一基板光電二極體及一讀出電路。該讀出電路包含一轉移閘極(TX)、一重設閘極(RG)、一源極隨耦器電晶體及一像素選擇開關。為簡化起見，圖9中之緩衝器放大器表示源極隨耦器電晶體及像素選擇開關。在此實施例中，用一n型(亦即，輕摻雜n型)或一純質半導體形成一豎立奈米線以使得奈米線可在來自VP閘極1之一低負偏壓電壓之情況下而容易地空乏。較佳地，來自垂直光閘極VP閘極1之一負偏壓電壓可致使在奈米線之表面處累積電洞以抑制歸因於奈米線之表面狀態之暗電流，如圖5b中所圖解說明。
第二垂直光閘極VP閘極2可係一接通/關斷開關。此開關可經組態以分離產生於奈米線中之光電荷與整合於基板光電二極體中之光電荷。光電荷係同時整合於奈米線光電二極體與基板光電二極體兩者中。然而，該等光電荷係整合於分開電位井中，此乃因第二光閘極VP閘極-2之關斷狀態在該奈米線光電二極體與該基板光電二極體之間形成一電位障壁。以此方式，來自奈米線光電二極體及基板光電二極體之信號不混合在一起。此等兩個光電二極體可用以收集由不同波長之輻射所形成之電荷。
此實施例中所實施之垂直光閘極允許能夠在不使用一複雜離子植入製程之情況下容易地修改奈米線中之電位分佈。習用光閘極像素遭受極不良量子效率及不良藍色回應。習用光閘極通常係由覆蓋基板之頂部表面且吸收接近於藍色光之短波長之多晶矽製成，因此減少到達光電二極體之藍色光。相比之下，垂直光閘極不阻擋光路徑。此乃因垂直光閘極不橫向地橫跨光電二極體以控制半導體中之電位分佈。
另外，隨著影像感測器之像素大小按比例縮小，該影像感測器之孔徑大小變得與波長相當。對於一習用平面類型光電二極體，此導致不良量子效率(QE)。然而，一垂直光閘極結構與一奈米線感測器之組合允許具有良好QE之一超小像素。
本實施例之奈米線光感測器使用兩步驟製程以在奈米線光電二極體與基板光電二極體之間分開地讀出信號。在第一步驟中，讀出基板光電二極體中之信號電荷。然後，使該基板中之n-區空乏。在第二步驟中，可首先接通第二光閘極VP閘極2。接下來，讀出奈米線中之信號電荷。
此實施例之一裝置可以一「快照」操作來操作。在一「快照」操作中，較佳同時接通或關斷像素陣列中之所有光閘極VP閘極2。對於轉移閘極TX，同樣可較佳同時接通或關斷所有轉移閘極TX。為達成此，所有第二光閘極VP閘極2皆係與一全域連接相連接。此外，所有轉移閘極TX皆係與一第二全域連接相連接。
通常，應出於實際原因而避免重設閘極RG之全域操作。在一像素陣列中，逐列全域地重設該陣列係一常見實踐。若不使用快照操作，則個別像素操作係可能。在此情形下，不必具有全域連接。
圖10及圖11展示具有奈米線結構p-i-n光電二極體及在奈米線周圍之垂直光閘極之CMOS主動像素之實施例。在一項實施例中，一奈米線可經組態以藉由在每一端分別具有p+及n-而具有一軸向型p-i-n光電二極體。在另一實施例中，一奈米線可具有如圖11中所示之一同軸型p-i-n組態。除p-i-n組態之外，一奈米線還可具有包括諸如導電層及金屬層等磊晶生長層之一個或多個垂直光閘極。
在諸如圖10中所示實施例之一項實施例中，像素可包含兩個光電二極體(一奈米線光電二極體及一基板光電二極體)。此實施例亦包含兩個垂直光閘極(VP閘極1、VP閘極2)、一轉移閘極(TX)及一重設閘極(RG)。較佳地，光電二極體中之兩者皆係輕摻雜。此乃因一輕摻雜區可係在一低偏壓電壓下而容易空乏。如所圖解說明，光電二極體中之兩者皆係(n-)。然而，另一選擇係，奈米線像素可經組態以使得光電二極體中之兩者皆係(p-)。
該基板光電二極體之表面區可因製作期間所造成之製程誘致損壞及與該豎立奈米線相關聯之晶格應力而易具有缺陷。此等缺陷可充當暗電流之一源。為抑制n-光電二極體之表面處之暗電流，較佳地，在該基板中之n-光電二極體之頂部上製作一淺p+區。
較佳地，將該基板連接至接地，亦即，零電壓。在此實施例中，該重設汲極較佳係經摻雜n+且係受正偏壓。當轉移閘極TX及重設閘極係接通時，基板中之n-區變為受正偏壓。此重設操作導致n-區因p-基板與n-區之間的反向偏壓條件而變為空乏的。當轉移閘極TX及重設閘極RG係關斷時，n-區保持其正偏壓，從而相對於p-基板(p-sub)區形成一浮動電容器。
第一垂直光閘極VP閘極1可經組態以控制奈米線中之電位以使得可在奈米線光電二極體與基板光電二極體之間形成一電位梯度。以此方式，奈米線中之光電荷可在讀出期間快速地漂移至基板之n-區。第二垂直光閘極VP閘極2可係一接通/關斷開關。
圖12及圖13展示背側照明影像感測器之實施例。奈米線可形成於一p-基板之背側處。可藉由移除含有像素陣列之區域上方之半導體基板材料來使基板薄化。舉例而言，可使一p-基板薄化至3微米與50微米之間(更佳地，6微米與20微米之間)的一厚度。該基板光電二極體現可得到來自背側(而非來自含有所有金屬線(如習用影像感測器中)之側)之其所有光。
前側可包含4-T讀出電路，其包含一轉移閘極TX、具有一重設閘極RG之一重設開關、一源極隨耦器放大器及一選擇開關。讀出電路亦可組態為3-T像素電路，其包含具有一重設閘極RG之一重設開關、一源極隨耦器放大器及一選擇開關。在前側中，一基板光電二極體可係用一淺p+層形成，如圖12及圖13中所示。在基板之兩個側處具有p+之目的係抑制暗電流。可將一隱埋p層放置於n+擴散部層下面以阻擋來自背側之傳入電荷流且使電荷朝向n-區轉向。較佳地，該隱埋p層之摻雜高於該p-基板之摻雜，但不高至該p+層之摻雜。前側光電二極體不係用於光吸收，而用於收集來自奈米線及來自其中發生光吸收之背側p-基板之電荷。奈米線可具有環繞奈米線之一電介質層(包覆層)及兩個垂直光閘極，一垂直光閘極用於開關且另一垂直光閘極用於控制奈米線中之電位。
通常，在圖12及圖13之實施例中，使用兩步驟製程以自該等光電二極體中之每一者分開地讀出信號電荷。第一步驟將係自前側處之基板二極體讀出電荷。緊鄰此後，藉由接通VP閘極1，將讀出來自奈米線之電荷。
較佳地，圖12及圖13之實施例應具有在背側基板處之在中心具有一孔之一淺p+層，以使得該p+層不阻擋來自背側奈米線之電荷。此外，較佳地，在前側處應存在位於該淺p+層下面之一輕摻雜n-井或n-層以使得n-井可係容易空乏的。
圖13展示一背側照明CMOS像素之一替代實施例。在此實施例中，替代針對奈米線具有垂直光閘極，可將p+層塗佈於奈米線之外殼處以幫助在奈米線中形成一內建電場。在此組態之情況下，光電荷可容易地沿向上方向漂移。背側照明CMOS像素之特徵類似於圖12之像素之彼等特徵。
出於圖解說明及說明之目的，已呈現本發明之上述說明。並非意欲窮舉或將本發明限制為所揭示之精確形式，且可根據上文教示做出修改及變化或可根據本發明之實踐來取得修改及變化。該等圖式及說明經挑選以闡釋本發明及其實際應用之原理。意欲使本發明之範疇由本文隨附申請專利範圍及其等效形式界定。
100．．．讀出電路
101．．．半導體基板
102．．．奈米線結構光偵測器
103．．．金屬線
104．．．電介質層
105．．．光學耦合器
106．．．前側金屬及絕緣層
107．．．背側金屬及絕緣層
108．．．基板
109．．．奈米線
圖1圖解說明一先前技術小CMOS像素之一剖視圖。
圖2a圖解說明在前側照明之情況下具有一奈米線結構光偵測器之一像素之一實施例之一經簡化剖視圖。
圖2b圖解說明圖2a中所圖解說明實施例之在奈米線結構光偵測器上具有二元微透鏡之一態樣。
圖3圖解說明在背側照明之情況下具有一奈米線結構光偵測器之一像素之一實施例之經簡化剖視圖。
圖4圖解說明具有具有一奈米線及一垂直光閘極(VPG)之一CMOS像素之一實施例。
圖5a圖解說明具有具有一n型奈米線及一垂直光閘極之一CMOS像素之一實施例。
圖5b圖解說明圖5a之實施例之沿線A1-A2之一電位分佈。
圖5c圖解說明具有具有一p性奈米線及一垂直光閘極之一CMOS像素之一實施例。
圖5d圖解說明圖5c之實施例之沿線B1-B2之一電位分佈。
圖6圖解說明圖4之實施例之沿線C1-C2之一電位分佈。
圖7a圖解說明具有一負光閘極偏壓及在電介質包覆層之厚度上之一逐漸變化之一實施例。
圖7b圖解說明具有一負光閘極偏壓及在電介質包覆層之厚度上之一逐階梯變化之一實施例。
圖7c圖解說明具有一正光閘極偏壓及在電介質包覆層之厚度上之一逐漸變化之一實施例。
圖7d圖解說明具有一正光閘極偏壓及在電介質包覆層之厚度上之一逐階梯變化之一實施例。
圖8圖解說明具有其中用一n+磊晶層塗佈p摻雜奈米線以形成一p-n接面之雙光電二極體之一實施例之一剖視圖。
圖9圖解說明具有一奈米線結構光閘極偵測器之一CMOS像素之一實施例。
圖10圖解說明具有奈米線結構p-i-n光電二極體及在奈米線周圍之垂直光閘極之一CMOS主動像素之一實施例。
圖11圖解說明具有奈米線結構p-i-n光電二極體及在奈米線周圍之垂直光閘極之一CMOS主動像素之另一實施例。
圖12圖解說明一背側照明影像感測器之一實施例。
圖13圖解說明另一背側照明影像感測器之一實施例。
100．．．讀出電路
101．．．半導體基板
102．．．奈米線結構光偵測器
103．．．金屬線
104．．．電介質層
105．．．光學耦合器

Claims (25)

  1. 一種像素感測裝置，其包括：一基板；一奈米線光偵測器，其位於該基板上，該奈米線光偵測器包括具有一表面及一核心之一奈米線，其中該奈米線之軸向方向係與該基板成一角度；一主動像素讀出電路，其位於該基板中；及至少一個垂直光閘極，其環繞該奈米線。
  2. 如請求項1之裝置，其中該奈米線光偵測器包括一光導體或一光電二極體。
  3. 如請求項1之裝置，其中在該垂直光閘極上之一偏壓電壓經組態以電鈍化該奈米線之該表面，從而抑制暗電流。
  4. 如請求項3之裝置，其中光載子壽命係相對於一未鈍化之奈米線光電二極體增加。
  5. 如請求項3之裝置，其中該裝置相對於一未鈍化之奈米線光電二極體具有較大量子效率。
  6. 如請求項1之裝置，其中該奈米線包括一n型半導體。
  7. 如請求項6之裝置，其中施加至該奈米線之一負偏壓致使該奈米線中之電荷載子空乏。
  8. 如請求項1之裝置，其中該奈米線包括一p型半導體。
  9. 如請求項8之裝置，其中施加至該奈米線之一正偏壓致使該奈米線中之電荷載子空乏。
  10. 如請求項1之裝置，其中該主動像素讀出電路包括呈3-T 組態之三個電晶體。
  11. 如請求項1之裝置，其中該主動像素讀出電路包括呈4-T組態之四個電晶體。
  12. 如請求項1之裝置，其進一步包括以操作方式附接至該奈米線之一微透鏡耦合器。
  13. 如請求項12之裝置，其中該微透鏡耦合器係一球形球透鏡或二元微透鏡。
  14. 如請求項7之裝置，其中高於一臨限值之該負偏壓之一增加使該奈米線之該表面反轉。
  15. 如請求項9之裝置，其中高於一臨限值之該負偏壓之增加使該奈米線之該表面及該核心之移動電荷空乏。
  16. 如請求項1之裝置，其進一步包括環繞該奈米線的一電介質包覆層。
  17. 如請求項16之裝置，其中該電介質包覆層之厚度沿該奈米線在該軸向方向上變化。
  18. 如請求項1之裝置，其進一步包括一基板光電二極體。
  19. 如請求項18之裝置，其中該奈米線係位於該基板之一第一側上且該基板光電二極體係位於該基板之一第二側上。
  20. 如請求項18之裝置，其中該奈米線及該基板光電二極體兩者係位於該基板之同一側上。
  21. 如請求項1之裝置，其中該奈米線之該軸向方向大致垂直於該基板。
  22. 一種像素感測裝置，其包括： 一像素陣列，該等像素包括：一基板；一奈米線光偵測器，其位於該基板上，該奈米線光偵測器包括具有一表面及一核心之一奈米線，其中該奈米線之軸向方向係與該基板成一角度；一主動像素讀出電路，其位於該基板中；及至少一個垂直光閘極，其環繞該奈米線。
  23. 如請求項22之裝置，其中該裝置包括一單體式CMOS電路。
  24. 如請求項22之裝置，其中該奈米線之該軸向方向大致垂直於該基板。
  25. 如請求項22之裝置，其中存在兩個光偵測器允許收集不同波長之電磁輻射。
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