TWI424543B - 電子元件及其製作方法 - Google Patents

電子元件及其製作方法 Download PDF

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Publication number
TWI424543B
TWI424543B TW100100454A TW100100454A TWI424543B TW I424543 B TWI424543 B TW I424543B TW 100100454 A TW100100454 A TW 100100454A TW 100100454 A TW100100454 A TW 100100454A TW I424543 B TWI424543 B TW I424543B
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Taiwan
Prior art keywords
substrate
conductive
layer
electronic component
recess
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TW100100454A
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English (en)
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TW201203483A (en
Inventor
wen wei Shen
Yao Chun Chuang
Chen Shien Chen
Ming Fa Chen
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Taiwan Semiconductor Mfg
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Publication of TW201203483A publication Critical patent/TW201203483A/zh
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Publication of TWI424543B publication Critical patent/TWI424543B/zh

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Description

電子元件及其製作方法
本發明有關於積體電路，且特別是有關於與半導體晶片一起使用的柱狀結構。
自積體電路問世以來，由於各種電子組件(例如電晶體、二極體、電阻、電容等)的積集度不斷提高，半導體工業已經歷了連續的快速成長。在大多數的情況下，積集度的提高是來自於最小特徵尺寸(minimum feature size)一再地縮小，且最小特徵尺寸的縮小可使更多的組件集成到一給定的面積中。
前述積集度的進步本質上是在二維(two-dimensional，2D)空間上的進步，積體組件所佔據的體積實際上是在半導體晶圓的表面上。雖然微影技術的大幅進步已使得二維積體電路的形成有了很大的進步，然而，在二維空間中能達到的密度仍有其物理限制。其中一個限制是製造這些組件所需的最小尺寸(minimum size)。再者，當將較多的元件置於一晶片中時，會需要更加複雜的設計。
為了要進一步地增加電路密度，已開始研發三維(three-dimensional，3D)積體電路。典型的三維積體電路的製程是接合二個晶片，並於各個晶片以及一基板上的接墊之間形成電性連接結構。舉例來說，一個方法是接合二個晶片的頂部。之後，將堆疊好的晶片接合至一載板，並且打線接合以電性耦接各晶片上的接墊至載板上的接墊。然而，此種方法需要載板面積大於晶片面積，以進行打線接合製程。
近來的目標已集中在覆晶式的互連結構以及以導電球/凸塊作為晶片與其下的基板之間的連接結構，從而允許一較小的封裝體具有高導線密度。在這種情況下，一導電凸塊係形成在一表面上並直接接觸在另一表面上的一柱狀結構或是接墊。然而，在相對的表面上的接點之間時常發生對不準(misalignment)的情形。對不準的情形可能會導致接點之間短路及/或傷害到元件。
再者，材料以及個別的熱膨脹係數(coefficient of thermal expansion，CTE)的差異會在連接區產生應力。應力可能會使接點(joint)破裂及/或導致其他的問題，例如介電層剝離(delamination)的問題。
本發明一實施例提供一種電子元件，包括一第一基板，具有一接點；一凸塊底部金屬結構，電性接觸接點；以及一凹陷的導電柱，位於凸塊底部金屬結構上並電性接觸凸塊底部金屬結構，凹陷的導電柱具有一形成於其中的凹槽，凹槽具有大體上垂直的側壁。
本發明另一實施例提供一種電子元件的製作方法，包括提供一第一基板，第一基板具有一形成於其上的導電接墊；於第一基板上形成一導電柱，導電柱電性接觸導電接墊；以及於導電柱的一頂面中形成一凹槽，以形成一凹陷的導電柱。
為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下。
以下將詳述多個實施例之製作方法與使用方式。然而，值得注意的是，本文將提供許多可供實施的發明概念，其可在多種不同的情況下實施。在此討論的特定實施例僅用以介紹以特定的方法製作與使用所揭露的主題，而非用以限定不同實施例的範圍。
此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一元件位於一第二元件“上”、“之上”、“下”或“之下”時，包括第一元件與第二元件直接接觸或間隔有一或更多其他元件之情形。在圖式中，可能誇大實施例的形狀與厚度以便清楚表現出本發明之特徵。再者，在下文中，將特別描述構成本發明裝置之元件或與之直接相關之元件，而圖中未繪示或描述之元件則可以該技術人士所熟知之各種形式存在。
本說明書的實施例係關於利用凸塊或是銲球(在此統稱為凸塊)使一基板與另一基板互相連接，其中各基板可為積體電路晶片、轉接板(interposer)、封裝基板、印刷電路板、高密度內連線結構及/或其相似物。以下即將討論的實施例係揭露利用一具有一凹槽的柱狀結構。已經發現的是，本發明的實施例(例如在此討論的這些實施例)可減少對不準的問題發生，從而增加產能與可靠度。在此，揭露一柱狀結構的形成方法的中間步驟。這些實施例例如可適用於三維積體電路或是堆疊式晶片結構(stacked die configuration)中。在全部的圖示與說明實施例中，相似之標號將用以標示相似之元件。
第1圖至第5圖繪示本發明一實施例之一具有一柱狀結構的半導體元件的製程的中間步驟，其中柱狀結構具有一形成於其中的凹槽。請參照第1圖，其繪示一實施例之一基板100的局部。基板100可包括例如塊狀矽基板、摻雜或未摻雜的基板、或是絕緣層上半導體基板的主動層。通常，絕緣層上半導體基板包括一層形成在絕緣層上的半導體材料(例如矽)。絕緣層例如為一埋入氧化物(buried oxide，BOX)層或是一氧化矽層。將絕緣層配置於一基板上，該基板一般是矽或玻璃基板。亦可使用其他的基板，例如多層(multi-layered)或是梯度基板(gradient substrate)。在其他實施例中，基板100可包括一可貼附積體電路晶片的基板。舉例來說，基板100可包括轉接板、封裝基板、高密度內連線結構、印刷電路板、另一積體電路晶片、或其相似物。
值得注意的是，在一些實施例中，特別是在基板100包括一積體電路晶片的實施例中，基板100可包括電路(electrical circuitry，未繪示)。在一實施例中，電路包括形成在基板100上的電子元件以及位於電子元件上的一或多層介電層。可在介電層之間形成金屬層以傳輸(route)電子元件之間的電訊號。電子元件亦可形成在一或多個介電層中。
舉例來說，電路可包括各種N型金氧半導體(N-type metal-oxide semiconductor，NMOS)及/或P型金氧半導體(P-type metal-oxide semiconductor，PMOS)元件(例如電晶體、電容、電阻、二極體、光二極體、保險絲、及其相似物)相互連接以執行一或多個功能。這些功能可包括記憶結構、處理結構、感測器、增幅器、電源分配器(power distribution)、輸入/輸出電路、或其相似物。本領域具有通常知識者當可知道上述實施例僅用以說明以更進一步解釋說明實施例的應用，而並非以任何形式限定本發明。在特定的應用上可使用其他的電路。當基板100為一轉接板時，轉接板可包括被動元件、主動元件、主動元件與被動元件、或者是兩者都不包括。
導電接墊(conductive pad)102配置於基板100的一上表面中，以提供外部的電性連接。值得注意的是，導電接墊102可代表一連接至形成於基板100上的電路的電性連接結構、連接至貫穿基板導孔(through-substrate via)的電性連接結構、重佈線路、及/或其相似物。導電接墊102可包括一導電材料，例如銅，但也可使用其他的導電材料，例如鎢、鋁或銅合金。可以鑲嵌製程(damascene process)或雙鑲嵌製程(dual damascene process)形成導電接墊102，前述製程可包括將銅過量填入(overfill)一開口中，之後，以一製程(例如化學機械研磨)移除過量的銅。然而，可選擇任何適合的材料(例如鋁)以及任何適合的製程(例如沉積與蝕刻)來形成導電接墊102。
可在基板100的表面上形成一第一保護層104，第一保護層104係由介電材料(例如聚亞醯胺、高分子、氧化物、氮化物、或其相似物)所構成，並於基板100的表面上圖案化第一保護層104以形成一位於導電接墊102上的開口，第一保護層104可保護其下層免於遭受到各種環境污染。在一實施例中，第一保護層104包括一複合層，其包括一氮化矽層與一氧化物層。可以化學氣相沉積法形成氮化矽層，其係使用矽烷(silane)與氨氣(ammonia)為前驅氣體沉積氮化矽層至厚度約為2000埃()。可以任何的氧化製程形成氧化物層，例如在一包含氧化物、水、氧化氮、或前述之組合的環境下進行濕式或乾式熱氧化製程，或是以四乙氧基矽甲烷(tetra-ethyl-ortho-silicate，TEOS)與氧氣為前驅物的化學氣相沉積法。在一實施例中，氧化物層的厚度約為10000埃。
在一實施例中，第一保護層104包括一氮化矽層與一氧化物層，可利用濕式蝕刻製程形成一開口以暴露出導電接墊102，濕式蝕刻製程包括以稀釋的氫氟酸蝕刻二氧化矽層以及利用磷酸蝕刻氮化矽層。
之後，於第一保護層104上形成接墊106，並圖案化接墊106。接墊106可做為一電性連接結構，且其上可形成有一凸塊底部金屬(UBM)結構以於後續製程步驟中作為外部的連接結構(external connection)。接墊106可由任何適合的導電材料構成，例如銅、鈦、鎢、鋁、銀、前述之組合、或其相似物。
在一實施例中，可利用物理氣相沉積法沉積一鈦阻障層至厚度約500埃，並利用物理氣相沉積法沉積一銅晶種層(copper seed layer)至厚度約3000埃。之後，可利用電鍍法(electroplating，ECP)沉積一銅層至厚度約3微米。一般而言，在電鍍製程中，可將晶圓淹沒(submerge)或浸漬(immerse)於電鍍液中。晶圓表面電性連接至一外部直流電源供應器(external DC power supply)的陰極側(negative side)，因此，晶圓在電鍍製程中是作為陰極。一固態導電陽極(例如銅陽極)亦浸入溶液中並貼附至電源供應器的陽極側(positive side)。來自於陽極的原子會溶入溶液中並且被陰極(例如晶圓)取得，藉此電鍍晶圓的外露導電區(例如晶種層的表面)。可以濕式浸泡法(wet dip)或是其他的清潔製程移除多餘的材料，濕式浸泡法係將多餘的材料浸泡於含有磷酸與過氧化氫(稱為DPP)以及2%的氫氟酸的化學溶液中。
如第1圖所示，可形成一或多層第二保護層(例如一第二保護層108)於接墊106上，並圖案化第二保護層。可以任何適合的方法(例如化學氣相沉積、物理氣相沉積或其相似的方法)形成第二保護層108，其可由介電材料(例如高分子材料、氮化物、氧化物、或其相似物)構成。在一實施例中，第二保護層108包括一厚度約為4000埃的氮化矽層。
本領域具有通常知識者當可知道圖示的一層導電/接墊以及一保護層僅用於說明，並非用以限定本發明。因此，其他實施例可包括任何數量的導電層及/或保護層。再者，值得注意的是，一或多個導電層可做為一重佈線層(redistribution layer，RDL)以提供所需的接腳(pin)或是銲球佈局(layout)。舉例來說，第1圖右側的接墊106包括一重佈線，其中第二保護層108的開口並未直接對齊於導電接墊102上方。
可使用任何適合的製程形成上述結構，且在此將不會對其進行更進一步的討論。如同本領域具有通常知識者將了解到的，上述內容係提供實施例的特徵的一般性描述，但是也可能有許多其他的特徵。舉例來說，可能有其他的電路、襯層(liner)、阻障層、凸塊底部金屬結構、及其相似物。以上的描述在此僅用以討論實施例，並非用以將本發明或是任何申請專利範圍限制在那些特定的實施例中。
請參照第2圖，將一晶種層210共形地沉積在第二保護層108的表面以及接墊106的外露部上。晶種層210為一導電材料薄層，其有助於在後續的製程步驟中形成一較厚層。在一實施例中，可利用化學氣相沉積法或是物理氣相沉積法沉積一薄導電層以形成晶種層210，薄導電層例如為Cu、Ti、Ta、TiN、TaN及/或前述之組合的薄膜。舉例來說，在一實施例中，晶種層210包括一鈦層與一銅層，其中係以物理氣相沉積法沉積鈦層至厚度約500埃並以物理氣相沉積法沉積銅層至厚度約3000埃。
第3圖繪示本發明一實施例之在晶種層210上形成並圖案化一第一圖案化罩幕層312，以形成開口314。在後續製程步驟中，第一圖案化罩幕層312可作為形成導電接墊的模子(mold)。第一圖案化罩幕層312可為一圖案化光阻罩幕、硬罩幕、或是其相似物。
之後，如第3圖所示，於第一圖案化罩幕層312的開口314中形成導電柱316。導電柱316係由導電材料所構成，例如銅、鎢或是其他的導電材料，且其形成法例如為電鍍、無電鍍或是其相似的方法。
第4圖繪示本發明一實施例之在第一圖案化罩幕312與導電柱316上形成一第二圖案化罩幕418。第二圖案化罩幕418可做為一蝕刻罩幕以於導電柱316中形成一凹槽420，藉此形成凹陷的導電柱316。在一實施例中，凹槽420具有大體上垂直的側壁，例如經由蝕刻製程所能得到的側壁。如同以下將進行的更詳細的描述，在後續的製程步驟中係將一銲料填入凹槽420中。凹槽420的形成方法例如為濕式浸泡入一化學溶液中，該化學溶液含有磷酸與過氧化氫。在一實施例中，凹槽的深度約為20000埃至80000埃，例如30000埃。
之後，如第5圖所示，在一實施例中，一導電材料522填滿凹槽420。導電材料522例如為鉛錫(SnPb)、銀錫(SnAg)、銅銀錫(SnAgCu)、高鉛材料(high-Pb material)、錫基銲料(Sn-based solder)、無鉛銲料、或是其他適合的導電材料。第5圖亦繪示形成一介金屬化合物(inter-metallic compound，IMC)層524。在銲接的過程中，介金屬化合物層524會自然地形成在銲料與其下的表面的連接之處。在一些實施例中，也許會在凹陷的導電柱316與導電材料522之間視情況而配置一蓋層(cap layer，未繪示)。已經知道的是，有一些材料可製作出更堅固且更耐用的介金屬化合物層。因此，可藉由形成一蓋層來形成一具有較佳特性的介金屬化合物層。舉例來說，在一實施例中，凹陷的導電柱316是由銅構成，較理想的的情況是使用由鎳所構成的導電蓋層。亦可使用其他的材料，例如Pt、Au、Ag、前述之組合、或是其相似物。導電蓋層可以任何數量的適合的製作方法製得，包括物理氣相沉積、化學氣相沉積、電化學沉積法(electrochemical deposition，ECD)、分子束磊晶沉積法(molecular beam epitaxy，MBE)、原子層沉積(atomic layer deposition，ALD)、電鍍、及其相似的方法。
在一實施例中，第5圖亦介紹移除第一圖案化罩幕層312與第二圖案化罩幕層418。在一實施例中，第一圖案化罩幕層312與第二圖案化罩幕層418為光阻罩幕，可使用氧氣電漿灰化製程(O2 plasma ashing process)或是濕式剝除製程(wet strip process)移除第一圖案化罩幕層312。可以例如濕式蝕刻製程或是其他的清潔製程移除晶種層210的外露部，其中濕式蝕刻製程例如將晶種層210的外露部濕式浸泡於含有磷酸與過氧化氫(稱為DPP)以及2%的氫氟酸的化學溶液中。或者是，可濕式浸泡於硫酸溶液中以清潔晶圓並移除剩下的光阻材料。可進行一迴銲製程(reflow process)以使銲料522呈圓形。
可視情況而在導電柱上形成一處理層(finish layer，未繪示)。在一實施例中，處理層包括直接配置於導電柱316上且直接接觸導電柱316的鎳層。可視情況而形成額外的膜層，故處理層可為一化鎳浸金(electroless nickel immersion gold，ENIG)層、無電鍍鎳鈀金(nickel electroless palladium immersion gold，ENEPIG)層或是鎳鈀層(nickel palladium layer)。處理層的形成方法包括電鍍法、無電鍍法以及其相似的方法。
第6a圖、第6b圖與第6c圖繪示本發明之一實施例之連接二個基板的方法。第一基板600代表一基板(例如前述在第1-4圖中討論的基板100)，其中相似的元件符號代表相似的元件。第二基板650代表一貼附至第一基板600的基板，其可為積體電路晶片、轉接板、封裝基板、高密度內連線結構、印刷電路板、或其相似物。
為了說明起見，第二基板650介紹了一內連線結構的例子，內連線結構係用以貼附至第一基板600。值得注意的是，其他種類的內連線結構亦可用以連接第一基板600與第二基板650。在這個例子中，第二基板650包括一電接點(electrical contact)657以及一第一保護層654，第一保護層654可由一或多層介電層構成，介電層的材質例如為聚亞醯胺(polyimide)、高分子材料、氧化物、氮化物、或其相似物。在一實施例中，第一保護層654包括一複合層，該複合層包括一厚度約為750埃的氮化矽層以及位於其上的一厚度約為8500埃的氧化物層。可利用矽烷與氨氣為前驅氣體進行化學氣相沉積製程以形成氮化矽層，且可以任何的氧化製程形成氧化物層，例如在一包含氧化物、水、氧化氮、或前述之組合的環境下進行濕式或乾式熱氧化製程，或是以四乙氧基矽甲烷與氧氣為前驅物的化學氣相沉積法。第一保護層654中的一開口暴露出其下的部分電接點657。
一導電接墊656形成於第一保護層654上並接觸其下的電接點657。導電接墊656可以任何適合的導電材料構成，例如銅、鎢、鋁、銀、前述之組合、或其相似物。值得注意的是，導電接墊656及/或電接點657可為部分的重佈線層或貫穿基板導孔。在一實施例中，導電接墊656的材質可為鋁，其可以化學氣相沉積法、物理氣相沉積法、電鍍法或其相似的方法形成至厚度約為12000埃。
在導電接墊656上形成並圖案化一或多層第二保護層，例如一第二保護層660。第二保護層660可以介電材料構成，例如高分子材料、氧化物、氮化物、或其相似物，第二保護層660可以任何適合的方法形成，例如化學氣相沉積法、物理氣相沉積法或其相似的方法。在一實施例中，第二保護層660為一複合層，其包括一厚度約為300埃的電漿加強氮氧化矽(plasma-enhanced silicon oxynitride，PESION)層、一厚度約為4000埃的未摻雜的矽酸鹽玻璃(undoped silicate glass，USG)層、以及一厚度約為6000埃的電漿加強氮化矽(plasma-enhanced silicon nitride，PESIN)層。
之後，在導電接墊656上形成一晶種層662、一導電柱664、一蓋層666以及一銲料層668。晶種層662、導電柱664、蓋層666以及銲料層668的組成成分與形成方法可分別相似於上述的晶種層210、凹陷的導電柱316、以及銲料層522的組成成分與形成方法。
如第6b圖與第6c圖所示，第一基板600連接第二基板650，因此，導電柱664/蓋層666位於凹陷的導電柱316的凹槽上。導電柱664/蓋層666的接觸面的寬度W1 小於或等於凹陷的導電柱316的凹槽的寬度W2 。在一實施例中，導電柱664/蓋層666的接觸面的寬度W1 約為0.1至1.0倍的凹槽寬度W2 。
第6b圖繪示第二基板650的導電柱664/蓋層666並未插入凹陷的導電柱316的凹槽中，更確切地說，導電柱664/蓋層666是位於凹陷的導電柱316上。在一實施例中，第二基板650的導電柱664/蓋層666是位於凹陷的導電柱316上方約5000埃至50000埃之處。第6c圖繪示本發明一實施例之第二基板650的導電柱664/蓋層666插入或齊平於(even with)凹陷的導電柱316的凹槽。值得注意的是，導電柱664/蓋層666繪示為梯形(trapezoidal shape)僅是用以說明，其他的實施例可能採用其他形狀，例如矩形。導電柱664/蓋層666可插入凹陷的導電柱316的凹槽中約0埃至50000埃。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧基板
102、656‧‧‧導電接墊
104、654‧‧‧第一保護層
106‧‧‧接墊
108、660‧‧‧第二保護層
210、662‧‧‧晶種層
312‧‧‧第一圖案化罩幕層
314‧‧‧開口
316‧‧‧(凹陷的)導電柱
418‧‧‧第二圖案化罩幕
420‧‧‧凹槽
522‧‧‧導電材料、銲料層
524‧‧‧介金屬化合物層
600‧‧‧第一基板
650‧‧‧第二基板
657‧‧‧電接點
664‧‧‧導電柱
666‧‧‧蓋層
668‧‧‧銲料層
W1 、W2 ‧‧‧寬度
第1圖至第5圖繪示本發明一實施例之一具有一凸塊結構的半導體元件的製程的中間步驟。
第6a圖、第6b圖與第6c圖繪示本發明之多個實施例之貼附二個基板的方法。
102、656．．．導電接墊
104、654．．．第一保護層
106．．．接墊
108、660．．．第二保護層
210、662．．．晶種層
316．．．(凹陷的)導電柱
522．．．導電材料、銲料層
600．．．第一基板
650．．．第二基板
657．．．電接點
664．．．導電柱
666．．．蓋層
668．．．銲料層

Claims (10)

  1. 一種電子元件，包括：一第一基板，具有一接點；一凸塊底部金屬結構，電性接觸該接點；以及一凹陷的導電柱，位於該凸塊底部金屬結構上並電性接觸該凸塊底部金屬結構，該凹陷的導電柱具有一形成於其中的凹槽，該凹槽具有大體上垂直的側壁。
  2. 如申請專利範圍第1項所述之電子元件，更包括：一銲料，位於該凹槽中。
  3. 如申請專利範圍第1項所述之電子元件，更包括：一第二基板，具有一第二導電柱，該第二基板貼附該第一基板，以使該第二導電柱橫向地位於該第一基板上的該凹陷的導電柱的該凹槽中。
  4. 如申請專利範圍第3項所述之電子元件，其中該第二導電柱插入該凹槽中。
  5. 如申請專利範圍第3項所述之電子元件，其中該第二導電柱水平地位於該凹陷的導電柱之上。
  6. 一種電子元件的製作方法，包括：提供一第一基板，該第一基板具有一形成於其上的導電接墊；於該第一基板上形成一導電柱，該導電柱電性接觸該導電接墊；以及於該導電柱的一頂面中去除該導電柱的一部分以形成一凹槽，以使得該導電柱成為一凹陷的導電柱。
  7. 如申請專利範圍第6項所述之電子元件的製作方 法，更包括：於該凹槽中形成一銲料。
  8. 如申請專利範圍第6項所述之電子元件的製作方法，更包括：提供一第二基板，該第二基板具有一第二導電柱，該第二基板貼附該第一基板，以使該第二導電柱位於該第一基板上的該凹陷的導電柱的該凹槽上。
  9. 如申請專利範圍第8項所述之電子元件的製作方法，其中該第二導電柱插入該凹槽中。
  10. 如申請專利範圍第8項所述之電子元件的製作方法，其中該第二導電柱位於該凹陷的導電柱之上。
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