TWI255543B - A CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture - Google Patents

A CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture Download PDF

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TWI255543B
TWI255543B TW093100051A TW93100051A TWI255543B TW I255543 B TWI255543 B TW I255543B TW 093100051 A TW093100051 A TW 093100051A TW 93100051 A TW93100051 A TW 93100051A TW I255543 B TWI255543 B TW I255543B
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Taiwan
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layer
insulating layer
source
region
wafer
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TW093100051A
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TW200428638A (en
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Paul D Agnello
Byoung H Lee
Heemyong Park
Dominic J Schepis
Ghavam G Shahidi
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Ibm
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Description

1255543
【發明所屬之技術領域] 本發明係關於一種互補式金氧半導體（CM〇S)裝置，特 別是，關於一種在超薄絕緣層上矽製造具有增高式源/沒 極層之互補式金氧半導體裝置。 二、【先前技術】 於CMOS發展中發現到習知以矽選擇性磊晶之增高式源 極/沒極（RSD)層的問題。已發展出一些解決方案，如形成 消耗較少量矽的N i S i，但仍有一些限制如熱穩定性差。再 者，於絕緣層上薄膜矽基材上形成具有增高式源極/汲極 層之高性能CMOS裝置的習知製程具有下列的問題。首先， 以矽選擇性磊晶形成增高式源極/汲極層極具挑戰性。增 高式源極/汲極的習知製程包含於高溫（一般>825°C )選擇 性蠢晶成長，以及於摻雜的源極/沒極表面的前清潔製輕 之化學蝕刻/清潔製程。磊晶製程習知為阻礙製造具有增 南式源極/沒極於超薄絕緣層上碎之CMOS裝置的技術挑戰 的因素。首先’南溫循j哀造成換雜質（源極/没極延伸及環 區（S/D extension and halo))的瞬間增強擴散 (transient enhanced diffusion, TED)，其係於蠢晶步 驟前即介入通道區域。習知如此會造成顯著的短通道效 應，如臨界電壓（Vth)下滑（rolloff)。 其次，磊晶層及於基材上存在的源極/汲極區域之間 的介面可造成相當大的變異性，且使得蠢晶製程後形成的
4IBM03138TW.ptd 第8頁 1255543 五、發明說明（2) 金屬石夕化物層缺乏一致性，亦會增加源極/沒極阻值。再 三，前清潔製程會破壞薄的淺溝渠隔離區域，其係亦由氧 化物所形成。第四，形成於間隙壁上的磊晶層（面）的殘 留，於磊晶製程期間可能改變於磊晶製程後植入之源極/ 沒極摻雜質的分佈。因此對裝置性能造成負面的影響。總 之，於CMOS裝置的製程中，習知的磊晶製程涉及複雜的表 面化學作用。再者，如此使得產業中的CMOS量產不容易實 施。 因此’需要一種創新的在超薄絕緣層上；e夕製造具有增 高式源/汲極層之互補式金氧半導體裝置及其製造方法， 以克服習知製程及結構的限制。 【發 綜觀 電晶 晶圓 上、 矽晶 層及 鄰接 係高 隙壁 且源 上石夕 上石夕 晶圓 層上 植入 區域 表面 緣間 度， 明内容】 上述，本發明提供一種增高式源極/汲極絕緣層 體裝置，包含一埋入式氧化（Β〇χ)層、一絕緣層 於埋入式氧化層上、一閘極介電層於絕緣層上矽 一閘極區域於閘極介電層上、一植入層鄰接絕緣 圓，植入層包一沉積的材料、源極/汲極區域於 絕緣層上石夕晶圓上方、以及一淺溝渠隔離（STI) 源極/汲極區域，其中淺溝渠隔離區域具有一上 於閘極介電層之上表面。此裝置更包含至少一絕 包圍閘極區域。絕緣層上矽晶圓具有一預定厚 極/汲極區域具有一厚度係大於絕緣層上矽晶圓
第9頁 I255543 " ----- 角 予又 此外，淺溝渠隔離區域具有大體為圓形的 再其中淺溝渠隔離區域鄰接（borders)源極/汲極區域。 沒極i推雜質層包含多晶矽及非晶矽之一。此外，源極/ 包2區域無磊晶相關的缺陷。換句話說，源極/汲極區域 補二 非磊晶材料。選替地，發明之一實施例提供一種互 緣^金氧半導體（CM〇S)裝置’包含一埋入式氧化層、一絕 預二^矽晶圓於埋入式氧化層上，絕緣層上矽晶圓具有一 層5厚度、一間極結構於絕緣層上石夕晶圓上、一閘極介電 入^，極結構及絕緣層上矽晶圓之間，閘極介電層位於埋 圓，氧化層上之一第一高度、一植入層鄰接絕緣層上矽晶 ’植入層包一沉積的材料、源極/汲極區域於植入層及 於=層上矽晶圓内，其中源極/汲極區域具有一厚度係大 右、f緣層上矽晶圓之預定厚度、以及一淺溝渠隔離區域具 泪3體為圓形的角，且位於埋入式氧化層上方，其中淺溝 二隔離區域之一上表面係高於埋入式氧化層上之第一高 ς爲cmos震置更包含至少一絕緣間隙壁包圍閘極結構。絕 试曰上石夕晶圓之預定厚度係小於5 5奈米，且源極/汲極區 s之厚度係於200-30 0埃之範圍。又，摻雜質層包含多晶 石夕及非晶矽之一。 人”一種形成一互補式金氧半導體（CM0S)裝置之方法，包 3 /儿積一絕緣層上矽（s〇I )晶圓於一埋入式氧化（Β〇χ)基材 ^方，其中絕緣層上矽晶圓具有一預定厚度；形成一閘極 ”电層於絕緣層上矽晶圓上；形成一淺溝渠隔離（ST 〇區
1255543 五、發明說明（4) ί = 氧：基材上’其中淺溝渠隔離區域具有-大體 ”、、7 、角，形成一閘極結構於閘極介電 入層於絕緣層上矽曰圓卜·拙> _ Ώ电層上，/儿積植 植入於絕緣it 仃型及Ρ型之其—的摻雜質 入層及絕緣；上：t ί及植入層内"乂及加熱装置以自植 汲極區域且；士： 形成源極及汲極區域，纟中源極及 苴中閘極二：展度係大於絕緣層上矽晶圓之預定厚度； 八1桎"電層位於較淺溝渠隔離區域為低。 再者本：ί : 5含形成至少一絕緣間隙壁包圍閘極結構。 曰匕含多晶矽及非晶矽之一。此外 社 ==積7第一閘極多晶石夕層於絕緣層上矽晶；； 於氧化墊上·&第一閘極多晶矽層上；沉積一犧牲氮化層 化層上。絕绫：t沉積一犧牲第二閘極多晶矽層於犧牲氮 搞層矽晶圓之預定厚度係小於55奈米。源 / 區域之厚度係於200-30 0埃之範圍。 ^ ί ί Γ提，一種獨特的解決方案，對於在超薄絕緣層 -/皿增同式源極/汲極的形成、閘極後摻、 源極/汲極及客曰访拟攸 古次夕曰日石夕摻雜、、以及閘極堆疊高度的降低，一 八有咼的可用性及可製造性。相較於習知裝置及製程， 發明具有許多顯著不同的特徵。首先，本發明於淺溝準 :離Ϊ面及閉極介電層介面之間提供-高度差(階梯); 省头裝置固有以蠢晶為基礎的增高式源極/沒極特 性，如面、多晶矽晶粒、氧的面劑濃度、以及於多晶矽閘
1255543
極上的選擇性蠢晶橫向成長，係不存在於本發明。此外， 依據本發明，非磊晶增高式源極/汲極多晶矽層係全範圍 地形成於淺溝渠隔離區域及主動區域上方。 本發明達成下列的優點。本發明藉由形成無需磊晶的 增高式源極/汲極，解決所有於超薄絕緣層上矽之⑽㈧的 選擇性磊晶增高式源極/沒極的基本問題。同時，本發明 利用於源極/汲極上之多晶矽為緩衝層，後摻雜多晶矽閘 極。再者，本發明係利用與增高式源極/汲極多晶矽平坦 化相同的化學機械研磨，導致多晶矽閘極高度的降低。再 者，對咼性成邏輯CMOS裝置的製造，本發明達成於超薄絕 緣層上石夕之增高式源極/汲極，其係具有較習知閘極結構 更積極的尺寸。此外，本發提供一種隔離源極/汲極電極 的方法，係藉由階梯化淺溝渠隔離且利用淺溝渠隔離表面 為標記回蚀刻多晶矽。此外，本發明提供一種解決與圍繞 淺溝渠隔離邊緣之階梯狀角的多晶矽軌相關的問題，係於 墊氧化層蝕刻及襯層氧化時圓化此角。 四、【實施方式】 如前所述，需要一種創新的在超薄絕緣層上矽製造具 有增高式源/汲極層之互補式金氧半導體裝置及其製造方 法，以克服習知製程及結構的限制。本發明提供、一種形成 縮小的CMOS結構於非常薄的絕緣層上矽具有增高式源極淚 極層’係藉由多晶係沉積以及利用新設計的回制製輕’
1255543 五、發明說明（6) 而非用於習知製程的矽選擇性磊晶。 為方便說明，僅繪示一半的CMOS裝置1、2於圖式中 (例如，僅繪示源極或汲極區域）。圖1 5A及1 5B則呈現整個 結構。熟習技術之人士應明白實際上每一裝置1、2存在著 鏡像結構（例如，對應的沒極或源極區域分別存在於閘極 結構4 0的另一側）。本發明一般以下列方式執行。以圖1 5 a 所示的N型塲效電晶體（NFET)裝置：1為例，一電信號由源 極/汲極區域79(a)、79(b)進入，且通過通道區域2 0到達 互補的源極/沒極區域7 9 ( a )、7 9 ( b )。如上所述，僅一半 的CMOS裝置卜2繪示於圖1 A至圖14B。CMOS裝置卜2包含 一淺溝渠隔離區域3 5具有大體為圓形的角37，且形成於一 埋入式氧化層1 〇上方，以及一閘極介電層2 5作為閘極4 〇及 源極/沒極區域7 9 ( a )、7 9 ( b )間的傳導阻障層。本發明之 一獨特的特徵為淺溝渠隔離區域3 5之上表面3 6係結構上高 於閘極介電介面25。如此設計的好處是因為於製程時，即 使在回蝕刻製程之後移除大部分的植入層6 5，升高的淺溝 渠隔離區域35允許保留植入層。65的一部份。如此實質上允 ^ ϊί f製程，有助於去除摻雜f的瞬間增強擴散效應， 亦降低短通道效應，如臨界電壓（vth)下滑「此外，大 體上曲型的淺溝渠隔離的角^ 九，再示⑽雕J月d 7沩減在多晶矽沉積後留在淺 月6 溝^隔離上的多晶矽殘留量，藉此改進裳置性 參考圖式’ m別參考圖呢18，纟係本發明之較
1255543 ____ 五、發明說明⑺ 一 ~ 佳實施例。本發明提供之NFET製程進行的步驟詳細繪示於 圖1A至15A，而本發明提供之pFET製程進行的步驟詳細繪 示於圖1B至15B。特別如圖1A(NFET)& 1B(pFET)所示，一 超薄的絕緣層上矽晶圓20 (如通道區域），其較佳為厚度小 於5 5奈米’係位於一埋入式氧化層1 〇上。之後，依序沉積 一氧化塾2 5及氮化層3 0於絕緣層上石夕晶圓2 0上。氧化墊2 5 為一犧牲層，用以保護一通道區域26(示於圖5A及5B)，且 於濕餃刻移除時，亦用以協助形成淺溝渠隔離區域35的圓 角（示於圖2 A及2 B )。氮化層3 0於後續的蝕刻製程·中會被移 除’其厚度較佳為尺寸化以接近等於後續增高式源極/汲 極層的目標厚度，其較佳約2 0 〇 - 3 0 0埃。 製程的下一步驟示於圖2A(NFET)及2B(PFET)，於氮 化/氧化/絕緣層上矽堆疊1 5後，罩幕且蝕刻一淺溝渠隔離 區域3 5。此製程包含淺溝渠隔離襯層氧化，以助於形成淺 溝渠隔離的圓角37，如後續圖4A及4B所示。 然後，如圖3A(NFET)及3B(PFET)所示，利用濕蝕刻製 程移除氮化層30，藉此以淺溝渠隔離區域35配置一階梯， 使得淺溝渠隔離表面3 5高於絕緣層上矽表面2 0。之後，利 用濕蝕刻製程移除氧化層2 5，且同時圓化角3 7，較佳如圖 4A(NFET)及4B(PFET)所示。圓化淺溝渠隔離35的角37的製 程避免於下個步驟中發生多晶矽執的問題。多晶矽軌的問 題涉及在反應性離子蝕刻後，留下閘極多晶矽的殘留於淺
4IBM03138TW.ptd 第14頁 1255543 、發明說明（8) 溝渠隔離邊界，因此負面影響裝置的性能。因此，藉由圓 化淺溝渠隔離3 5的角3 7，本發明較習知無圓化的淺溝渠隔 離區域之裝置達到較佳的裝置性能。於製程的此步驟，淺 溝渠隔離區域3 5於絕緣層上矽表面2 0上方的階梯高度較佳 約為3 0 〇埃。 圖5A(NFET)及5B(PFET)繪示本發明的下一步驟。一多 晶石夕閘極堆疊40係利用四乙基正矽酸鹽（TEOS)硬遮罩（未 綠不）圖案化。多晶矽閘極堆疊4 〇係設計以於後續步驟中 可減低其高度。多晶矽閘極堆疊4 0的形成係利用沉積一多 晶石夕層42，較佳係具有目標縮小高度約為1 〇〇埃。然後， 依序沉積一氧化層44、一氮化層46及緩衝仿多晶矽層48。 接著’進行反應性離子蝕刻以形成閘極堆疊4 〇。假若淺溝 渠隔離3 5，係較佳約為3 〇 〇埃，於淺溝渠隔離3 5邊界造成 多晶石夕薄化，於多晶矽層42沉積後，可選擇性利用化學機 械研磨製程平坦化堆疊4〇，然後可沉積薄氧化層44、氮化 層46及緩衝仿多晶矽層48，且之後可進行反應性離子蝕刻 製程’以一致地定義閘極堆疊40於淺溝渠隔離35邊界Λ 方0 製程的下一步驟如圖6A(NFET)及6B(PFET)所示係為閘 極再氧化’其中一氧化或氮氧化絕緣層5〇係沉積於絕緣層 上石夕晶圓2 0、淺溝渠隔離區域3 5及多晶矽閘極堆疊4 〇上 方。此外，如圖6 A所示，一 N -延伸/ N -環植入發生於絕緣
1255543 五、發明說明（9) —- 層上矽晶圓20内。區域51表示為所致的^型未回火摻雜區 域，而區域5 2表示為所致的p型未回火摻雜區域。之後， 沉積一低溫氧化（LTO)帽蓋55於氧化/氮氧化絕緣層5〇上 方，較佳如圖7A(NFET)及7BCPFET)所示。選擇性二，可沿 多晶矽閘極40之侧壁形成一氮化間隙壁6〇。如圖7B所示， P-延伸/環植入發生於絕緣層上矽晶圓2 〇内。區域5 3表示 為所致的P型未回火摻雜區域，而區域5 4表示為所致的n型 未回火摻雜區域。
圖8A(NFET)及8B(PFET)繪示氮化間隙壁60的進一步形 成的製程，係利用快速熱化學氣相沉積（RTCVD)，其中間 隙壁6 0被加寬。此外，移除除了介於間隙壁6 〇及絕緣層上 矽20間的部份以及介於間隙壁60及多晶矽閘極堆疊40間的 部份以外的低溫氧化帽蓋5 5及絕緣層50。製程的下一步驟 如圖9八（評£1')及98(卩『£1')所示，沉積（如非磊晶地）一層多 晶矽65於NFET裝置1及PFET裝置2上，較佳於低溫約62 0°C 或更低。多晶矽層6 5避免摻雜質遷移入通道2 0，係利用低 壓化學氣相沉積（LPCVD)。選替地，一非晶矽層（未繪示） 可較佳以低溫沉積於於裝置1、2上。因此，相對於習知源 極/没極結構利用蠢晶成長技術，換雜的源極/沒極導體6 5 係利用共形沉積技術形成。如此允許共形沉積層6 5無磊晶 缺陷。 接著，圖10A(NFET )及1 〇B(PFET )綠示利用化學機械研
4IBM03138TW.ptd 第16頁 1255543 五、發明說明（10) 磨製程平坦化多晶石夕層6 5 (例如，可使用習知〇 b s i d i a η化 學機械研磨製程），其中暴露出於多晶矽閘極4 0頂端的氮 化層46。假如並未使用圖5人及5B的製程中所述之選擇性化 學機械研磨製程，利用現行的0bsidian化學機械研磨製程 可能不會均勻地暴露氮化層46，係因為於圖3A及3B的製程 中所產生的淺溝渠隔離階梯3 5。於此例中，當暴露及平坦 化於氮化層46頂端之仿多晶矽層48時，Obsidian化學機械 研磨製程可選擇性地終止。之後，進行多晶矽層4 8的短回 蚀刻製程’以暴露氮化層4 6。再次說明，假如使用圖5 A及 5B的製程中所述之選擇性化學機械研磨製程，是不必要此 回餘刻製程。不論是使用上述的較佳製程或選擇性製程的 哪一種，其所致的結構如圖l〇A(NFET)A l〇B(pFET)所示， 於閘極結構4 0之氮化層4 6頂端的仿多晶石夕層4 8利用 Obsidian化學機械研磨製程移除，且其結果為多晶矽閘極 40的高度被減低至所欲達到的目標高度，同時形成了源 極/汲極遮擋多晶矽層6 5。 依據本發明製程的下一步驟，裝置卜2將進行閘極後 摻雜植入。更明確地說，如圖ua(nfet)及ub(pfet_ 示，裝置1、2經歷中性物種的前非晶化製程 (preamorphization)，然後分別利用N型及p型摻 N閘極及P閘極摻雜。因此，於源極/汲極區域上的平坦仃 的多晶矽65作為緩衝層，以將閘極摻雜及源極/汲極拎 分開。區域66、67(與區域5卜54)表示N型未回火摻ς區
1255543 五、發明說明（11) 域，而域區域 區域。之後， 6 5經歷回蝕刻 於淺溝渠離氧 極/汲極區域< 低溫沉積，植 循環。因此， 瞬間增強擴散 的上表面3 6及 也就是說，於 閘極介電介面 在蝕刻製程移 晶矽層6 5，因 68、69(與區域52、53)表示p型未回火摻雜 如圖12A(NFET)及12B(PFET)所示，多晶矽層 製程（乾蝕刻或選替地計時濕蝕刻），而停止 化表面35。殘留的多晶矽65包含增高式源 此外’因為多晶矽增高式源極/汲極6 5係於 入的延伸及環摻雜質並未受到任何顯著的熱 了避免如刖所解釋蠢晶增高式源極/汲極的 的問題’再者，本發明於淺溝渠隔離區域35 閘極介電層25介面間提供了高度差（階梯）。 淺溝渠隔離區域3 5的上表面3 5係結構上高於 2 5。因為升高的淺溝渠隔離區域3 5允許即使 除大部分的多晶矽層65後，仍保留部分的多 此對摻雜質植入提供非磊晶層係為有益的。 於圖13A(NFET)中，NFET 1經歷NFET源極/汲極（NSD) 砷植入。於此藉由執行砷植入係利用既存的薄氮化間隙壁 60，延伸/NSD掺雜係盡可能的靠近閘極通道26，因此最 大化杈向摻雜程度而不傷害短通道特性，因為相較於p F E T 中的硼而曰’石申係低擴散質。因此，區域7 1與區域5 1、6 7 表示為所致的N-型未回火的摻雜區域。繪示於圖13β之 P F E T係保持於先前步驟未改變。 於圖14A(NFET)及14B(PFET)中，利用RTCVD沉積一第 二氮化間隙壁6 1係相鄰第一氮化間隙壁6 〇。之後，於過蝕
4IBM03138TW.ptd 第18頁 1255543 五、發明說明（12) 刻（overetch)時，RIE製程移除多晶矽閘極40頂端的薄保 護性氮化層4 6。假如此過蝕刻影響增高式源極/汲極層 71、72的表面，則在最終RTCVD氮化間隙壁沉積前，選擇 性地沉積一 LT0帽蓋層（未繪示），以保護增高式源極/汲極 層7 1、7 2。圖1 4 B顯示一 P F E T源極/沒極（P S D )爛/ B F 2植 入，接著形成最終氮化間隙壁6 1，其於後續最終熱循環時 係提供足夠的橫向閒距以最小化於PFET元件2的硼橫向侵 姓。區域7 2與區域5 3、6 9表示為所致的p _型未回火的摻雜 區域，而區域54表示所致的N-型未回火的摻雜區域。 之後，如圖15A(NFET)及15B(PFET)所繪示，裝置卜2 經歷一最終快速熱回火（RTA)製程，以回火所有摻雜質， 且較佳於溫度9 5 0 -1 1 5 (TC。因為非磊晶增高式源極/汲極 ^、72係形成於非常低的溫度，且先前並未有其他的熱循 裱，RTA製程所有在裝置！、2中摻雜質的是唯一的回火製 程。因此’本發明對高性能之深次〇·丨微米的CM0S裝置製 造而言’提供摻雜質絕對最小的重分佈。區域73、85、86 (不於圖15A)及區域87(示於圖15B)表示所致的N-型活化摻 雜區域，而區域74 (示於圖15A)及區域75、88、89 (示於圖 15B)表不為所致的p—型活化摻雜區域。區域7〇表示為裝置 1、2的主動區域。裝置的不同區域經歷不同的摻雜、植入 及回火製程，導致新的材料性質及物理結構。例如，示於 圖1 3 A的區域6 7變成圖1 5 a的區域7 3。此外，示於圖1 3 A的 區域5 2變成圖15 A的區域74。同時，示於圖13 A的區域51的
4IBM03138TW.ptd 第19頁 1255543 五、發明說明（13) 一部份變成圖15 A的區域85。再者，示於圖13 A的區域51的 另一部份變成圖1 5A的區域86。又，示於圖1 4B的區域69變 成圖1 5 B的區域7 5。同樣地，示於圖1 4 B的區域5 4變成圖 1 5 B的區域8 7。此外，示於圖1 4 B的區域5 3變成圖1 5 B的區 域88。再者，示於圖14B的區域65變成圖15B的區域89。 最後，示於圖13A及圖14B的區域7卜72分別變成圖15A及 圖15 B的區域79(a)、79(b)。於此之後，石夕金屬化及後端 製程完成程序（未繪示）。 一種製造裝置1、2的方法繪示於圖1 6的流程圖，其中 此方法包含形成100STI區域35鄰接一 SOI晶圓20，其中SOI 晶圓20具有一 NFET區域51及一 PFET區域53，且其中淺溝渠 隔離區域3 5具有一大體為圓形的角37。接下來的步驟包含 形成110—閘極結構40於SOI晶圓20，執行120 N-延伸及N-環植入於SOI晶圓之NFET區域51，且執行130 P-延伸及p-環植入於SOI晶圓之PFET區域53。之後，一非磊晶植入層 6 5，較佳為包含多晶石夕及非晶石夕之其一，係於一極小溫度 約620°C或更低之溫度，沉積於SOI晶圓上。製程的下一步 驟涉及植入1 5 0閘極後摻雜植入於裝置1、2。選擇性地， 此方法包含形成1 5 5至少一絕緣間隙壁6 0、6 1鄰接閘極結 構4 0。然後，執行1 6 0 N型及P型源極/汲極植入於植入層 6 5内。最後，裝置1、2歷經回火製程1 7 0係於一升高的溫 度約於9 5 0 - 1 1 5 0°C的範圍。
4IBM03138TW.ptd 第20頁 1255543
如圖1 7所示的流程圖，閘極結構4〇係沉積i丨2一第一 閘極多晶矽層42於絕緣層上矽晶圓2〇上，沉積114一氧化 墊於第一閘極多晶矽層42上，沉積116一犧牲氮化層46 於氧化墊44上，以及沉積！丨8一犧牲第二閘極多晶矽層48 於犧牲氮化層46上。 再者，本發明提供一種製造CMOS裝置卜2的方法，如 圖18之流程圖所示，其中此方法包含沉積2〇〇一 s〇i晶圓2〇 於一埋入式氧化（BOX)基材1 〇上方，其中絕緣層上矽晶圓 2 〇具有一預定厚度。下一步驟涉及形成一閘極介電層2 5於 絕緣層上石夕晶圓2 0上。接下來，形成2 2 〇一淺溝渠隔離區 域3 5於埋入式氧化基材丨〇上，其中淺溝渠隔離區域3 5具有 一大體為圓形的角3 7，且其中閘極介電層2 5係位於較淺溝 渠隔離區域3 5為低。然後，形成2 3 〇一閘極結構4 〇於閘極 介電層2 5上’且一非磊晶植入層6 5沉積2 4 〇於絕緣層上矽 晶圓20上。製程的下一步驟包含執行25〇 n型及p型摻雜質 植入於絕緣層上矽晶圓2 〇及植入層6 5内，以及加熱2 6 0裝 置1、2以自植入層6 5及絕緣層上矽晶圓2 〇形成源極及汲極 區域85、86、88、89，其中源極及汲極區域85、86、88、 89具有一厚度係大於絕緣層上矽晶圓2〇之預定厚度。此方 法更包含形成至少一絕緣間隙壁6〇、61包圍閘極結構40以 及於一升高溫度回火280 CMOS裝置1、2。 本發明提供一種獨特的解決方案，係為形成低溫增高
1255543 五、發明說明（15) 式源極/ j：及極於超簿$ 〇丨、 B ^ ^ ^ 、，β 〇I閘極摻雜、分離源極/汲極及多 曰曰石夕摻雜，以及降低閘極堆聂古 * ^ 及可製造性…本發明卜起為高可用性 徵，以下描述其中一此。；及製程的幾個突出特 二==之間’㊣供一高度差。因為-升高的sn 留=大部分的多晶石夕層65的回蚀刻製程後，保 部份，因此對摻雜質植入提供非蠢晶層 源極/汲極特性，如而夕B & 磊日日為基礎的增同式 及於多曰欲Ρϋ如面、夕日日矽晶粒、氧的面劑濃度、以 石夕芦入依據本發明，非蠢晶增高式源極/汲極多晶 曰5,王範圍地形成於淺溝渠隔離區域35及主動區域上 85、於矽金屬化製程後，源極/汲極區域（全體地為 、8、89)於主動區域79(a)、79(b)間為短路。 本發月般以下列方式操作。以圖1 5 Α中的N F Ε Τ裝置1 、、电仏旎於源極/汲極區域7 9 (a )、7 9 ( b)進入，且 f f通道區域2 0到達互補的汲極/源極區域7 9 ( a )、7 9 b °因此’本發明作用與傳統的電晶體作用一樣。然 =备褒置^ 2包含一 STI區域35係具有一大體為圓形 ' >成於一 BOX^及一閘極介電介面25上方，係作為 日1和4 0及源極/沒極區域7 $、8 5、8 6間的傳導屏障。本^ 明之獨特特徵為ST I區域3 5之上表面3 6係結構性地高於 閘極介雷八 w々、 "面2 5。如此為有益的，因為於製程期間，升高
1255543 五、發明說明（16) 的心溝ίκ隔離區域3 5允终即使在後續回钱刻製程移除大部 分的多晶矽層65後，仍保留部分的多晶矽層65。如此實質 上允許一非磊晶基礎製程，有益於去除摻雜質的瞬間增強 擴散效應，並且減少短通道效應，如臨界電壓（v t卜）下 滑。此外，一大體為曲化的ST I角3 7降低在多晶係沉積後 剩餘在S T I上的多晶石夕殘留物的量，藉此改進元件性能。 、本發明達到以下的優點。本發明藉由形成無需磊晶的 增高式源極/汲極，解決所有於超薄絕緣層上矽之CMOS的 選擇性磊晶增高式源極/汲極的基本問題。同時，本發明 利用於源極/没極上之多晶矽為緩衝層，後摻雜多晶矽閘 極。再者’本發明係利用與增高式源極/汲極多晶矽平坦 化相同的化學機械研磨，導致多晶矽閘極高度的降低。 者，對高性能邏輯CM0S裝置的製造，本發明達成於超 緣層上矽之增高式源極/汲極，其係具有較習知閘極結構 更積極的尺1。此外，本發提供一種隔離源極/汲極^極 的方法，係藉由階梯化淺溝渠隔離且利用淺溝渠隔 為標記回蝕刻多晶矽。此外，本發明提供一種解決盎= 淺溝渠隔離邊緣之階梯狀角的多晶矽執相關的問題，、、、’ 墊氧化層蚀刻及襯層氧化時圓化此角。 ’、於 綜上所述之優點，本發明利用SO I基材藉經由於非A 低的溫度建造增高式源極/汲極區域，使能製造最大二 能的CM0S裝置，因此完全地避免許多問題，如在薄S0I上
1255543
五、發明說明（17) 形成金屬矽化物、短通道降級，以及高、、W +啊± w /皿之選擇性吞日辦 高式源極/汲極製程於磊晶基材介面所引如μ 曰 問題等。 "起的缺陷相關的 以上所述僅為本發明之較佳實施例 ^ 之人士應明瞭凡其它未脫離本發明所揭干 t f此技術 丨判不之精神下所完成 之等效改變或修飾，均應包含在下述之申&奎^ 、肀喷專利範圍内。 此外’為使容易瞭解本發明，於圖式中僅繪示一半的CM0S 裝置1、2 (例如，僅緣示源極或沒極區域）。熟習技術之人 士應明白實際上每一裝置1、2存在著鏡像結構（例如，對 應的沒極或源極區域分別存在於閘極結構4 0的另一侧）。
4IBM03138TW.ptd 第24頁 1255543 圖式簡單說明 五、【圖式簡單說明】 本發明由較佳實施例的詳細說明配合圖式可更加的了 解： 圖1 A係本發明CMOS裝置之部分完成NFET元件之示意 圖， 圖1B係本發明CMOS裝置之部分完成PFET元件之示意 圖； 圖2A係本發明CMOS裝置之部分完成NFET元件之示意 圖， 圖2B係本發明CMOS裝置之部分完成PFET元件之示意 圖； 圖3A係本發明CMOS裝置之部分完成NFET元件之示意 回 · 圖， 圖3B係本發明CMOS裝置之部分完成PFET元件之示意 圖； 圖4A係本發明CMOS裝置之部分完成NFET元件之示意 圖， 圖4B係本發明CMOS裝置之部分完成PFET元件之示意 圖； 圖5A係本發明CMOS裝置之部分完成NFET元件之示意 圖； 圖5B係本發明CMOS裝置之部分完成PFET元件之示意 圖； 圖6A係本發明CMOS裝置之部分完成NFET元件之示意
4IBM03138TW.ptd 第25頁 1255543 圖式簡單說明 圖； 圖6B係本發明CMOS裝置之部分完成PFET元件之示意 圖， 圖7A係本發明CMOS裝置之部分完成NFET元件之示意 圖； 圖7B係本發明CMOS裝置之部分完成PFET元件之示意 圖； 圖8A係本發明CMOS裝置之部分完成NFET元件之示意 圖； 圖8B係本發明CMOS裝置之部分完成PFET元件之示意 圖； 圖9A係本發明CMOS裝置之部分完成NFET元件之示意 圖； 圖9B係本發明CMOS裝置之部分完成PFET元件之示意 圖， 圖10A係本發明CMOS裝置之部分完成NFET元件之示意 圖， 圖10B係本發明CMOS裝置之部分完成PFET元件之示意 圖； 圖11 A係本發明CMOS裝置之部分完成NFET元件之示意 圖； 圖1 1B係本發明CMOS裝置之部分完成PFET元件之示意 圖； 圖12A係本發明CMOS裝置之部分完成NFET元件之示意
4IBM03138TW.ptd 第26頁 1255543 圖式簡單說明 圖， 圖12B係本發明CMOS裝置之部分完成PFET元件之示意 圖； 圖13A係本發明CMOS裝置之部分完成NFET元件之示意 圖； 圖13B係本發明CMOS裝置之部分完成PFET元件之示意 圖， 圖14A係本發明CMOS裝置之部分完成NFET元件之示意 圖， 圖14B係本發明CMOS裝置之部分完成PFET元件之示意 S3 · 圖， 圖1 5A係本發明CMOS裝置之NFET元件之示意圖； 圖15B係本發明CMOS裝置之PFET元件之示意圖； 圖1 6係本發明一較佳實施方法之流程圖； 圖1 7係本發明一較佳實施方法之流程圖；以及 圖1 8係本發明一較佳實施方法之流程圖。 圖式元件符號說明 1 CMOS裝置 2 CMOS裝置 10 埋入式氧化基材 15 氮化/氧化/絕 20 絕緣層上矽晶圓 25 閘極介電層 26 通道區域 30 氮化層 35 淺溝渠隔離區域 36 上表面 37 圓角 40 閘極
4IBM03138TW.ptd 第27頁 1255543
圖式簡單說明 42 多晶矽層 44 氧化層 46 氮化層 48 緩衝仿多晶矽層 50 絕緣層 51 N型未回火摻雜區域 52 P型未回火摻雜區域 53 P型未回火摻雜區域 54 N型未回火摻雜區域 55 帽蓋層 60 間隙壁 61 間隙壁 65 植入層 66 N型未回火摻雜區域 67 N型未回火摻雜區域 68 P型未回火摻雜區域 69 P型未回火摻雜區域 71 N型未回火摻雜區域 72 P型未回火摻雜區域 73 N-型活化摻雜區域 74 P-型活化摻雜區域 75 P-型活化摻雜區域 79(a： 1源極/沒極區域 79(b： >源極/汲極區域 85 N -型活化摻雜區域 86 N-型活化摻雜區域 87 N-型活化摻雜區域 88 P-型活化摻雜區域 89 P-型活化摻雜區域 4IBM03138TW.ptd 第28頁

Claims (1)

1255543 六、申請專利範圍 1 ·一種增高式源極/汲極（RSD)之絕緣層上矽（SOI )電晶體 裝置，包含： 一埋入式氧化（BOX)層； 一絕緣層上矽晶圓於該埋入式氧化層上； 一閘極介電層於該絕緣層上矽晶圓上； 一閘極區域於該閘極介電層上； 一植入層鄰接該絕緣層上石夕晶圓，該植入層包一沉積 的材料， 源極/汲極區域於該植入層及該絕緣層上矽晶圓上 方；以及 一淺溝渠隔離（ST I )區域鄰接該源極/汲極區域，其中 該淺溝渠隔離區域具有一上表面係高於該閘極介電層之一 上表面。 2 .如申請專利範圍第1項所述之裝置，更包含至少一絕緣 間隙壁包圍該閘極區域。 3 .如申請專利範圍第1項所述之裝置，其中該絕緣層上矽 晶圓具有一預定厚度，且該源極/汲極區域具有一厚度係 大於該絕緣層上矽晶圓之該預定厚度。 4.如申請專利範圍第3項所述之裝置，其中該淺溝渠隔離 區域具有大體為圓形的角，其中該淺溝渠隔離區域鄰接 (b 〇 r d e r s )該源極/汲極區域。
4IBM03138TW.ptd 第29頁 1255543 六、申請專利範圍 5.如申請專利範圍第1項所述之裝置，其中該摻雜質層包 含多晶矽及非晶矽之一。 6 .如申請專利範圍第1項所述之裝置，其中該源極/汲極區 域無蟲晶相關的缺陷。 7. 如申請專利範圍第1項所述之裝置，其中該源極/汲極區 域包含一非蠢晶材料。 8. —種互補式金氧半導體（CMOS)裝置，包含： 一埋入式氧化層； 一絕緣層上矽晶圓於該埋入式氧化層上，該絕緣層上 矽晶圓具有一預定厚度； 一閘極結構於該絕緣層上矽晶圓上； 一閘極介電層於該閘極結構及該絕緣層上矽晶圓之 間，該閘極介電層位於該埋入式氧化層上之一第一高度； 一植入層鄰接該絕緣層上矽晶圓，該植入層包一沉積 的材料， 源極/汲極區域於該植入層及該絕緣層上矽晶圓内， 其中該源極/汲極區域具有一厚度係大於該絕緣層上矽晶 圓之該預定厚度；以及 一淺溝渠隔離區域具有大體為圓形的角且位於該埋入 式氧化層上方，其中該淺溝渠隔離區域之一上表面係高於
4IBM03138TW.ptd 第30頁 1255543 六、申請專利範圍 該埋入式氧化層上之該第一高度。 9.如申請專利範圍第8項所述之CMOS裝置，更包含至少一 絕緣間隙壁包圍該閘極結構。 1 0 .如申請專利範圍第8項所述之CMOS裝置，其中該絕緣層 上矽晶圓之該預定厚度係小於5 5奈米。 11. 如申請專利範圍第8項所述之CMOS裝置，其中該源極/ 汲極區域之該厚度係於2 0 0 _ 3 0 0埃之範圍。 12. 如申請專利範圍第8項所述之CMOS裝置，其中該摻雜質 層包含多晶矽及非晶矽之一。 13. —種形成一互補式金氧半導體（CMOS)裝置之方法，該 方法包含： 沉積一絕緣層上矽（SOI )晶圓於一埋入式氧化（BOX)基 材上方，其中該絕緣層上矽晶圓具有一預定厚度； 形成一閘極介電層於該絕緣層上矽晶圓上； 形成一淺溝渠隔離（ST I )區域於該埋入式氧化基材 上，其中該淺溝渠隔離區域具有一大體為圓形的角； 形成一閘極結構於該閘極介電層上； 沉積一植入層於該絕緣層上矽晶圓上； 執行N型及P型之其一的摻雜質植入於該絕緣層上矽晶
4IBM03138TW.ptd 第31頁 1255543 六、申請專利範圍 圓及該植入層内；以及 加熱該裝置以自該植入層及該絕緣層上矽晶圓形成源 極及汲極區域，其甲該源極及汲極區域具有一厚度係大於 該絕緣層上矽晶圓之該預定厚度； 其中該閘極介電層位於較該淺溝渠隔離區域為低。 1 4.如申請專利範圍第1 3項所述之方法，更包含形成至少 一絕緣間隙壁包圍該閘極結構。 1 5 .如申請專利範圍第1 3項所述之方法，其中該植入層包 含多晶矽及非晶矽之一。 1 6 .如申請專利範圍第1 3項所述之方法，其中該閘極結構 之形成包含： 沉積一第一閘極多晶矽層於該絕緣層上矽晶圓； 沉積一氧化墊於該第一閘極多晶矽層上； 沉積一犧牲氮化層於該氧化墊上；以及 沉積一犧牲第二閘極多晶矽層於該犧牲氮化層上。 1 7.如申請專利範圍第1 3項所述之方法，其中該絕緣層上 矽晶圓之該預定厚度係小於5 5奈米。 1 8.如申請專利範圍第1 3項所述之方法，其中該源極/汲極 區域之該厚度係於2 0 0 - 3 0 0埃之範圍。
4IBM03138TW.ptd 第32頁
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