CN100388426C - 半导体mos、cmos器件和电容器及其制造方法 - Google Patents
半导体mos、cmos器件和电容器及其制造方法 Download PDFInfo
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- CN100388426C CN100388426C CNB2004800124954A CN200480012495A CN100388426C CN 100388426 C CN100388426 C CN 100388426C CN B2004800124954 A CNB2004800124954 A CN B2004800124954A CN 200480012495 A CN200480012495 A CN 200480012495A CN 100388426 C CN100388426 C CN 100388426C
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Abstract
本发明包括形成电路器件的方法。厚度不超过20埃(或者说由不超过70个ALD周期形成的厚度)的含金属材料在经导电掺杂的硅和介质层之间形成。经导电掺杂的硅可以为n-型硅,介质层可以为高k介质材料。含金属材料可直接在介质层上形成,经导电掺杂的硅可直接在含金属材料上形成。电路器件可为电容器结构或晶体管结构。如果电路器件是晶体管结构,则该电路器件可包含在CMOS组件内。本发明的各种器件可被包含在存储结构内,并且可被包含在电子系统中。
Description
技术领域
[0001]本发明涉及晶体管器件(包括n沟道金属-氧化物半导体(NMOS)器件和p沟道金属-氧化物半导体(PMOS)器件)和互补型金属-氧化物半导体(CMOS)结构。本发明还涉及制造电容器、晶体管器件和CMOS结构的方法。在一些特定形态中,本发明涉及包含晶体管器件、电容器结构和/或CMOS组件的存储器,并且在某些形态中本发明涉及动态随机存取存储器(DRAM)。在一些特定形态中,本发明涉及包含电容器结构、晶体管器件和/或CMOS组件的电子系统。
发明背景
[0002]可能存在着与各种半导体结构(包括如晶体管器件和电容器)中高k栅介质材料的使用相关联的优势。可将高k介质理解为介电常数比二氧化硅大的介质材料,包括如Ta2O5、Al2O3和许多的其它材料。
[0003]过去试图将高k介质材料合集成到标准CMOS流中的作法曾经引起大家的一些兴趣。然而,当这种高k介质材料和代表CMOS结构的硅栅电极一起使用时会带来一些困难。例如,通常直接在高k栅介质薄膜上淀积硅(例如多晶硅)会在硅和介质交界面处形成一个反应层。该反应层可能在硅淀积期间和/或接下来的硅高温退火期间出现。反应层在硅和介质材料之间生成一个界面薄膜(如硅酸盐)。这个界面层减小了介质叠层的有效介电常数,因而限制了介质的可量测性。另外,部分由于金属原子d的状态和带电原子的缺陷,该界面层可以是电荷截获/固定电荷的源。电荷截获/固定电荷可受到栅后退火的影响,并可导致晶体管器件临界电压的无法控制的改变。另外,由于从p-型导电掺杂的硅进入高k栅介质的硼扩散,临界电压可改变。对于高热堆积处理(如存储单元处理)来说,这种临界电压的改变可能会特别明显并难以解决。尽管与高k薄膜的使用有关的介质厚度增加,但是通过介质的硼扩散可能会是一个问题。
[0004]针对上面讨论的原因,最好是开发出将高k介质材料结合到CMOS流中的新方法。另外,因为高k介质材料被用于除CMOS组件之外的其它半导体结构,所以假如该方法可应用于除CMOS流之外的其它半导体的制造,尤其是假如该方法可应用于电容器的制造,那将是最理想的。此外,如果该方法不仅可应用于高k介质材料还可应用于其它介质材料,那就很最理想了。
发明内容
[0005]在一形态中,本发明包括一种形成电路器件的方法。介质层在衬底上构成,含金属的材料(例如包含有金属元素、金属硅化物和/或金属氮化物的材料;含有金属如钨、铪、钽、钛元素中的一种或多种)直接在介质层上构成。所构成的含金属的材料厚度不超过20埃。随后,导电掺杂硅可直接在含金属的材料上构成。电路器件可以是如晶体管器件或电容器。
[0006]在另一形态中,本发明包括一种构成晶体管器件的方法。栅介质在衬底上构成。含金属的材料在介质上构成,所构成的含金属的材料厚度不超过20埃。导电掺杂硅在含金属的材料上形成,随后含金属的材料和导电掺杂硅经过图案处理形成栅叠层。接着,在靠近栅叠层的地方设置源/漏区。
[0007]在另一形态中,本发明包括一个CMOS。该CMOS包括一个位于衬底上的介质层。PMOS栅极和NMOS栅极位于介质层上。第一含金属材料位于介质层上的PMOS栅极内,其厚度大于20埃,更典型的厚度大于150埃。第二含金属材料位于介质层上的NMOS栅极内,其厚度小于或等于约20埃。n-型掺杂硅的第一层位于PMOS栅极内及第一含金属材料上,n-型掺杂硅的第二层位于NMOS栅极内及第二含金属材料上。
[0008]在另一形态中,本发明包括一个电容器结构。该结构包括第一电容器电极,第一电容器电极包括导电掺杂硅。介质层靠近第一电容器电极,第二电容器电极相对于第一电容器电极位于介质层的另一端。含金属材料位于第一电容器电极的经导电掺杂的硅和介质层之间。该含金属材料的厚度小于或等于约20埃。
[0009]可以将本发明的各种不同结构结合进存储器件(如DRAM器件)。此外,可以将本发明的各种不同结构包含在电子系统内。
附图简述
[0010]下面,将参考下列附图对本发明的优选实施例进行描述。
[0011]图1是关于在氧化铝和多晶硅之间含有原子层淀积(ALD)形成的氮化钛的各种不同结构的电容-电压曲线图。氮化钛层的厚度在曲线图中的插入框内给出,插入框中指明了下列情形下的曲线线型:无钛层存在,或者在形成氮化钛层的过程中利用了特定数目的ALD周期,或者有厚度为100埃的氮化钛层存在。每个ALD周期对应于约0.3埃至0.4埃的氮化钛生长率(growth rate)。
[0012]图2是关于预处理阶段半导体晶圆结构的断片示意图,图中显示了一对晶圆结构的断片。
[0013]图3显示的是图2所示晶圆断片在图2预处理过程之后的处理阶段的晶圆结构。
[0014]图4显示的是图2所示晶圆断片在图3处理过程之后的处理阶段的晶圆结构。
[0015]图5显示的是图2所示晶圆断片在图4处理过程之后的处理阶段的晶圆结构。
[0016]图6显示的是图2所示的晶圆断片在图5处理过程之后的处理阶段的晶圆结构。
[0017]图7显示的是关于本发明另一实施例的半导体晶圆断片的剖面图,图中所示为一个DRAM单元。
[0018]图8是说明本发明应用示例的计算机示意图。
[0019]图9显示的是图8所示计算机主板的特定特征的框图。
[0020]图10显示的是本发明的一例电子系统的高级框图。
[0021]图11显示的是本发明的一例电子系统的简化框图。
优选实施例的详细说明
[0022]在本发明的一形态中,判明:将介质材料和经导电掺杂的硅之间的含金属材料加入CMOS结构的NMOS和PMOS器件可能是有益的。另外,判明PMOS器件中使用的含金属材料实质上比NMOS器件中使用的含金属材料厚(PMOS器件中含金属材料厚度大于20埃,通常大于100埃,甚至大于或等于150埃)可能是有益的,而NMOS器件中使用的含金属材料较薄。在NMOS器件中使用的含金属材料通常不超过20埃,常常小于或等于约15埃,甚至小于或等于约10埃。或者认为,在NMOS器件中使用的含金属材料通常由不超过70个原子层淀积(ALD)周期形成,常常少于50个ALD周期,甚至少于40个ALD周期;本发明应用中使用的典型ALD包括每个周期大约0.3埃至0.4埃的淀积率。然而,将会了解到:本发明可利用具有与每个周期大约0.3埃至0.4埃不同的淀积率的ALD。因为在NMOS器件中使用的含金属层较薄,因此它可以是不连续的,仍适合于本发明的特定应用。
[0023]在一些特定形态中,含金属材料包含钛、铪、钽或钨。示例含金属材料包括/基本上包括/由以下部分组成:钛、铪、钽和钨元素中的一种或多种和/或钛、铪、钽或钨中的一种或多种组成的氮化物和硅化物中的一个或多个。在某些形态中,可以期望含金属材料包括/基本上包括/由以下部分组成:氮化钽、氮化钨、氮化铪和氮化钛中的一个或多个。
[0024]在特定应用中,在介质材料和掺杂硼的多晶硅之间使用含金属材料可以减少甚至可阻止硼向外扩散进介质材料。此外,可选择特定的含金属材料(例如带有适当的、由氮化钛和氮化钨组成的含金属材料),这样,含金属材料和p-型硅的功函数之间的相似性导致一个可忽略的PMOS器件临界电压的变化。另外,在高k介质和多晶硅材料之间使用这种含金属材料可减少甚至可防止硅酸盐界面层的形成,因为若硅直接与介质材料接触,就会产生该硅酸盐。
[0025]尽管在PMOS栅极中使用带有与p-型掺杂硅相似功函数的含金属材料可能是最好的,但是这种含金属材料的功函数在NMOS栅极中可能有问题。例如,氮化钛是一种含金属材料,其功函数与p-型掺杂硅的功函数相似,并且相对于缺少氮化钛的栅极而言,较厚的氮化钛层将使NMOS临界电压产生将近1伏的变化。通过在NMOS栅极中使用一种功函数与在PMOS栅极中使用的含金属材料的功函数不同的含金属材料可以避免这个问题。然而,可能是n-型硅的适当替代品的功函数较低的金属在高温时往往不稳定。因此,这种金属不适于半导体器件制作期间典型的热处理状态。
[0026]本发明的一个形态是在NMOS器件内使用非常薄的含金属材料阻挡层(几个单原子层或更薄),并且其中含金属材料的功函数实质上不同于n-型硅的功函数。含金属材料被放置于硅与介质材料(如氧化铝这样的高k介质)之间。含金属材料最好足够薄,以避免n-型硅和含金属材料的组合功函数完全占优势;但是又充分厚,以缓和甚至阻止硅与介质材料之间的反应。通过缓和硅与介质材料之间的反应,可以避免现有技术水平下、在硅和高k介质材料的界面处截获电荷的问题,这可使NMOS器件的临界电压更可控。
[0027]可采用任何适当的方法(包括如原子层淀积(ALD)和/或化学汽相淀积(CVD))形成在NMOS器件中使用的薄含金属材料阻挡层。原子层淀积可能是最好的,因为这样可以对含金属材料的厚度和均匀性实施更好的控制,而且可缓和甚至阻止对表面以下的介质的损害以及表面以下的介质与含金属材料进行直接物理接触时所发生的相互作用。
[0028]通常含金属材料直接在介质材料上形成。用语“直接在......上”意指:如果含金属材料是通过CVD形成的,则含金属材料是与介质材料通过物理接触而形成的;或者如果过程是ALD,则在含金属材料的形成过程中使用的层是在与介质材料进行物理接触时沉积形成的。在某些实施形态中,在形成含金属材料块之前就可在介质材料块上形成界面层,并且含金属材料可在界面层上形成。界面层可包括如氮化物(例如氮化硅或氮化铪)。例如,可以通过对特定介质材料进行表面氮化处理来形成氮化物。
[0029]可通过任何适当的方法(包括如化学汽相淀积)在含金属材料上形成硅。增强导电性的掺杂物可于淀积期间在硅内形成或者是在淀积后与适当的注入物一起形成。
[0030]硅直接在含金属材料上形成(术语“直接在......上”表示:如果过程是化学汽相淀积,则硅是与含金属材料进行物理接触而形成的。)可以使硅和含金属材料发生反应,以此形成含金属和硅的合成材料,例如:包含钛、氮和硅的材料(TiNxSiy,其中x和y均大于0);包含铪、氮和硅的材料;包含钨、氮和硅的材料;或者包含钽、氮和硅的材料。如果合成材料包含钛、氮和硅,则这种材料的功函数介于硅化钛和氮化钛的功函数之间。文献资料表明:硅化钛和氮化钛的功函数范围分别是3.67-4.25电子伏特和4.83-4.95电子伏特。
[0031]图1显示的是高频电容/电压数据,表示通过原子层淀积形成的氮化钛阻挡层的厚度对平带电压(Vfb)的影响。厚度为100埃的氮化钛阻挡层展示了成块氮化钛的功函数并且在闪光(flash)晶体管试验中被证明是与PMOS临界电压相匹配的。氮化钛薄膜变薄至15个ALD周期(估计约为5埃至7埃厚),可将Vfb改变负300毫伏。另外,Vfb可能随着氮化钛阻挡层的进一步变薄而改变。图1的数据表明:相对于在氧化铝上使用氮化钛,原子层淀积氮化钛的5个周期并无明显的影响。事实上,由3个周期形成的氮化钛和由5个周期形成的氮化钛的电容/电压曲线与不带居间氮化钛阻挡层而是直接在氧化铝上形成的多晶硅栅的电容/电压曲线是完全一样的。延伸开的电容/电压曲线表示界面状态的增加。这与累积电容的减少一起支持了在不存在氮化钛的条件下或者在由5个或更少ALD周期(所示的ALD周期与氮化钛每个周期约0.3-0.4埃的增长率相对应)形成的氮化硅存在的条件下界面硅酸盐层的形成。
[0032]将参考图2-7对本发明的一个示范形态进行描述。先看图2,所示的半导体结构10包括第一断片12和第二断片14。断片12和14分别与NMOS区域和PMOS区域相对应,并且可以一起包含到CMOS结构内。
[0033]结构10包括衬底16,所述衬底16在NMOS区域12为p-型掺杂、在PMOS区域14为n-型掺杂。衬底16例如可包括单晶硅。为了对后续的权利要求的解释有所帮助,术语“半导体的衬底”和“半导体衬底”的定义为包含半导体材料的任何结构,包括(但不限于)成块半导体材料,如半导体晶圆(单一或其上包含有其它材料的组合);还包括半导体材料层(单一或包含有其它材料的组合)。术语“衬底”指任何支撑结构,包括(但不限于)上述的半导体衬底。
[0034]介质材料18在衬底16上延续。如图所示,介质材料18包括一对独立层,下面的薄层20直接在衬底16的上表面形成,上面的厚层22在薄层20上形成。薄层20可包括如二氧化硅,并且在特定的应用中薄层20可与在单晶体衬底16上表面形成的自然氧化物相对应。介质材料22可对应于任何适当的介质材料,包括如高k介质材料。例如,层22可包括一种或多种氧化物和/或一种或多种硅酸盐。在特定的应用中,层22将包括钽、铪和铝中的一种或多种。例如,层可包括钽的氧化物(如Ta2O5)、铝的氧化物(Al2O3)、氧化铪和/或硅酸铪;在某些应用中,层可包括多层不同材料(如Al2O3/HfO2等)。例如,多层可以是纳米叠层(nanolaminates)。尽管所示的介质材料18包括两个独立层,但是还要了解:材料可包括单层或者可包括不止两个独立层。在特定的处理中,可省略二氧化硅层20,并且可将高k介质材料用作介质层18的实体。在其它形态中,整个介质材料可以是除高k材料以外的材料,如二氧化硅。
[0035]含金属材料层24在介质材料22上方形成,在所示的实施例中含金属材料层24实际上对着介质材料22形成,或者换句话说,含金属材料层24直接在介质材料22上形成。含金属层24可被称为厚含金属层或第一含金属层,以此将层24与随后形成的含金属层区别开来。可通过任何适当的方法(包括如化学汽相淀积)形成含金属层24。层24的金属可包括如钛、钽、钨或铪。在一些特定形态中,层24可包括/基本上包括/由以下部分组成:钛、钽、钨或铪元素中的一种或多种;或者层24可包括/基本上包括/由以下部分组成:钛、钽、钨或铪中的一种或多种的氮化物和/或硅化物。所形成的层24的厚度大于20埃,并且通常其厚度大于100埃,比如大于或等于150埃。
[0036]参见图3,对层24进行图案处理,使层24的材料位于PMOS区域14上而不是位于NMOS区域12上。对层24的图案处理使该层的材料形成块(block)。这种图案处理可通过如下方法完成:通过光刻加工在层24上形成经图案化的光刻胶掩模(图中未示出),对层24实施适当的蚀刻以此将图案从掩模转移到材料层,然后剥去光刻胶掩模。图2和图3所示的过程只是可用来在PMOS区域14上而不是在NMOS区域12上形成含金属材料块(图3中保留了层24的部分)的若干方法中的一种。
[0037]参见图4,叠层30、32、34和36在NMOS区域12和PMOS区域14上形成。层30包括含金属材料,并且其厚度小于或等于约20埃。层30可称为第二含金属层,以此将该层和第一含金属层24区分开来。在所示的本发明的实施例中,在NMOS区域12上,层30实际上对着介质材料22形成,在PMOS区域14上,层30实际上对着第一含金属层24形成。例如可以通过原子层淀积形成含金属层30,并且其形成厚度可小于或等于约15埃,在一些特定形态中,该形成厚度可小于或等于约10埃;或者,所形成的层可以是小于或等于约50个ALD周期,或者小于或等于约30个ALD周期。第二含金属层30可具有与第一含金属层24相同或不同的成分。含金属层30可主要包括氮化钛(即,按重量计算,含金属层30中超过50%可能是氮化钛)。另外,含金属层30可主要包括氮化钽、氮化钨或氮化铪。在一些特定形态中,层30可包括/由或基本上由一些部分组成:钛、钽、钨和铪元素中的一种或多种;以及,层30可包括/基本上包括/由以下部分组成:钛、钽、钨和铪中的一种或多种的氮化物和/或硅化物。
[0038]层32包括/基本上包括/由以下部分组成:经导电掺杂的硅(如导电掺杂非晶形硅或导电掺杂多晶硅)。在所示出的本发明的形态中,含硅层32实际上与含金属层30相对而置。此外,在所示出的本发明的实施形态中,相同的经导电掺杂的硅层在NMOS区域和PMOS区域上延续。因此,如果导电掺杂层32主要是n-型掺杂,则这种材料被用于NMOS区域和PMOS区域。还将了解到:本发明可包含其它实施形态(图中未示出),其中相对于NMOS区域,PMOS区域可使用不同的导电掺杂材料,或者NMOS区域和PMOS区域中的一个省略经导电掺杂的硅材料。然而,所示的本发明的实施形态可以被优选,因为若相同的经导电掺杂的硅在整个衬底的NMOS区域和PMOS区域上形成,该形态可简化加工工序。
[0039]层34可包含如金属和/或金属合金;在一些特定形态中,层34将包含钨。
[0040]层36可包含一个电绝缘盖(如氮化硅)。
[0041]参见图5,对层30、32、34和36进行图案化处理,以此分别在NMOS区域12和PMOS区域14上形成栅叠层40和42。叠层40和42的经图案化的材料可分别称为第一材料和第二材料,以此区分特定叠层内的材料。例如,可将经图案化的硅层32称为叠层40内的第一硅材料和叠层42内的第二硅材料。
[0042]叠层40和42之间显著的差别是:栅叠层40只带有一个位于经导电掺杂的硅层32和介质材料22之间的薄层含金属材料30,而栅叠层42除了带有一个薄层含金属材料30之外还带有一个位于经导电掺杂的硅层32和介质材料之间的厚层含金属材料24。
[0043]栅叠层42内位于经导电掺杂的硅层32和介质材料22之间的含金属材料最好足够厚,这样栅叠层42的功函数与单纯形式的含金属材料的功函数相当。相反,栅叠层40内的含金属材料最好足够薄,这样叠层40的功函数不等于单纯形式的含金属材料的功函数,而是被经导电掺杂的硅层32所调制。然而,含金属材料层30最好足够厚,这样叠层40的功函数也不等于单纯形式的经导电掺杂的硅层32的功函数,而是介于单纯形式的含金属材料和单纯形式的经导电掺杂的硅的功函数之间。在一些特定形态中,相对于以单纯形式出现的经导电掺杂的硅和含金属材料的功函数,在NMOS叠层40内合并的经导电掺杂的硅层32和含金属材料层30的功函数被改变,并且比起单纯形式的含金属材料的功函数至少改变了50毫伏。
[0044]在NMOS栅叠层40的功函数包括了来自经导电掺杂的硅层32的影响的应用中,材料32的多数掺杂类型一般为n-型。
[0045]由于PMOS栅叠层42的功函数事实上是含金属材料24的功函数,所以对于栅叠层的功函数,硅层32的导电型掺杂是无关的。因此,对层32来说,PMOS栅叠层42既可包含n-型硅也可包含p-型硅。然而,最好栅叠层利用n-型硅作为叠层42的硅。接着,如图4所示的加工过程,叠层42的硅可与叠层40的硅在单个步骤中一起形成。
[0046]栅叠层40由层30、32、34和36形成,可认为是将这些层的材料加入NMOS栅叠层而形成的。同样地,栅叠层42由层24、30、32、34和36形成,可认为是将这些层的材料加入PMOS栅叠层而形成的。
[0047]在本发明的特定实施形态中,可将栅叠层40和42下的区域分别称为NMOS栅区和PMOS栅区。此外,可将栅叠层40和42下的介质材料20和22视为本发明特定实施形态中的栅介质层。
[0048]与含金属层30接触的层32的硅可以和本发明各实施形态中的含金属材料发生反应,以此在硅和含金属材料的界面处形成包含有金属、硅且可能还有氮的合成物。这种合成物的功函数介于金属硅化物和含金属材料的功函数之间,并且在NMOS栅极40的场合,这种功函数最终可影响栅叠层的总功函数。
[0049]参见图6,侧壁隔层46和48分别沿栅叠层的两个侧壁形成。隔层46和48可包括任何适当的绝缘材料(包括如氮化硅和二氧化硅中的一种或两种),并且可在材料的各向异性蚀刻过程之后通过适当的材料淀积来形成。
[0050]N-型源/漏区50在衬底16内靠近栅叠层40处形成,从而完成NMOS晶体管器件的形成;p-型源/漏区52在衬底16内靠近栅叠层42处形成,从而完成PMOS晶体管器件的形成。源/漏区50和52可通过任何适当的方式形成(包括如发生在侧壁隔层46和48形成前和/或后的各种注入)。
[0051]尽管对图2至图6加工过程的描述以NMOS晶体管和PMOS晶体管的形成(即CMOS结构的形成)为参照进行,但是将会了解到本发明的各个实施形态也适用于单个晶体管的形成。例如,图6所示类型的NMOS晶体管可单独形成,以包含到各种电路器件内。
[0052]上述的形成NMOS晶体管器件的加工过程可用于其它器件(包括如电容器)的形成。这一点可参见图7来说明,图7显示了包含DRAM单元102的结构100。DRAM单元包含具有与电容器结构106以及位线130电连接的源/漏区107的晶体管结构104。
[0053]晶体管结构104以NMOS结构示出。因此,源/漏区107是n-型掺杂区域。源/漏区延续进p-型衬底108。衬底108可包括任何适当的结构(包括如单晶硅)。晶体管器件104还包括一个导电栅110,该导电栅110与衬底108之间被栅介质112隔开。栅介质112可包含任何适当的材料(包括如二氧化硅和/或高k介质材料)。导电栅材料110可包含任何适当的材料或这些材料的组合。在一些特定实施形态中,图7的NMOS晶体管器件将与图6所示的NMOS器件相对应,因此栅极110将包含层30、32和34。在其它实施形态中,栅极110可包含传统结构。
[0054]绝缘盖114在导电栅材料110上形成,绝缘的侧壁隔层116沿导电栅材料的侧壁形成。盖114和隔层116可包含任何适当的材料(例如包括二氧化硅和氮化硅中的一种或两种)。
[0055]电绝缘材料118在晶体管器件104上方及周围延续。绝缘材料118可包括一种或多种适当的材料(例如包括硼磷酸盐玻璃(BPSG))。
[0056]有一个通路穿过材料118延伸到源/漏区107中的一个。导电基座120位于通路内,并且与源/漏区电连接。导电基座可包含任何适当的导电材料(例如包括经导电掺杂的硅、金属和/或金属化合物)。
[0057]电容器结构106也在绝缘材料118中的通路内延续,并且与导电基座120电连接。电容器结构106包含存储节点122、介质材料124和含金属材料126。
[0058]存储节点122可包含任何适当的导电材料,例如包括凸凹不平的经导电掺杂的硅(例如半球状颗粒硅)。
[0059]介质材料124可包括任何适当的材料,例如包括高k介质材料(例如上述的、用于图2的介质区域18的高k材料)和/或二氧化硅、和/或二氧化硅与氮化硅的结合物。在一些特定实施形态中,介质材料124可包含氧化铝和二氧化硅,并且二氧化硅是位于存储节点122的经导电掺杂的硅和氧化铝之间的一个薄层(图中未示出)。
[0060]含金属材料126可包括与前述用于含金属材料层30相同的组成,并且含金属材料126可通过例如ALD或CVD形成。
[0061]电容器电极128例如可包含经导电掺杂的硅,并且它既可以是p-型掺杂也可以是n-型掺杂。含金属材料126薄层与电容极板128的经导电掺杂的硅一起使用的好处是可使得包含材料126和128的叠层的功函数可控且可操作。
[0062]尽管所示的含金属材料126位于介质材料124和第二电容器电极128之间,但是将会了解到含金属材料可代之以和/或另外又在介质材料和电容器存储节点122之间形成。
[0063]含有依照本发明方法形成的凸凹不平的半导体材料的电路器件可用于许多系统(例如包括计算机系统和其它电子系统)。
[0064]图8通过举例的方式(但不是以限制的方式)示出本发明一个实施形态的计算机系统400。计算机系统400包含监视器401或其它的通信输出器件、键盘402或其它通信输入器件以及主板404。主板404上载有微处理器406或其它数据处理部件,以及至少一个存储器件408。存储器件408可包括本发明的上述各个形态(例如包括一个或多个晶体管器件、CMOS结构、电容器结构和DRAM单元)。存储器件408可包含存储单元阵列,这样的阵列可与寻址电路连接,用于访问阵列中各存储单元。另外,存储单元阵列可连接到读出电路,以从存储单元读取数据。寻址电路和读出电路可用来在存储器件408和处理器406之间传递信息。这在图9所示的主板404的框图中说明。在这种框图中,寻址电路标示为410,读出电路标示为412。
[0065]在本发明的一些特定实施形态中,存储器件408可与一个存储模块相对应。例如,单列直插式内存组件(SIMM)和双列直插式内存组件(DIMM)可在基于本发明讲述内容的实现方式中使用。该存储器件可结合到能提供从器件的存储单元读取和写入数据的不同方法的多种设计的任何一种中。一种方法是页式操作。DRAM中的页式操作由这样的方法确定:对存储单元阵列进行行访问并对阵列的不同列进行随机访问。当某列被访问时,在行和列交叉点存储的数据即可被读取并输出。
[0066]一个可选的器件类型是扩充数据输出(EDO)存储器,该EDO存储器让存储在存储阵列地址的数据在被寻址列关闭后可供输出。通过允许较短的存取信号,这个存储器可在不减少存储器输出数据占用存储总线时间的条件下提高一些通信速度。其它可选的器件类型包括SDRAM、DDR SDRAM、SLDRAM、VRAM和直接RARAM,以及其它如SRAM或快闪存储器。
[0067]图10是说明本发明一个示范性电子系统700的各实施例的高级组织(high-level organization)的简化框图。系统700可与比如一个计算机系统、一个处理控制系统或任何其它使用处理器和相关存储器的系统相对应。电子系统700具有功能元件,包括:处理器或运算/逻辑部件(ALU)702、控制部件704、存储设备706和输入/输出(I/O)设备708。通常,电子系统700将带有一组本机指令,指定由处理器702对数据实施的操作以及在处理器702、存储设备706和输入/输出设备708之间的其它互动。通过连续循环从存储器件706取出指令并执行的一组操作,控制部件704调整处理器702、存储器706和输入/输出器件708的所有操作。在各种实施形态中,存储设备706包括(但不限于)随机存取存储(RAM)器件、只读存储(ROM)器件以及外围设备(如软盘驱动器和光盘驱动器)。本领域普通的技术人员在阅读和理解了本公开内容后将会了解到:任何所描述的电器件都能包含基于本发明各实施形态的元件而制造。
[0068]图11是本发明一个示范性电子系统800的各种实施例的高级组织的简化框图。系统800包括由存储单元804阵列形成的存储器件802、地址解码器806、行存取电路808、列存取电路810、用于控制操作的读/写控制电路812和输入/输出电路814。存储器件802还包括电源电路816和传感器820(如电流传感器,用于确定一个存储单元是处于低临界导电状态还是处于高临界非导电状态)。所描述的电源电路816包括供电电路880、用于提供基准电压的电路882、用于提供带脉冲的第一字线的电路884、用于提供带脉冲的第二字线的电路886,用于提供带脉冲的位线的电路888。系统800还包括处理器822或用于存储器存取的存储控制器。
[0069]存储器件802从处理器822并经由接线或镀金属线接收控制信号824。存储器件802被用来存储通过输入/输出线存取的数据。本领域的技术人员将会理解:可设置另外的电路和控制信号,且存储器件802已被简化,以有助于将注意点集中到本发明上。处理器822或存储器件802中的至少一个可包含本公开中已描述的类型的DRAM单元、CMOS以及电容器或晶体管。
[0070]本公开所描述的各种系统用以为本发明的电路和结构的各种应用提供一般的了解,并不作为是对本发明所有要素和使用存储单元的电子系统的特征的完整描述。本领域普通的技术人员将理解:为了减少处理器和存储器件之间的通信时间,可在单独封装的处理单元甚至在单个半导体芯片上制作各种电子系统。
[0071]存储单元的应用可包括在存储模块、设备驱动器、功率模块、通信调制解调器、处理器模块和专用模块中使用的电子系统,并可包括多层、多片模块。这样的电路还可包括多种电子系统(如时钟、电视、移动电话、个人电脑、汽车、工业控制系统、飞行器等等)的子部件。
Claims (7)
1.一种形成PMOS器件和NMOS器件的方法,包括:
设置包含PMOS栅区和NMOS栅区的衬底;
在所述衬底的PMOS和NMOS栅区上形成栅介质层;
在所述PMOS栅区上而不在NMOS栅区上形成厚层含金属材料,该厚层含金属材料形成为大于20埃的厚度;所述厚层含金属材料包含钛、钽、钨和铪中的一者或一者以上;
在所述PMOS和NMOS栅区上形成薄层含金属材料,该薄层含金属材料形成为小于或等于20埃的厚度,并且形成在所述PMOS栅区上的所述厚层含金属材料之上;所述薄层含金属材料包含钛、钽、钨和铪中的一者或一者以上;
在所述薄层含金属材料上形成经导电掺杂的硅层,该硅层在整个PMOS和NMOS栅区上延续;
将所述厚层含金属材料、薄层含金属材料和经导电掺杂的硅包含到所述PMOS栅区上的PMOS晶体管栅叠层中;以及
将所述薄层含金属材料和经导电掺杂的硅包含到所述NMOS栅区上的NMOS晶体管栅叠层中。
2.如权利要求1所述的方法,其中,所述经导电掺杂的硅为n-型掺杂。
3.如权利要求1所述的方法,其中,所述栅介质层包含二氧化硅上的氧化铝。
4.一种CMOS,包括:
衬底上的介质层;
所述介质层上的PMOS栅极和NMOS栅极;
所述介质层上的所述PMOS栅极内的第一含金属材料,所述第一含金属材料具有大于20埃的厚度;所述第一含金属材料包含钛、钽、钨和铪中的一者或一者以上;
所述介质层上的所述NMOS栅极内的第二含金属材料,所述第二含金属材料具有小于或等于20埃的厚度;所述第二含金属材料包含钛、钽、钨和铪中的一者或一者以上;
所述第一含金属材料上的所述PMOS栅极内的第一n-型掺杂硅层;以及
所述第二含金属材料上的所述NMOS栅极内的第二n-型掺杂硅层。
5.如权利要求4所述的CMOS,其中,所述介质层包含钽、铪和铝中的一种或多种。
6.如权利要求4所述的CMOS,其中,所述第一含金属材料的厚度为大于或等于150埃,且其中,所述第二含金属材料的厚度小于或等于15埃。
7.一个包括权利要求4所述的CMOS的电子系统。
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Families Citing this family (85)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6613620B2 (en) * | 2000-07-31 | 2003-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
US8026161B2 (en) | 2001-08-30 | 2011-09-27 | Micron Technology, Inc. | Highly reliable amorphous high-K gate oxide ZrO2 |
US6551893B1 (en) * | 2001-11-27 | 2003-04-22 | Micron Technology, Inc. | Atomic layer deposition of capacitor dielectric |
KR100460273B1 (ko) * | 2003-03-25 | 2004-12-08 | 매그나칩 반도체 유한회사 | 모스 바랙터의 제조방법 |
KR100502426B1 (ko) * | 2003-09-18 | 2005-07-20 | 삼성전자주식회사 | 듀얼 게이트를 갖는 반도체 소자 및 그 형성 방법 |
US7904039B2 (en) | 2004-01-30 | 2011-03-08 | UNIVERSITé LAVAL | Multi-user adaptive array receiver and method |
KR100634167B1 (ko) * | 2004-02-06 | 2006-10-16 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US7514360B2 (en) * | 2004-03-17 | 2009-04-07 | Hong Yu Yu | Thermal robust semiconductor device using HfN as metal gate electrode and the manufacturing process thereof |
US6921691B1 (en) * | 2004-03-18 | 2005-07-26 | Infineon Technologies Ag | Transistor with dopant-bearing metal in source and drain |
US8399934B2 (en) * | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
US7592678B2 (en) * | 2004-06-17 | 2009-09-22 | Infineon Technologies Ag | CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof |
US8178902B2 (en) | 2004-06-17 | 2012-05-15 | Infineon Technologies Ag | CMOS transistor with dual high-k gate dielectric and method of manufacture thereof |
US7145208B2 (en) * | 2004-06-25 | 2006-12-05 | United Microelectronics Corp. | MOS transistor having a work-function-dominating layer |
US7081421B2 (en) | 2004-08-26 | 2006-07-25 | Micron Technology, Inc. | Lanthanide oxide dielectric layer |
US7588988B2 (en) | 2004-08-31 | 2009-09-15 | Micron Technology, Inc. | Method of forming apparatus having oxide films formed using atomic layer deposition |
WO2006030522A1 (ja) * | 2004-09-17 | 2006-03-23 | Sharp Kabushiki Kaisha | 薄膜半導体装置及びその製造方法 |
US7344934B2 (en) | 2004-12-06 | 2008-03-18 | Infineon Technologies Ag | CMOS transistor and method of manufacture thereof |
US7560395B2 (en) * | 2005-01-05 | 2009-07-14 | Micron Technology, Inc. | Atomic layer deposited hafnium tantalum oxide dielectrics |
US7297588B2 (en) * | 2005-01-28 | 2007-11-20 | Freescale Semiconductor, Inc. | Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same |
US7508648B2 (en) | 2005-02-08 | 2009-03-24 | Micron Technology, Inc. | Atomic layer deposition of Dy doped HfO2 films as gate dielectrics |
US7374964B2 (en) | 2005-02-10 | 2008-05-20 | Micron Technology, Inc. | Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics |
US7160781B2 (en) | 2005-03-21 | 2007-01-09 | Infineon Technologies Ag | Transistor device and methods of manufacture thereof |
US7687409B2 (en) | 2005-03-29 | 2010-03-30 | Micron Technology, Inc. | Atomic layer deposited titanium silicon oxide films |
KR100706244B1 (ko) | 2005-04-07 | 2007-04-11 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US7361538B2 (en) * | 2005-04-14 | 2008-04-22 | Infineon Technologies Ag | Transistors and methods of manufacture thereof |
US7572695B2 (en) | 2005-05-27 | 2009-08-11 | Micron Technology, Inc. | Hafnium titanium oxide films |
US20070001231A1 (en) * | 2005-06-29 | 2007-01-04 | Amberwave Systems Corporation | Material systems for dielectrics and metal electrodes |
US7432139B2 (en) * | 2005-06-29 | 2008-10-07 | Amberwave Systems Corp. | Methods for forming dielectrics and metal electrodes |
JP2007019400A (ja) * | 2005-07-11 | 2007-01-25 | Renesas Technology Corp | Mos構造を有する半導体装置およびその製造方法 |
US7473637B2 (en) | 2005-07-20 | 2009-01-06 | Micron Technology, Inc. | ALD formed titanium nitride films |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US7989290B2 (en) | 2005-08-04 | 2011-08-02 | Micron Technology, Inc. | Methods for forming rhodium-based charge traps and apparatus including rhodium-based charge traps |
US7575978B2 (en) * | 2005-08-04 | 2009-08-18 | Micron Technology, Inc. | Method for making conductive nanoparticle charge storage element |
US7867845B2 (en) | 2005-09-01 | 2011-01-11 | Micron Technology, Inc. | Transistor gate forming methods and transistor structures |
US7538001B2 (en) * | 2005-09-01 | 2009-05-26 | Micron Technology, Inc. | Transistor gate forming methods and integrated circuits |
US20070052036A1 (en) * | 2005-09-02 | 2007-03-08 | Hongfa Luan | Transistors and methods of manufacture thereof |
US8188551B2 (en) | 2005-09-30 | 2012-05-29 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20070052037A1 (en) * | 2005-09-02 | 2007-03-08 | Hongfa Luan | Semiconductor devices and methods of manufacture thereof |
JP2007088122A (ja) * | 2005-09-21 | 2007-04-05 | Renesas Technology Corp | 半導体装置 |
US7332433B2 (en) * | 2005-09-22 | 2008-02-19 | Sematech Inc. | Methods of modulating the work functions of film layers |
US7651935B2 (en) * | 2005-09-27 | 2010-01-26 | Freescale Semiconductor, Inc. | Process of forming an electronic device including active regions and gate electrodes of different compositions overlying the active regions |
US7462538B2 (en) * | 2005-11-15 | 2008-12-09 | Infineon Technologies Ag | Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials |
US7592251B2 (en) | 2005-12-08 | 2009-09-22 | Micron Technology, Inc. | Hafnium tantalum titanium oxide films |
US7495290B2 (en) * | 2005-12-14 | 2009-02-24 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US7510943B2 (en) * | 2005-12-16 | 2009-03-31 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20070152276A1 (en) * | 2005-12-30 | 2007-07-05 | International Business Machines Corporation | High performance CMOS circuits, and methods for fabricating the same |
US20070178634A1 (en) * | 2006-01-31 | 2007-08-02 | Hyung Suk Jung | Cmos semiconductor devices having dual work function metal gate stacks |
KR100662850B1 (ko) * | 2006-02-02 | 2007-01-02 | 삼성전자주식회사 | 복수 개의 금속층을 적층한 반도체 소자 |
US7446026B2 (en) * | 2006-02-08 | 2008-11-04 | Freescale Semiconductor, Inc. | Method of forming a CMOS device with stressor source/drain regions |
US7709402B2 (en) | 2006-02-16 | 2010-05-04 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride films |
US7544559B2 (en) * | 2006-03-07 | 2009-06-09 | Micron Technolog, Inc. | Methods of forming semiconductor constructions |
KR100762238B1 (ko) * | 2006-03-21 | 2007-10-01 | 주식회사 하이닉스반도체 | 반도체 소자의 트랜지스터 및 이의 형성 방법 |
JP4967407B2 (ja) * | 2006-03-29 | 2012-07-04 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US8153502B2 (en) * | 2006-05-16 | 2012-04-10 | Micron Technology, Inc. | Methods for filling trenches in a semiconductor material |
KR100788371B1 (ko) * | 2006-08-02 | 2008-01-02 | 동부일렉트로닉스 주식회사 | 플래시 메모리 소자 제조 방법 |
US20080050898A1 (en) * | 2006-08-23 | 2008-02-28 | Hongfa Luan | Semiconductor devices and methods of manufacture thereof |
US7563730B2 (en) | 2006-08-31 | 2009-07-21 | Micron Technology, Inc. | Hafnium lanthanide oxynitride films |
US7759747B2 (en) | 2006-08-31 | 2010-07-20 | Micron Technology, Inc. | Tantalum aluminum oxynitride high-κ dielectric |
US7432548B2 (en) * | 2006-08-31 | 2008-10-07 | Micron Technology, Inc. | Silicon lanthanide oxynitride films |
US7544604B2 (en) | 2006-08-31 | 2009-06-09 | Micron Technology, Inc. | Tantalum lanthanide oxynitride films |
US7776765B2 (en) | 2006-08-31 | 2010-08-17 | Micron Technology, Inc. | Tantalum silicon oxynitride high-k dielectrics and metal gates |
US7605030B2 (en) | 2006-08-31 | 2009-10-20 | Micron Technology, Inc. | Hafnium tantalum oxynitride high-k dielectric and metal gates |
KR100843230B1 (ko) * | 2007-01-17 | 2008-07-02 | 삼성전자주식회사 | 금속층을 가지는 게이트 전극을 구비한 반도체 소자 및 그제조 방법 |
US7812414B2 (en) * | 2007-01-23 | 2010-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid process for forming metal gates |
KR100868768B1 (ko) * | 2007-02-28 | 2008-11-13 | 삼성전자주식회사 | Cmos 반도체 소자 및 그 제조방법 |
US7435652B1 (en) * | 2007-03-30 | 2008-10-14 | International Business Machines Corporation | Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET |
US7642616B2 (en) * | 2007-05-17 | 2010-01-05 | Micron Technology, Inc. | Tunnel and gate oxide comprising nitrogen for use with a semiconductor device and a process for forming the device |
KR100852212B1 (ko) * | 2007-06-12 | 2008-08-13 | 삼성전자주식회사 | 반도체 소자 및 이를 형성하는 방법 |
US20090008725A1 (en) * | 2007-07-03 | 2009-01-08 | International Business Machines Corporation | Method for deposition of an ultra-thin electropositive metal-containing cap layer |
JP2009111222A (ja) * | 2007-10-31 | 2009-05-21 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US20100123993A1 (en) * | 2008-02-13 | 2010-05-20 | Herzel Laor | Atomic layer deposition process for manufacture of battery electrodes, capacitors, resistors, and catalyzers |
JP5104373B2 (ja) * | 2008-02-14 | 2012-12-19 | 日本ゼオン株式会社 | 位相差板の製造方法 |
US7700469B2 (en) * | 2008-02-26 | 2010-04-20 | Micron Technology, Inc. | Methods of forming semiconductor constructions |
US8536660B2 (en) * | 2008-03-12 | 2013-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid process for forming metal gates of MOS devices |
US8324090B2 (en) * | 2008-08-28 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to improve dielectric quality in high-k metal gate technology |
US20100102393A1 (en) * | 2008-10-29 | 2010-04-29 | Chartered Semiconductor Manufacturing, Ltd. | Metal gate transistors |
US8106455B2 (en) | 2009-04-30 | 2012-01-31 | International Business Machines Corporation | Threshold voltage adjustment through gate dielectric stack modification |
US8124515B2 (en) * | 2009-05-20 | 2012-02-28 | Globalfoundries Inc. | Gate etch optimization through silicon dopant profile change |
US8518758B2 (en) * | 2010-03-18 | 2013-08-27 | Globalfoundries Inc. | ETSOI with reduced extension resistance |
CN105256276B (zh) * | 2010-06-10 | 2018-10-26 | 应用材料公司 | 具有增强的离子化和rf 功率耦合的低电阻率钨pvd |
US8354703B2 (en) | 2010-07-15 | 2013-01-15 | International Business Machines Corporation | Semiconductor capacitor |
US9276004B2 (en) * | 2012-03-30 | 2016-03-01 | Broadcom Corporation | ROM arrays having memory cell transistors programmed using metal gates |
KR101977286B1 (ko) * | 2012-12-27 | 2019-05-30 | 에스케이하이닉스 주식회사 | 듀얼 일함수 게이트스택, 그를 구비한 반도체장치 및 제조 방법 |
US9218976B2 (en) * | 2013-08-13 | 2015-12-22 | Globalfoundries Inc. | Fully silicided gate formed according to the gate-first HKMG approach |
FR3011382B1 (fr) * | 2013-09-27 | 2019-03-29 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de realisation d'un circuit integre |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6214724B1 (en) * | 1996-12-16 | 2001-04-10 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method therefor |
US6255698B1 (en) * | 1999-04-28 | 2001-07-03 | Advanced Micro Devices, Inc. | Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit |
US6297539B1 (en) * | 1999-07-19 | 2001-10-02 | Sharp Laboratories Of America, Inc. | Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same |
JP2001339061A (ja) * | 2000-05-30 | 2001-12-07 | Univ Nagoya | Mosデバイス及びその製造方法 |
JP2003023152A (ja) * | 2001-07-10 | 2003-01-24 | Sony Corp | Mis型トランジスタ及びその製造方法 |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3228702A (en) * | 1961-11-02 | 1966-01-11 | Union Tank Car Co | Inflatable seal for floating roof |
JP3104534B2 (ja) * | 1994-06-27 | 2000-10-30 | ヤマハ株式会社 | 半導体装置とその製法 |
US5705428A (en) * | 1995-08-03 | 1998-01-06 | Chartered Semiconductor Manufacturing Pte, Ltd. | Method for preventing titanium lifting during and after metal etching |
TW389944B (en) * | 1997-03-17 | 2000-05-11 | United Microelectronics Corp | Method for forming gate oxide layers with different thickness |
JPH10303412A (ja) | 1997-04-22 | 1998-11-13 | Sony Corp | 半導体装置及びその製造方法 |
US6777759B1 (en) * | 1997-06-30 | 2004-08-17 | Intel Corporation | Device structure and method for reducing silicide encroachment |
KR100276389B1 (ko) * | 1998-07-03 | 2000-12-15 | 윤종용 | 커패시터 및 그 제조방법 |
JP3189813B2 (ja) * | 1998-11-30 | 2001-07-16 | 日本電気株式会社 | 半導体装置の製造方法 |
JP3287403B2 (ja) * | 1999-02-19 | 2002-06-04 | 日本電気株式会社 | Mis型電界効果トランジスタ及びその製造方法 |
US6319832B1 (en) * | 1999-02-19 | 2001-11-20 | Micron Technology, Inc. | Methods of making semiconductor devices |
US20020063711A1 (en) * | 1999-05-12 | 2002-05-30 | Imove Inc. | Camera system with high resolution image inside a wide angle view |
JP2000349258A (ja) * | 1999-06-08 | 2000-12-15 | Mitsubishi Electric Corp | メモリセル並びにその制御方法及び製造方法 |
JP3480373B2 (ja) * | 1999-07-07 | 2003-12-15 | 松下電器産業株式会社 | トレイフィーダにおける部品供給高さ位置の補正方法 |
US6373111B1 (en) * | 1999-11-30 | 2002-04-16 | Intel Corporation | Work function tuning for MOSFET gate electrodes |
US6780704B1 (en) * | 1999-12-03 | 2004-08-24 | Asm International Nv | Conformal thin films over textured capacitor electrodes |
US6573160B2 (en) * | 2000-05-26 | 2003-06-03 | Motorola, Inc. | Method of recrystallizing an amorphous region of a semiconductor |
JP2002009169A (ja) * | 2000-06-20 | 2002-01-11 | Nec Corp | 半導体装置とその製造方法 |
US6228721B1 (en) * | 2000-06-26 | 2001-05-08 | Advanced Micro Devices, Inc. | Fabrication of metal oxide structures with different thicknesses on a semiconductor substrate |
JP2002057287A (ja) * | 2000-08-09 | 2002-02-22 | Rohm Co Ltd | 半導体装置 |
US7217615B1 (en) | 2000-08-31 | 2007-05-15 | Micron Technology, Inc. | Capacitor fabrication methods including forming a conductive layer |
US6436749B1 (en) * | 2000-09-08 | 2002-08-20 | International Business Machines Corporation | Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion |
JP3636978B2 (ja) * | 2000-09-18 | 2005-04-06 | 住友重機械工業株式会社 | ディスク成形装置 |
JP2002124650A (ja) * | 2000-10-17 | 2002-04-26 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
KR100351907B1 (ko) * | 2000-11-17 | 2002-09-12 | 주식회사 하이닉스반도체 | 반도체 소자의 게이트 전극 형성방법 |
KR20020056260A (ko) * | 2000-12-29 | 2002-07-10 | 박종섭 | 반도체 소자의 금속 게이트 형성방법 |
JP3547419B2 (ja) * | 2001-03-13 | 2004-07-28 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6693333B1 (en) * | 2001-05-01 | 2004-02-17 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator circuit with multiple work functions |
US6696345B2 (en) * | 2002-01-07 | 2004-02-24 | Intel Corporation | Metal-gate electrode for CMOS transistor applications |
KR100464650B1 (ko) * | 2002-04-23 | 2005-01-03 | 주식회사 하이닉스반도체 | 이중 유전막 구조를 가진 반도체소자의 캐패시터 및 그제조방법 |
US6818500B2 (en) * | 2002-05-03 | 2004-11-16 | Micron Technology, Inc. | Method of making a memory cell capacitor with Ta2O5 dielectric |
US6617210B1 (en) * | 2002-05-31 | 2003-09-09 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric |
US20040005003A1 (en) | 2002-07-02 | 2004-01-08 | Koninklijke Philips Electronics N.V. | Quality improvement for FGS BL coding with U/V coarse quantization |
US7030024B2 (en) * | 2002-08-23 | 2006-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual-gate structure and method of fabricating integrated circuits having dual-gate structures |
KR100477807B1 (ko) * | 2002-09-17 | 2005-03-22 | 주식회사 하이닉스반도체 | 캐패시터 및 그의 제조 방법 |
US6858524B2 (en) * | 2002-12-03 | 2005-02-22 | Asm International, Nv | Method of depositing barrier layer for metal gates |
KR100502426B1 (ko) * | 2003-09-18 | 2005-07-20 | 삼성전자주식회사 | 듀얼 게이트를 갖는 반도체 소자 및 그 형성 방법 |
-
2003
- 2003-03-12 US US10/388,103 patent/US7019351B2/en not_active Expired - Lifetime
-
2004
- 2004-01-02 TW TW093100051A patent/TWI255543B/zh not_active IP Right Cessation
- 2004-01-13 US US10/757,253 patent/US7253053B2/en not_active Expired - Lifetime
- 2004-01-13 US US10/757,252 patent/US7081656B2/en not_active Expired - Lifetime
- 2004-03-03 AT AT04716958T patent/ATE535012T1/de active
- 2004-03-03 CN CNB2004800124954A patent/CN100388426C/zh not_active Expired - Lifetime
- 2004-03-03 KR KR1020057016323A patent/KR100699116B1/ko active IP Right Grant
- 2004-03-03 WO PCT/US2004/006584 patent/WO2004082005A1/en active Application Filing
- 2004-03-03 EP EP04716958A patent/EP1604392B1/en not_active Expired - Lifetime
- 2004-03-03 JP JP2005518891A patent/JP4352410B2/ja not_active Expired - Lifetime
- 2004-03-11 TW TW093106473A patent/TWI233687B/zh not_active IP Right Cessation
- 2004-12-03 US US11/003,642 patent/US7126181B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6214724B1 (en) * | 1996-12-16 | 2001-04-10 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method therefor |
US6255698B1 (en) * | 1999-04-28 | 2001-07-03 | Advanced Micro Devices, Inc. | Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit |
US6297539B1 (en) * | 1999-07-19 | 2001-10-02 | Sharp Laboratories Of America, Inc. | Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same |
JP2001339061A (ja) * | 2000-05-30 | 2001-12-07 | Univ Nagoya | Mosデバイス及びその製造方法 |
JP2003023152A (ja) * | 2001-07-10 | 2003-01-24 | Sony Corp | Mis型トランジスタ及びその製造方法 |
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US20040178432A1 (en) | 2004-09-16 |
WO2004082005A1 (en) | 2004-09-23 |
JP4352410B2 (ja) | 2009-10-28 |
EP1604392B1 (en) | 2011-11-23 |
KR100699116B1 (ko) | 2007-03-21 |
US20050101078A1 (en) | 2005-05-12 |
ATE535012T1 (de) | 2011-12-15 |
US7126181B2 (en) | 2006-10-24 |
US20040180487A1 (en) | 2004-09-16 |
EP1604392A1 (en) | 2005-12-14 |
US7253053B2 (en) | 2007-08-07 |
TW200427055A (en) | 2004-12-01 |
US7081656B2 (en) | 2006-07-25 |
TW200428638A (en) | 2004-12-16 |
WO2004082005B1 (en) | 2004-11-04 |
US20040178458A1 (en) | 2004-09-16 |
TWI233687B (en) | 2005-06-01 |
US7019351B2 (en) | 2006-03-28 |
TWI255543B (en) | 2006-05-21 |
CN1784769A (zh) | 2006-06-07 |
JP2006515471A (ja) | 2006-05-25 |
KR20050108380A (ko) | 2005-11-16 |
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