CN100477112C - 形成含氘化氮化硅的材料的方法 - Google Patents

形成含氘化氮化硅的材料的方法 Download PDF

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CN100477112C
CN100477112C CNB2004800252632A CN200480025263A CN100477112C CN 100477112 C CN100477112 C CN 100477112C CN B2004800252632 A CNB2004800252632 A CN B2004800252632A CN 200480025263 A CN200480025263 A CN 200480025263A CN 100477112 C CN100477112 C CN 100477112C
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deuterated
silicon nitride
silicon
compound
sub
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CN1849704A (zh
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R·A·韦默
L·D·布雷纳
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明包括自至少一种氘化氮化合物与一种或多种不含有氢同位素的含硅化合物组合形成含氘化氮化硅的材料的方法。适合的氘化氮化合物包括如NH2D、NHD2和ND3。适合的含硅化合物包括如SiCl4和Si2Cl6。本发明的含氘化氮化硅的材料可结合到如晶体管装置中。该晶体管装置可用在DRAM单元中，其又可用在电子系统中。

Description

形成含氘化氮化硅的材料的方法
技术领域
本发明涉及一种形成含氘化氮化硅的材料的方法。
背景技术
在半导体工艺中大量使用含氘化氮化硅的材料。例如，含氘化氮化硅材料在硬化硅/二氧化硅界面期间可用作氘的储积，如例如在Clark，W.F等人的“Improved Hot-Electron Reliability In High-PerformanceMultilevel-Metal CMOS Using Deuterated Barrier-Nitride Processing”，IEEE Electron Device Letters，第20卷第10号，501-503页，1999年10月中所描述的。
已经提出各种方法用于形成含有氘化氮化硅的材料。该方法利用含氘化的硅前驱物(如SiD4)与可或不可氘化的含氮前驱物组合(范例的非氘化含氮前驱物为NH3，和范例的氘化含氮前驱物为ND3)。
上述用于形成含氘化氮化硅的材料的方法相对昂贵，因此需要开发更加经济的方法，用于形成含氘化氮化硅的材料。
发明内容
一方面，本发明涉及一种自至少一种氘化氮化合物和一种或多种不含有氢同位素(即，不含有氢、氘或氚)的含硅化合物形成含有氘化氮化硅的材料的方法。该含硅化合物例如选自由SiCl4、Si2Cl6及其混合物构成的组的卤化硅化合物；和至少一种氘化氮化合物例如选自由NH2D、NHD2、ND3及其混合物构成的组。
一方面，本发明包括接近二氧化硅与非氧化的硅的界面形成含氘化氮化硅的材料的方法。直接相对于非氧化的硅表面形成含二氧化硅材料。含氘化氮化硅的材料沉积于含二氧化硅材料上方。含氘化氮化硅的材料的沉积使用至少一种氘化氮化合物和一种或多种不含有氢同位素的卤化硅化合物。
一方面，本发明包括沿着导电线侧壁形成电绝缘侧壁衬垫的方法。导电线形成于半导体衬底上方。该线包括一对相对的侧壁。使用自至少一种氘化氮化合物和一种或多种不含氢同位素的卤化硅化合物的沉积，沿着侧壁并在半导体衬底上方形成含氮化硅的材料。
附图说明
以下参考附图描述本发明的优选实施例。
图1是本发明范例方面的初步处理步骤的半导体晶片一部分的概略截面图；
图2是图1示出晶片一部分在图1的步骤之后的处理步骤的图；
图3是图1示出晶片一部分在图2的步骤之后的处理步骤的图；
图4是图1示出晶片一部分在图3的步骤之后的处理步骤的图；
图5是图1示出晶片一部分在图4的步骤之后的处理步骤的图；
图6是示出本发明范例应用的计算机的概略图；
图7是示出图6计算机的主板的特定特征的框图；
图8是根据本发明范例方面的电子系统的高层次框图；
图9是根据本发明方面的范例电子系统的简化框图。
具体实施方式
本发明涉及一种形成含氘化的氮化硅材料的方法。为了解释该公开以及后面的权利要求的目的，应当理解，术语“含氮化硅材料”包括含有硅和氮的任何材料，例如，包括包含实质上由或是由氮化硅(SixNy，其中x和y是大于0的数字，且其中x和y通常分别为3和4)组成的材料，和包括实质上由或是由氧氮化硅(SixNyOz，其中x、y和z为大于0的数字)构成的材料。因此，术语“含氘化的氮化硅材料”包括含氘化的氧氮化硅材料。
本发明的一个方面是认识到，与现有技术相关的用于形成含氮化硅材料的非常昂贵的费用是由于使用含氘化硅化合物作为形成含氘化氮化硅材料的前驱物。因此，本发明包括通过其可形成含氘化氮化硅的材料而不需要使用含氘化硅的前驱物的方法。作为替换，本发明使用含氘化氮的前驱物与不具有氢或其同位素的含硅前驱物组合。范例的含硅前驱物为不含有氢同位素的卤化硅化合物，例如为，由硅和氯构成的化合物。根据本发明的范例方面适合用作含氘化氮化硅材料的前驱物的特定含硅化合物为SiCl4和Si2Cl6。
本发明的方法可用于在其中需要这种材料的任何应用中形成含氘化氮化硅的材料。参考图1-5描述本发明范例的方面，其中，含氘化氮化硅的材料结合到晶体管装置中。
最初，参考图1，半导体结构10包括衬底12。衬底12包括例如用p型掺杂剂作背景轻掺杂的单晶硅。为了有助于解释以下的权利要求，将术语“半导体的衬底”和“半导体衬底”限定为意指包括半导体材料的任何结构，包括但不限于体半导体材料如半导体晶片(单独的或是在其上包括其它材料的组件)和半导体材料层(单独的或是包括其它材料的组件)。术语“衬底”涉及任何支撑衬底，包括但不限于上述的半导体衬底。
电绝缘材料层14形成于衬底12上方，且示出，直接相对于衬底12的上部表面形成。层14例如可包括二氧化硅、实质上由或是由二氧化硅构成，且可称作焊盘层或焊盘氧化层。
如果层14包括二氧化硅，则该层可通过在衬底12上方沉积二氧化硅来形成(如，化学气相沉积)，或通过将衬底12的表面暴露到适合的氧化条件从而自衬底12的硅生长二氧化硅来形成。
在绝缘层14结合到衬底12的位置处产生界面16。在具体应用中，绝缘层14可包括二氧化硅，衬底12包括非氧化的硅，界面16由此包括二氧化硅接触非氧化的硅的界面。
尽管将绝缘材料14示出为单个的均质层，但是应当理解，在本发明各个方面，绝缘材料可包括电绝缘的多层。
在绝缘材料14上方形成导电材料18。导电材料18可包括任何适合的导电化合物，包括例如金属、金属化合物和导电掺杂的硅。在具体方面，导电材料18可包括p型掺杂的硅，且最终结合以作为用于PMOS场效应晶体管的栅。另一方面，导电材料18可包括n型掺杂的硅。尽管将导电材料18示出为单个的均质层，但是应当理解，在本发明各个方面中导电材料18可包括不同导电成分的多层。
电绝缘材料20形成于导电材料18上方，且在示出的实施例中，其直接相对于导电材料18而形成。电绝缘材料20可包括任何适合的材料，包括例如，二氧化硅、氮化硅和氧氮化硅中的一种或多种。在本发明的具体方面，绝缘材料20包括含氘化氮化硅的材料，且在这一方面，材料20可包括实质上由或是由例如氘化的氮化硅和氘化氧氮化硅中的一种或两种。
如果层20包括含氘化氮化硅的材料，则可通过自至少一种氘化氮化合物和一种或多种不含有氢同位素的卤化硅化合物的沉积来形成该层。该至少一种氘化氮化合物例如可选自由NH2D、NHD2、ND3及其混合物的组。该一种或多种卤化硅化合物例如可选自由硅和氯构成的组，且在具体方面可选自由SiCl4、Si2Cl6及其混合物构成的组。用于形成含氘化氮化硅材料的沉积可为原子层沉积(ALD)、化学气相沉积(CVD)或ALD和CVD的混合。在具体方面，该沉积将为低压CVD(LPCVD)。该LPCVD可在反应室内部实施，且在室内部，沉积期间通常包括小于或等于约5乇的压力。该LPCVD通常在反应室内部的温度保持在从约500℃至约850℃的温度时进行。当卤化硅化合物实质上由或是由Si2Cl6构成时通常使用的温度为从约500℃至约700℃；和当卤化硅化合物实质上由或是由SiCl4构成时通常使用的温度为从约600℃至约800℃。
化学气相沉积期间，在反应室内部氘化氮化合物与卤化硅化合物的比率可用数量表示为氘化氮化合物的体积百分比相对于卤化硅化合物的体积百分比。具体地，提供于室中的一种或多种氘化氮化合物的总体积可限定为氘化氮化合物体积，提供于室中的一种或多种卤化硅化合物的总体积可限定为卤化硅化合物体积。在室中的氘化氮前驱物相对于卤化硅前驱物的比率可称为氘化氮化合物体积对卤化硅化合物体积的体积比率。在本发明特定方面，在含氘化的氮化硅材料的CVD期间，氘化氮化合物体积对卤化硅化合物体积的体积比率为从约1∶1至约20∶1，示例性的比率为约10∶1。如果含氮化硅材料实质上由或是由氮化硅构成，则在沉积含氮化硅材料期间在反应室中存在的仅有的反应化合物为氘化氮化合物和卤化硅化合物。如果将含氘化氮化硅的材料替换为氘化氧氮化硅，则除了氘化氮化合物和卤化硅化合物之外，也可将含氧前驱物提供于反应室中。适合的含氧前驱物包括例如氧(O2)和臭氧(O3)。在可选处理中，氘化氧氮化硅可通过在沉积该材料之后将实质上由或是由氘化氮化硅构成的材料暴露到氧化气氛中来形成。而且，在特定方面，氘化的氧氮化硅材料的氧含量通过将材料暴露到氧化气氛中而增长。
参考图2，将层14、18和20图案化为线22。该线在图2的截面图中为矩形块，且应当理解，该线相对于图2的截面图延伸入和延伸出页面。线22最终用作半导体结构中的字线。线22具有一对相对的侧壁24和26。
图案化线22包括例如在材料14、18和20上方形成光致抗蚀剂(未示出)的图案化的掩模，随后蚀刻以移除层14、18和20未被掩膜保护的部分，然后移除掩模。可利用光刻处理形成光致抗蚀剂掩模。
图2的截面图中示出的线22的部分可最终结合到晶体管装置的栅中。因此，层14、18和20的叠置层称作栅叠层。尽管示出的处理将所有的层14、18和20图案化为线状以形成栅叠层，但是应当理解，本发明包括其中在形成栅叠层期间不将焊盘层14图案化为线状的其它方面(未示出)。
使用栅叠层以对准接近于栅叠层而形成的源/漏区28和30。区28和30包括延伸到衬底12中的导电掺杂扩散区。在特定方面，区28和30可具有适合的掺杂剂类型以被结合到n型金属氧化物半导体(NMOS)晶体管装置中，且在其它方面，区28和30可具有适合的掺杂剂类型以被结合到p型金属氧化物半导体(PMOS)装置中。形成源/漏区28和30可使用常规处理来完成。在特定方面，除了示出的那些步骤之外本发明还包括其它的步骤。例如，可在形成源/漏区28和30之前，沿着导电材料18的侧壁24、26形成氧化物薄层(未示出)。
参考图3，在线22和衬底12上方形成电绝缘材料32。材料32沿着线22的侧壁24和26延伸。绝缘材料32可包括任何适合的材料，例如包括氮化硅、二氧化硅和氧氮化硅中的一种或多种。在特定方面，层32可包括实质上由或是由一种或多种含氘化氮化硅的材料。在这种方面，层32可通过自至少一种氘化氮化合物和一种或多种不含有氢同位素的卤化硅化合物的沉积来形成，相对于形成层20的含氘化氮化硅材料，使用上述的处理。
参考图4，各向异性蚀刻层32(图3)以沿着线22的侧壁24和26形成侧壁间隔物34(在此也称作侧壁衬垫)。
在形成侧壁间隔物34之后，将导电增强掺杂剂注入到衬底12中以形成源/漏扩散区36和38。区域36和38的形成可使用常规方法来完成，且在本发明的特定方面，用在区域36和38中的掺杂剂适合于形成NMOS晶体管装置，在本发明的其它方面可适合于形成PMOS装置。通过线22的栅叠层门控地将源/漏区36和38相互连接。因此，栅叠层和源/漏区一起结合到晶体管装置39中。
参考图5，在线22、间隔物34和源/漏区36和38上方形成电绝缘层40。层40可包括任何适合的电绝缘材料，且在特定方面，包括含氘化氮化硅材料。在前面描述的用于形成层20的含氘化氮化硅材料的处理类型中，如果层40包括含氘化氮化硅材料，则该层可自至少一种氘化氮化合物和一种或多种不含有氢同位素的卤化硅化合物而形成。如果层20还包括含氘化氮化硅材料的话，则阻挡层40可称作第二含氘化氮化硅材料，以将阻挡层与材料20区分开来。
根据上面讨论的方法，图5结构的材料34、20和40中的一种或多种可包括含氘化氮化硅材料。这种材料在随后的处理中是有益的。例如，如果界面16为硅/二氧化硅界面，则来自氘化材料的氘可迁移到硅/二氧化硅的界面，以硬化该界面并降低这种界面对会发生在热处理步骤中的热载流子降低的敏感性。范例的热处理步骤为钝化退火，其可包括加热衬底12和因此加热界面16从约350℃至约450℃的温度达从约5分钟至约2小时的时间。该钝化退火可包括常规处理，因此可在大气压力下实施，同时结构10暴露到包括约10％(体积计)氢气的氛围中。在没有接近界面的氘化材料的情况下，钝化退火通常导致硅/二氧化硅界面16的热载流子降低。本发明的方法可提供接近界面的氘化材料，且因此可减轻甚至防止热载流子降低。
在另外的和/或可选方面中，导电材料18可包括p型掺杂硅。根据Tanaka等人的观察资料(Tanaka，M等人的“Realization Of HighPerformance Dual Gate DRAMs Without Boron Penetration By ApplicationOf Tetrachlorosilane Silicon Nitride Films”2001，VLSI Technology Digestof Technical Papers的学术讨论会，123和124页)有利的是在PMOSFET结构中使用较少SiH的含氮化硅的膜。本发明的方法可用于形成所谓的较少SiH的含氮化硅的膜。
尽管希望具有至少一种含氘化氮化硅的材料结合到结构10中，但是应当理解，各种材料20、34和40可包括除了含氘化氮化硅成分之外的成分，和/或如果其它层20、34和40包括含氘化氮化硅成分的话则可将其省略。例如，在本发明的各个方面，如果侧壁间隔物34和/或帽盖20包括含氘化氮化硅成分的话，则可省略阻挡层40。
晶体管39可结合到各种半导体结构中。在本发明范例的方面，晶体管装置39可结合到DRAM结构中。具体地，源/漏区36和38中的一个可电连接到存储装置，其它的源/漏区可电连接到位线。在图5的结构中，示出的源/漏区36连接到存储装置50，且示出的源/漏区38连接到位线52。存储装置50可包括例如电容器。至源/漏区36和38的电连接可通过任何适合的方法来完成，该方法包括例如通过延伸导电互联(未示出)穿过层40以与源/漏区36和38连接。
可使用本发明的方法完成的晶体管装置特性中的改进例如为热电子电阻、降低的硅/电介电质界面恶化和DRAM刷新改进。
根据本发明的方法形成的结构(如上述的字线和DRAM单元)可用在多种组件中，包括例如计算机系统和其它电子系统。
图6借助于实例但并非以限制的方式常规地示出根据本发明方面的计算机系统400的实施例。计算机系统400包括显示器(monitor)401或其它的通信输出装置，键盘402或其它的通信输入装置和主板404。主板404可承载微处理器406或其它的数据处理单元和至少一个存储装置408。存储装置408可包括上述本发明的各个方面，包括例如，字线和DRAM单位单元中的一种或多种。存储装置408可包括存储单元阵列，且这种阵列可与用于存取所述阵列中的单独存储单元的寻址电路耦合。而且，该存储单元阵列可以耦合到用于从存储单元中读取数据的读取电路。寻址和读取电路可用于在存储装置408和处理器406之间传输信息。在图7中示出的主板404的框图中示出了这种结构。在这种框图中，将寻址电路示出为410和将读取电路示出为412。
在本发明的特定方面，存储装置408可对应于存储模块。例如，单列直插式存储模块(SIMM)和双列直插式存储模块(DIMM)可用在使用本发明教导的实施中。存储装置可结合到提供从装置的存储单元进行读取或写入到该装置的存储单元的各种设计中的任一种设计中。这些方法中的一种方法是页面模式操作。在DRAM中的页面模式操作通过存取存储单元阵列行和任意存取不同阵列的列来限定。当存取该列时，可读取并输出存储于行和列交叉处的数据。
装置的可选类型为扩充数据输出(EDO)存储器，其允许在闭合了寻址列之后可获得存储在存储阵列地址处的数据作为输出。该存储器可通过允许较短的存取信号来增加通信速度，而不降低在存储总线上可获得存储器输出数据的时间。装置的其它可选类型包括SDRAM、DDRSDRAM、SLDRAM、VRAM和Direct RDRAM，以及其它的装置类型如SRAM或闪存。
图8示出本发明范例电子系统700的各种实施例的高层次结构的简化框图。系统700可对应于如计算机系统、处理控制系统或任何其它使用处理器和相关存储器的系统。电子系统700具有功能元件，包括处理器或算术/逻辑单元(ALU)702、控制单元704、存储器单元706和输入/输出(I/O)装置708。通常，电子系统700具有通过处理器702和处理器702之间的相互作用指定对数据进行操作的本地指令集、存储器单元706和I/O装置708。控制单元704通过持续地循环使得指令从存储装置706取出并执行的一系列操作来协调处理器702、存储装置706和I/O装置708的所有操作。在各个实施例中，存储装置706包括但不限于随机存储(RAM)装置、只读存储(ROM)装置和外围装置如软盘驱动和高密度磁盘CD-ROM驱动。本领域技术人员将理解，在阅读并理解了该公开的基础上，根据本发明的各个方面，任何示出的电子元件都能够制造为包括DRAM单元和字线。
图9是范例电子系统800的各个实施例的高层次结构的简化框图。系统800包括具有存储单元804的阵列、地址解码器806、行存取电路808，列存取电路810、用于控制操作的读取/写入控制电路812和输出/输出电路814的存储装置802。存储装置802还包括电源电路816和传感器820，如用于确定存储单元是否处于低阈值导通状态或处于高阈值非导通状态的电流传感器。示出的电源电路816包括电源电路880、用于提供参考电压的电路882、用于提供具有脉冲的第一字线的电路884、用于提供具有脉冲的第二字线的电路886和用于提供具有脉冲的位线的电路888。该系统800还包括处理器822或用于存储器存取的存储控制器。
存储装置802通过导线或金属化线接收来自处理器822的控制信号824。存储装置802用于存储通过I/O线存取的信号。本领域技术人员将理解，可提供另外的电路和控制信号，且简化了存储装置802以有助于集中本发明。处理器822或存储装置802中的至少一个可包括本发明中之前描述类型的DRAM单元。
本公开示出的各个系统意为提供用于本发明电路和结构的各种应用的一般理解，且并不意为用作根据本发明方面使用存储单元的电子系统的全部元件和特征的完整表述。本领域技术人员将理解，可在单封装处理单元中、甚至在单个的半导体芯片上制造各种电子系统，以降低处理器和存储装置之间的通信时间。
用于存储单元和字线的应用包括用在存储模块、装置驱动器、功率模块、通信模块、处理模块和特定应用模块中的电子系统，并包括多层、多芯片模块。这种电路还可以是各种电子系统如时钟、电视、手提电话、个人计算机、汽车、工业控制系统、飞行器或其它的子部件。

Claims (7)

1.一种形成晶体管装置的方法，包括：
在半导体衬底(12)上方形成栅叠层(22)，所述栅叠层包括电绝缘焊盘(14)，在所述焊盘上方的至少一种导电材料(18)和在该至少一种导电材料上方的电绝缘帽盖(20)；所述栅叠层包括至少沿着所述一种或多种导电材料和所述帽盖延伸的一对相对的侧壁(24和26)；
沿着所述侧壁形成电绝缘材料(32)；
沿着所述侧壁各向异性蚀刻所述电绝缘材料以形成侧壁间隔物(34)；
接近于所述栅叠层将掺杂剂注入到衬底中，以形成通过栅叠层门控地相互连接的一对源/漏扩散区(36和38)；和
在所述栅叠层上方和侧壁间隔物上方沉积含氘化氮化硅的材料(40)；该含氘化氮化硅的材料自至少一种氘化氮化合物和一种或多种不含有氢同位素的卤化硅化合物沉积得到；所述含氘化氮化硅的材料为含氘化氧氮化硅的材料。
2.根据权利要求1的方法，其中电绝缘帽盖是含氘化氮化硅的材料，所述含氘化氮化硅的材料自至少一种氘化氮化合物和一种或多种不含有氢同位素的卤化硅化合物沉积得到。
3.根据权利要求2的方法，其中沿着侧壁形成且用于形成侧壁间隔物的电绝缘材料是含氘化氮化硅的材料，所述含氘化氮化硅的材料自至少一种氘化氮化合物和一种或多种不含有氢同位素的卤化硅化合物沉积得到。
4.根据权利要求1的方法，其中一种或多种卤化硅化合物包含硅和氯。
5.根据权利要求4的方法，其中一种或多种卤化硅化合物选自由SiCl4、Si2Cl6及其混合物构成的组。
6.根据权利要求5的方法，其中至少一种氘化氮化合物选自由NH2D、NHD2、ND3及其混合物构成的组。
7.根据权利要求1的方法，其中钝化退火是在形成含氘化氮化硅的材料之后进行的；该钝化退火包括将衬底加热到从350℃至450℃的温度达从5分钟至2小时的时间。
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