TW576544U - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
TW576544U
TW576544U TW092217566U TW92217566U TW576544U TW 576544 U TW576544 U TW 576544U TW 092217566 U TW092217566 U TW 092217566U TW 92217566 U TW92217566 U TW 92217566U TW 576544 U TW576544 U TW 576544U
Authority
TW
Taiwan
Prior art keywords
semiconductor device
semiconductor
Prior art date
Application number
TW092217566U
Other languages
English (en)
Inventor
Muneaki Maeno
Kenji Kimura
Toshikazu Sei
Original Assignee
Tokyo Shibaura Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co filed Critical Tokyo Shibaura Electric Co
Publication of TW576544U publication Critical patent/TW576544U/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW092217566U 1999-09-10 2000-09-05 Semiconductor device TW576544U (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25797999A JP4008629B2 (ja) 1999-09-10 1999-09-10 半導体装置、その設計方法、及びその設計プログラムを格納したコンピュータ読み取り可能な記録媒体

Publications (1)

Publication Number Publication Date
TW576544U true TW576544U (en) 2004-02-11

Family

ID=17313872

Family Applications (2)

Application Number Title Priority Date Filing Date
TW092113344A TWI223322B (en) 1999-09-10 2000-09-05 Design method of semiconductor device and recording medium for storing its design program
TW092217566U TW576544U (en) 1999-09-10 2000-09-05 Semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW092113344A TWI223322B (en) 1999-09-10 2000-09-05 Design method of semiconductor device and recording medium for storing its design program

Country Status (4)

Country Link
US (3) US6753611B1 (zh)
JP (1) JP4008629B2 (zh)
KR (1) KR100384805B1 (zh)
TW (2) TWI223322B (zh)

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JP3924550B2 (ja) * 2003-05-22 2007-06-06 Ｎｅｃエレクトロニクス株式会社 半導体装置及びレイアウト装置及び方法並びにプログラム
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JP4768980B2 (ja) * 2004-10-28 2011-09-07 ルネサスエレクトロニクス株式会社 露光用マスク及び配線層マスクのパターン設計方法
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JP4986114B2 (ja) * 2006-04-17 2012-07-25 ルネサスエレクトロニクス株式会社 半導体集積回路及び半導体集積回路の設計方法
WO2008020266A1 (en) * 2006-08-16 2008-02-21 Freescale Semiconductor, Inc. Method and apparatus for designing an integrated circuit
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JP2008205122A (ja) * 2007-02-19 2008-09-04 Nec Electronics Corp 半導体装置およびその製造方法
US20080312845A1 (en) * 2007-05-14 2008-12-18 Abbott Diabetes Care, Inc. Method and apparatus for providing data processing and control in a medical communication system
WO2009025015A1 (ja) * 2007-08-17 2009-02-26 Fujitsu Microelectronics Limited フォトマスクの形成方法および半導体装置の製造方法
WO2009084092A1 (ja) * 2007-12-27 2009-07-09 Fujitsu Limited マクロ用レイアウト検証装置及び検証方法
US8198188B1 (en) * 2008-01-28 2012-06-12 Cadence Design Systems, Inc. Self-aligned VIAS for semiconductor devices
CN102160465A (zh) * 2008-10-10 2011-08-17 夏普株式会社 照明装置和具备它的液晶显示装置
CN101960583B (zh) 2009-02-17 2014-05-07 松下电器产业株式会社 半导体装置、基本单元以及半导体集成电路
JP2011014576A (ja) * 2009-06-30 2011-01-20 Renesas Electronics Corp 半導体チップ、半導体ウエハ、及び半導体チップの製造方法
JP2010187005A (ja) * 2010-03-30 2010-08-26 Fujitsu Semiconductor Ltd 複数の配線層を有する半導体回路の端子層設定に用いられる端子延長用コンポーネント
EP2684180B1 (en) 2011-03-07 2023-04-12 Intelligent Imaging Systems, Inc. Vehicle traffic and vehicle related transaction control system
US8421237B2 (en) * 2011-07-07 2013-04-16 Cisco Technology, Inc. Stacked memory layers having multiple orientations and through-layer interconnects
US10741489B2 (en) * 2011-09-19 2020-08-11 Texas Instruments Incorporated Rectangular via for ensuring via yield in the absence of via redundancy
US20130320451A1 (en) 2012-06-01 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") Semiconductor device having non-orthogonal element
KR102029645B1 (ko) * 2013-01-14 2019-11-18 삼성전자 주식회사 맞춤형 마스크의 제조 방법 및 맞춤형 마스크를 이용한 반도체 장치의 제조 방법
KR102661932B1 (ko) * 2016-12-16 2024-04-29 삼성전자주식회사 멀티플 패터닝 리소그래피를 위한 집적 회로, 집적 회로의 설계를 위한 컴퓨팅 시스템 및 컴퓨터 구현 방법
US10964639B2 (en) 2017-10-20 2021-03-30 Samsung Electronics Co., Ltd. Integrated circuits including via array and methods of manufacturing the same

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Also Published As

Publication number Publication date
KR100384805B1 (ko) 2003-05-22
JP2001085614A (ja) 2001-03-30
JP4008629B2 (ja) 2007-11-14
US6753611B1 (en) 2004-06-22
TW200304667A (en) 2003-10-01
TWI223322B (en) 2004-11-01
US6826742B2 (en) 2004-11-30
US20060012050A1 (en) 2006-01-19
KR20010030379A (ko) 2001-04-16
US7444614B2 (en) 2008-10-28
US20040065907A1 (en) 2004-04-08

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Legal Events

Date Code Title Description
MK4K Expiration of patent term of a granted utility model