TW564526B - Laminated type semiconductor device - Google Patents

Laminated type semiconductor device Download PDF

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Publication number
TW564526B
TW564526B TW091122148A TW91122148A TW564526B TW 564526 B TW564526 B TW 564526B TW 091122148 A TW091122148 A TW 091122148A TW 91122148 A TW91122148 A TW 91122148A TW 564526 B TW564526 B TW 564526B
Authority
TW
Taiwan
Prior art keywords
circuit
integrated circuit
semiconductor integrated
aforementioned
semiconductor device
Prior art date
Application number
TW091122148A
Other languages
English (en)
Chinese (zh)
Inventor
Mie Matsuo
Kenichi Imamiya
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW564526B publication Critical patent/TW564526B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/401—Marks applied to devices, e.g. for alignment or identification for identification or tracking
    • H10W46/403—Marks applied to devices, e.g. for alignment or identification for identification or tracking for non-wireless electrical read out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/284—Configurations of stacked chips characterised by structural arrangements for measuring or testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
TW091122148A 2001-09-29 2002-09-26 Laminated type semiconductor device TW564526B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001375022A JP3959264B2 (ja) 2001-09-29 2001-09-29 積層型半導体装置

Publications (1)

Publication Number Publication Date
TW564526B true TW564526B (en) 2003-12-01

Family

ID=19183475

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091122148A TW564526B (en) 2001-09-29 2002-09-26 Laminated type semiconductor device

Country Status (5)

Country Link
US (2) US6791175B2 (https=)
JP (1) JP3959264B2 (https=)
KR (1) KR100506105B1 (https=)
CN (1) CN1224102C (https=)
TW (1) TW564526B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI482260B (zh) * 2012-03-30 2015-04-21 國立清華大學 多層三維晶片之層識別電路及其方法

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Also Published As

Publication number Publication date
US6791175B2 (en) 2004-09-14
US6991964B2 (en) 2006-01-31
JP2003110086A (ja) 2003-04-11
KR20030028412A (ko) 2003-04-08
CN1224102C (zh) 2005-10-19
CN1411062A (zh) 2003-04-16
US20030062612A1 (en) 2003-04-03
US20050001306A1 (en) 2005-01-06
JP3959264B2 (ja) 2007-08-15
KR100506105B1 (ko) 2005-08-04

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