TW201203496A - 3D-IC device and decreasing type layer-ID detector for 3D-IC device - Google Patents

Abstract

The present invention discloses a 3D-IC device formed by stacking plural the same or the different type chips, comprising: a plurality of decrement circuit coupled in sequence to perform an operation of minus 1, which is to operate an input value from a chip of the 3D-IC device and output a plurality of layer-ID to each chips stacked within said 3D-IC device; and a plurality of bump coupled to each stacked chip of said 3D-IC device, wherein said layer-ID is represented by a combination of N bits and M chips to which M said layer-ID satisfying a relation of M ≤ 2N are assigned are stacked.

Description

201203496 VI. Description of the Invention: [Technical Field] The present invention relates to a detection circuit for a three-dimensional wafer device, and more particularly to a descending layer identification detection circuit for a three-dimensional wafer device. [Prior Art] In order to achieve the best efficiency of size reduction, in recent years, a number of wafers of the same or different types have been gradually integrated in a three-dimensional space, and the structure of the upper and lower conduction is adopted in a three-dimensionally stacked manner to reduce the cost. The most important feature of the planar surface is that the wafers of different functions, properties or substrates can be fabricated separately by the most suitable process, and the three-dimensional stacking integration is performed by using the Thr〇ughsi Via 'TSV technology to effectively shorten the metal wires. The length and wiring resistance not only reduce the area, but also achieve the advantages of reduced size, integration, high efficiency and low power consumption. Therefore, three-dimensional wafers are attracting attention from various industries, especially for the memory industry that emphasizes small size and high efficiency. Currently, personal computers and server workstations are in the data processing application category. Three Dimension Integral Circuits (3D-IC), such as various consumer applications, communication, communication applications, etc., used for dynamic random access

Set, south performance, small size, storage capacity for DRAM, & memory device stack, ‘application category. DRAM emphasizes the need for high capacity, low power consumption and low cost. In order to increase the number of small ones in the 3D 1C technology in order to form a high-capacity memory device in recent years. In 201203496, the three-dimensional stacking of three-dimensional wafers using the Through-Si Via (TSV) technology has been published in the journal paper, see Uks〇ng Kang, 8Gb 3-D DDR3 DRAM Using Through-Silicon-Via echnology 5 IEEE , Journal of Solid-State Circuits, Vol. 45 NO. 1, January 2010.

After forming a three-dimensional wafer with the same or different types of wafers, in order to select a specific wafer to operate in the system operation, it is necessary to identify the number of individual materials of the same or different types of wafers in advance, so that the system can be selected when operating. The specific wafer action required. In the past, many people have proposed related methods. However, not only has the cost increased, but it has not been able to overcome the fact that when the number of stacked three-dimensional wafers is increasing, the number of electrodes is also increased. Some references suggest that the stacked layer structure is divided into selective paths, the numbering is the same as the stacking order, so that the more the number of wafer stacks, the more the number of electrodes, to match the complex stack structure, and the cost of the product. Also ^ mention of _ such as the Japanese Patent Case No. 20〇2_3 () 5283). ^References' For example, Japanese Patent Application (4) No. _u嶋 Jie Lu A stacked device includes a plurality of wafers, and for each - another! distribution - layer identification number ^ in order to suppress the number of electrodes accompanying the increase in the number of stacked layers Alternatively, a layer having the same level as the selection signal may be selected. In such a stacked device, the connection θ, ~, for example, may be selected to be equal to: the path may be simplified to simplify the electrode structure.形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施Japanese Patent Application No. 201203496 SUMMARY OF THE INVENTION In order to solve the above problems, the detection circuit of the wafer device of the present invention, in particular, provides: a three-reduction layer identification number detection circuit - a quasi-wafer device For each day of the three-dimensional wafer device, the series of wire reduction circuits, /1 clothing straight heart valley day and day, when individually operating, can select the specific wafer number required, so that the number of points = point is provided - A three-dimensional wafer formed by a complex resistance, a memory crystal ",:::, for example, a capacitor, which can be assigned a number from the different layer from the second & 曰u +, from the —,, 隹日日Selecting the three-dimensional wafer device into which the month to be specified is entered: the plurality of wafers of the same or different types are formed, and the second and the decreasing circuits are connected in sequence to perform the subtraction operation, the operation one, the standard Bracts 4 An input value of the wafer, and outputting a plurality of layers to each stacked wafer in the three-dimensional wafer device; and a plurality of lands that are coupled to each of the stacked wafers of the three-dimensional wafer device. wherein the «. The other numbers are expressed in a combination of N bits, and the μ semiconductor wafers satisfying the 2 ' 2n relationship are calibrated. The other aspect of the present invention is to provide a three-dimensional wafer device. The decrementing layer identification number detecting circuit 'includes a plurality of decrementing circuits that are sequentially connected 'to perform a subtractive i operation for calculating an input value of the three-dimensional wafer device wafer' and output a plurality of layer identification numbers to the three-dimensional wafer device Each of the stacked wafers, wherein the layer identification number is represented by a combination of N bits, and a plurality of semiconductor wafers satisfying the MS 2N relationship are assigned to be assigned the layer identification 201203496 number. The explanations of the present invention will be described in terms of preferred embodiments and viewpoints, and such statements are intended to be illustrative and not intended to be limiting. The invention is also to be construed as being limited to the scope of the invention. The invention may be embodied in other embodiments. The details of the invention are described, including the embodiments of the invention. 'The same reference numerals are used to identify the same or functional two: components, and it is intended to illustrate the main features of the embodiments in a highly simplified schematic manner. Moreover, the drawings do not depict each feature of the actual embodiment, The graphic elements are all drawn in relative dimensions and not drawn to scale. The one-dimensional day device 1 is formed by stacking a plurality of wafers, which may be connected to the same or different types of Α Α 、 /, (6)...", such as memory The wafer contains two = volatile memory. The first figure shows a structural side view of the third embodiment of the present invention::: device. As shown, the three-dimensional wafer device has a wafer layer on the lowermost substrate 2, and the interface wafer 3 is stacked on its five wafers. Further, the "wafer layer_~" of the three-dimensional wafer device is sequentially numbered, such as five wafers two, one (1), one (1), one (1), and one (1). 4 is formed below, and the solder balls 4 can connect the three-dimensional wafer set 1 to the external device. The interface wafer 3 controls the input/output signals of the five wafer layers of the three-dimensional wafer device 1 called 1 (4). A plurality of bumps 5 are formed on the upper surface and the back surface of the two-dimensional wafer device i and the back surface of the interface wafer 3. The bumps 5 are connected to each of the stacked wafers of the three-dimensional wafer package 201203496 1(0)-1 ( 4) 'The bumps 5 can be made by the perforation technology, and can be made with the last name and the laser drilled hole' or by other suitable techniques. The perforation technology is formed on the wafer and connected to each other in the vertical direction to The stacked wafer layers can be interconnected. The bumps 5 are electrical connection paths between the wafers 1(0)-1(4) of the three-dimensional wafer device 1. Further, the three-dimensional wafer device! The signal transmission of layer 1 (0M (4) is connected to each other in the vertical direction by the bumps 5. In an embodiment of the invention, the device The wafer layers 1(0)_1(4) are DRAM wafers. In this embodiment, the dram wafers K4) have the same memory capacity and the same structure, and can be read or written separately. In the example, all of the crystals > 5 (or wafer layers) 1 (0) - 1 (4) of the three-dimensional wafer device 1 have an inherent layer identification, numbering as a distinction. The desired wafer can be identified by different layer identification numbers from three dimensions. The wafer layer 1 (0) 1 (4) of the wafer device 1 is selected. A detection circuit is provided for each of the wafers i(9)·i(4) of the two-dimensional wafer device i, which is disposed outside the memory circuit and is responsible for executing a #层 identification number. (4) The specific configuration and operation of the circuit are as follows. In the embodiment of the present invention, a three-dimensional wafer device is provided, which is formed by stacking a plurality of wafers 1 (〇)_1(4) of the same or different types. The method includes: a plurality of decrement circuits 22 connected in sequence to perform a subtraction operation for calculating the input value of the wafer 1 (〇) 1 (4) of the three-dimensional wafer device! and outputting the plurality of layer identification numbers to the three-dimensional wafer device Each of the wafer layers 1 (0)-1 (4) 'and a plurality of bumps 5 coupled to each of the wafer layers 1(0)-1(4) of the three-dimensional wafer device; wherein the layer identification number is N bits of 201203496, and σ is not M semiconductor wafers satisfying the MS 2n relationship are stacked with the semiconductor chips assigned the layer identification number.

The first figure shows a detection circuit 2 (〇)_21 (4) of an embodiment of the present invention, which is formed in each three-dimensional wafer device! Each wafer layer 1 (〇)·1 (4). In the second figure, the detection circuit paste -21(4) is constructed by connecting three-dimensional wafer device k wafer layers (〇) 1 (4) in series. Each detection circuit 21 (〇)_21 (sentence execution of a Xianli circuit in this embodiment, each wafer layer i (9) · 丨 (4) is a dream perforation: connection. Since the five detection circuits 21 (〇) _21 (4) have the same composition The following is mainly described by the declining layer identification number detecting circuit 任意 of any wafer. The decrementing layer identification number detecting circuit 21(〇)-21(4) automatically generates the wafer layers of the three-capacitor diaphragm. Layer identification number of 1(4). For better understanding, each decrementing layer identification number detecting circuit 2 丨(0)_2丨(4) includes a decrement circuit 22 (shown in the fourth figure), and performs layer identification. The number of the two values is 1. The first layer identification number detecting circuit 21 (〇) The second value is further divided into 4, and this value is assigned as a layer of the wafer layer (10) of the three-dimensional wafer device i. Identification number. Next, the first layer identification number is reduced by 1 different, which is the second layer identification number detecting circuit 2] (]) minus "the input value of the circuit 22" and its output value will be assigned as a three-dimensional The second layer identification number 3 of the wafer device <second wafer layer (1)). Similarly, the layer identification number detecting circuits 21 (2), 21 (3), and 21 (4) are formed, and the operational output of the circuit 22 is sequentially decremented by 1 and simultaneously transmitted to the subsequent stage. 'The third wafer layer 1 (7) of the three-dimensional wafer device i is assigned the third layer identification ^ 2 the fourth wafer layer 1 (3) is assigned the fourth layer identification number and the fifth crystal 201203496 layer 1 (4) is assigned the fifth layer identification number Hey. Next, the final operational output value of the subtractive circuit 22 of the final wafer layer U4) is 〇', which can be used as an output for discriminating the total number of stacked wafers of the stacked semiconductor device. The figure shows the detection circuit of another embodiment of the present invention.

21(0)-21(4), which are formed on each of the wafer layers of each three-dimensional wafer device, ^0)-1(4). The input value of the decrementing circuit u of the first layer identification number detecting circuit 21 (〇) is set to 5' while performing subtraction! The operation is performed and the output value is 4, which is assigned to the first layer identification code of the first wafer I 1 (〇) of the three-dimensional wafer device 1. Next, the second layer identification number detecting circuit 21 (丨) operates the first layer identification number 4 minus i, and the output value thereof is assigned as the input value of the third layer identification number detecting circuit 21(2). The output value of the second layer identification number detecting circuit is calculated by subtracting 1 from the first layer identification number 4, and is the second layer identification number 3 of the second chip | i(1) of the triple chip device 1. Similarly, the operation outputs of the respective decrement circuits 22 of the layer identification number detecting circuits .21 (2), 21 (3), and 21 (4) are sequentially decremented by 1 and simultaneously transmitted to the subsequent stage. = The third wafer of the three-dimensional wafer assembly i 1 ^ 2 (2) is assigned the third layer identification, the delivery 2, the fourth wafer layer 1 (3) is assigned the fourth layer identification number! And the fifth wafer layer J (4) is assigned a fifth layer identification number 〇. Next, the final wafer layer...): The final operational output value of the subtraction circuit 22 is 〇, which can be used as an output for discriminating the total number of wafers of the stacked semiconductor memory device. . . The fourth figure is a block diagram showing the structure of the decremental layer identification number detection in the embodiment of the present invention. The decreasing layer identification number detecting circuit 21 (4) is formed on each of the wafer layers 1 (1) (4) of the three-dimensional wafer device j, and includes the configuration and operation of each of the subtracting circuits 22. In one embodiment of the present invention, the decrement 201203496 circuit 22 includes three sequentially connected full adders 221, 222, 223 to perform a 3-bit it decrement operation, and each full adder includes two half-porters And an OR circuit.

The fifth figure shows the circuit configuration of the full gain of the bit circuit of the decrementing circuit in the embodiment of the present invention. The full 11 is a logic circuit' which performs three i-bit binary numbers, which is the addition of the input bit A b and the input carrier Q, and produces a 2-bit output value C. And S. As shown in the figure, each full-mouth device consists of two half-adders and milk, connecting A and B as the first-half adder-like input value, and connecting the sum to the input of the first half of Jiajie 225. The value and the 〇R circuit, and then the Ci to the second input 225 of the second half adder 225, obtain two output values c. And s. The half adder is a logic circuit having two input values, typically A 盥 B for ' and two output values' for output bit 8 and carrier c. Similarly, the output bit S can be A, B, and. 3-bit x〇R circuit, and c. It can be a 3-bit majority function for A, B and Cl2. The circuit of the half-adder is one-bit half of the full adder. The seventh figure shows the clamped example of the embodiment of the present invention, and the eighth figure shows the threshold table of the adder of the embodiment of the present invention. The sixth figure is the depreciation table of the bit full adder. As shown in the figure = input carrier. And input bits a, b are both. , then output and carrier output C. Both are G' or when all input carriers Μ: into η, : are both, then output bit s and carrier output c. All are. Although one of the input carrier Q and the input bits A and B is i, the bit is output and the carrier is rotated by C. Is 0. At the same time, when the input load 201203496 and the input bits A, B are both 丨, the output bit 3 is 〇, and the carrier output C. Is 1. As shown in the fourth figure, the 1-bit decrement circuit 22 is connected by three full adders 221, 222, and 223. The output signal of the first full adder 221 is the carrier output C. It is input to the second full adder 222 as the input carrier Q of the second full adder 222. Next, the output signal of the second full adder 222 is the carrier output C. And input it to the third full adder 223 as the input carrier Ci of the third full adder 223. Further, the 3-bit layer identification number is composed of 3-bit A, A, and A2, and the bit A is input to the first full adder 22, and the bit Ai is input to the second full adder 222. Similarly, the bit Element VIII is input to the third full adder 223. The 3-bit of the decrement circuit 22 is composed of the bits S〇, S! and S2 output after the operation, the first full adder 221 outputs the bit %, and the second full adder 222 outputs the bit Si, and the third full The adder 223 outputs the bit S2. The ninth drawing shows a threshold value table of the decrementing circuit of the fourth figure in the embodiment of the present invention. The 3-bit s〇, heart, and & output of the operation output are changed as shown in the ninth figure with respect to the 3-bit Α(), Αι, and #A2 constituting the input layer identification number. Decrease the circuit by 1 and follow the order of the effort A0, eight! And A? performs the operation, and outputs the white effort values 8〇, 81, and S2 in order. Enter 1U to 〇〇〇 to get the round 1 1 0 to 1 1 1 . In the second figure, 'all declining type layer identification number detecting circuits 21(0)-2 1(4) respectively include the configuration of the aforementioned decrementing circuit 22, and these decrementing type layer identification code detecting circuits 21(0)-21(4) The system is sequentially connected and operates as in the embodiment. The lower five values of the threshold table of the ninth graph correspond to the decrementing circuit 11 201203496 22 of the decrementing layer identification number detecting circuit 21(0)·21(4) of the second figure, respectively. In one embodiment of the present invention, the input value of the decrement circuit 22 of the first wafer layer K0 of the wafer device 1 is set to 4 because the three bits a, a, and a2 are three. Next, the decrement circuit 22 calculates the three bits A 〇 , 八 、 and A ′ ' and transmits the calculated output values s 〇 , & and ^ as the rounding value of a wafer under the three-dimensional wafer device 1 ' Each input value function is a layer identification number. Therefore, the layer identification number, i.e., the input values of the five decrement circuits 22, continuously changes from 4 to 0 (the white effort value is combined from 011 to 〇〇〇). Next, the layer identification numbers 4 to 0 can be assigned to the respective wafer layers of the three-dimensional wafer device 1 (〇)_i (4). Since the layer identification number 4-0 is assigned to each wafer layer of the three-dimensional wafer device 1 (〇)_1 (4) is unique and different from the other (per_) wafer layer, the layer identification number 4-0 can be used to specify the required Wafer.

The above description is a preferred embodiment of the invention. Those skilled in the art should be able to appreciate the scope of the patent rights which are used to illustrate the invention and not to limit the invention. The scope of patent protection depends on the patent application and its equivalent fields. Any person skilled in the art, without departing from the spirit or scope of this patent, may change the equivalents or materials that are completed under the spirit of the present invention, and shall include the following claims. Within the scope. BRIEF DESCRIPTION OF THE DRAWINGS The structural side of the device shows a three-dimensional wafer surface illustration of an embodiment of the present invention. The first drawing shows the identification of the degraded layer identification number of each slice of the three-dimensional wafer device according to the embodiment of the present invention. The schematic diagram of the structure of the circuit; m 12 201203496 is a structural diagram showing the structure of the decreasing layer identification number detecting circuit of the three-dimensional cymbal according to another embodiment of the present invention, and showing: the decreasing layer of the embodiment of the present invention; The block diagram of the number detection benefit; the fifth figure shows the circuit configuration example of the device of the decrement circuit in the embodiment of the present invention; and the sixth figure shows the 八 of one of the decrement circuits in the embodiment of the present invention. The seventh table shows a circuit of a one-bit half adder in the embodiment of the present invention; the eighth figure of the adder shows a one-digit half-table in the embodiment of the present invention; The ninth figure shows a threshold table of the decreasing type layer number measurement circuit of the fourth embodiment of the embodiment of the present invention. Ά [Main component symbol description] 1 Two-dimensional wafer device 2 Substrate 3 Interface wafer 1 (0)-1 (4) First to fifth wafer layer 4 Bead 5 Bump 22 Decrement circuit 21 (0)-21 (4 Decreasing layer identification number detection circuit (detection circuit) 13 201203496 221, 222, 223 full adder 224 ' 225 half adder A, B input bit Ci input carrier C 〇 carrier output S output bit So, Si, S2 bit A〇, Ai, A2 bit

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Claims (1)

201203496 VII. Patent application scope: 1 · A two-dimensional wafer device, which is composed of a plurality of wafer stacks, and includes: a plurality of subtraction circuits sequentially connected to perform a subtraction operation for calculating the input of the three-dimensional wafer device chip a value, and a layer identification number of each of the wafer layers of the three-dimensional wafer device is rotated; and a plurality of bumps coupled to each of the wafer layers of the three-dimensional wafer device; wherein the layer identification number is! The combination of the ^ bits indicates that the μ semiconductor wafers that satisfy the M $ 2 relationship are stacked with the μ semiconductor wafers assigned the layer identification number. 2. The three-dimensional wafer device of claim 3, wherein each of the decrementing circuits comprises three sequentially connected full adders, wherein each of the full adders comprises two half adders and one 〇R circuit . 3. The three-dimensional chip device of claim 1, wherein among the M-1 of the decrementing circuits sequentially connected, the input value of the decrementing circuit is set to 攸Μ-1, and the μ decrementing circuit is The input values are respectively m_1 to 〇 as the layer identification number, which are sequentially assigned to the one wafer layer. 4. The three-dimensional chip device of claim 3, wherein among the ones of the subtractive circuits sequentially connected, the input value of the decrementing circuit is set from Μ, and the input values of the ones of the decrementing circuits are respectively Μ·〗 至〇 As the layer identification number, it is sequentially assigned to the one wafer layer. m 15 201203496 One of the two-dimensional wafer devices 'each of the wafer layers is a semiconductor memory wafer for storing data. 6. The three-dimensional wafer device of claim 5, wherein each of the semiconductor memory chips includes an arithmetic circuit in addition to the memory circuit. 7. The three-dimensional wafer device of claim 5, wherein each of the semiconductor memory wafers has the same capacity and the same configuration. 8. The three-dimensional wafer device of claim 5, wherein each of the semiconductor memory chips is a DRAM wafer. 9. A descending layer identification number detecting circuit for a one-dimensional chip device, comprising: - a plurality of decrementing circuits sequentially connected to perform a subtractive i operation, wherein the X operation is performed, and the quasi-chip device chip Inputting a value and outputting a layer identification number of each wafer layer of the three-dimensional wafer device; and a plurality of bumps coupled to each of the wafer layers of the three-dimensional wafer device; the layer identification number is represented by a combination of N bits One of the semiconductors that satisfy the ΜS2N relationship is assigned a stack of semiconductor wafers assigned the layer identification number. 10. The decremental layering of the three-dimensional wafer device of claim 9 of the patent application scope. 201203496 The numbering detection circuit, wherein each of the decrementing circuits comprises three serially connected full adders. The descending layer identification number detecting circuit of the three-dimensional chip device of claim 9 wherein, in the sequentially connected M·the one of the decreasing circuits, the input value of the decrementing circuit is set from M-1, The input values of the p decrement circuits are respectively M_! to 〇 as the layer identification number, and are sequentially allocated to the one wafer layer. The descending type of the three-dimensional wafer device of the ninth item of the benefit range ===' wherein the number of the decrementing circuits connected in sequence is reduced by the I:: the input value is set from Μ, and the input values of the circuits are respectively As for this, the M wafer layers are sequentially assigned. The layer of cleverness is not compiled. 17