JP2013115349A - Manufacturing method and manufacturing system of semiconductor wafer laminate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield of semiconductor chip laminate manufactured by a wafer-to-wafer lamination method.SOLUTION: The manufacturing method of a semiconductor wafer laminate formed by laminating a first kind of semiconductor wafer 10 on which a plurality of first semiconductor chips 11 are formed, and a second kind of semiconductor wafer 30 on which a plurality of second semiconductor chips 31 are formed, includes the steps of: preparing a plurality of first kind of semiconductor wafers where the physical or electrical characteristics of each first semiconductor chip are known; preparing a plurality of second kind of semiconductor wafers where the physical or electrical characteristics of each second semiconductor chip are known; and selecting first kind and second kind of semiconductor wafers to be laminated among the plurality of first kind and second kind of semiconductor wafers, on the basis of the physical or electrical characteristics of each first semiconductor chip on each first kind of semiconductor wafer, and the physical or electrical characteristics of each second semiconductor chip on each second kind of semiconductor wafer.

Description

  The present invention relates to a manufacturing method and a manufacturing system for a semiconductor wafer laminate.

  The speed, size and cost of integrated circuit elements mounted on electronic devices are being promoted. An integrated circuit element can be manufactured by stacking a plurality of semiconductor chips having a predetermined function and packaging the stacked semiconductor chips (semiconductor chip stack) with a mold resin or the like (for example, Patent Document 1). .

  A semiconductor chip is formed by performing optical processing or the like on the surface of a semiconductor substrate called a wafer. For example, hundreds to thousands of semiconductor chips can be formed on a wafer having a diameter of 300 mm.

  Examples of a method for obtaining a semiconductor chip laminate include a chip-to-chip lamination method and a wafer-to-wafer lamination method. The chip-to-chip stacking method is a method of dividing a variety of wafers on which a plurality of semiconductor chips are formed into single semiconductor chips, and then stacking the divided semiconductor chips to obtain a semiconductor chip stack. . The wafer-to-wafer laminating method is a method of obtaining a semiconductor chip laminated body by laminating various wafers on which a plurality of semiconductor chips are formed and then dividing the laminated wafer (wafer laminated body). The wafer-to-wafer laminating method has higher productivity than the chip-to-chip laminating method, and can contribute to cost reduction of the integrated circuit element to be manufactured.

JP 2009-53081 A

  The productivity of wafer-to-wafer stacking needs to be further improved. An object of the present invention is to improve the yield of a semiconductor chip stacked body manufactured by a wafer-to-wafer stacking method.

  According to one aspect of the present invention, a semiconductor wafer formed by laminating a first type semiconductor wafer in which a plurality of first semiconductor chips are formed and a second type semiconductor wafer in which a plurality of second semiconductor chips are formed. A method of manufacturing a laminated body, comprising preparing a plurality of the first type semiconductor wafers whose physical or electrical characteristics of each of the first semiconductor chips are known, and physically or each of the second semiconductor chips. A plurality of the second type semiconductor wafers having known electrical characteristics are prepared, the physical or electrical characteristics of each of the first semiconductor chips in each of the first type semiconductor wafers, and the second type semiconductors Based on the physical or electrical characteristics of each of the second semiconductor chips in each wafer, the first type and the second type of the plurality of first type and second type semiconductor wafers to be stacked are stacked. Method of manufacturing a semiconductor wafer stack that performs selection of conductor wafer, is provided.

  According to another aspect of the present invention, a semiconductor formed by laminating a first type semiconductor wafer in which a plurality of first semiconductor chips are formed and a second type semiconductor wafer in which a plurality of second semiconductor chips are formed. A wafer stack manufacturing system, comprising: a physical or electrical characteristic of each of the first semiconductor chips formed on the first type semiconductor wafer; and a second type formed on the second type semiconductor wafer. A measuring device for measuring physical or electrical characteristics of each of the semiconductor chips, a physical or electrical characteristic of each of the first semiconductor chips in the first type semiconductor wafer measured by the measuring device, and a plurality of A memory for storing physical or electrical characteristics of each of the second semiconductor chips in the second type semiconductor wafer for a plurality of the first type and second type semiconductor wafers. And physical or electrical characteristics of each of the first semiconductor chips in each of the first type semiconductor wafers stored in the storage device, and the second semiconductor chips in each of the second type semiconductor wafers An arithmetic unit for selecting a first type and a second type semiconductor wafer to be laminated from the plurality of first type and second type semiconductor wafers based on each physical or electrical characteristic; A semiconductor wafer stack manufacturing system is provided.

  The yield of the semiconductor chip stack manufactured by the wafer-to-wafer stack method is improved.

FIG. 1A is a schematic perspective view showing a state in which a plurality of types of semiconductor wafers are stacked to form a semiconductor wafer stack, and FIG. 1B is a diagram in which a plurality of types of semiconductor wafers are stacked and semiconductors formed on various types of semiconductor wafers. It is a schematic sectional drawing which shows a part of a mode that the chip | tip was electrically connected mutually. 2A to 2D are plan views showing defect distributions of the semiconductor chips 11 to 41 in the semiconductor wafers 10a to 40a, respectively. FIG. 2E is a semiconductor chip stack in the semiconductor wafer stacked body 50a in which the semiconductor wafers 10a to 40a are stacked. 4 is a plan view showing a defect distribution of a body 53. FIG. 3A to 3D are plan views showing defect distributions of the semiconductor chips 11 to 41 in the semiconductor wafers 10b to 40b, respectively. FIG. 3E is a semiconductor chip stacking in the semiconductor wafer stacked body 50b in which the semiconductor wafers 10b to 40b are stacked. 4 is a plan view showing a defect distribution of a body 53. FIG. FIG. 4 is a diagram schematically showing a semiconductor wafer laminate manufacturing system according to an embodiment. 5A and 5B are diagrams schematically showing the first processing by the arithmetic device. 6A and 6B are diagrams schematically showing the second processing by the arithmetic device. 7A and 7B are diagrams schematically showing another process performed by the arithmetic device.

  FIG. 1A is a schematic perspective view showing a state in which a plurality of types of semiconductor wafers are stacked to form a semiconductor wafer stacked body. The semiconductor wafer laminate 50 is formed, for example, by laminating about 2 to 5 semiconductor wafers composed of silicon substrates, and has a thickness of about 10 μm to 50 μm. FIG. 1A shows a case where four semiconductor wafers 10, 20, 30, 40 are stacked as an example. A plurality of semiconductor chips 11, 21, 31, and 41 are respectively formed on the semiconductor wafers 10 to 40 (the semiconductor chips 31 and 41 are not shown in FIG. 1A). For example, an integrated circuit such as a CPU (Central Processing Unit), a DRAM (Dynamic Random Access Memory), or a flash memory is formed in each of the semiconductor chips 11 to 41. Each of the semiconductor wafers 10 to 40 has a diameter of about 300 mm, for example, and hundreds to thousands of semiconductor chips 11 to 41 are formed. In FIG. 1A, for convenience, the size of the semiconductor chip is shown larger than the actual size.

  FIG. 1B is a schematic cross-sectional view showing a part of a state in which a plurality of types of semiconductor wafers are stacked and semiconductor chips formed on the various types of semiconductor wafers are electrically connected to each other.

  The semiconductor chip 11 formed on the semiconductor wafer 10 includes, for example, a semiconductor element layer 12 and a wiring layer 13. A plurality of semiconductor elements such as MOS transistors are formed in the semiconductor element layer 12. In the wiring layer 13, wirings that electrically connect a plurality of semiconductor elements formed in the semiconductor element layer 12 are formed. Thus, the semiconductor chip 11 operates as an integrated circuit that performs a predetermined function.

  The semiconductor chip 11 is further connected to a plurality of electrode terminals 51 provided through the semiconductor chip 11 and a plurality of electrode terminals 51, and a plurality of electrode pads or solder bumps 52 provided on both surfaces of the semiconductor chip 11. Including. For example, tens of thousands of electrode terminals 51 can be formed on a single semiconductor chip 11. The electrode terminal 51 may be referred to as TSV (Through Silicon Via).

  The semiconductor wafers 20 to 40 have the same configuration as that of the semiconductor wafer 10 and include semiconductor element layers 22 to 42, wiring layers 22 to 24, electrode terminals 51, and solder bumps 52, respectively. The semiconductor wafers 10 to 40 are stacked and electrically connected to each other through solder bumps 52 formed on both surfaces of each of the semiconductor wafers 10 to 40. Thereby, the semiconductor wafer laminated body 50 is formed.

  Furthermore, the semiconductor chip laminated body 53 can be obtained by dividing the formed semiconductor wafer laminated body 50 into individual laminated semiconductor chips 11 to 41. The semiconductor chip stacked body 53 operates as a device that performs a predetermined function in which the semiconductor chips 11 to 41 cooperate with each other. When the semiconductor chips 11 to 41 are, for example, integrated circuits that function as an imaging sensor circuit, an analog-digital conversion circuit, a register circuit, and a processor circuit, respectively, the semiconductor chip stacked body 53 operates as an imaging sensor device.

  Not a few defective semiconductor chips can be formed on a semiconductor wafer due to variations in manufacturing equipment. Further, the position / distribution at which the defective semiconductor chip is formed may be different for each manufactured semiconductor wafer. The semiconductor chip stacked body operates as a device that performs a predetermined function by the cooperation of a plurality of semiconductor chips constituting the semiconductor chip stacked body. Therefore, when any one of the plurality of semiconductor chips does not operate properly, the semiconductor chip stack cannot operate properly, and the semiconductor chip stack becomes a defective product.

  2A to 2D are plan views showing defect distributions of the semiconductor chips 11 to 41 in the semiconductor wafers 10a to 40a, respectively. Here, 32 semiconductor chips 11 to 41 are formed on each of the semiconductor wafers 10a to 40a, and 4 defective semiconductor chips 11d to 41d (defective chips) among the 32 semiconductor chips are formed. To do. That is, the defect rate of each of the semiconductor wafers 10a to 40a is 4/32. In the drawing, defective chips formed in the wafer are indicated by hatching.

  As shown in FIG. 2A, it is assumed that defective chips 11d are concentrated and distributed on the upper left side of the semiconductor wafer 10a. As shown in FIG. 2B, it is assumed that defective chips 21d are concentrated and distributed on the upper right side of the semiconductor wafer 20a. As shown in FIG. 2C, it is assumed that defective chips 31d are concentrated and distributed on the lower left side of the semiconductor wafer 30a. As shown in FIG. 2D, it is assumed that defective chips 41d are concentrated and distributed on the lower right side of the semiconductor wafer 40a.

  The semiconductor wafers 10a to 40a having such a defective chip distribution are stacked to form a semiconductor wafer stacked body 50a and a semiconductor chip stacked body 53. Each of the formed semiconductor chip stacks 53 is regarded as defective when at least one of the semiconductor chips 11 to 41 constituting the semiconductor chip stacked body 53 is a defective chip.

  2E is a plan view showing a defect distribution of the semiconductor chip stacked body 53 in the semiconductor wafer stacked body 50a in which the semiconductor wafers 10a to 40a illustrated in FIGS. 2A to 2D are stacked. When the semiconductor wafer stack 50a is formed by stacking the semiconductor wafers 10a to 40a shown in FIGS. 2A to 2D, the defect rate of the semiconductor wafer stack 50 is a simple sum of the defect rates of the semiconductor wafers 10a to 40a. Becomes 16/32.

  3A to 3D are plan views showing the distribution of defects of the semiconductor chips 11 to 41 in the semiconductor wafers 10b to 40b, respectively. Here, the defect rate of each of the semiconductor wafers 10b to 40b is assumed to be 4/32 as in FIGS. 2A to 2D. However, unlike the defective chip distribution shown in FIGS. 2A to 2D, it is assumed that defective chips 11d to 41d are concentrated and distributed in the upper left of the wafer in any of the semiconductor wafers 10b to 40b.

  3E is a plan view showing a defect distribution of the semiconductor chip stacked body 53 in the semiconductor wafer stacked body 50b in which the semiconductor wafers 10b to 40b illustrated in FIGS. 3A to 3D are stacked. When the semiconductor wafer stack 50b is formed by stacking the semiconductor wafers 10b to 40b shown in FIGS. 3A to 3D, the defect rate of the semiconductor wafer stack 50b is 8/32. The defective rate of the formed semiconductor chip stacked body is lower than when the semiconductor wafers 10a to 40a illustrated in FIGS. 2A to 2D are stacked. In this way, by stacking more defective chips formed on various semiconductor wafers, that is, by stacking semiconductor wafers having a defective chip distribution at similar positions in the wafer, semiconductor chip stacking that is a defective product It is possible to reduce the body and obtain more non-defective semiconductor chip stacks.

  For example, the yield of a semiconductor wafer in which the structure of each semiconductor chip is complicated and the mounting density of the semiconductor chips is high is approximately 70 to 80%. The stacking yield of a semiconductor wafer stack formed by stacking four semiconductor wafers with a yield of approximately 70-80% extracted at random is approximately 24-41%. On the other hand, the stacking yield of a semiconductor wafer stack formed by selecting a semiconductor wafer having a defective chip distribution at the same position in the wafer is ideally equivalent to the yield of a single semiconductor wafer. It can be about 80%.

  Hereinafter, a manufacturing method and a manufacturing system capable of improving the yield of the semiconductor wafer laminate will be specifically described.

  FIG. 4 is a diagram schematically showing a semiconductor wafer laminate manufacturing system according to an embodiment. In the following, a case where three semiconductor wafer stacks composed of two types of semiconductor wafers are formed will be described.

  The conductor wafer laminate manufacturing system according to the embodiment has a configuration including a measuring device 61, a storage device 62, and an arithmetic device 63.

  The measuring device 61 includes physical or electrical characteristics of a plurality of semiconductor chips 11 (FIGS. 1A to 1B) formed on each of the first type semiconductor wafers 10a to 10c, and the second type semiconductor wafers 20a to 20c. The physical or electrical characteristics of a plurality of semiconductor chips 21 (FIGS. 1A to 1B) formed in each are measured. The physical characteristics of the semiconductor chips 11 and 21 include, for example, the layer thicknesses of the semiconductor element layers 12 and 22 (FIG. 1B) to the wiring layers 13 and 23 (FIG. 1B), and the wiring formed on the wiring layers 13 and 23. For example, the width and the density of lattice defects included in the semiconductor chips 11 and 21. The electrical characteristics of the semiconductor chips 11 and 21 include, for example, current / voltage values (including electrical shorts / openings) and operation clocks in each circuit block of the integrated circuit formed on the semiconductor chips 11 and 21. For example, frequency characteristics.

  The characteristic data of each semiconductor chip 11 in each of the semiconductor wafers 10 a to 10 c and the characteristic data of each semiconductor chip 21 in each of the semiconductor wafers 20 a to 20 c measured by the measuring device 61 are transferred to the storage device 62. The measuring device 61 may be a measuring device configured separately from a measuring device that measures the semiconductor wafers 10a to 10c and a measuring device that measures the semiconductor wafers 20a to 20c. Further, the measuring device for measuring the physical characteristics of the semiconductor chip and the measuring device for measuring the electrical characteristics may be separately configured, or other characteristics / performances of the semiconductor wafer or the semiconductor chip may be used. There may be a separate measuring device for measuring.

  The storage device 62 stores the characteristic data of each semiconductor chip 11 in each of the semiconductor wafers 10a to 10c and the characteristic data of each semiconductor chip 21 in each of the semiconductor wafers 20a to 20c measured by the measuring device 61. As the storage device 62, for example, an HDD (Hard Disk Drive), a flash memory, or the like can be used. The characteristic data of each semiconductor wafer stored in the storage device 62 can be read from an external device such as the arithmetic device 63.

  Based on the characteristic data of each of the semiconductor chips 11 in each of the semiconductor wafers 10a to 10c and the characteristic data of each of the semiconductor chips 21 in each of the semiconductor wafers 20a to 20c, the arithmetic unit 63 stores the semiconductor wafers 10a to 10c. 10c and the distribution of defective chips in each of the semiconductor wafers 20a to 20c are calculated. Furthermore, the arithmetic unit 63 selects the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c to be stacked based on the calculated defective chip distributions of the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c. At that time, for example, the arithmetic unit 63 selects a combination of the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c so that the yield of a plurality of finally formed semiconductor wafer stacks becomes the highest. As the arithmetic device 63, for example, a personal computer (PC) can be used.

  Thereafter, the semiconductor wafers 10 a to 10 c and the semiconductor wafers 20 a to 20 c are stacked by the wafer stacking device 64 in the combination selected by the arithmetic device 63. Thus, the semiconductor wafer laminated bodies 50a-50c are manufactured.

  Next, the first process of the arithmetic unit 63 that optimizes the combination of the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c to be stacked will be described.

  FIG. 5A is a plan view showing defective chip distribution of the first type semiconductor wafer 10a and the second type semiconductor wafer 20a. In addition, the semiconductor wafer stack 50 formed when the semiconductor wafer 10a and the semiconductor wafer 20a are stacked is a plan view showing a defect distribution.

  The arithmetic device 63 calculates the defective chip distribution of each of the semiconductor wafers 10a to 10c based on the characteristic data of each of the semiconductor chips 11 in each of the semiconductor wafers 10a to 10c stored in the storage device 62. For example, as shown in FIG. 5A, the arithmetic unit 63 sets a flag of numerical value 0 on a semiconductor chip 11d that does not operate properly due to an electrical short circuit / opening or the like, and sets a numerical value 1 on other semiconductor chips 11g. Set the flag.

  Similarly, the arithmetic device 63 calculates the defective chip distribution of each of the semiconductor wafers 20a to 20c based on the characteristic data of each of the semiconductor chips 21 in each of the semiconductor wafers 20a to 20c stored in the storage device 62. For example, the arithmetic unit 63 sets a flag of numerical value 0 on a semiconductor chip 21d that does not operate properly due to, for example, an electrical short circuit / opening, as in the semiconductor wafer 20a shown in FIG. 5A, and sets numerical values on the other semiconductor chips 21g. Set the 1 flag.

  Further, the arithmetic unit 63 is configured such that each semiconductor chip stack 53 formed by stacking the semiconductor wafer 10a and the semiconductor wafer 20a as in the semiconductor wafer stack 50 shown in FIG. , 21 is set to a flag obtained by integrating the flags attached thereto. At this time, the semiconductor chip stacked body 53 with the flag set to 0 becomes a defective semiconductor chip stacked body 53d, and the semiconductor chip stacked body 53 with the flag set to 1 becomes a non-defective semiconductor chip stacked body 53g.

  The arithmetic device 63 further calculates the total number of flags attached to each of the semiconductor chip stacks 53. In other words, when the semiconductor wafer 10a and the semiconductor wafer 20a are stacked, the total of the flags obtained by integrating the flags of the semiconductor chips 11 and the flags of the semiconductor chips 21 respectively superimposed on the semiconductor chips 11 is calculated. The cumulative number of flags in the semiconductor wafer stack 50 shown in FIG. Here, the total of the flags attached to each of the semiconductor chip stacks 53 of the semiconductor wafer stack 50 in which the semiconductor wafers 10a and 20a are stacked is referred to as a non-defective product total value C11 of the semiconductor wafers 10a and 20a. And

  The arithmetic device 63 performs the above processing on all pairs of the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c, and calculates the good product cumulative value of each pair. Assume that the non-defective product cumulative values of the semiconductor wafer 10a and the semiconductor wafers 20a to 20c are C11, C12, and C13, respectively. Assume that the non-defective product accumulated values of the semiconductor wafer 10b and the semiconductor wafers 20a to 20c are C21, C22, and C23, respectively. Assume that the non-defective product cumulative values of the semiconductor wafer 10c and the semiconductor wafers 20a to 20c are C31, C32, and C33, respectively.

  FIG. 5B shows combinations P1 to P6 of semiconductor wafers 10a to 10c and semiconductor wafers 20a to 20c that can be stacked. The arithmetic unit 63 calculates the sum S1 to S6 of the good product cumulative values for each of the combinations P1 to P6 of the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c that can be stacked. The arithmetic unit 63 selects the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c to be stacked in a combination that maximizes the total sum of the good product cumulative values.

  When the arithmetic unit 63 performs such processing, the yield can be improved as compared with the case where a semiconductor wafer stack is formed by randomly extracting semiconductor wafers. Even when two or more types of semiconductor wafers are stacked to form a stack of three or more semiconductor wafers, the number of combinations increases. It is possible to select a combined combination. The number of various semiconductor wafers to be verified at a time may be set to a number corresponding to the production lot of various semiconductor wafers (for example, 25).

  Next, a second process of the arithmetic unit 63 that optimizes the combination of the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c to be stacked will be described.

  6A and 6B are plan views showing the distribution of defective chips in the first type semiconductor wafers 10a to 10c and the second type semiconductor wafers 20a to 20c. The arithmetic device 63 calculates the defective chip distribution of each of the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c, as in the first process described above.

  The arithmetic unit 63 has the largest cumulative number of flags attached to each of the semiconductor chips 11 out of one of the first-type and second-type semiconductor wafers, for example, the first-type semiconductor wafers 10a to 10c. Select a type of semiconductor wafer. In the semiconductor wafers 10a to 10c shown in FIG. 6A, the cumulative number of flags is 27, 28, and 30, respectively. Therefore, the semiconductor wafer 10c having a cumulative flag of 30 is selected.

  Next, the arithmetic unit 63 selects the second type semiconductor wafer having the highest non-defective product accumulated value when stacked with the semiconductor wafer 10c from the second type semiconductor wafers 20a to 20c. The non-defective product cumulative values of the semiconductor wafer 10c and the semiconductors 20a to 20c are 26, 26, and 28, respectively. Therefore, the semiconductor wafer 20c having a non-defective product cumulative value of 28 is selected. A semiconductor wafer laminate is formed by the selected semiconductor wafer 10c and semiconductor wafer 20c.

  Next, the arithmetic unit 63 performs the same processing on the semiconductor wafers excluding the semiconductor wafer 10c and the semiconductor wafer 20c. That is, as shown in FIG. 6B, when the semiconductor wafer 10b having a large cumulative flag is selected from the semiconductor wafers 10a and 10b, and the semiconductor wafer 10b is stacked from the semiconductor wafers 20a and 20b, the good product cumulative value is obtained. A semiconductor wafer 20a with a large value is selected. A semiconductor wafer stack is formed by the selected semiconductor wafer 10b and semiconductor wafer 20a. Further, a semiconductor wafer laminate is formed from the remaining semiconductor wafer 10a and semiconductor wafer 20b.

  Even in such a process, the yield can be improved as compared with the case where a semiconductor wafer stack is formed by randomly extracting semiconductor wafers. In the above, a flag of 0 is set for a semiconductor chip determined to be defective and a flag of 1 is set for a semiconductor chip determined to be non-defective. Conversely, a flag of 1 is set for a semiconductor chip determined to be defective. The optimum combination of various semiconductor wafers may be calculated by setting a flag of 0 to a semiconductor chip determined to be a non-defective product. Further, the numerical value attached to the semiconductor chip may be a numerical value other than 0 and 1.

  In the above description, the non-defective product / defective product is determined for each semiconductor chip formed on the semiconductor wafer. However, the non-defective product region / defective product region may be determined for each region in the semiconductor wafer. In addition, the non-defective product area / defective product area may be judged as a non-standard area that satisfies the required physical or electrical characteristics / a non-standard area that does not satisfy the required physical or electrical characteristics. Absent. Hereinafter, another process of the arithmetic device 63 that optimizes the combination of the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c to be stacked will be described.

  FIG. 7A is a plan view showing a nonstandard region of the first type semiconductor wafer 10a and the second type semiconductor wafer 20a. Further, FIG. 5 is a plan view showing a defective region of the semiconductor wafer stacked body 50 formed when the semiconductor wafer 10a and the semiconductor wafer 20a are stacked.

  Based on the semiconductor chip characteristic data in each of the plurality of semiconductor wafers 10a to 10c stored in the storage device 62 and the required physical or electrical characteristics, the arithmetic unit 63 applies to each of the semiconductor wafers 10a to 10c. And defining a region having a predetermined characteristic distribution. The arithmetic device 63 defines, as the nonstandard region 15, a region where a semiconductor chip that does not satisfy the required physical or electrical characteristics, such as the semiconductor wafer 10a shown in FIG.

  Similarly, the arithmetic unit 63 uses the semiconductor wafers 20a to 20c based on the characteristic data of the semiconductor chips in each of the plurality of semiconductor wafers 20a to 20c stored in the storage device 62 and the required physical or electrical characteristics. For each, a region having a predetermined characteristic distribution is defined. For example, the arithmetic unit 63 defines, as the nonstandard region 25, a region where a semiconductor chip that does not satisfy the required physical or electrical characteristics is formed as in the semiconductor wafer 20a shown in FIG. 7A.

  The nonstandard regions 15 and 25 are formed, for example, in the semiconductor element layers 12 and 22 (FIG. 1B) to the wiring layers 13 and 23 (FIG. 1B) or in the wiring layers 13 and 23 (FIG. 1B). This is a region where the width of the wiring and the density of lattice defects included in the semiconductor chips 11 and 21 are out of the required standards.

  Further, the arithmetic unit 63 defines a defective region 55 obtained by synthesizing the nonstandard regions 15 and 25 when the semiconductor wafer 10a and the semiconductor wafer 20a are stacked, like a semiconductor wafer stacked body 50 shown in FIG. 7A. Thereafter, in the same manner as in the first process, a defective region is defined for all pairs of the semiconductor wafers 10a to 10c and the semiconductor wafers 20a to 20c, and the combination of the total areas of the defective regions is minimized. The first and second type semiconductor wafers to be selected are selected. Even in such a process, it is possible to extract more semiconductor chip stacks that meet the standards than when a semiconductor wafer stack is formed by randomly extracting semiconductor wafers.

  FIG. 7B is a plan view showing a predetermined characteristic distribution in the first type semiconductor wafers 10a to 10c and the second type semiconductor wafers 20a to 20c. The computing device 63 defines the nonstandard regions 15 and 25 for each of the plurality of first and second type semiconductor wafers, and then stacks the first and second types in the same manner as in the second process. Two types of semiconductor wafers may be selected. That is, as shown in FIG. 7B, when the semiconductor wafer 10c having the smallest area of the nonstandard region 15 is selected from the first type semiconductor wafers 10a to 10c and then laminated with the semiconductor wafer 10c, The semiconductor wafer 20c having the smallest area is selected. Such processing is repeated to select the first and second type semiconductor wafers to be stacked. Even in such a process, it is possible to extract more semiconductor chip stacks that meet the standards than when a semiconductor wafer stack is formed by randomly extracting semiconductor wafers. In the above description, the nonstandard region that does not satisfy the required standard is defined in the wafer. However, the optimal region of the first and second type semiconductor wafers is defined by defining the intrastandard region that satisfies the required standard. You can choose any combination.

  As mentioned above, although this invention was demonstrated using the Example, this invention is not restrict | limited to these Examples. For example, in the embodiment, the semiconductor wafer on which the orientation flat is formed has been described, but a semiconductor wafer on which a notch is formed may be used. It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like can be made.

10 type 1 semiconductor wafer,
11 First semiconductor chip,
12 1st semiconductor element layer,
13 First wiring layer,
15 first non-standard area,
20 Second type semiconductor wafer,
21 a second semiconductor wafer,
22 2nd semiconductor element layer,
23 second wiring layer,
25 second non-standard area,
30 Third type semiconductor wafer,
31 Third semiconductor chip,
32 3rd semiconductor element layer,
33 third wiring layer,
40 Fourth type semiconductor wafer,
41 4th semiconductor chip,
42 a fourth semiconductor element layer;
43 Fourth wiring layer,
50 Semiconductor wafer laminate,
51 electrode terminals,
52 Solder bump,
53 Semiconductor chip laminate,
55 defective area,
61 measuring device,
62 storage devices,
63 arithmetic unit,
64 Wafer stacking device.

Claims (10)

A method for manufacturing a semiconductor wafer laminate, in which a first type semiconductor wafer in which a plurality of first semiconductor chips are formed and a second type semiconductor wafer in which a plurality of second semiconductor chips are formed are laminated,
Preparing a plurality of semiconductor wafers of the first type whose physical or electrical characteristics of each of the first semiconductor chips are known;
Preparing a plurality of semiconductor wafers of the second type whose physical or electrical characteristics of each of the second semiconductor chips are known;
Based on the physical or electrical characteristics of each of the first semiconductor chips in each of the first type semiconductor wafers, and the physical or electrical characteristics of each of the second semiconductor chips in each of the second type of semiconductor wafers. Selecting a first type and a second type semiconductor wafer to be laminated from among the plurality of first type and second type semiconductor wafers,
Manufacturing method of semiconductor wafer laminated body. In the first type semiconductor wafer, a region where the first semiconductor chip deviating from a predetermined physical or electrical characteristic is formed as a first nonstandard region,
In the second type semiconductor wafer, a region where the second semiconductor chip deviating from a predetermined physical or electrical characteristic is formed as a second nonstandard region,
When a region obtained by combining the first and second nonstandard regions when the first type and second type semiconductor wafers are stacked is defined as a defective region,
2. The first and second types of semiconductor wafers to be stacked are selected from among the plurality of first and second type semiconductor wafers in a combination that minimizes the total area of the defective regions. The manufacturing method of the semiconductor wafer laminated body of description. In the first type semiconductor wafer, a region where the first semiconductor chip deviating from a predetermined physical or electrical characteristic is formed as a first nonstandard region,
In the second type semiconductor wafer, a region where the second semiconductor chip deviating from a predetermined physical or electrical characteristic is formed as a second nonstandard region,
When a region obtained by combining the first and second nonstandard regions when the first type and second type semiconductor wafers are stacked is defined as a defective region,
The first type semiconductor wafer having the smallest area of the first nonstandard region is selected as the first type best semiconductor wafer from the plurality of first type semiconductor wafers,
2. The second type semiconductor wafer that minimizes the area of the defective region when being laminated with the first type best semiconductor wafer is selected from the plurality of second type semiconductor wafers. Manufacturing method of semiconductor wafer laminates. In the first type semiconductor wafer, the first semiconductor chip deviating from a predetermined physical or electrical characteristic is assigned a numerical value of 0, and the first semiconductor chip other than the first semiconductor chip assigned the numerical value of 0 is assigned to the first semiconductor chip. A finite number larger than 0 is attached to the semiconductor chip,
In the second type semiconductor wafer, a numerical value 0 is assigned to the second semiconductor chip that deviates from a predetermined physical or electrical characteristic, and the second semiconductor chip other than the second semiconductor chip having the numerical value 0 is added. A finite number larger than 0 is attached to the semiconductor chip,
When the first-type and second-type semiconductor wafers are stacked, the numerical value assigned to each of the first semiconductor chips and the second semiconductor chip superimposed on each of the first semiconductor chips. When the total of the numerical values obtained by integrating the numerical values obtained is the non-defective product cumulative value,
2. The first and second type semiconductor wafers to be stacked are selected from the plurality of first and second type semiconductor wafers in a combination that maximizes the total sum of the good product cumulative values. Manufacturing method of semiconductor wafer laminates. In the first type semiconductor wafer, the first semiconductor chip deviating from a predetermined physical or electrical characteristic is assigned a numerical value of 0, and the first semiconductor chip other than the first semiconductor chip assigned the numerical value of 0 is assigned to the first semiconductor chip. A finite number larger than 0 is attached to the semiconductor chip,
In the second type semiconductor wafer, a numerical value 0 is assigned to the second semiconductor chip that deviates from a predetermined physical or electrical characteristic, and the second semiconductor chip other than the second semiconductor chip having the numerical value 0 is added. A finite number larger than 0 is attached to the semiconductor chip,
When the first-type and second-type semiconductor wafers are stacked, the numerical value assigned to each of the first semiconductor chips and the second semiconductor chip superimposed on each of the first semiconductor chips. When the total of the numerical values obtained by integrating the numerical values obtained is the non-defective product cumulative value,
From among the plurality of first type semiconductor wafers, select the first type semiconductor wafer having the maximum sum of the numerical values assigned to each of the first semiconductor chips as the first type best semiconductor wafer,
2. The semiconductor according to claim 1, wherein a second type of semiconductor wafer having a maximum non-defective product accumulated value is selected from the plurality of second type semiconductor wafers when stacked with the first type of best semiconductor wafer. Manufacturing method of wafer laminated body. A manufacturing system for a semiconductor wafer laminate in which a first type semiconductor wafer in which a plurality of first semiconductor chips are formed and a second type semiconductor wafer in which a plurality of second semiconductor chips are formed are stacked,
Physical or electrical characteristics of each first semiconductor chip formed on the first type semiconductor wafer, and physical or electrical characteristics of each second semiconductor chip formed on the second type semiconductor wafer. A measuring device for measuring
Physical or electrical characteristics of each of the first semiconductor chips in the first type semiconductor wafer measured by the measurement apparatus, and physics of each of the second semiconductor chips in the plurality of second type semiconductor wafers. A storage device for storing a plurality of the first type and second type semiconductor wafers,
Physical or electrical characteristics of each of the first semiconductor chips in each of the first type semiconductor wafers stored in the storage device, and physics of each of the second semiconductor chips in each of the second type semiconductor wafers. An arithmetic device for selecting a first type and a second type of semiconductor wafer to be stacked from among the plurality of first type and second type semiconductor wafers, based on physical or electrical characteristics;
A semiconductor wafer laminate manufacturing system including: The arithmetic unit is:
In the first type semiconductor wafer, a region where the first semiconductor chip deviating from a predetermined physical or electrical characteristic is formed as a first nonstandard region,
In the second type semiconductor wafer, a region where the second semiconductor chip deviating from a predetermined physical or electrical characteristic is formed as a second nonstandard region,
When a region obtained by combining the first and second nonstandard regions when the first type and second type semiconductor wafers are stacked is defined as a defective region,
7. The first and second types of semiconductor wafers to be stacked are selected from the plurality of first and second type semiconductor wafers in a combination that minimizes the total area of the defective regions. The manufacturing system of the semiconductor wafer laminated body of description. The arithmetic unit is:
In the first type semiconductor wafer, a region where the first semiconductor chip deviating from a predetermined physical or electrical characteristic is formed as a first nonstandard region,
In the second type semiconductor wafer, a region where the second semiconductor chip deviating from a predetermined physical or electrical characteristic is formed as a second nonstandard region,
When a region obtained by combining the first and second nonstandard regions when the first type and second type semiconductor wafers are stacked is defined as a defective region,
The first type semiconductor wafer having the smallest area of the first nonstandard region is selected as the first type best semiconductor wafer from the plurality of first type semiconductor wafers,
7. The second type semiconductor wafer that minimizes the area of the defective region when being stacked with the first type best semiconductor wafer is selected from the plurality of second type semiconductor wafers. Manufacturing system for semiconductor wafer stacks. The arithmetic unit is:
In the first type semiconductor wafer, the first semiconductor chip deviating from a predetermined physical or electrical characteristic is assigned a numerical value of 0, and the first semiconductor chip other than the first semiconductor chip assigned the numerical value of 0 is assigned to the first semiconductor chip. A finite number larger than 0 is attached to the semiconductor chip,
In the second type semiconductor wafer, a numerical value 0 is assigned to the second semiconductor chip that deviates from a predetermined physical or electrical characteristic, and the second semiconductor chip other than the second semiconductor chip having the numerical value 0 is added. A finite number larger than 0 is attached to the semiconductor chip,
When the first-type and second-type semiconductor wafers are stacked, the numerical value assigned to each of the first semiconductor chips and the second semiconductor chip superimposed on each of the first semiconductor chips. When the total of the numerical values obtained by integrating the numerical values obtained is the non-defective product cumulative value,
7. The first and second types of semiconductor wafers to be stacked are selected from among the plurality of first and second type semiconductor wafers in a combination that maximizes the total sum of the non-defective product cumulative values. Manufacturing system for semiconductor wafer stacks. The arithmetic unit is:
In the first type semiconductor wafer, the first semiconductor chip deviating from a predetermined physical or electrical characteristic is assigned a numerical value of 0, and the first semiconductor chip other than the first semiconductor chip assigned the numerical value of 0 is assigned to the first semiconductor chip. A finite number larger than 0 is attached to the semiconductor chip,
In the second type semiconductor wafer, a numerical value 0 is assigned to the second semiconductor chip that deviates from a predetermined physical or electrical characteristic, and the second semiconductor chip other than the second semiconductor chip having the numerical value 0 is added. A finite number larger than 0 is attached to the semiconductor chip,
When the first-type and second-type semiconductor wafers are stacked, the numerical value assigned to each of the first semiconductor chips and the second semiconductor chip superimposed on each of the first semiconductor chips. When the total of the numerical values obtained by integrating the numerical values obtained is the non-defective product cumulative value,
From among the plurality of first type semiconductor wafers, select the first type semiconductor wafer having the maximum sum of the numerical values assigned to each of the first semiconductor chips as the first type best semiconductor wafer,
7. The semiconductor according to claim 6, wherein a second type of semiconductor wafer having a maximum non-defective product accumulated value is selected from the plurality of second type semiconductor wafers when stacked with the first type of best semiconductor wafer. Wafer stack manufacturing system.

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