JP2020038946A - Semiconductor device manufacturing system, semiconductor device, and method for manufacturing semiconductor device - Google Patents

Abstract

To improve a yield of a semiconductor device in a laminated semiconductor device.SOLUTION: An information acquisition unit acquires information showing each semiconductor ship, the measurement value within a prescribed range of which is measured, among a plurality of semiconductor chips formed in each of a plurality of semiconductor wafers, as a non-defective chip. A rotation angle acquisition unit acquires, on the basis of the information, a rotation angle at which the number of overlapping non-defective chips is maximum when one of a pair of semiconductor wafers is rotated with respect to the other to be laminated among rotation angles made between a line segment from a specific place of an outer periphery before rotating the one of the pair of semiconductor wafers among the plurality of semiconductor wafers to the center and a line segment from the specific place to the center after the rotation. A lamination processing unit performs processing for rotating the one of the pair of semiconductor wafers with respect to the other to laminate the one only by the rotation angle.SELECTED DRAWING: Figure 4

Description

  The present technology relates to a semiconductor device manufacturing system, a semiconductor device, and a semiconductor device manufacturing method. More specifically, the present invention relates to a semiconductor element manufacturing system in which a plurality of semiconductor chips are stacked, a semiconductor element, and a semiconductor element manufacturing method.

  2. Description of the Related Art Conventionally, a stacked semiconductor element in which a plurality of semiconductor chips are stacked has been used in various electronic devices for the purpose of reducing the area. For example, a manufacturing system has been proposed in which a plurality of semiconductor chips are formed on each of two semiconductor wafers, and the semiconductor wafers are stacked (for example, see Patent Document 1).

JP 2013-115349 A

  In the above-described conventional technique, a large number of stacked semiconductor elements can be efficiently manufactured by stacking semiconductor wafers. However, in the above-described manufacturing system, if even one defective product is present in a plurality of semiconductor chips to be stacked, the entire semiconductor element does not operate normally and becomes a defective product. Therefore, it is difficult to improve the yield, which is the ratio of non-defective products when mass-producing semiconductor devices.

  The present technology has been developed in view of such a situation, and has as its object to improve the yield of semiconductor elements in a stacked semiconductor element.

  The present technology has been made to solve the above-described problem, and a first aspect of the present technology is that a measurement value within a predetermined range among a plurality of semiconductor chips formed on each of a plurality of semiconductor wafers is measured. An information acquisition unit for acquiring information indicating each of the processed semiconductor chips as non-defective chips, and a line segment from a specific portion of the outer circumference of one of the pair of semiconductor wafers before rotation to the center of the pair of semiconductor wafers and after rotation. Of the rotation angles formed by the line segment from the specific location to the center, the number of the non-defective chips that overlap when the one of the pair of semiconductor wafers is rotated with respect to the other and stacked is maximized. A rotation angle acquisition unit that acquires a rotation angle based on the information, and a lamination that performs a process of laminating the one of the pair of semiconductor wafers by rotating the one by the rotation angle with respect to the other. Manufacturing system for a semiconductor device comprising a processing section, and a manufacturing method thereof. This brings about an effect that the number of overlapping good chips is maximized.

  Further, in the first aspect, the shape of the semiconductor chip is a shape that does not change even when the semiconductor chip is rotated around a predetermined axis by a predetermined angle, and the rotation angle obtaining unit determines any one of multiples of the predetermined angle. The rotation angle may be obtained. This brings about the effect that the semiconductor wafer is rotated by the rotation angle corresponding to the rotational symmetry.

  In the first aspect, the shape of the semiconductor chip may be a square, and the rotation angle obtaining unit may obtain any one of multiples of 90 degrees as the rotation angle. This brings about an effect that square semiconductor chips are stacked.

  In the first aspect, a predetermined number of terminals are formed on the semiconductor chip corresponding to the other of the pair of semiconductor wafers, and the one of the pair of semiconductor wafers is provided at every predetermined angle. The predetermined number of terminals may be formed, and the arrangement of the terminals on the one of the pair of semiconductor wafers may be in a shape that does not change even when rotated about the predetermined axis by the predetermined angle. This brings about the effect that the number of terminals according to the rotational symmetry is arranged.

  Further, in the first aspect, the terminal according to the one of the pair of semiconductor wafers belongs to a different group for each predetermined angle, and the semiconductor chip corresponding to the one of the pair of semiconductor wafers includes: A circuit commonly connected to the terminals at the rotationally symmetric positions of the respective groups may be further formed. This brings about an effect that the electrical connection relationship is not changed before and after the rotation.

  In the first aspect, the arrangement of the terminals on the one of the pair of semiconductor wafers may be rectangular. This brings about an effect that terminals in a rectangular array are connected to signal lines.

  Further, in the first aspect, the arrangement of the terminals according to the one of the pair of semiconductor wafers may be a cross shape. This brings about an effect that terminals in a cross-shaped arrangement are connected to signal lines.

  Further, in the first aspect, the arrangement of the terminals according to the one of the pair of semiconductor wafers may be in an oblique cross shape. This brings about an effect that the terminals arranged in an oblique cross shape are connected to the signal lines.

  In the first aspect, the arrangement of the terminals on the one of the pair of semiconductor wafers may be circular. This brings about an effect that terminals in a circular array are connected to signal lines.

  Further, in the first aspect, a notch may be formed at the specific location on the one side of the pair of semiconductor wafers. This has the effect that the semiconductor wafer is rotated at an angle formed by the line segment from the notch to the center.

  In the first aspect, the arrangement of the plurality of semiconductor chips may be a shape that does not change even when rotated by a predetermined angle around a predetermined axis. This brings about an effect that semiconductor wafers having semiconductor chips arranged in a rotationally symmetric shape are stacked.

  Further, in the first aspect, any one of the plurality of semiconductor chips may be arranged at the center of each of the pair of semiconductor wafers. This brings about an effect that the number of semiconductor chips per semiconductor wafer increases.

  In the first aspect, each of the plurality of semiconductor chips may not be located at the center of each of the pair of semiconductor wafers. Thus, there is an effect that the positions of all the semiconductor chips change when rotated.

  Further, in the first aspect, an inspection unit that inspects whether the measured value is within the predetermined range and outputs a determination result, and an external unit that generates and holds the information based on the inspection result And a database. As a result, there is an effect that information on good and defective products is obtained from the external database.

  Further, a second side surface of the present technology is configured such that a predetermined number of terminals are arranged, a first semiconductor chip having a shape that does not change even when rotated by a predetermined angle around a predetermined axis, and stacked on the first semiconductor chip, A second semiconductor chip on which the predetermined number of terminals are arranged at each predetermined angle. This brings about an effect that a semiconductor device is manufactured by a manufacturing system in which semiconductor wafers are rotated and stacked.

FIG. 1 is a block diagram illustrating a configuration example of a manufacturing system according to an embodiment of the present technology. FIG. 3 is a block diagram illustrating a configuration example of an upper wafer manufacturing unit and a lower wafer manufacturing unit according to the embodiment of the present technology. FIG. 4 is a diagram illustrating an example of good / defective product information according to an embodiment of the present technology. It is a block diagram showing an example of 1 composition of a lamination wafer manufacturing part in an embodiment of this art. It is an example of the top view of the upper wafer before and after inspection in an embodiment of this art. It is an example of a top view of a lower wafer before and after inspection in an embodiment of the present technology. It is an example of a top view of a wafer before and after lamination in case a rotation angle is 0 degrees in an embodiment of the present technology. It is an example of the top view of the wafer before and after lamination in case a rotation angle is 90 degrees in an embodiment of the present technology. It is an example of a top view of a wafer before and after lamination in case a rotation angle is 180 degrees in an embodiment of the present technology. It is an example of a top view of a wafer before and after lamination in case a rotation angle is 270 degrees in an embodiment of the present technology. FIG. 2 is a diagram illustrating an example of a stacked structure of a semiconductor element according to an embodiment of the present technology. It is an example of a top view of an upper chip in an embodiment of the present technology. It is an example of a top view of a lower chip in an embodiment of the present technology. FIG. 5 is an example of a plan view of a lower chip in which the arrangement of pads is changed in the embodiment of the present technology. 5 is a flowchart illustrating an example of an operation of the manufacturing system according to the embodiment of the present technology. 11 is a flowchart illustrating a rotation angle calculation process according to the embodiment of the present technology. It is an example of the top view of the upper wafer in the modification of an embodiment of this art.

Hereinafter, a mode for implementing the present technology (hereinafter, referred to as an embodiment) will be described. The description will be made in the following order.
1. Embodiment (an example in which the lower chip is rotated and stacked)
2. Modified example

<1. First Embodiment>
[Example of configuration of manufacturing system]
FIG. 1 is a block diagram illustrating a configuration example of a manufacturing system according to an embodiment of the present technology. This manufacturing system is a system for manufacturing a stacked semiconductor device, and includes an upper wafer manufacturing unit 110, a lower wafer manufacturing unit 120, an external database 130, and a stacked wafer manufacturing unit 200.

  A semiconductor element manufactured by the manufacturing system is obtained by stacking a plurality of (for example, two) semiconductor chips, and one of the semiconductor chips is hereinafter referred to as an “upper chip” and the other is referred to as a “lower chip”. . The upper chip and the lower chip are formed on different semiconductor wafers. Hereinafter, the semiconductor wafer on which the upper chip is formed is referred to as “upper wafer”, and the semiconductor wafer on which the lower chip is formed is referred to as “lower wafer”.

  The upper wafer manufacturing unit 110 manufactures an upper wafer. The upper wafer manufacturing unit 110 manufactures a semiconductor wafer on which a plurality of upper chips are formed as an upper wafer, and adds wafer identification information each time the upper wafer is manufactured. The upper wafer manufacturing unit 110 measures physical and electrical characteristics of each upper chip. Physical characteristics include, for example, the thickness of a wiring layer of a semiconductor chip, the width of a wiring, and the density of lattice defects. The electrical characteristics are, for example, current values, voltage values, and frequency characteristics of a circuit formed on the semiconductor chip.

  Then, the upper wafer manufacturing unit 110 checks for each upper chip whether or not the measured values of the physical and electrical characteristics are within a predetermined range for normal operation of the chip. If the measured value is out of the predetermined range, the chip is determined to be defective, and if it is within the predetermined range, it is determined to be non-defective. Hereinafter, a defective semiconductor chip is referred to as a “defective chip”, and a non-defective semiconductor chip is referred to as a “non-defective chip”. The upper wafer manufacturing unit 110 transmits the inspection result to the external database 130. The upper wafer manufacturing unit 110 supplies the manufactured upper wafer to the laminated wafer manufacturing unit 200.

  The lower wafer manufacturing unit 120 manufactures a lower wafer. The lower wafer manufacturing unit 120 manufactures a semiconductor wafer on which a plurality of lower chips are formed as a lower wafer, and adds wafer identification information every time the lower wafer is manufactured. The lower wafer manufacturing unit 120 measures the physical and electrical characteristics of each lower chip, checks whether the measured value is within a predetermined range for each upper chip, and stores the inspection result in the external database 130. Send. Further, the lower wafer manufacturing unit 120 supplies the manufactured lower wafer to the laminated wafer manufacturing unit 200.

  The external database 130 generates non-defective / defective product information indicating whether the chip is a defective chip or a non-defective chip for each of the upper chip and the lower chip based on the inspection results of the upper wafer and the lower wafer. To keep.

  The laminated wafer manufacturing section 200 is for laminating an upper wafer and a lower wafer. The laminated wafer manufacturing unit 200 acquires information on good / defective products of the upper wafer and the lower wafer from the external database 130. Then, based on the information, the laminated wafer manufacturing unit 200 rotates and laminates one of the upper wafer and the lower wafer (for example, the upper wafer) with the other (for example, the lower wafer) to form a wafer laminate. It is supplied to the subsequent manufacturing equipment. The stacked upper chip and lower chip in this wafer stack function as one stacked semiconductor element.

  Although the laminated wafer manufacturing unit 200 rotates the lower wafer with respect to the upper wafer, it is also possible to rotate the upper wafer with respect to the lower wafer. The upper wafer and the lower wafer are examples of a plurality of semiconductor wafers described in the claims.

  FIG. 2 is a block diagram illustrating a configuration example of the upper wafer manufacturing unit 110 and the lower wafer manufacturing unit 120 according to the embodiment of the present technology. FIG. 2A is a block diagram illustrating a configuration example of an upper wafer manufacturing unit 110, and FIG. 2B is a block diagram illustrating a configuration example of a lower wafer manufacturing unit 120. The upper wafer manufacturing unit 110 includes a defect inspection unit 111 and an electrical inspection unit 112. On the other hand, the lower wafer manufacturing unit 120 includes a defect inspection unit 121 and an electrical inspection unit 122. In the figure, various manufacturing apparatuses for manufacturing the upper wafer and the lower wafer are omitted.

  The defect inspection section 111 inspects the density of each lattice defect of the upper chip. The defect inspection unit 111 supplies the inspection result to the external database 130. The electrical inspection unit 112 inspects each electrical characteristic of the upper chip. The electrical inspection unit 112 supplies the inspection result to the external database 130.

  The defect inspection unit 121 inspects the density of each lattice defect of the lower chip. The defect inspection unit 121 supplies the inspection result to the external database 130. The electrical inspection unit 122 inspects each electrical characteristic of the lower chip. The electrical inspection unit 122 supplies the inspection result to the external database 130.

  FIG. 3 is a diagram illustrating an example of non-defective / defective product information according to the embodiment of the present technology. The non-defective / defective information includes a lamination position, wafer identification information, a chip position, and an inspection result. The stacking position indicates whether the semiconductor wafer is located on the upper side or the lower side when the semiconductor wafer is stacked. The wafer identification information is identification information for identifying a semiconductor wafer. The chip position indicates the position of the semiconductor chip in the semiconductor wafer. The inspection result indicates the inspection result of the physical and electrical characteristics. For example, let us consider a case where the upper wafer manufacturing unit 110 inspects the upper chip of the chip position “L01” on the upper wafer of the upper wafer identification information “W01”, and all the measured values are within a normal range. In this case, the external database 130 generates and holds “Pass” indicating that the chip is a non-defective chip as an inspection result of the chip.

  Further, it is assumed that the upper wafer manufacturing unit 110 inspects the upper chip of the chip position “L02” on the upper wafer of the upper wafer identification information “W01”, and one of the measured values is outside the normal range. In this case, the external database 130 generates and retains “Fail” indicating that the chip is a defective chip as an inspection result of the chip on the external database.

[Configuration example of laminated wafer manufacturing unit]
FIG. 4 is a block diagram illustrating a configuration example of the laminated wafer manufacturing unit 200 according to the embodiment of the present technology. The laminated wafer manufacturing section 200 includes an upper wafer setting section 211, a lower wafer setting section 212, and a take-out arm section 220. Further, the laminated wafer manufacturing unit 200 includes a non-defective / defective product information acquisition unit 230, a rotation angle acquisition unit 240, a lamination processing unit 250, a transfer arm unit 260, a pre-lamination processing unit 270, and a laminated wafer delivery unit 280.

  The upper wafer setting unit 211 takes out the upper wafer from the upper wafer manufacturing unit 110 and sets it on the arm unit 220. The lower wafer setting section 212 takes out the lower wafer from the lower wafer manufacturing section 120 and sets it on the arm section 220.

  The take-out arm section 220 takes out the upper wafer and the lower wafer from the set position and supplies them to the transfer arm section 260. The transfer arm 260 transfers the upper wafer and the lower wafer from one end to the other end thereof.

  The non-defective / defective product information acquisition unit 230 obtains non-defective / defective product information from the external database 130. The non-defective / defective product information acquisition section 230 temporarily takes out the upper wafer and the lower wafer from the transfer arm section 260 and reads the wafer identification information of those wafers. The wafer identification information is written at a predetermined position on the semiconductor wafer by the upper wafer manufacturing unit 110 and the lower wafer manufacturing unit 120, for example. The non-defective / defective product information acquisition unit 230 inquires of the external database 130 about the chip position and the inspection result in the non-defective / defective product information corresponding to the read wafer identification information, and receives the information. Then, the good / defective product information acquiring unit 230 supplies the acquired information to the rotation angle acquiring unit 240, and returns the upper wafer and the lower wafer to the transfer arm unit 260. The non-defective / defective product information acquisition unit 230 is an example of the information acquisition unit described in the claims.

  The lamination pre-processing unit 270 performs a predetermined lamination pre-processing such as cleaning on the upper wafer and the lower wafer. The stacking pre-processing unit 270 takes out the upper wafer and the lower wafer from the transfer arm unit 260 after acquiring the non-defective / defective product information, and executes the pre-lamination processing on them. After the processing, the lamination pre-processing unit 270 returns the upper wafer and the lower wafer to the transfer arm unit 260.

  The rotation angle acquisition unit 240 acquires a rotation angle at which the number of non-defective chips overlapping when the lower wafer is rotated with respect to the upper wafer is maximized, based on the non-defective / defective information. Here, as the rotation angle of the lower wafer, an angle formed by a line segment from a specific location on the outer periphery of the lower wafer before rotation to the center before rotation and a line segment from the specific location after rotation to the center is used. The rotation angle acquisition unit 240 supplies the acquired rotation angle to the lamination processing unit 250.

  The lamination processing unit 250 is configured to rotate the lower wafer with respect to the upper wafer by the acquired rotation angle, and to laminate those wafers. The stacking unit 250 takes out the upper wafer and the lower wafer after the pre-stacking process from the transfer arm unit 260 and rotates and stacks the lower wafer. Then, the stacking unit 250 returns the stacked wafer stack to the transfer arm unit 260.

  The stacked wafer discharging unit 280 discharges the wafer stacked body from the transfer arm unit 260 to the outside.

  FIG. 5 is an example of a plan view of the upper wafer 510 before and after the inspection according to the embodiment of the present technology. In the figure, a is an example of a plan view of the upper wafer 510 before the defect inspection. B in the figure is an example of a plan view of the upper wafer 510 after the defect inspection, and c in the same figure is an example of a plan view of the upper wafer 510 after the electrical inspection.

  The shape of the upper wafer 510 is circular, and a notch 512 is formed at a specific location on the outer periphery of the upper wafer 510. A plurality of upper chips 511 are formed on the upper wafer 510. The arrangement of the upper chips 511 has a shape that does not change even when rotated by a predetermined angle around the central axis of the upper wafer 510. Such a characteristic that the shape does not change even if rotated by a predetermined angle is called rotational symmetry. Rotational symmetry that does not change even when rotated by 360 / n (n is an integer) degrees is called n-fold symmetry. For example, a square has the same shape even when rotated by 90 degrees, and is four-fold symmetric. The rectangle has the same shape even when rotated by 180 degrees, and is symmetric twice.

  Each shape of the upper chip 511 is symmetrical n times like the arrangement. For example, both the arrangement of the upper chips 511 and the individual shapes are symmetric four times in the same shape even when rotated by 90 degrees. For example, a square chip is used as the four-fold symmetric upper chip 511. In order to make the shape of the arrangement of the upper chips 511 four-fold symmetric, for example, when the arrangement is made such that the center is located at the center of the upper wafer 510 in i rows × j columns (i and j are integers). First, an array in which chips (eg, four corners) not located in the upper wafer 510 are used is used. Hereinafter, the position of the semiconductor chip is represented by coordinates (i, j).

  Further, the plurality of upper chips 511 are arranged such that the respective chips are not located at the center of the upper wafer 510. For example, i and j are set to even numbers. With such an arrangement, all positions of the lower chip can be changed when rotated by 90 degrees.

  The upper wafer manufacturing unit 110 performs a defect inspection, and it is assumed that the measured value is outside the normal range at the position (1, 2). In this case, non-defective / defective information indicating that the upper chip 511 at the position (1, 2) is a defective chip and the other chips are non-defective chips is held in the external database 130. The hatched portion b in the figure indicates a defective chip at the end of the defect inspection.

  Then, the upper wafer manufacturing unit 110 performs an electrical inspection, and it is assumed that the measured value is outside the normal range at the position (2, 2). In this case, in the non-defective / defective product information, the inspection result corresponding to the upper chip 511 at the position (2, 2) is updated to information indicating a defective chip. The hatched portion c in FIG. 7 indicates a defective chip at the end of the electrical inspection.

  FIG. 6 is an example of a plan view of the lower wafer 520 before and after the inspection according to the embodiment of the present technology. “A” in the figure is an example of a plan view of the lower wafer 520 before the defect inspection. B in the drawing is an example of a plan view of the lower wafer 520 after the defect inspection, and c in the same drawing is an example of a plan view of the lower wafer 520 after the electrical inspection.

  The shape and size of the lower wafer 520 are the same as those of the upper wafer 510. A notch is also formed as a notch 522 on the outer periphery of the lower wafer 520. A plurality of lower chips 521 are formed on the lower wafer 520. The shape, size, and arrangement of the lower chips 521 are the same as those of the upper chip 511. Further, each of the notch 512 of the upper wafer 510 and the notch 522 of the lower wafer 520 is located at a position where they are overlapped when they are stacked without being rotated in the initial state.

  The lower wafer manufacturing unit 120 performs a defect inspection, and it is assumed that the measured value is outside the normal range at the position (3, 1). The hatched portion b in the figure indicates a defective chip at the end of the defect inspection. Then, the lower wafer manufacturing unit 120 performs an electrical inspection, and it is assumed that the measured value is outside the normal range at the position (3, 2). The hatched portion c in FIG. 7 indicates a defective chip at the end of the electrical inspection.

  Based on the positions of the defective chips illustrated in FIGS. 5 and 6, the rotation angle obtaining unit 240 obtains a rotation angle at which the number of non-defective chips overlapping each other when the lower wafer is rotated with respect to the upper wafer is maximized. . This rotation angle is an angle formed by a line segment from a specific location (such as a notch) on the outer periphery of the lower wafer before rotation to the center and a line segment from the specific location (such as a notch) to the center after rotation. The candidate for the rotation angle is a multiple of 360 / n degrees when the shape of the semiconductor chip is n-fold symmetric. For example, if the shape of the semiconductor chip is four-fold symmetric (such as a square), 0, 90, 180, and 270 degrees, which are multiples of 90 degrees, are candidates for the rotation angle.

  The rotation angle obtaining unit 240 obtains, for each candidate angle, the number of good chips that overlap each other when rotated at that angle. The position of the defective chip is not always the same for each semiconductor wafer and varies due to various factors. For this reason, the number of overlapping good chips may differ for each rotation angle. As described above, in a stacked semiconductor device, since a plurality of stacked semiconductor chips operate in cooperation with each other, if at least one of them has a defective product, the entire semiconductor device does not operate normally. Therefore, as the number of non-defective chips overlapping the defective chips increases, the ratio of defective products after lamination increases, and the yield, which is the ratio of non-defective products, decreases. Conversely, as the number of non-defective chips overlapping with other non-defective chips increases, the ratio of defective products decreases, and the yield increases.

  FIG. 7 is an example of a plan view of the wafer before and after lamination when the rotation angle is 0 degree in the embodiment of the present technology. A in the figure is an example of a plan view of the upper wafer 510, and b in the figure is an example of a plan view of the lower wafer 520 having a rotation angle of 0 degrees. C in the figure is an example of a plan view of the semiconductor device after the lamination. Also, the hatched portions in the figure indicate defective semiconductor chips or semiconductor elements.

  The defective chips on the upper wafer 510 are at the positions (1, 2) and (2, 2), and the defective chips on the lower wafer 520 are at the positions (3, 1) and (3, 2). When stacked at a rotation angle of 0 degrees (that is, without rotation), after lamination, defective semiconductor elements are (1, 2), (2, 2), (3, 1) and (3, 1). 2). Since the number of non-defective products is 8 out of 12, the yield is 8/12. The stacked semiconductor elements are not actually manufactured, and the yield is obtained by simulation by the rotation angle acquisition unit 240.

  FIG. 8 is an example of a plan view of wafers before and after lamination when the rotation angle is 90 degrees in the embodiment of the present technology. A in the figure is an example of a plan view of the upper wafer 510, and b in the figure is an example of a plan view of the lower wafer 520 before rotation. C in the figure is an example of a plan view of the lower wafer 520 rotated by 90 degrees. D in the figure is an example of a plan view of the semiconductor device after the lamination. Also, the hatched portions in the figure indicate defective semiconductor chips or semiconductor elements.

  In FIG. 8, the positions of defective chips on the upper wafer 510 and the lower wafer 520 before rotation are the same as those in FIG. When the lower wafer 520 is rotated 90 degrees clockwise with respect to the upper wafer 510, the coordinates of the defective chips (3, 1) and (3, 2) are (1, 2) by the product of the rotation matrix. ) And (2, 2). When the lower wafer 520 after this rotation is stacked on the upper wafer 510, both of the upper defective chips overlap the lower defective chip. As a result, after lamination, defective semiconductor elements are located at positions (1, 2) and (2, 2). Since the number of non-defective products is 10 out of 12, the yield is 10/12.

  FIG. 9 is an example of a plan view of wafers before and after lamination when the rotation angle is 180 degrees in the embodiment of the present technology. A in the figure is an example of a plan view of the upper wafer 510, and b in the figure is an example of a plan view of the lower wafer 520 before rotation. C in the figure is an example of a plan view of the lower wafer 520 rotated by 180 degrees. D in the figure is an example of a plan view of the semiconductor device after the lamination. Also, the hatched portions in the figure indicate defective semiconductor chips or semiconductor elements.

  In FIG. 9, the positions of defective chips on the upper wafer 510 and the lower wafer 520 before rotation are the same as those in FIG. When the lower wafer 520 is rotated by 180 degrees with respect to the upper wafer 510, the coordinates of (3, 1) and (3, 2) of the defective chip are (2, 4) and ( 2, 3). When the lower wafer 520 after this rotation is stacked on the upper wafer 510, each of the upper and lower defective chips overlaps with a good chip. As a result, after lamination, defective semiconductor elements are located at positions (1, 2), (2, 2), (2, 4) and (2, 3). Since the number of non-defective products is 8 out of 12, the yield is 8/12. The stacked semiconductor elements are not actually manufactured, and the yield is obtained by simulation by the rotation angle acquisition unit 240.

  FIG. 10 is an example of a plan view of wafers before and after lamination when the rotation angle is 270 degrees in the embodiment of the present technology. A in the figure is an example of a plan view of the upper wafer 510, and b in the figure is an example of a plan view of the lower wafer 520 before rotation. C in the figure is an example of a plan view of the lower wafer 520 rotated by 270 degrees. D in the figure is an example of a plan view of the semiconductor device after the lamination. Also, the hatched portions in the figure indicate defective semiconductor chips or semiconductor elements.

  In FIG. 10, the positions of defective chips on the upper wafer 510 and the lower wafer 520 before rotation are the same as those in FIG. When the lower wafer 520 is rotated 270 degrees clockwise with respect to the upper wafer 510, the coordinates of the defective chips (3, 1) and (3, 2) are (4, 3) by the product of the rotation matrix. ) And (3, 3). When the lower wafer 520 after this rotation is stacked on the upper wafer 510, each of the upper and lower defective chips overlaps with a good chip. As a result, after lamination, defective semiconductor elements are located at positions (1, 2), (2, 2), (4, 3) and (3, 3). Since the number of non-defective products is 8 out of 12, the yield is 8/12. The stacked semiconductor elements are not actually manufactured, and the yield is obtained by simulation by the rotation angle acquisition unit 240.

  As illustrated in FIGS. 7 to 10, the position of the defective chip changes by changing the rotation angle. For this reason, the number of overlapping good chips changes depending on the rotation angle, and the yield also changes. 7 to 10, the yield is 8/12 when the rotation angles are 0 degree, 180 degrees, and 270 degrees, whereas the yield is 10/12 when the rotation angle is 90 degrees. Therefore, the rotation angle acquisition unit 240 acquires 90 degrees as the rotation angle at which the yield is the highest. Then, the later-stage lamination processing unit 250 rotates the lower wafer 520 by 90 degrees with respect to the upper wafer 510, and laminates those wafers. As a result, the yield can be improved as compared with the case where no rotation is performed, that is, the case where the rotation angle is 0 degree.

  In addition, the lamination processing unit 250 laminates two wafers, the upper wafer 510 and the lower wafer 520, but can laminate three or more wafers. When three or more sheets are stacked, the stacking processing unit 250 may rotate two of the three sheets with respect to the remaining one. In addition, although the shape of each of the semiconductor chips of the upper chip 511 and the lower chip 521 is a square, the shape is not limited to a square as long as it has rotational symmetry. For example, the shape of the semiconductor chip may be a two-fold symmetrical rectangle.

  FIG. 11 is a diagram illustrating an example of a stacked structure of a semiconductor element according to an embodiment of the present technology. As a semiconductor element, for example, a solid-state imaging element is manufactured. This solid-state imaging device includes a lower chip 521 and an upper chip 511 stacked on the lower chip 521. These chips are electrically connected via connection parts such as vias. Note that, in addition to vias, connection can be made by inductive coupling communication technology such as Cu-Cu bonding, bumps, and TCI (ThruChip Interface). Further, the manufacturing system manufactures the solid-state imaging device by stacking, but it is also possible to manufacture semiconductor devices other than the solid-state imaging device by stacking.

[Configuration example of upper chip]
FIG. 12 is an example of a plan view of the upper chip 511 according to the embodiment of the present technology. The upper chip 511 is provided with a pixel array unit 310 and m (m is an integer) pads 321. In the pixel array section 310, a plurality of pixels 311 are arranged in a two-dimensional lattice.

  Each of the m pads 321 is arranged in a line along any one of the four sides of the upper chip 511. These pads are used as terminals for electrically connecting to the lower chip 521. The pad 321 is an example of a “terminal” described in the claims.

  The pixel 311 generates a pixel signal corresponding to the amount of light by photoelectric conversion. A plurality of drive lines and one vertical signal line are wired to each of the pixels 311. The drive line is a signal line through which a drive signal for driving the pixel 311 is transmitted, and the vertical signal line is a signal line through which the generated pixel signal is transmitted. These signal lines are connected to different pads 321. For example, one of the drive lines of the pixel 311 at the coordinates (0, 0) is connected to the pad 321 (that is, the terminal) of the pad number “1”. Further, any one of the drive lines of the pixel 311 at the coordinates (0, 1) is connected to the pad 321 of the pad number “2”. The other drive lines and vertical signal lines of the pixel 311 at the coordinates (0, 0) and the other drive lines and the vertical signal lines of the pixel 311 at the coordinates (0, 1) are respectively connected to the pad numbers “3” and subsequent. Connected to pad 321.

  The upper chip 511 is an example of a first semiconductor chip described in the claims.

[Configuration example of lower chip]
FIG. 13 is an example of a plan view of the lower chip 521 according to the embodiment of the present technology. The circuit arrangement section 330 is arranged on the lower chip 521. Further, with the shape of the semiconductor chip being symmetrical n times, m pads 322 are arranged every 360 / n degrees (for example, 90 degrees) around the circuit arrangement section 330. When the semiconductor chip is a four-fold symmetrical square, a total of 4 × m pads 322 are arranged. When the semiconductor chip is a two-fold symmetric rectangle, 2 × m pads 322 are arranged in total. In the circuit arrangement section 330, for example, a drive circuit 331, a control circuit 332, a signal processing circuit 333, and a DAC (Digital to Analog Converter) 334 are arranged.

  The drive circuit 331 drives each of the pixels 311. The signal processing circuit 333 processes a pixel signal from each of the pixels 311. For example, an AD conversion process of generating a digital signal by performing counting over a time until the comparison result between the analog pixel signal and the ramp signal is inverted is executed.

  The DAC 334 generates a ramp signal by DA conversion and supplies the ramp signal to the signal processing circuit 333. The control circuit 332 controls the drive circuit 331, the signal processing circuit 333, and the DAC 334.

  Each of the pads 322 belongs to a different group every 360 / n degrees. If the semiconductor chip is a four-fold symmetrical square, the 4 × m pads 322 are divided into four groups of m each. Each of the four groups is arranged along different sides of the lower chip 521, and the arrangement is square. The same pad number is assigned to the pad 322 having the same relative position (in other words, rotationally symmetric position) in each group. Therefore, when a pad having a specific pad number (such as “1”) in a certain group is rotated in units of 360 / n degrees (such as 90 degrees), the same pad number (such as “1”) in another group is used. Will overlap with the pad.

  The drive circuit 331 is commonly connected to the pads 322 having the same relative position (for example, the pad number is “1”) in each of the groups. When there are four groups, the drive circuit 331 is commonly connected to the four pads 322 having the same pad number. The drive circuit 331 drives the corresponding pixel 311 via the pads 322. Similarly, the signal processing circuit 333 is connected to the pads having the same pad number in each of the groups, and processes the pixel signals from those pads.

  By arranging m pads on the lower chip 521 at every 90 degrees as illustrated in the figure, when the lower chip 521 is rotated by 90 degrees, any one of the pads 322 of the four groups is rotated. , Can be connected to the pad 321 at the corresponding position of the upper chip 511. For example, the pad of pad number “1” of the upper chip 511 is connected to the pad of pad number “1” of any of the four groups in the lower chip 521. Thus, the electrical connection between the circuit in the upper chip 511 and the circuit in the lower chip 521 does not change before and after rotation. Accordingly, it is possible to prevent the electrical connection relationship from being changed due to the rotation of the lower chip 521, thereby preventing malfunction.

  The lower chip 521 is an example of a second semiconductor chip described in the claims. Further, although the pads 322 of the lower chip 521 are arranged in a square, the arrangement of the pads 322 is not limited to a square as long as it is n-fold symmetrical (four-fold symmetrical). For example, as illustrated in FIG. 14A, the shape may be a cross shape, or as illustrated in FIG. 14B, an oblique cross shape. Alternatively, the shape may be circular as illustrated in FIG.

  FIG. 15 is a flowchart illustrating an example of an operation of the manufacturing system according to the embodiment of the present technology. This operation is started, for example, when an instruction to manufacture a stacked semiconductor device is issued.

  The upper wafer manufacturing unit 110 in the manufacturing system manufactures one lot of the upper wafer 510 and sets the same as the upper wafer lot in the laminated wafer manufacturing unit 200 (step S901). In addition, the lower wafer manufacturing unit 120 manufactures one lot of the lower wafer 520 and sets the lower wafer 520 as the lower wafer lot in the laminated wafer manufacturing unit 200 (step S902).

  Then, the laminated wafer manufacturing unit 200 executes a rotation angle calculation process for calculating an appropriate rotation angle (Step S910), and performs a pre-lamination process (Step S903).

  The laminated wafer manufacturing unit 200 determines whether the calculated rotation angle is greater than 0 degree (Step S904). If the rotation angle is larger than 0 degrees (step S904: Yes), the laminated wafer manufacturing unit 200 rotates the lower wafer by the calculated rotation angle with respect to the upper wafer (step S905). When the rotation angle is 0 degree (Step S904: No), or after Step S905, the laminated wafer manufacturing unit 200 measures the position of the lower wafer (Step S906), and moves the lower wafer so that the position is not shifted during lamination. The wafer is aligned (step S907).

  Subsequently, the stacked wafer manufacturing unit 200 stacks the upper wafer on the lower wafer after the alignment (Step S908), and pays out the wafer stack (Step S909). After step S909, the manufacturing system ends the operation for manufacturing the laminated wafer.

  FIG. 16 is a flowchart illustrating a rotation angle calculation process according to the embodiment of the present technology. The laminated wafer manufacturing unit 200 acquires information on good and defective products of the upper wafer and the lower wafer from the external database 130 (step S911). Then, based on the non-defective / defective product information, the laminated wafer manufacturing unit 200 calculates a rotation angle at which the number of non-defective chips overlapping when stacked is maximized (step S912). After step S912, the laminated wafer manufacturing unit 200 ends the rotation angle calculation processing.

  Note that the combination of the upper lot and the lower lot may be fixed, or may be changed to a combination different from that at the start of the production based on the good / defective product information. In the latter case, before the upper and lower wafers are set in the laminated wafer manufacturing unit 200 of FIG. 4, the laminated wafer manufacturing unit 200 acquires good / defective product information from the external database 130. Then, the laminated wafer manufacturing unit 200 executes the rotation angle calculation processing and the like in FIG. 16 before manufacturing based on the acquired non-defective / defective product information, and determines the optimal combination of upper and lower lots from all the resources, Find the combination of the upper and lower wafers. Then, by the combination thereof, the manufacture of the stacked semiconductor element is started. As a result, the yield can be further improved.

  As described above, according to the first embodiment of the present technology, since the lower wafer is rotated and stacked with respect to the upper wafer by the rotation angle that maximizes the number of overlapping good chips, the number of overlapping good chips Can be maximized to improve the yield.

<2. Modification>
In the above-described embodiment, a plurality of semiconductor chips are arranged so that the semiconductor chips are not located at the center of the semiconductor wafer. However, in this arrangement method, the number of semiconductor chips per semiconductor wafer needs to be sufficiently increased. May not be possible. The manufacturing system according to the modification of this embodiment is different from the embodiment in that the number of semiconductor chips per semiconductor wafer is increased by arranging one of the semiconductor chips at the center of the semiconductor wafer.

  “A” in FIG. 17 is an example of a plan view of the upper wafer 510 according to the modification of the embodiment of the present technology. The upper wafer 510 according to the modification of this embodiment is different from the embodiment in that a plurality of upper chips 511 are arranged such that one of the upper chips 511 is located at the center. For example, if the number of rows i and the number of columns j of the semiconductor chip are odd, any of the upper chips 511 can be arranged at the center of the upper wafer 510. With such an arrangement, the number of upper chips 511 per upper wafer 510 can be increased as compared with the embodiment.

  For example, assume that the diameter of a semiconductor wafer is “6”, the semiconductor chips are squares each having a side of “1”, and the semiconductor chips are arranged in a two-dimensional lattice without leaving any space between adjacent ones to simplify the description. Think. Assuming that the number of rows and the number of columns are even numbers as in the embodiment, 16 semiconductor chips of a maximum of 4 rows × 4 columns can be arranged as illustrated in FIG. On the other hand, assuming that the number of rows and the number of columns are odd numbers as in the modification of the embodiment, a maximum of 21 semiconductor chips can be arranged as illustrated in c of FIG.

  The arrangement of the lower chips 521 on the lower wafer 520 is the same as that of the upper chips 511.

  As described above, according to the modification of the embodiment of the present technology, the plurality of semiconductor chips are arranged so that any one of the semiconductor chips is located at the center of the semiconductor wafer, so that the number of semiconductor chips per semiconductor wafer is reduced. Can increase.

  Note that the above-described embodiment is an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a corresponding relationship. Similarly, the matters specifying the invention in the claims and the matters in the embodiments of the present technology with the same names have a correspondence relationship. However, the present technology is not limited to the embodiments, and can be embodied by variously modifying the embodiments without departing from the gist thereof.

  It should be noted that the effects described in this specification are merely examples, are not limited, and may have other effects.

Note that the present technology may have the following configurations.
(1) an information acquisition unit that acquires information indicating, as non-defective chips, each of the semiconductor chips having measured values within a predetermined range among the plurality of semiconductor chips formed on each of the plurality of semiconductor wafers;
Of the plurality of semiconductor wafers, a rotation angle between a line segment from a specific portion of the outer periphery of one of the pair of semiconductor wafers before rotation and a line segment from the specific portion to the center after rotation, A rotation angle acquisition unit that acquires the rotation angle at which the number of the non-defective chips overlapping when the one of the pair of semiconductor wafers is rotated with respect to the other and stacked is based on the information,
A lamination processing unit for performing lamination processing by rotating the one of the pair of semiconductor wafers by the rotation angle with respect to the other to perform lamination.
(2) The shape of the semiconductor chip is a shape that does not change even when rotated by a predetermined angle around a predetermined axis;
The manufacturing system according to (1), wherein the rotation angle acquisition unit obtains any of multiples of the predetermined angle as the rotation angle.
(3) The shape of the semiconductor chip is square,
The manufacturing system according to (2), wherein the rotation angle obtaining unit obtains any one of multiples of 90 degrees as the rotation angle.
(4) a predetermined number of terminals are formed on the semiconductor chip corresponding to the other of the pair of semiconductor wafers;
On the one of the pair of semiconductor wafers, the predetermined number of terminals are formed at each predetermined angle,
The manufacturing system according to (2) or (3), wherein the arrangement of the terminals on the one of the pair of semiconductor wafers has a shape that does not change even when rotated by the predetermined angle around the predetermined axis.
(5) The terminals according to the one of the pair of semiconductor wafers belong to different groups for each of the predetermined angles,
The manufacturing system according to claim 4, wherein a circuit commonly connected to the terminals at rotationally symmetric positions of the respective groups is further formed on the semiconductor chip corresponding to the one of the pair of semiconductor wafers.
The manufacturing system according to the above (4).
(6) The manufacturing system according to (4) or (5), wherein the arrangement of the terminals on the one of the pair of semiconductor wafers is rectangular.
(7) The manufacturing system according to (4) or (5), wherein the arrangement of the terminals on the one of the pair of semiconductor wafers has a cross shape.
(8) The manufacturing system according to (4) or (5), wherein the arrangement of the terminals on the one of the pair of semiconductor wafers has an oblique cross shape.
(9) The manufacturing system according to (4) or (5), wherein the arrangement of the terminals on the one of the pair of semiconductor wafers is circular.
(10) The manufacturing system according to any one of (1) to (9), wherein a notch is formed at the specific location on the one of the pair of semiconductor wafers.
(11) The manufacturing system according to any one of (1) to (10), wherein the arrangement of the plurality of semiconductor chips has a shape that does not change even when rotated by a predetermined angle around a predetermined axis.
(12) The manufacturing system according to (11), wherein any one of the plurality of semiconductor chips is arranged at the center of each of the pair of semiconductor wafers.
(13) The manufacturing system according to (11), wherein each of the plurality of semiconductor chips is not located at the center of each of the pair of semiconductor wafers.
(14) an inspection unit that inspects whether the measured value is within the predetermined range and outputs a determination result;
The manufacturing system according to any one of (1) to (13), further comprising: an external database that generates and holds the information based on the inspection result.
(15) a first semiconductor chip in which a predetermined number of terminals are arranged and which does not change even when rotated about a predetermined axis by a predetermined angle;
A second semiconductor chip stacked on the first semiconductor chip and having the predetermined number of terminals arranged at each of the predetermined angles.
(16) an information acquisition procedure for acquiring information indicating, as non-defective chips, each of the semiconductor chips for which a measurement value within a predetermined range has been measured among the plurality of semiconductor chips formed on each of the plurality of semiconductor wafers;
Of the plurality of semiconductor wafers, one of the pair of semiconductor wafers is a rotation angle between a line segment from a specific portion of the outer circumference before rotation and a line segment from the specific portion to the center after rotation. A rotation angle acquisition step of acquiring the rotation angle at which the number of the non-defective chips overlapping when the one of the pair of semiconductor wafers is rotated with respect to the other and stacked is based on the information,
A laminating process of performing lamination by rotating the one of the pair of semiconductor wafers relative to the other by the rotation angle.

110 Upper wafer manufacturing unit 111, 121 Defect inspection unit 112, 122 Electrical inspection unit 120 Lower wafer manufacturing unit 130 External database 200 Stacked wafer manufacturing unit 211 Upper wafer setting unit 212 Lower wafer setting unit 220 Pick-up arm unit 230 Good / defective product Information acquisition unit 240 Rotation angle acquisition unit 250 Stack processing unit 260 Transfer arm unit 270 Stacking pre-processing unit 280 Stacked wafer dispensing unit 310 Pixel array unit 311 Pixel 321 322 Pad 330 Circuit arrangement unit 331 Drive circuit 332 Control circuit 333 Signal processing circuit 334 DAC
510 Upper wafer 511 Upper chip 512, 522 Notch 520 Lower wafer 521 Lower chip

Claims (16)

An information acquisition unit that acquires information indicating each of the semiconductor chips whose measured values within a predetermined range have been measured as non-defective chips among the plurality of semiconductor chips formed on each of the plurality of semiconductor wafers;
Of the plurality of semiconductor wafers, a rotation angle between a line segment from a specific portion of the outer periphery of one of the pair of semiconductor wafers before rotation and a line segment from the specific portion to the center after rotation, A rotation angle acquisition unit that acquires the rotation angle at which the number of the non-defective chips overlapping when the one of the pair of semiconductor wafers is rotated with respect to the other and stacked is based on the information,
A lamination processing unit for performing lamination processing by rotating the one of the pair of semiconductor wafers by the rotation angle with respect to the other to perform lamination. The shape of the semiconductor chip is a shape that does not change even when rotated by a predetermined angle around a predetermined axis,
The manufacturing system according to claim 1, wherein the rotation angle acquisition unit obtains any one of multiples of the predetermined angle as the rotation angle. The semiconductor chip has a square shape,
The manufacturing system according to claim 2, wherein the rotation angle obtaining unit obtains any one of multiples of 90 degrees as the rotation angle. A predetermined number of terminals are formed on the semiconductor chip corresponding to the other of the pair of semiconductor wafers,
On the one of the pair of semiconductor wafers, the predetermined number of terminals are formed at each predetermined angle,
3. The manufacturing system according to claim 2, wherein the arrangement of the terminals on the one of the pair of semiconductor wafers has a shape that does not change even when rotated by the predetermined angle around the predetermined axis. 4. The terminals according to the one of the pair of semiconductor wafers belong to different groups for each of the predetermined angles,
The manufacturing system according to claim 4, wherein a circuit commonly connected to the terminals at rotationally symmetric positions of the respective groups is further formed on the semiconductor chip corresponding to the one of the pair of semiconductor wafers. The manufacturing system according to claim 4, wherein the arrangement of the terminals related to the one of the pair of semiconductor wafers is rectangular. The manufacturing system according to claim 4, wherein the arrangement of the terminals related to the one of the pair of semiconductor wafers is a cross shape. The manufacturing system according to claim 4, wherein the arrangement of the terminals on the one of the pair of semiconductor wafers is oblique cross shape. The manufacturing system according to claim 4, wherein the arrangement of the terminals on the one of the pair of semiconductor wafers is circular. The manufacturing system according to claim 1, wherein a notch is formed at the specific location on the one of the pair of semiconductor wafers. The manufacturing system according to claim 1, wherein the arrangement of the plurality of semiconductor chips has a shape that does not change even when rotated by a predetermined angle around a predetermined axis. The manufacturing system according to claim 11, wherein one of the plurality of semiconductor chips is arranged at a center of each of the pair of semiconductor wafers. The manufacturing system according to claim 11, wherein each of the plurality of semiconductor chips is not located at a center of each of the pair of semiconductor wafers. An inspection unit that outputs whether or not the measurement value is within the predetermined range and outputs a determination result;
The manufacturing system according to claim 1, further comprising: an external database that generates and holds the information based on the inspection result. A first semiconductor chip in which a predetermined number of terminals are arranged and which does not change even when rotated by a predetermined angle around a predetermined axis;
A second semiconductor chip stacked on the first semiconductor chip and having the predetermined number of terminals arranged at each of the predetermined angles. An information acquisition procedure for acquiring information indicating each of the semiconductor chips whose measured values within a predetermined range have been measured as non-defective chips among the plurality of semiconductor chips formed on each of the plurality of semiconductor wafers,
Of the plurality of semiconductor wafers, a rotation angle between a line segment from a specific portion of the outer periphery of one of the pair of semiconductor wafers before rotation and a line segment from the specific portion to the center after rotation, A rotation angle acquisition step of acquiring the rotation angle based on the information, in which the number of the non-defective chips overlapping when the one of the pair of semiconductor wafers is rotated with respect to the other and stacked is based on the information;
A laminating process of performing lamination by rotating the one of the pair of semiconductor wafers relative to the other by the rotation angle.

Images