JP7169132B2 - Semiconductor device manufacturing system, semiconductor device, and semiconductor device manufacturing method - Google Patents

Description

The present technology relates to a semiconductor device manufacturing system, a semiconductor device, and a semiconductor device manufacturing method. More specifically, the present invention relates to a system for manufacturing a semiconductor element in which a plurality of semiconductor chips are stacked, a semiconductor element, and a method for manufacturing a semiconductor element.

2. Description of the Related Art Conventionally, a stacked semiconductor element in which a plurality of semiconductor chips are stacked has been used in various electronic devices for the purpose of reducing the area. For example, a manufacturing system has been proposed in which a plurality of semiconductor chips are formed on each of two semiconductor wafers and the semiconductor wafers are stacked (see, for example, Patent Document 1).

JP 2013-115349 A

In the conventional technology described above, a large number of stacked semiconductor devices can be efficiently manufactured by stacking semiconductor wafers. However, in the manufacturing system described above, if even one defective product exists among the plurality of stacked semiconductor chips, the entire semiconductor element does not operate normally and becomes a defective product. Therefore, it is difficult to improve the yield, which is the ratio of non-defective products when semiconductor devices are mass-produced.

The present technology has been developed in view of such circumstances, and aims to improve the yield of semiconductor devices in stacked semiconductor devices.

The present technology has been made to solve the above-described problems. an information acquiring unit for acquiring information indicating that each of the semiconductor chips obtained is a non-defective chip; wherein the number of non-defective chips that overlap when one of the pair of semiconductor wafers is rotated with respect to the other and stacked is maximized, A semiconductor device comprising: a rotation angle acquisition unit that acquires a rotation angle based on the information; and a stacking processing unit that stacks one of the pair of semiconductor wafers by rotating the other by the rotation angle with respect to the other. An element manufacturing system and a manufacturing method thereof. This brings about the effect of maximizing the number of overlapping non-defective chips.

Further, in this first aspect, the shape of the semiconductor chip is a shape that does not change even if it is rotated by a predetermined angle around a predetermined axis, and the rotation angle obtaining unit obtains any of the multiples of the predetermined angle. You may obtain|require it as the said rotation angle. This provides an effect that the semiconductor wafer is rotated by a rotation angle corresponding to the rotational symmetry.

Further, in this first aspect, the shape of the semiconductor chip is square, and the rotation angle obtaining section may obtain any multiple of 90 degrees as the rotation angle. This brings about the effect of stacking square semiconductor chips.

Further, in the first aspect, the semiconductor chip corresponding to the other of the pair of semiconductor wafers is formed with a predetermined number of terminals, and the one of the pair of semiconductor wafers is provided with terminals at intervals of the predetermined angle. The predetermined number of terminals may be formed, and the arrangement of the terminals associated with the one of the pair of semiconductor wafers may have a shape that does not change even if the semiconductor wafer is rotated by the predetermined angle about the predetermined axis. This brings about the effect of arranging the number of terminals corresponding to the rotational symmetry.

Further, in this first aspect, the terminals associated with the one of the pair of semiconductor wafers belong to different groups for each predetermined angle, and the semiconductor chip corresponding to the one of the pair of semiconductor wafers includes: A circuit commonly connected to the terminals at rotationally symmetrical positions of the respective groups may be further formed. This brings about an effect that the electrical connection relationship is not changed before and after rotation.

Moreover, in this first aspect, the arrangement of the terminals on the one of the pair of semiconductor wafers may be rectangular. This brings about the effect that the terminals in the rectangular array are connected to the signal lines.

Moreover, in this first side surface, the terminals on the one of the pair of semiconductor wafers may be arranged in a cross shape. This provides an effect that the terminals arranged in a cross shape are connected to the signal lines.

Moreover, in this first side surface, the arrangement of the terminals related to the one of the pair of semiconductor wafers may be an oblique cross shape. This brings about the effect that the terminals arranged in the oblique cross shape are connected to the signal lines.

Moreover, in this first aspect, the arrangement of the terminals on the one of the pair of semiconductor wafers may be circular. This brings about the effect that the terminals arranged in a circle are connected to the signal lines.

Also, on the first side surface, a notch may be formed at the specific location of the one of the pair of semiconductor wafers. This has the effect of rotating the semiconductor wafer at the angle formed by the line segment from the notch to the center.

Moreover, in this first aspect, the arrangement of the plurality of semiconductor chips may have a shape that does not change even if it is rotated by a predetermined angle around a predetermined axis. This brings about the effect of stacking semiconductor wafers in which semiconductor chips are arranged in a rotationally symmetrical shape.

Moreover, in this first side surface, one of the plurality of semiconductor chips may be arranged at the center of each of the pair of semiconductor wafers. This brings about the effect of increasing the number of semiconductor chips per semiconductor wafer.

Moreover, in this first aspect, each of the plurality of semiconductor chips need not be positioned at the center of each of the pair of semiconductor wafers. This brings about the effect that the positions of all the semiconductor chips change when they are rotated.

In the first aspect, an inspection unit that inspects whether the measured value is within the predetermined range and outputs a determination result, and an external unit that generates and holds the information based on the inspection result. A database may further be provided. This brings about the effect of obtaining information on non-defective products and defective products from the external database.

A second aspect of the present technology includes a first semiconductor chip having a shape that does not change even if a predetermined number of terminals are arranged and rotated by a predetermined angle around a predetermined axis, and is stacked on the first semiconductor chip, and a second semiconductor chip on which the predetermined number of terminals are arranged at every predetermined angle. As a result, a semiconductor element is manufactured by a manufacturing system that rotates and stacks semiconductor wafers.

It is a block diagram showing an example of 1 composition of a manufacturing system in an embodiment of this art. It is a block diagram which shows one structural example of the upper wafer production|production part in embodiment of this technique, and a lower wafer production|production part. It is a figure which shows an example of non-defective product/defective product information in embodiment of this technique. It is a block diagram which shows one structural example of the lamination wafer manufacturing part in embodiment of this technique. It is an example of a top view of an upper wafer before and after inspection in an embodiment of this art. It is an example of a top view of a lower wafer before and after inspection in an embodiment of this art. It is an example of a plan view of wafers before and after stacking when the rotation angle is 0 degrees in the embodiment of the present technology. It is an example of a plan view of wafers before and after stacking when the rotation angle is 90 degrees in the embodiment of the present technology. It is an example of a plan view of wafers before and after stacking when the rotation angle is 180 degrees in the embodiment of the present technology. It is an example of a plan view of wafers before and after stacking when the rotation angle is 270 degrees in the embodiment of the present technology. It is a figure showing an example of lamination structure of a semiconductor element in an embodiment of this art. It is an example of a top view of an upper chip in an embodiment of this art. It is an example of a top view of a lower chip in an embodiment of this art. It is an example of the top view of the lower chip|tip which changed the arrangement|sequence of the pad in embodiment of this technique. It is a flow chart which shows an example of operation of a manufacturing system in an embodiment of this art. 6 is a flowchart showing rotation angle calculation processing according to the embodiment of the present technology; It is an example of a top view of an upper wafer in a modification of an embodiment of this art.

Hereinafter, a form for carrying out the present technology (hereinafter referred to as an embodiment) will be described. Explanation will be given in the following order.
1. Embodiment (example of stacking by rotating the lower chip)
2. Modification

<1. First Embodiment>
[Configuration example of manufacturing system]
FIG. 1 is a block diagram showing one configuration example of a manufacturing system according to an embodiment of the present technology. This manufacturing system is a system for manufacturing stacked semiconductor devices, and includes an upper wafer manufacturing section 110 , a lower wafer manufacturing section 120 , an external database 130 and a stacked wafer manufacturing section 200 .

A semiconductor device manufactured by a manufacturing system is a stack of a plurality of (for example, two) semiconductor chips, one of which is hereinafter referred to as an "upper chip" and the other as a "lower chip". . Also, the upper chip and the lower chip are formed on different semiconductor wafers. A semiconductor wafer on which upper chips are formed is hereinafter referred to as an "upper wafer", and a semiconductor wafer on which lower chips are formed is hereinafter referred to as a "lower wafer".

The upper wafer manufacturing section 110 manufactures upper wafers. The upper wafer manufacturing unit 110 manufactures a semiconductor wafer on which a plurality of upper chips are formed as an upper wafer, and assigns wafer identification information each time an upper wafer is manufactured. Also, the upper wafer manufacturing unit 110 measures the physical and electrical characteristics of each upper chip. The physical properties are, for example, the layer thickness of the wiring layer of the semiconductor chip, the width of the wiring, and the density of lattice defects. The electrical characteristics are, for example, the current value, voltage value and frequency characteristics of the circuit formed on the semiconductor chip.

Then, the upper wafer manufacturing unit 110 inspects each upper chip whether the measured values of the physical and electrical characteristics are within a predetermined range for the chip to operate normally. If the measured value is outside the predetermined range, then the chip is determined to be defective, and if it is within the predetermined range, the chip is determined to be good. Hereinafter, a defective semiconductor chip will be referred to as a "defective chip", and a non-defective semiconductor chip will be referred to as a "non-defective chip". Upper wafer manufacturing unit 110 transmits the inspection results to external database 130 . Further, the upper wafer manufacturing section 110 supplies the manufactured upper wafer to the laminated wafer manufacturing section 200 .

The lower wafer manufacturing section 120 manufactures a lower wafer. The lower wafer manufacturing unit 120 manufactures a semiconductor wafer on which a plurality of lower chips are formed as a lower wafer, and assigns wafer identification information each time a lower wafer is manufactured. In addition, the lower wafer manufacturing unit 120 measures the physical and electrical characteristics of each lower chip, inspects each upper chip to see if the measured values are within a predetermined range, and stores the inspection results in the external database 130. Send. Further, the lower wafer manufacturing section 120 supplies the manufactured lower wafer to the laminated wafer manufacturing section 200 .

The external database 130 generates non-defective product/defective product information indicating whether the chip is a defective chip or a non-defective chip for each of the upper chip and the lower chip based on the inspection results of the upper wafer and the lower wafer. to hold.

The laminated wafer production unit 200 laminates an upper wafer and a lower wafer. This laminated wafer manufacturing unit 200 acquires non-defective product/defective product information for each of the upper wafer and the lower wafer from the external database 130 . Then, based on the information, the laminated wafer production unit 200 rotates and laminates one of the upper wafer and the lower wafer (for example, the upper wafer) with respect to the other (for example, the lower wafer) to form a wafer laminated body. Supplied to subsequent manufacturing equipment. The stacked upper chip and lower chip in this wafer stack function as one stacked semiconductor element.

Although the laminated wafer production unit 200 rotates the lower wafer with respect to the upper wafer, it is also possible to rotate the upper wafer with respect to the lower wafer. Also, the upper wafer and the lower wafer are examples of a plurality of semiconductor wafers described in the claims.

FIG. 2 is a block diagram showing one configuration example of the upper wafer production unit 110 and the lower wafer production unit 120 in the embodiment of the present technology. In the figure, a is a block diagram showing a configuration example of the upper wafer manufacturing section 110, and b in the same drawing is a block diagram showing a configuration example of the lower wafer manufacturing section 120. As shown in FIG. Upper wafer manufacturing section 110 includes defect inspection section 111 and electrical inspection section 112 . On the other hand, the lower wafer manufacturing section 120 includes a defect inspection section 121 and an electrical inspection section 122 . In the figure, various manufacturing apparatuses for manufacturing the upper wafer and the lower wafer are omitted.

The defect inspection unit 111 inspects the density of each lattice defect of the upper chip. This defect inspection unit 111 supplies inspection results to the external database 130 . The electrical inspection section 112 inspects the electrical characteristics of each upper chip. This electrical inspection unit 112 supplies inspection results to the external database 130 .

The defect inspection unit 121 inspects the density of each lattice defect of the lower chip. This defect inspection unit 121 supplies inspection results to the external database 130 . The electrical inspection section 122 inspects the electrical characteristics of each lower chip. This electrical inspection unit 122 supplies inspection results to the external database 130 .

FIG. 3 is a diagram showing an example of non-defective product/defective product information according to the embodiment of the present technology. This non-defective product/defective product information includes stacking positions, wafer identification information, chip positions, and inspection results. The stacking position indicates whether the semiconductor wafer is positioned on the upper side or the lower side when stacked. Wafer identification information is identification information for identifying a semiconductor wafer. The chip position indicates the position of the semiconductor chip within the semiconductor wafer. The test result indicates the test result of the physical and electrical properties. For example, consider a case where the upper wafer manufacturing unit 110 inspects the upper chip at the chip position "L01" on the upper wafer with the upper wafer identification information "W01" and all measured values are within the normal range. In this case, the external database 130 generates and holds "Pass" indicating that the chip is a non-defective chip as the inspection result of the upper chip.

Also, consider a case where the upper wafer manufacturing unit 110 inspects the upper chip at the chip position "L02" on the upper wafer with the upper wafer identification information "W01" and any of the measured values is out of the normal range. In this case, the external database 130 generates and stores "Fail" indicating that the chip is defective as the result of inspection of the upper chip.

[Configuration example of laminated wafer manufacturing department]
FIG. 4 is a block diagram showing a configuration example of the laminated wafer production unit 200 according to the embodiment of the present technology. This laminated wafer manufacturing section 200 includes an upper wafer setting section 211 , a lower wafer setting section 212 and a pick-up arm section 220 . The laminated wafer production unit 200 also includes a non-defective/defective product information acquisition unit 230 , a rotation angle acquisition unit 240 , a lamination processing unit 250 , a transfer arm unit 260 , a pre-lamination processing unit 270 and a laminated wafer delivery unit 280 .

The upper wafer setting section 211 sets the upper wafer from the upper wafer manufacturing section 110 on the take-out arm section 220 . The lower wafer setting section 212 sets the lower wafer from the lower wafer manufacturing section 120 on the take-out arm section 220 .

The take-out arm section 220 takes out the upper wafer and the lower wafer from the set positions and supplies them to the transfer arm section 260 . The transfer arm part 260 transfers the upper wafer and the lower wafer from one end of itself to the other end.

The non-defective/defective product information acquisition unit 230 acquires non-defective/defective product information from the external database 130 . This non-defective product/defective product information acquisition unit 230 temporarily takes out the upper wafer and the lower wafer from the transfer arm unit 260 and reads the wafer identification information of those wafers. For example, the wafer identification information is written at a predetermined position on the semiconductor wafer by the upper wafer manufacturing section 110 and the lower wafer manufacturing section 120 . The non-defective/defective product information acquisition unit 230 inquires of the external database 130 about the chip positions and inspection results in the non-defective/defective product information corresponding to the read wafer identification information, and receives the information. The non-defective/defective product information acquisition unit 230 then supplies the acquired information to the rotation angle acquisition unit 240 and returns the upper wafer and the lower wafer to the transfer arm unit 260 . The non-defective product/defective product information acquisition unit 230 is an example of the information acquisition unit described in the claims.

The pre-stacking processing unit 270 performs predetermined pre-stacking processing such as cleaning on the upper wafer and the lower wafer. The pre-stacking processing unit 270 takes out the upper wafer and the lower wafer from the transfer arm unit 260 after obtaining the non-defective/defective product information, and performs pre-stacking processing on them. After processing, the pre-stacking processing section 270 returns the upper wafer and the lower wafer to the transfer arm section 260 .

The rotation angle acquisition unit 240 acquires the rotation angle that maximizes the number of non-defective chips that overlap when the lower wafer is rotated with respect to the upper wafer, based on the non-defective/defective product information. Here, as the rotation angle of the lower wafer, an angle formed by a line segment from a specific point on the periphery of the lower wafer before rotation to the center and a line segment from the specific point to the center after rotation is used. The rotation angle acquisition unit 240 supplies the acquired rotation angle to the layering processing unit 250 .

The stacking processing unit 250 rotates the lower wafer with respect to the upper wafer by the obtained rotation angle and stacks the wafers. The stacking processing unit 250 takes out the upper wafer and the lower wafer after the stacking pretreatment from the transfer arm unit 260, rotates the lower wafer, and stacks them. Then, the stacking processing section 250 returns the stacked wafer stack to the transfer arm section 260 .

The stacked wafer unloading unit 280 unloads the wafer stack from the transfer arm unit 260 to the outside.

FIG. 5 is an example of plan views of the upper wafer 510 before and after inspection in the embodiment of the present technology. In FIG. 4, a is an example of a plan view of the upper wafer 510 before defect inspection. b in the figure is an example of a plan view of the upper wafer 510 after the defect inspection, and c in the figure is an example of a plan view of the upper wafer 510 after the electrical inspection.

The shape of the upper wafer 510 is circular, and notches 512 are formed at specific locations on the outer circumference. A plurality of upper chips 511 are formed on the upper wafer 510 . The arrangement of these upper chips 511 has a shape that does not change even if it is rotated by a predetermined angle around the center axis of the upper wafer 510 . Such a characteristic that the shape does not change even if it is rotated by a predetermined angle is called rotational symmetry. A rotational symmetry that does not change when rotated by 360/n (n is an integer) degrees is called n-fold symmetry. For example, a square has the same shape when rotated 90 degrees and has 4-fold symmetry. Also, a rectangle has the same shape even if it is rotated by 180 degrees, and has 2-fold symmetry.

Also, the shape of each of the upper chips 511 is n-fold symmetrical as well as the arrangement. For example, both the arrangement of the upper chip 511 and the shape of the individual pieces have four-fold symmetry of the same shape even when rotated by 90 degrees. For example, a square chip is used as the upper chip 511 with four-fold symmetry. Further, in order to make the shape of the array of the upper chips 511 four-fold symmetrical, for example, when they are arranged in rows of i and columns of j (i and j are integers) so that the center is positioned at the center of the upper wafer 510 . In addition, an arrangement is used in which the chips (four corners, etc.) that are not located in the upper wafer 510 are eliminated. Below, the position of the semiconductor chip is represented by coordinates (i, j).

Also, the plurality of upper chips 511 are arranged such that none of the chips is positioned at the center of the upper wafer 510 . For example, i and j are set to even numbers. Such an arrangement allows all positions of the lower chip to be changed when rotated 90 degrees.

It is assumed that the upper wafer manufacturing section 110 performs a defect inspection and that the measured value at the position (1, 2) is out of the normal range. In this case, the external database 130 holds non-defective/defective product information indicating that the upper chip 511 at the position (1, 2) is a defective chip and the other chips are non-defective chips. The hatched portion of b in FIG. 10 indicates a defective chip at the end of the defect inspection.

Then, the upper wafer manufacturing unit 110 performs an electrical inspection, and assumes that the measured value at the position (2, 2) is out of the normal range. In this case, in the non-defective/defective product information, the inspection result corresponding to the upper chip 511 at the position (2, 2) is updated to information indicating that it is a defective chip. A hatched portion c in the figure indicates a defective chip at the end of the electrical test.

FIG. 6 is an example of a plan view of the lower wafer 520 before and after inspection in the embodiment of the present technology. In the figure, a is an example of a plan view of the lower wafer 520 before defect inspection. b in the figure is an example of a plan view of the lower wafer 520 after the defect inspection, and c in the figure is an example of a plan view of the lower wafer 520 after the electrical inspection.

The lower wafer 520 has the same shape and size as the upper wafer 510 . A notch 522 is also formed in the outer circumference of the lower wafer 520 . A plurality of lower chips 521 are formed on the lower wafer 520 . The shape, size and arrangement of these lower chips 521 are similar to those of the upper chips 511 . Also, the notch 512 of the upper wafer 510 and the notch 522 of the lower wafer 520 are assumed to be positioned at overlapping positions when the wafers are stacked without being rotated in the initial state.

Assume that the lower wafer manufacturing unit 120 performs a defect inspection and that the measured value at the position (3, 1) is out of the normal range. The hatched portion of b in FIG. 10 indicates a defective chip at the end of the defect inspection. Then, the lower wafer manufacturing unit 120 conducts an electrical test, and assumes that the measured value at the position (3, 2) is out of the normal range. A hatched portion c in the figure indicates a defective chip at the end of the electrical test.

Based on the positions of the defective chips illustrated in FIGS. 5 and 6, the rotation angle obtaining unit 240 obtains the rotation angle that maximizes the number of non-defective chips that overlap each other when the lower wafer is rotated with respect to the upper wafer. . This rotation angle is the angle formed by a line segment extending from a specific location (such as a notch) on the outer periphery of the lower wafer before rotation to the center and a line segment extending from that specific location (such as a notch) to the center after rotation. Candidates for the rotation angle are multiples of 360/n degrees when the shape of the semiconductor chip is n-fold symmetrical. For example, if the shape of the semiconductor chip is 4-fold symmetrical (square, etc.), 0 degrees, 90 degrees, 180 degrees, and 270 degrees, which are multiples of 90 degrees, are candidate rotation angles.

The rotation angle obtaining unit 240 obtains, for each candidate angle, the number of non-defective chips that overlap each other when rotated by that angle. Due to various factors, the position of the defective chip is not always the same for each semiconductor wafer and varies. Therefore, the number of non-defective chips that overlap may differ for each rotation angle. As described above, in a stacked semiconductor device, the plurality of stacked semiconductor chips operate cooperatively, so if one or more of them are defective, the entire semiconductor device will not operate normally. Therefore, the larger the number of non-defective chips overlapping with the defective chips, the higher the ratio of defective products after stacking, and the yield, which is the ratio of non-defective products, decreases. Conversely, the larger the number of non-defective chips overlapping other non-defective chips, the lower the ratio of defective products and the higher the yield.

FIG. 7 is an example of a plan view of wafers before and after stacking when the rotation angle is 0 degrees in the embodiment of the present technology. In the figure, a is an example of a plan view of the upper wafer 510, and b in the figure is an example of a plan view of the lower wafer 520 with a rotation angle of 0 degree. c in the same figure is an example of the top view of the semiconductor element after lamination|stacking. In addition, shaded portions in the figure indicate defective semiconductor chips or semiconductor elements.

The bad chips on the top wafer 510 are at locations (1,2) and (2,2), and the bad chips on the bottom wafer 520 are at locations (3,1) and (3,2). When laminated at a rotation angle of 0 degrees (i.e., no rotation), after lamination the defective semiconductor devices are (1,2), (2,2), (3,1) and (3, 2) position. The yield is 8/12 because 8 out of 12 are non-defective. It should be noted that the semiconductor element after this lamination is not actually manufactured, and the yield is obtained by simulation by the rotation angle acquisition unit 240 .

FIG. 8 is an example of a plan view of wafers before and after stacking when the rotation angle is 90 degrees in the embodiment of the present technology. In the figure, a is an example of a plan view of the upper wafer 510, and b in the figure is an example of a plan view of the lower wafer 520 before rotation. c in the figure is an example of a plan view of the lower wafer 520 rotated by 90 degrees. d in the figure is an example of a plan view of the semiconductor element after lamination. In addition, shaded portions in the figure indicate defective semiconductor chips or semiconductor elements.

In FIG. 8, the positions of defective chips on each of the upper wafer 510 and the lower wafer 520 before rotation are the same as in FIG. When the lower wafer 520 is rotated 90 degrees clockwise with respect to the upper wafer 510, the coordinates (3, 1) and (3, 2) of the defective chips are obtained by multiplying the rotation matrix with the coordinates of (1, 2 ) and (2,2). When the lower wafer 520 after this rotation is stacked with the upper wafer 510, the two defective chips on the upper side both overlap the defective chips on the lower side. As a result, after lamination, defective semiconductor elements are located at positions (1,2) and (2,2). Since 10 out of 12 are non-defective, the yield is 10/12.

FIG. 9 is an example of a plan view of wafers before and after lamination when the rotation angle is 180 degrees in the embodiment of the present technology. In the figure, a is an example of a plan view of the upper wafer 510, and b in the figure is an example of a plan view of the lower wafer 520 before rotation. c in the same figure is an example of a plan view of the lower wafer 520 rotated by 180 degrees. d in the figure is an example of a plan view of the semiconductor element after lamination. In addition, shaded portions in the figure indicate defective semiconductor chips or semiconductor elements.

In FIG. 9, the positions of defective chips in each of the upper wafer 510 and the lower wafer 520 before rotation are the same as in FIG. When the lower wafer 520 is rotated 180 degrees with respect to the upper wafer 510, the coordinates (3, 1) and (3, 2) of the defective chip are obtained by multiplying the rotation matrix with (2, 4) and ( 2, 3). When the lower wafer 520 after this rotation is stacked on the upper wafer 510, the defective chips on the upper and lower sides overlap good chips. As a result, after lamination, defective semiconductor elements are located at positions (1,2), (2,2), (2,4) and (2,3). The yield is 8/12 because 8 out of 12 are non-defective. It should be noted that the semiconductor element after this lamination is not actually manufactured, and the yield is obtained by simulation by the rotation angle acquisition unit 240 .

FIG. 10 is an example of a plan view of wafers before and after stacking when the rotation angle is 270 degrees in the embodiment of the present technology. In the figure, a is an example of a plan view of the upper wafer 510, and b in the figure is an example of a plan view of the lower wafer 520 before rotation. c in the figure is an example of a plan view of the lower wafer 520 rotated by 270 degrees. d in the figure is an example of a plan view of the semiconductor element after lamination. In addition, shaded portions in the figure indicate defective semiconductor chips or semiconductor elements.

In FIG. 10, the positions of defective chips in each of the upper wafer 510 and the lower wafer 520 before rotation are the same as in FIG. When the lower wafer 520 is rotated 270 degrees clockwise with respect to the upper wafer 510, the coordinates (3, 1) and (3, 2) of the defective chip are multiplied by the rotation matrix to obtain (4, 3 ) and (3,3). When the lower wafer 520 after this rotation is stacked on the upper wafer 510, the defective chips on the upper and lower sides overlap good chips. As a result, after lamination, defective semiconductor elements are located at positions (1,2), (2,2), (4,3) and (3,3). The yield is 8/12 because 8 out of 12 are non-defective. It should be noted that the semiconductor element after this lamination is not actually manufactured, and the yield is obtained by simulation by the rotation angle acquisition unit 240 .

As illustrated in FIGS. 7 to 10, changing the rotation angle changes the position of the defective chip. Therefore, the number of non-defective chips that are overlapped changes depending on the rotation angle, and the yield also changes. 7 to 10, the yield is 8/12 when the rotation angles are 0 degrees, 180 degrees and 270 degrees, whereas the yield is 10/12 when the rotation angle is 90 degrees. Therefore, the rotation angle acquisition unit 240 acquires 90 degrees as the rotation angle that maximizes the yield. Then, the subsequent stacking processing section 250 rotates the lower wafer 520 by 90 degrees with respect to the upper wafer 510 and stacks those wafers. As a result, the yield can be improved as compared to the case of no rotation, that is, the case of the rotation angle being 0 degrees.

Note that the stacking processing unit 250 stacks two wafers, the upper wafer 510 and the lower wafer 520, but it is also possible to stack three or more wafers. When stacking three or more sheets, the stacking processing section 250 may rotate two of the three sheets with respect to the remaining one sheet. Moreover, although the shape of each of the semiconductor chips of the upper chip 511 and the lower chip 521 is square, it is not limited to a square as long as it has rotational symmetry. For example, the shape of the semiconductor chip may be a rectangle with two-fold symmetry.

FIG. 11 is a diagram illustrating an example of a laminated structure of a semiconductor element according to an embodiment of the present technology; Solid-state imaging devices, for example, are manufactured as semiconductor devices. This solid-state imaging device has a lower chip 521 and an upper chip 511 stacked on the lower chip 521 . These chips are electrically connected through connections such as vias. In addition to vias, connection can also be made by inductive coupling communication techniques such as Cu--Cu bonding, bumps, and TCI (ThruChip Interface). Moreover, although the manufacturing system manufactures the solid-state imaging device by lamination, it is also possible to manufacture semiconductor devices other than the solid-state imaging device by lamination.

[Configuration example of upper chip]
FIG. 12 is an example of a plan view of the upper chip 511 according to the embodiment of the present technology. The upper chip 511 is provided with a pixel array section 310 and m (m is an integer) pads 321 . A plurality of pixels 311 are arranged in a two-dimensional grid in the pixel array section 310 .

Each of the m pads 321 is arranged in a line along one of the four sides of the upper chip 511 . These pads are used as terminals for electrical connection with the lower chip 521 . Note that the pad 321 is an example of the "terminal" described in the claims.

The pixel 311 generates a pixel signal according to the amount of light by photoelectric conversion. A plurality of drive lines and one vertical signal line are wired to each of the pixels 311 . The drive lines are signal lines through which drive signals for driving the pixels 311 are transmitted, and the vertical signal lines are signal lines through which generated pixel signals are transmitted. These signal lines are connected to pads 321 different from each other. For example, one of the drive lines of the pixel 311 with coordinates (0, 0) is connected to the pad 321 (that is, terminal) with pad number "1". Also, one of the drive lines of the pixel 311 with the coordinates (0, 1) is connected to the pad 321 with the pad number "2". The other drive lines and vertical signal lines of the pixel 311 with coordinates (0, 0) and the other drive lines and vertical signal lines of the pixel 311 with coordinates (0, 1) are connected to pad numbers "3" and later. It is connected to pad 321 .

Note that the upper chip 511 is an example of the first semiconductor chip described in the claims.

[Configuration example of lower chip]
FIG. 13 is an example of a plan view of the lower chip 521 according to the embodiment of the present technology. A circuit arrangement portion 330 is arranged in the lower chip 521 . Further, the shape of the semiconductor chip is assumed to be n-fold symmetrical, and m pads 322 are arranged at intervals of 360/n degrees (for example, 90 degrees) around the circuit arrangement portion 330 . If the semiconductor chip is a square with four-fold symmetry, a total of 4×m pads 322 are arranged. If the semiconductor chip is a rectangle with two-fold symmetry, a total of 2×m pads 322 are arranged. A drive circuit 331 , a control circuit 332 , a signal processing circuit 333 and a DAC (Digital to Analog Converter) 334 are arranged in the circuit arrangement section 330 , for example.

The drive circuit 331 drives each pixel 311 . The signal processing circuit 333 processes pixel signals from each of the pixels 311 . For example, AD conversion processing is executed to generate a digital signal by counting the time until the comparison result between the analog pixel signal and the ramp signal is inverted.

The DAC 334 generates a ramp signal by DA conversion and supplies it to the signal processing circuit 333 . The control circuit 332 controls the drive circuit 331 , the signal processing circuit 333 and the DAC 334 .

Also, each of the pads 322 belongs to a different group every 360/n degrees. If the semiconductor chip is a square with four-fold symmetry, the 4×m pads 322 are divided into four groups of m each. Each of the four groups is arranged along different sides of the lower chip 521, and has a square shape. Also, the same pad number is assigned to the pads 322 having the same relative position (in other words, rotationally symmetrical positions) in each group. Therefore, rotating a pad with a specific pad number (such as "1") in one group by 360/n degrees (such as 90 degrees) rotates the same pad number (such as "1") in another group. pad.

The drive circuit 331 is commonly connected to the pads 322 having the same relative position (for example, pad number "1") in each group. When there are four groups, the drive circuit 331 is commonly connected to four pads 322 having the same pad number. The drive circuits 331 drive the corresponding pixels 311 through their pads 322 . Similarly, the signal processing circuit 333 is also connected to pads having the same pad number in each group, and processes pixel signals from these pads.

By arranging m pads on the lower chip 521 every 90 degrees as illustrated in FIG. , can be connected to pads 321 at corresponding positions on the upper chip 511 . For example, the pad number “1” of the upper chip 511 is connected to the pad number “1” of any one of the four groups in the lower chip 521 . As a result, the electrical connection relationship between the circuits in the upper chip 511 and the circuits in the lower chip 521 is not changed before and after rotation. Therefore, it is possible to prevent the electrical connection from being changed due to the rotation of the lower chip 521, thereby preventing normal operation.

Note that the lower chip 521 is an example of the second semiconductor chip described in the claims. Also, although the pads 322 of the lower chip 521 are arranged in a square shape, the shape of the arrangement of the pads 322 is not limited to a square as long as it is n-fold symmetrical (eg, 4-fold symmetrical). For example, it may be a cross shape as illustrated in a in FIG. 14, or an oblique cross shape as illustrated in b in the same figure. Moreover, it may be circular as illustrated in c in the figure.

FIG. 15 is a flow chart showing an example of the operation of the manufacturing system according to the embodiment of the present technology. This operation is started, for example, when manufacturing a laminated semiconductor device is instructed.

The upper wafer manufacturing unit 110 in the manufacturing system manufactures one lot of the upper wafer 510 and sets it as an upper wafer lot in the laminated wafer manufacturing unit 200 (step S901). Further, the lower wafer manufacturing section 120 manufactures one lot of the lower wafers 520 and sets them as a lower wafer lot in the laminated wafer manufacturing section 200 (step S902).

Then, the laminated wafer manufacturing section 200 executes rotation angle calculation processing for calculating an appropriate rotation angle (step S910), and performs lamination preprocessing (step S903).

The laminated wafer manufacturing unit 200 determines whether or not the calculated rotation angle is greater than 0 degrees (step S904). If the rotation angle is greater than 0 degrees (step S904: Yes), the laminated wafer manufacturing unit 200 rotates the lower wafer with respect to the upper wafer by the calculated rotation angle (step S905). If the rotation angle is 0 degrees (step S904: No), or after step S905, the laminated wafer production unit 200 measures the position of the lower wafer (step S906), The wafer is aligned (step S907).

Subsequently, the laminated wafer production unit 200 laminates the upper wafer on the lower wafer after alignment (step S908), and delivers the wafer laminated body (step S909). After step S909, the manufacturing system ends the operation for manufacturing stacked wafers.

FIG. 16 is a flowchart showing rotation angle calculation processing according to the embodiment of the present technology. The laminated wafer production unit 200 acquires non-defective/defective product information for each of the upper wafer and the lower wafer from the external database 130 (step S911). Then, based on the non-defective/defective product information, the laminated wafer manufacturing unit 200 calculates the rotation angle that maximizes the number of non-defective chips that overlap when stacked (step S912). After step S912, the laminated wafer manufacturing section 200 ends the rotation angle calculation process.

The combination of the lot on the upper side and the lot on the lower side may be fixed, or may be changed to a combination different from that at the start of manufacturing based on the non-defective product/defective product information. In the latter case, before the upper and lower wafers are set in the laminated wafer manufacturing section 200 of FIG. Then, the laminated wafer manufacturing section 200 executes the rotation angle calculation processing shown in FIG. A combination of upper and lower wafers is obtained. Then, by combining them, manufacturing of the stacked semiconductor device is started. Thereby, the yield can be further improved.

As described above, according to the first embodiment of the present technology, since the lower wafer is rotated with respect to the upper wafer by a rotation angle that maximizes the number of overlapping non-defective chips, the number of overlapping non-defective chips is increased. can be maximized to improve yield.

<2. Variation>
In the above-described embodiments, a plurality of semiconductor chips are arranged so that the semiconductor chips are not positioned in the center of the semiconductor wafer. may not be possible. The manufacturing system of the modification of this embodiment differs from the embodiment in that the number of semiconductor chips per semiconductor wafer is increased by arranging one of the semiconductor chips at the center of the semiconductor wafer.

FIG. 17a is an example of a plan view of the upper wafer 510 in the modified example of the embodiment of the present technology. The upper wafer 510 of the modification of this embodiment differs from the embodiment in that a plurality of upper chips 511 are arranged such that any one of the upper chips 511 is positioned at the center. For example, if the row number i and the column number j of the semiconductor chips are odd numbers, one of the upper chips 511 can be placed in the center of the upper wafer 510 . With such an arrangement, the number of upper chips 511 per upper wafer 510 can be increased compared to the embodiment.

For example, assume that the diameter of the semiconductor wafer is "6", the semiconductor chips are squares each side of which is "1", and the semiconductor chips are arranged in a two-dimensional grid with no space between them for the sake of simplicity of explanation. think. If the numbers of rows and columns are even numbers as in the embodiment, a maximum of 16 semiconductor chips of 4 rows×4 columns can be arranged as illustrated in b in FIG. On the other hand, if the numbers of rows and columns are odd numbers as in the modified example of the embodiment, a maximum of 21 semiconductor chips can be arranged as illustrated in c in FIG.

The arrangement of the lower chips 521 on the lower wafer 520 is also the same as that of the upper chips 511 .

As described above, according to the modification of the embodiment of the present technology, since a plurality of semiconductor chips are arranged such that one of the semiconductor chips is positioned at the center of the semiconductor wafer, the number of semiconductor chips per semiconductor wafer can be reduced. can be increased.

In addition, the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the scope of claims have corresponding relationships. Similarly, the matters specifying the invention in the scope of claims and the matters in the embodiments of the present technology with the same names have corresponding relationships. However, the present technology is not limited to the embodiments, and can be embodied by various modifications to the embodiments without departing from the scope of the present technology.

It should be noted that the effects described in this specification are only examples and are not limited, and other effects may be provided.

Note that the present technology can also have the following configuration.
(1) an information acquiring unit that acquires information indicating, as a non-defective chip, each of a plurality of semiconductor chips formed on each of a plurality of semiconductor wafers and for which a measurement value within a predetermined range is measured;
Among the rotation angles formed by a line segment from a specific point on the periphery of one of the plurality of semiconductor wafers to the center before rotation and a line segment from the specific point to the center after rotation, the a rotation angle acquisition unit configured to acquire, based on the information, the rotation angle at which the number of non-defective chips that overlap when one of the pair of semiconductor wafers is rotated with respect to the other and stacked is maximized;
A semiconductor device manufacturing system, comprising: a stacking processing unit that stacks one of the pair of semiconductor wafers by rotating the other by the rotation angle.
(2) the shape of the semiconductor chip is a shape that does not change even if it is rotated by a predetermined angle around a predetermined axis;
The manufacturing system according to (1), wherein the rotation angle obtaining unit obtains one of the multiples of the predetermined angle as the rotation angle.
(3) the semiconductor chip has a square shape;
The manufacturing system according to (2), wherein the rotation angle obtaining unit obtains any multiple of 90 degrees as the rotation angle.
(4) a predetermined number of terminals are formed on the semiconductor chip corresponding to the other of the pair of semiconductor wafers;
said one of said pair of semiconductor wafers is provided with said predetermined number of terminals at said predetermined angle;
The manufacturing system according to (2) or (3), wherein the arrangement of the terminals associated with the one of the pair of semiconductor wafers has a shape that does not change even if it is rotated by the predetermined angle around the predetermined axis.
(5) the terminals associated with the one of the pair of semiconductor wafers belong to different groups for each of the predetermined angles;
5. The manufacturing system according to claim 4, wherein said semiconductor chip corresponding to said one of said pair of semiconductor wafers is further formed with a circuit commonly connected to said terminals at rotationally symmetrical positions of each of said groups.
The manufacturing system according to (4) above.
(6) The manufacturing system according to (4) or (5), wherein the arrangement of the terminals associated with the one of the pair of semiconductor wafers is rectangular.
(7) The manufacturing system according to (4) or (5), wherein the terminals on the one of the pair of semiconductor wafers are arranged in a cross shape.
(8) The manufacturing system according to (4) or (5), wherein the terminals on the one of the pair of semiconductor wafers are arranged in an oblique cross shape.
(9) The manufacturing system according to (4) or (5), wherein the arrangement of the terminals associated with the one of the pair of semiconductor wafers is circular.
(10) The manufacturing system according to any one of (1) to (9), wherein a notch is formed at the specific location of the one of the pair of semiconductor wafers.
(11) The manufacturing system according to any one of (1) to (10), wherein the arrangement of the plurality of semiconductor chips has a shape that does not change even if it is rotated by a predetermined angle around a predetermined axis.
(12) The manufacturing system according to (11), wherein one of the plurality of semiconductor chips is arranged at the center of each of the pair of semiconductor wafers.
(13) The manufacturing system according to (11), wherein each of the plurality of semiconductor chips is not positioned at the center of each of the pair of semiconductor wafers.
(14) an inspection unit that inspects whether the measured value is within the predetermined range and outputs a determination result;
The manufacturing system according to any one of (1) to (13), further comprising an external database that generates and holds the information based on the inspection results.
(15) a first semiconductor chip in which a predetermined number of terminals are arranged and whose shape does not change even if it is rotated by a predetermined angle around a predetermined axis;
and a second semiconductor chip stacked on the first semiconductor chip and having the predetermined number of terminals arranged at the predetermined angle.
(16) an information acquisition procedure for acquiring information indicating, as non-defective chips, each of a plurality of semiconductor chips formed on each of a plurality of semiconductor wafers, for which a measurement value within a predetermined range has been measured;
Of the rotation angles formed by a line segment from a specific point on the periphery of one of the plurality of semiconductor wafers to the center before rotation and a line segment from the specific point to the center after rotation, the a rotation angle acquiring step for acquiring the rotation angle at which the number of the non-defective chips that overlap when the one of the pair of semiconductor wafers is rotated with respect to the other and stacked is maximized based on the information;
and a lamination processing procedure for laminating the one of the pair of semiconductor wafers by rotating the other by the rotation angle.

110 upper wafer production unit 111, 121 defect inspection unit 112, 122 electrical inspection unit 120 lower wafer production unit 130 external database 200 laminated wafer production unit 211 upper wafer setting unit 212 lower wafer setting unit 220 take-out arm unit 230 non-defective product/defective product Information Acquisition Unit 240 Rotation Angle Acquisition Unit 250 Lamination Processing Unit 260 Transfer Arm Unit 270 Lamination Pretreatment Unit 280 Laminated Wafer Dispensing Unit 310 Pixel Array Unit 311 Pixels 321, 322 Pads 330 Circuit Layout Unit 331 Drive Circuit 332 Control Circuit 333 Signal Processing Circuit 334 DACs
510 upper wafer 511 upper chip 512, 522 notch 520 lower wafer 521 lower chip

Claims (15)

an information acquisition unit configured to acquire information indicating, as a non-defective chip, each of a plurality of semiconductor chips formed on each of a plurality of semiconductor wafers, for which a measurement value within a predetermined range has been measured;
Among the rotation angles formed by a line segment from a specific point on the periphery of one of the plurality of semiconductor wafers to the center before rotation and a line segment from the specific point to the center after rotation, the a rotation angle acquisition unit configured to acquire, based on the information, the rotation angle at which the number of non-defective chips that overlap when one of the pair of semiconductor wafers is rotated with respect to the other and stacked is maximized;
A semiconductor device manufacturing system, comprising: a stacking processing unit that stacks one of the pair of semiconductor wafers by rotating the other by the rotation angle. the shape of the semiconductor chip is a shape that does not change even if it is rotated by a predetermined angle around a predetermined axis;
2. The manufacturing system according to claim 1, wherein the rotation angle obtaining unit obtains one of multiples of the predetermined angle as the rotation angle. The semiconductor chip has a square shape,
3. The manufacturing system according to claim 2, wherein the rotation angle obtaining unit obtains one of multiples of 90 degrees as the rotation angle. a predetermined number of terminals are formed on the semiconductor chip corresponding to the other of the pair of semiconductor wafers;
said one of said pair of semiconductor wafers is provided with said predetermined number of terminals at said predetermined angle;
3. The manufacturing system according to claim 2, wherein the arrangement of said terminals associated with said one of said pair of semiconductor wafers has a shape that does not change even if it is rotated by said predetermined angle around said predetermined axis. the terminals associated with the one of the pair of semiconductor wafers belong to different groups for each predetermined angle;
5. The manufacturing system according to claim 4, wherein said semiconductor chip corresponding to said one of said pair of semiconductor wafers is further formed with a circuit commonly connected to said terminals at rotationally symmetrical positions of each of said groups. 5. The manufacturing system according to claim 4, wherein the arrangement of said terminals associated with said one of said pair of semiconductor wafers is rectangular. 5. The manufacturing system according to claim 4, wherein the arrangement of the terminals associated with the one of the pair of semiconductor wafers is cross-shaped. 5. The manufacturing system according to claim 4, wherein the arrangement of said terminals associated with said one of said pair of semiconductor wafers is an oblique cross. 5. The manufacturing system according to claim 4, wherein the arrangement of said terminals associated with said one of said pair of semiconductor wafers is circular. 2. The manufacturing system according to claim 1, wherein a notch is formed at said specific location on said one of said pair of semiconductor wafers. 2. The manufacturing system according to claim 1, wherein the arrangement of the plurality of semiconductor chips has a shape that does not change even if it is rotated by a predetermined angle around a predetermined axis. 12. The manufacturing system according to claim 11, wherein one of said plurality of semiconductor chips is arranged at the center of each of said pair of semiconductor wafers. 12. The manufacturing system according to claim 11, wherein each of said plurality of semiconductor chips is not located at each center of said pair of semiconductor wafers. an inspection unit that inspects whether the measured value is within the predetermined range and outputs an inspection result;
2. The manufacturing system according to claim 1, further comprising an external database that generates and holds said information based on said inspection results. an information acquisition procedure for acquiring information indicating, as non-defective chips, each of a plurality of semiconductor chips formed on each of a plurality of semiconductor wafers, for which a measurement value within a predetermined range has been measured;
Among the rotation angles formed by a line segment from a specific point on the periphery of one of the plurality of semiconductor wafers to the center before rotation and a line segment from the specific point to the center after rotation, the a rotation angle acquisition procedure for acquiring the rotation angle at which the number of the non-defective chips that overlap when the one of the pair of semiconductor wafers is rotated with respect to the other and stacked is maximized based on the information;
and a lamination processing procedure for laminating the one of the pair of semiconductor wafers by rotating the other by the rotation angle.

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