TWI721424B - Space transformer, probe card, and manufacturing methods thereof - Google Patents
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本發明是關於一種空間轉換器、探針卡及其製造方法。The invention relates to a space converter, a probe card and a manufacturing method thereof.
傳統的積體電路晶片的製造方法是先在晶圓上形成多個晶粒,然後將晶圓進行切割而形成多個獨立的晶粒,各個獨立的晶粒再分別予以封裝而成。晶粒本身依據功能的不同而可以有不同的尺寸,功能複雜的晶粒的尺寸通常比較大,晶粒上的接觸點的數量也較多,因此接觸點的間距通常甚窄。功能較簡單的晶粒上的接觸點雖然較少,但因為晶粒的尺寸也比較小,因此接觸點的間距也同樣甚窄。因此,一般的晶粒難以與電路板直接進行電性連接。The traditional manufacturing method of integrated circuit chips is to first form a plurality of dies on the wafer, and then cut the wafer to form a plurality of independent dies, and then each independent dies are packaged separately. The crystal grains can have different sizes depending on their functions. The size of the crystal grains with complex functions is usually larger, and the number of contact points on the crystal grains is also large, so the distance between the contact points is usually very narrow. Although there are fewer contact points on a die with a simpler function, because the size of the die is also relatively small, the distance between the contact points is also very narrow. Therefore, it is difficult for the general die to directly electrically connect with the circuit board.
為了讓晶粒中的電路能夠和電路板進行電性連接,必須將晶粒上的接觸點的空間分布予以放大,此步驟稱之為空間轉換(space transform)。空間轉換通常是透過將晶粒焊接於積體電路載板上來實現。積體電路載板具有上表面與下表面,其上表面之上接觸點的空間分布與對應晶粒的接觸點的空間分布相同,下表面之下接觸點的分布則較為寬裕,上表面與下表面之間則存在一電路布局將上表面之上接觸點與下表面之下接觸點予以電性連接。如此一來,晶粒上的接觸點的空間分布便得以透過積體電路載板而放大。In order for the circuit in the die to be electrically connected to the circuit board, the spatial distribution of the contact points on the die must be enlarged. This step is called space transform. Space conversion is usually achieved by soldering the die to the integrated circuit carrier. The integrated circuit carrier board has an upper surface and a lower surface. The spatial distribution of the contact points on the upper surface is the same as the spatial distribution of the contact points of the corresponding die, and the distribution of the contact points under the lower surface is more generous. A circuit layout exists between the surfaces to electrically connect the contact points above the upper surface and the contact points below the lower surface. In this way, the spatial distribution of the contact points on the die can be enlarged through the integrated circuit carrier.
晶粒在與積體電路載板結合前,通常必須經過檢測程序,例如透過探針卡進行針測(probing test)。為了能夠對晶圓上的晶粒進行探測,探針卡上的探針分布也必須與晶粒上之接觸點分布相同,因此探針同樣也會有緊湊的分布。如同前面所述,晶粒上之接觸點因為緊湊分布所以難以直接與電路板電性連接,同樣地,緊湊分布的探針也會有難以直接與測試電路板進行電性連接的問題,因此探針同樣也必須經過「空間轉換器」進行空間轉換始能與測試電路板電性連接。Before the die is combined with the integrated circuit carrier board, it usually must go through a testing procedure, such as a probe test (probing test) through a probe card. In order to be able to detect the die on the wafer, the distribution of the probes on the probe card must also be the same as the distribution of the contact points on the die, so the probes will also have a compact distribution. As mentioned above, the contact points on the die are compactly distributed, so it is difficult to directly electrically connect to the circuit board. Similarly, the compactly distributed probes will also have the problem of being difficult to directly electrically connect to the test circuit board. Therefore, it is difficult to electrically connect directly to the test circuit board. The needle must also go through a "space converter" for space conversion before it can be electrically connected to the test circuit board.
空間轉換器係如同積體電路載板般具有上表面與下表面,其中與探針相連接的下表面具有與探針分布相同的緊湊的接觸點分布,朝向測試電路板的上表面則具有較寬裕的接觸點分布。空間轉換器之上表面與下表面之間同樣透過一電路布局來將上表面的接觸點與下表面的接觸點相互電性連接。The space converter has an upper surface and a lower surface like an integrated circuit carrier. The lower surface connected to the probes has the same compact contact point distribution as the probes, and the upper surface facing the test circuit board has a larger surface. Ample distribution of contact points. The upper surface and the lower surface of the space converter also electrically connect the contact points on the upper surface and the contact points on the lower surface through a circuit layout.
傳統半導體測試業者在進行探針分布的空間轉換時,均只考量空間轉換器之下表面的探針分布必須與晶粒上的接觸點分布相同,以及上表面的接觸點分布必須能夠和測試電路板進行電性連接,均未考量到空間轉換器之上下二表面之間的電路布局設計可能對晶粒電性測試表現的影響。由於晶粒必須進一步與積體電路載板連接後予以封裝成積體電路晶片,因此晶粒在進行測試時的電性表現不見得與其被封裝成積體電路晶片之後的電性表現一致。When traditional semiconductor testers perform the spatial conversion of the probe distribution, they only consider that the probe distribution on the lower surface of the space converter must be the same as the contact point distribution on the die, and the contact point distribution on the upper surface must be able to match the test circuit. The electrical connection of the board does not consider the influence of the circuit layout design between the upper and lower surfaces of the space converter on the electrical test performance of the die. Since the die must be further connected to the integrated circuit carrier and packaged into an integrated circuit chip, the electrical performance of the die during testing may not necessarily be consistent with the electrical performance after being packaged into an integrated circuit chip.
有鑑於此,本發明提出一種空間轉換器,適用於一探針卡,探針卡適用於探測包含有多個晶粒之一晶圓。各晶粒可與積體電路載板封裝成積體電路晶片,積體電路載板之上表面與下表面之間具有一電路布局。所述空間轉換器包含:一增厚層體,包含複數中間連接區塊;及一第一多層體,設置於該增厚層體之下表面,包含彼此間隔排列之複數空間轉換區塊,各該空間轉換區塊包含彼此相對之第一上接觸區與第一下接觸區,各該第一上接觸區分別電性連接於各該中間連接區塊,彼此相對之該第一上接觸區與該第一下接觸區之間具有一電路布局,且各該空間轉換區塊之電路布局相同於該積體電路載板之電路布局;相鄰二該第一下接觸區沿一軸向具有一間距D,各該第一下接觸區沿該軸向具有一寬度W,其中D=n × W,且n為大於或等於2的正整數。In view of this, the present invention proposes a space converter, which is suitable for a probe card, and the probe card is suitable for detecting a wafer containing a plurality of dies. Each die can be packaged with an integrated circuit carrier to form an integrated circuit chip, and a circuit layout is provided between the upper surface and the lower surface of the integrated circuit carrier. The space converter includes: a thickened layer body including a plurality of intermediate connecting blocks; and a first multilayer body disposed on the lower surface of the thickened layer body and including a plurality of space conversion blocks arranged at intervals, Each of the space conversion blocks includes a first upper contact area and a first lower contact area opposite to each other, each of the first upper contact areas is electrically connected to each of the intermediate connection blocks, and the first upper contact area opposite to each other There is a circuit layout between the first lower contact area, and the circuit layout of each space conversion block is the same as the circuit layout of the integrated circuit carrier; two adjacent first lower contact areas have A distance D, each of the first lower contact areas has a width W along the axial direction, where D=n×W, and n is a positive integer greater than or equal to 2.
本發明還提出一種探針卡,包含:上述空間轉換器;一電路板,設置於該增厚層體之上表面;及一探針頭,電性連接於該第一多層體之各該空間轉換區塊之第一下接觸區。The present invention also provides a probe card, including: the above-mentioned space converter; a circuit board disposed on the upper surface of the thickened layer body; and a probe head electrically connected to each of the first multilayer body The first lower contact area of the space conversion block.
本發明還提出一種空間轉換器的製造方法,所製造出的空間轉換器適用於一探針卡,該探針卡適用於探測一晶圓,該晶圓包含複數晶粒,各該晶粒可與一積體電路載板封裝成一積體電路晶片,該積體電路載板之上表面與下表面之間具有一電路布局,該方法包含:獲取該積體電路載板之電路布局;提供包含有複數中間連接區塊之一核心層體;以多層有機製程技術逐層於該核心層體之二表面分別形成一第一多層體與一第二多層體,該第一多層體包含彼此間隔排列之複數空間轉換區塊,各該空間轉換區塊包含彼此相對之第一上接觸區與第一下接觸區,各該第一上接觸區分別電性連接於各該中間連接區塊,彼此相對之該第一上接觸區與該第一下接觸區之間具有一電路布局,且各該空間轉換區塊之電路布局相同於該積體電路載板之電路布局;相鄰二該第一下接觸區沿一軸向具有一間距D,各該第一下接觸區沿該軸向具有一寬度W,其中D=n × W,且n為大於或等於2的正整數;該第二多層體包含彼此間隔排列之複數延伸電連接區塊,各該延伸電連接區塊包含彼此相對之第二上接觸區與第二下接觸區,各該第二下接觸區分別電性連接於各該中間連接區塊。The present invention also provides a method for manufacturing a space converter. The manufactured space converter is suitable for a probe card, and the probe card is suitable for detecting a wafer. The wafer includes a plurality of dies, each of which can be Packaged with an integrated circuit carrier board to form an integrated circuit chip with a circuit layout between the upper surface and the lower surface of the integrated circuit carrier, the method includes: obtaining the circuit layout of the integrated circuit carrier; There is a core layer body with a plurality of intermediate connecting blocks; a first multilayer body and a second multilayer body are formed layer by layer on the two surfaces of the core layer body by the multilayer mechanical process technology, and the first multilayer body includes A plurality of space conversion blocks arranged at intervals, each of the space conversion blocks includes a first upper contact area and a first lower contact area opposite to each other, each of the first upper contact areas is electrically connected to each of the intermediate connection blocks , There is a circuit layout between the first upper contact area and the first lower contact area opposite to each other, and the circuit layout of each space conversion block is the same as the circuit layout of the integrated circuit carrier; two adjacent ones The first lower contact area has a distance D along an axial direction, and each of the first lower contact areas has a width W along the axial direction, where D=n×W, and n is a positive integer greater than or equal to 2; The two multilayer bodies include a plurality of extended electrical connection blocks arranged at intervals, and each of the extended electrical connection blocks includes a second upper contact area and a second lower contact area opposite to each other, and each of the second lower contact areas is electrically connected to each other. Connect the blocks in each of the middle.
本發明還提出一種探針卡的製造方法,所製造出的探針卡適用於探測包含有多個晶粒的晶圓,各晶粒可與積體電路載板封裝成積體電路晶片,積體電路載板之上表面與下表面之間具有一電路布局,該方法包含:獲取該積體電路載板之電路布局;提供包含有複數中間連接區塊之一核心層體;以多層有機製程技術逐層於該核心層體之二表面分別形成一第一多層體與一第二多層體,該第一多層體包含彼此間隔排列之複數空間轉換區塊,各該空間轉換區塊包含彼此相對之第一上接觸區與第一下接觸區,各該第一上接觸區分別電性連接於各該中間連接區塊,彼此相對之該第一上接觸區與該第一下接觸區之間具有一電路布局,且各該空間轉換區塊之電路布局相同於該積體電路載板之電路布局;相鄰二該第一下接觸區沿一軸向具有一間距D,各該第一下接觸區沿該軸向具有一寬度W,其中D=n × W,且n為大於或等於2的正整數;該第二多層體包含彼此間隔排列之複數延伸電連接區塊,各該延伸電連接區塊包含彼此相對之第二上接觸區與第二下接觸區,各該第二下接觸區分別電性連接於各該中間連接區塊;電性連接一電路板於該第二多層體之各該延伸電連接區塊之第二上接觸區;及電性連接一探針頭於該第一多層體之各該空間轉換區塊之第一下接觸區。The present invention also provides a method for manufacturing a probe card. The manufactured probe card is suitable for detecting wafers containing multiple dies. Each die can be packaged with an integrated circuit carrier to form an integrated circuit chip. There is a circuit layout between the upper surface and the lower surface of the bulk circuit carrier. The method includes: obtaining the circuit layout of the integrated circuit carrier; providing a core layer body containing a plurality of intermediate connection blocks; The technology forms a first multilayer body and a second multilayer body layer by layer on the two surfaces of the core layer body. The first multilayer body includes a plurality of space conversion blocks spaced apart from each other, each of the space conversion blocks It includes a first upper contact area and a first lower contact area opposite to each other, each of the first upper contact areas is electrically connected to each of the intermediate connection areas, and the first upper contact area and the first lower contact opposite to each other There is a circuit layout between the areas, and the circuit layout of each space conversion area is the same as the circuit layout of the integrated circuit carrier; two adjacent first lower contact areas have a distance D along an axial direction, and each The first lower contact area has a width W along the axial direction, where D=n×W, and n is a positive integer greater than or equal to 2; the second multilayer body includes a plurality of extended electrical connection blocks arranged at intervals, Each of the extended electrical connection blocks includes a second upper contact area and a second lower contact area opposite to each other, each of the second lower contact areas is electrically connected to each of the intermediate connection blocks; and a circuit board is electrically connected to the The second upper contact area of each of the extended electrical connection blocks of the second multilayer body; and the first lower contact area of each of the space conversion blocks of the first multilayer body is electrically connected to a probe head.
由於上述空間轉換器的電路布局係設計成與積體電路載板的電路布局相同,使得整體測試條件更貼近晶粒被封裝成積體電路晶片時的狀態,所得到的測試結果也更貼近真實,可靠度也更高。Since the circuit layout of the above-mentioned space converter is designed to be the same as the circuit layout of the integrated circuit carrier, the overall test conditions are closer to the state when the die is packaged into an integrated circuit chip, and the test results obtained are closer to reality. , The reliability is also higher.
請參照圖1與圖2,分別為本發明之一實施例的示意圖(一)與示意圖(二),其繪示出一探針卡10,包含電路板11、電性連接於電路板11之空間轉換器13、以及電性連接於空間轉換器13之探針頭15。為方便說明空間轉換器13的結構,上述探針卡10之各元件並未按實際比例繪製。實際上電路板11的厚度大於空間轉換器13的厚度。1 and 2, respectively, a schematic diagram (a) and a schematic diagram (2) of an embodiment of the present invention, which depicts a
探針卡10適用於對晶圓90上的多個晶粒91進行針測。晶圓90經切割而得到個別的晶粒91之後,各個晶粒91可以進一步與相匹配的積體電路載板(圖未示)共同封裝成積體電路晶片。用來和晶粒91相結合的積體電路載板本身具有一電路布局,用以將積體電路載板之上表面的各個接觸點電性連接於下表面的各個接觸點。當晶粒91銲接於積體電路載板之上表面時,透過積體電路載板的空間轉換,晶粒91便能夠以具有較寬裕空間分布之積體電路載板之下表面的接觸點來與外界的電路板作電性連接。The
空間轉換器13包含增厚層體20與第一多層體132。本實施例之增厚層體20係包含核心層體131以及第二多層體133,但在另一實施例中,增厚層體20本身係可以只包含核心層體131而沒有第二多層體133。核心層體131為一具有硬度的基材,核心層體131的硬度大於第一多層體132。核心層體131包含多個中間連接區塊1311,各個中間連接區塊1311包含有多個透過機械鑽孔方式所形成的多個電連接通道1311a。The
第一多層體132包含彼此間隔排列之複數空間轉換區塊1321,各個空間轉換區塊1321包含彼此相對之第一上接觸區132a與第一下接觸區132b。各第一上接觸區132a分別電性連接於核心層體131之各中間連接區塊1311,彼此相對之第一上接觸區132a與第一下接觸區132b之間具有一電路布局139,且各空間轉換區塊1321之電路布局139相同於積體電路載板之電路布局。但在另一實施例中,各空間轉換區塊1321之電路布局139係至少70%以上等同於積體電路載板之電路布局。之所以會有差異(小於30%)是因為在此實施例中,空間轉換區塊1321的電路布局139可以增加例如具有回授(Loopback)測試功能的電路、電容等。The
增厚層體20之第二多層體133設置於核心層體131之上表面。第二多層體133包含彼此間隔排列之複數延伸電連接區塊1331,各延伸電連接區塊1331包含彼此相對之第二上接觸區133a與第二下接觸區133b,各第二下接觸區133b分別電性連接於各中間連接區塊1311。在本實施例中,第二多層體133之上表面即相當於增厚層體20之上表面。The
以上係本發明之一實施例的空間轉換器13的具體結構,若進一步將電路板11電性連接於第二多層體133之各延伸電連接區塊1331之第二上接觸區133a,以及將探針頭15電性連接於第一多層體132之各空間轉換區塊1321之第一下接觸區132b,即構成可對晶圓90之多個晶粒91進行針測的探針卡10。The above is the specific structure of the
請進一步參照圖3與圖4,分別為本發明之一實施例的空間轉換器13的仰視圖與俯視圖。如圖3所示,空間轉換器13的相鄰二第一下接觸區132b沿一軸向(例如x軸方向)具有一間距D,各個第一下接觸區132b沿X軸向具有一寬度W,且待測晶圓上各個待測裝置(DUT, Device Under Test)之間的切割道寬度為C(圖未示),其中D = n × W + (n+1)C,且n為正整數。當n=1的時候,間距D為一個DUT的寬度(相當於第一下接觸區132b沿X軸向的寬度)W加上DUT沿X軸向二側之兩個切割道的寬度C;當n=2的時候,間距D為二個DUT的寬度加上DUT沿X軸向二側之三個切割道的寬度C,依此類推。圖3所繪示的即為n=2的實施例。之所以限定相鄰二第一下接觸區132b之間的間距D = n × W + (n+1)C,是為了因應當待測晶圓上的待測晶粒(或待測裝置)的排列甚密時,由於探針排列密度有其先天限制,因此必須採取跳DUT(Device Under Test)的測試方式。亦即位於同一軸向上之連續相鄰兩待側晶粒(甚至是連續相鄰之三個以上的晶粒)在同一測試步驟中,只有一個會被測試探針卡所測試。進一步來說,探針排列密度有其先天限制是指空間轉換器13有其先天限制,第一下接觸區132b的下接觸點1322經由空間轉換之後對應第二上接觸區133a的上接觸點1332,上接觸點1332才能與電路板11電性連接,因此每一個第一下接觸區132b需要配合一個對應的第二上接觸區133a,空間轉換器13在對應一個待測晶粒的範圍時,應該以一個空間轉換區塊1321作為考量,所以空間轉換器13在下表面必須採取跳DUT的空間佈局方式。Please further refer to FIGS. 3 and 4, which are respectively a bottom view and a top view of the
承上,倘若單就空間轉換器13本身進行觀察,可透過第一下接觸區132b的尺寸來得知DUT沿特定軸向的寬度W。但若是不知悉空間轉換器13所對應的待側晶圓的DUT圖案,仍無法得知DUT沿特定軸向二側之切割道的寬度C,也就是僅能觀察到D = n × W ,n > 1,但所屬技術領域中具有通常知識者仍可了解當知悉空間轉換器13所對應的待側晶圓的DUT沿特定軸向二側之切割道的寬度C時,D將會滿足D = n × W + (n+1)C,且n為正整數。In addition, if the
上述係本發明之一實施例的空間轉換器13的具體結構,若進一步將一電路板11電性連接於空間轉換器13之增厚層體20的上表面,以及將一探針頭15電性連接於空間轉換器13的下表面,即可構成可用來對晶圓90之多個晶粒91進行針測的探針卡10。如圖1與圖2所示,電路板11朝向空間轉換器13的表面設置有多個相對於第二上接觸區133a的上接觸點1332之電接觸點112,以及相對於第二上接觸區133a的空接觸點135之空接觸點115。相對應之上接觸點1332與電接觸點112之間可以透過錫球電性連接在一起。同樣地,探針頭15上的多根探針151也可以透過錫球個別地電性連接於相對應之第一多層體132的下接觸點1322。The above is the specific structure of the
在此需特別強調的是,本實施例之空間轉換器13的第一多層體132與第二多層體133係以MLO製程所製成,且第一多層體132之電路布局139與待測試的晶粒91所適用之積體電路載板的電路布局相同。藉此可以讓整體測試條件可以更貼近晶粒91被封裝成積體電路晶片時的狀態,所得到的測試結果也更加貼近真實,而增加測試結果的可信度。It should be particularly emphasized that the
請參照圖5,為本發明另一實施例之示意圖。在本發明之另一實施例中,第一多層體132與第二多層體133的層數相同,均包含四個基層,其中第一多層體132包含四個基層132L1~132L4,第二多層體133包含四個基層133L1~133L4。倘若第一多層體132與第二多層體133的層數不同,則空間轉換器13容易發生板翹的情況,導致上表面的上接觸點1332或者是下表面的下接觸點1322不共平面,進而造成探針卡10良率不佳或者壽命減少。此外,空間轉換器13之第二多層體133面向核心層體131之表面還可以設置有一強化層138,其可增加空間轉換器13整體的強度。當強化層138本身係使用銅或者其他導電材料製成時,在電路上還以可作為整體的接地平面(ground plane)或者電源平面(power plane)之用。除此之外,強化層138也可以改設置在背向核心層體131之表面,或者是同時設置在面向核心層體131之表面以及背向核心層體131之表面,甚至也可以設置在第二多層體133之任意二個基層之間。核心層體131係以玻璃纖維作為骨幹並填充膠體製成,因此厚度會較第一多層體132的四個基層132L1~132L4其中之一厚。Please refer to FIG. 5, which is a schematic diagram of another embodiment of the present invention. In another embodiment of the present invention, the
在本實施例中,空間轉換器13之第二多層體133的上接觸點1332定義出一上接觸點空間分布,空間轉換器13之第一多層體132的下接觸點1322則定義出一下接觸點空間分布,其中下接觸點空間分布會比上接觸點空間分布來得更密。所謂「更密」的意思是指每單位面積的接觸點的數量較多,或者是相鄰二接觸點之間的距離較近,即空間轉換器13之上接觸點空間分布在空間轉換器13的內部電路進行空間轉換成下接觸點空間分布。在本實施例中,空間轉換器13之第二多層體133的電連接通道1331a與核心層體131的電連接通道1311a均為垂直穿孔,表示在第二多層體133及核心層體131並沒有前述空間轉換的狀況,空間轉換的布局方式只有在第一多層體132發生。In this embodiment, the
請參照圖4,本實施例之探針卡10的第二上接觸區133a周圍或者是相鄰兩個第二上接觸區133a之間係為一空間間隔區133c。空間間隔區133c中可以進一步設置空接觸點135。本實施例之空接觸點135並沒有電性連接於探針卡10的測試電子迴路中,設置空接觸點135的其中一個目的是當電路板11與空間轉換器13透過錫球進行回焊(reflow)製程連接在一起時,位於空接觸點135上的錫球可作為支撐結構,也就是用來增加空間轉換器13與電路板11之間的連接界面的支撐強度。此外,也可以使各錫球平均分配應力,避免在上接觸點1332的區域內單獨過度承受應力而造成錫球破裂的情況發生。在一實施例中,空間間隔區133c除了設置空接觸點135之外,也可以視需求規劃出至少一電子元件放置區以設置IC晶片。此外,IC晶片與第二多層體133之間的電接觸點也可以包含一個以上的空接觸點135。Please refer to FIG. 4, the area around the second
請參照圖6,其繪示出一例示空間轉換器23之空接觸區233d於第二多層體233的上表面上的分布。第二多層體233包含四個第二上接觸區233a,分別對應於四個第一下接觸區232b。在此實施例中,第二多層體233的上表面包含多個(圖中為五個)空接觸區233d,每個空接觸區233d包含多個空接觸點235。如圖6所示,空接觸區233d係分別位在四個角落以及第二多層體233的上表面的重心。Please refer to FIG. 6, which shows an example of the distribution of the
請參照圖7,第二多層體233的空接觸區233d也可以個別設置在第二多層體233的上表面的重心、以及以重心為基準沿X軸向與Y軸向延伸而與第二多層體233的上表面邊緣交會的四個區塊,這些空接觸區233d的連線構成相互正交的二條直線。此外,在本實施例中,空接觸區233d的空接觸點235的間距和第二上接觸區233a的上接觸點2332的間距相同。Referring to FIG. 7, the
請參照圖8,第二多層體233的空接觸區233d除了可以設置在四個角落以及第二多層體233的上表面的重心之外,還可以同時設置在以第二多層體233的上表面的重心為基準沿X軸向與Y軸向延伸到第二多層體233的上表面的邊緣的四個區域。Referring to FIG. 8, the
在一實施例中,核心層體131與第二多層體133二者的厚度總和可以大於0.3 mm,以達到特定的結構強度。在一實施例中,第一多層體132之空間轉換區塊1321的數量係為偶數。In an embodiment, the total thickness of the
本發明之另一實施例係為上述空間轉換器13的製造方法,所述空間轉換器13的製造方法包含以下所述的步驟,但不限於必須依照以下步驟的先後順序來製造,茲說明如下。Another embodiment of the present invention is the method of manufacturing the above-mentioned
首先先取得所欲測試之晶片所使用的積體電路載板的電路布局。然後提供如圖1所示之包含有多個中間連接區塊1311之核心層體131,其中中間連接區塊1311包含有多個利用機械鑽孔方式所形成的多個電連接通道1311a。請參照圖5,利用多層有機製程技術(Multi-layer Organic, MLO)於核心層體131之二表面分別形成第一多層體132的子層132L1以及第二多層體133的子層133L1。然後利用雷射在第一多層體132的子層132L1上預備作為空間轉換區塊1321的位置形成多個穿孔,以及在第二多層體133的子層133L1上預備作為延伸電連接區塊1331的位置形成多個穿孔。然後,繼續以MLO製程形成子層132L2以及子層133L2;同樣地,也必須利用雷射在子層132L2上預備作為空間轉換區塊1321的位置形成穿孔,以及在子層133L2上預備作為延伸電連接區塊1331的位置形成多個穿孔。依此類推直到第一多層體132的層數滿足需求(例如具有四個子層132L1~132L4)以及第二多層體133的層數滿足需求(例如具有四個子層133L1~133L4)為止。其中,第一多層體132之子層132L1~132L4上的穿孔會相互連通,只要在穿孔內形成導電材質(例如銅或銀)便可形成導電線路,而每個空間轉換區塊1321之所有導電線路便構成電路布局139。同理,每個延伸電連接區塊1331也會具有多個導電線路,且每個導電線路分別連通於中間連接區塊1311之各個電連接通道1311a。First, obtain the circuit layout of the integrated circuit carrier used by the chip to be tested. Then, a
承上,所製造出的第一多層體132包含彼此間隔排列之多個空間轉換區塊1321,各空間轉換區塊1321包含彼此相對之第一上接觸區132a與第一下接觸區132b,且各個第一上接觸區132a分別電性連接於核心層體131之各中間連接區塊1311。彼此相對之第一上接觸區132a與第一下接觸區132b之間具有電路布局139。如圖3所示,相鄰二個第一下接觸區132b沿一軸向(例如x軸)具有一間距D,各第一下接觸區132b沿同一軸向具有一寬度W,其中D=n × W,且n必須是大於或等於2的正整數。此外,各空間轉換區塊1321之電路布局139必須實質相同或者至少有70%以上等同於待測晶片所搭配使用之積體電路載板的電路布局。這邊指的電路布局相同,是指客戶提供積體電路載板的電路布局,根據空間轉換器13與積體電路載板使用材料的差異,可以對阻抗線路匹配進行微調,例如線寬、線距等。In addition, the manufactured
本發明之另一實施例係為探針卡10的製造方法,所述探針卡10的製造方法除了包含上述空間轉換器13的製造方法所包含的步驟之外,還進一步包含電性連接一電路板11於空間轉換器13之第二多層體133之各延伸電連接區塊1331之第二上接觸區133a,以及電性連接一探針頭15於第一多層體132之各空間轉換區塊1321之第一下接觸區132b。Another embodiment of the present invention is a manufacturing method of the
上述各實施例包含以下共同特點:(一)空間轉換器13之相鄰二個第一下接觸區132b沿一軸向具有一間距D,各第一下接觸區132b沿同一軸向具有一寬度W,其中D=n × W,且n為大於或等於2的正整數;以及(二)各空間轉換區塊1321之電路布局139必須相同於待測試的晶粒91所搭配使用之積體電路載板的電路布局。(三)實驗顯示單純只使用第一多層體132作為空間轉換器,一旦與電路板11以BGA製程結合會有平整度不佳的情況發生。透過將第一多層體132與增厚層體20相結合,整體強度大幅上升,與電路板11以回焊製程結合後也不會發生平整度不佳的情況。The above embodiments have the following common features: (1) Two adjacent first
雖然本發明已以實施例揭露如上然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之專利申請範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be subject to the scope of the attached patent application.
10‧‧‧探針卡 11‧‧‧電路板 112‧‧‧電接觸點 115‧‧‧空接觸點 13‧‧‧空間轉換器 131‧‧‧核心層體 1311‧‧‧中間連接區塊 1311a‧‧‧電連接通道 132‧‧‧第一多層體 1321‧‧‧空間轉換區塊 132a‧‧‧第一上接觸區 132b‧‧‧第一下接觸區 1322‧‧‧下接觸點 132L1~4‧‧‧基層 133L1~4‧‧‧基層 133‧‧‧第二多層體 133a‧‧‧第二上接觸區 133b‧‧‧第二下接觸區 133c‧‧‧空間間隔區 1331‧‧‧延伸電連接區塊 1331a‧‧‧電連接通道 1332‧‧‧上接觸點 135‧‧‧空接觸點 138‧‧‧強化層 139‧‧‧電路布局 15‧‧‧探針頭 151‧‧‧探針 20‧‧‧增厚層體 23‧‧‧ 空間轉換器 232b‧‧‧第一下接觸區 233‧‧‧第二多層體 233a‧‧‧第二上接觸區 233d‧‧‧空接觸區 2332‧‧‧上接觸點 235‧‧‧空接觸點 90‧‧‧晶圓 91‧‧‧晶粒 D‧‧‧間距 W‧‧‧寬度 10‧‧‧Probe card 11‧‧‧Circuit board 112‧‧‧Electrical contact point 115‧‧‧Empty touch point 13‧‧‧Space Converter 131‧‧‧Core layer body 1311‧‧‧Intermediate connection block 1311a‧‧‧Electrical connection channel 132‧‧‧The first multi-layer body 1321‧‧‧Space Conversion Block 132a‧‧‧The first upper contact area 132b‧‧‧The first lower contact area 1322‧‧‧Lower contact point 132L1~4‧‧‧Basic level 133L1~4‧‧‧Basic level 133‧‧‧Second multilayer body 133a‧‧‧Second upper contact area 133b‧‧‧The second lower contact area 133c‧‧‧Space compartment 1331‧‧‧Extended electrical connection block 1331a‧‧‧Electrical connection channel 1332‧‧‧Upper contact point 135‧‧‧Empty touch point 138‧‧‧Strengthening layer 139‧‧‧Circuit layout 15‧‧‧Probe head 151‧‧‧Probe 20‧‧‧Thickened layer body 23‧‧‧ Space Converter 232b‧‧‧The first lower contact area 233‧‧‧Second multilayer body 233a‧‧‧Second upper contact area 233d‧‧‧Empty contact area 2332‧‧‧Upper contact point 235‧‧‧Empty touch point 90‧‧‧wafer 91‧‧‧grain D‧‧‧Pitch W‧‧‧Width
[圖1] 為本發明一實施例之示意圖(一); [圖2] 為本發明一實施例之示意圖(二); [圖3] 為本發明一實施例之空間轉換器的仰視圖; [圖4] 為本發明一實施例之空間轉換器的俯視圖; [圖5] 為本發明另一實施例之示意圖; [圖6] 為本發明之一例示空間轉換器之空接觸區的分布示意圖(一); [圖7] 為本發明之一例示空間轉換器之空接觸區的分布示意圖(二); [圖8] 為本發明之一例示空間轉換器之空接觸區的分布示意圖(三)。[Figure 1] is a schematic diagram (1) of an embodiment of the present invention; [Figure 2] is a schematic diagram (2) of an embodiment of the present invention; [Figure 3] is a bottom view of the space converter according to an embodiment of the present invention; [Figure 4] is a top view of a space converter according to an embodiment of the present invention; [Figure 5] is a schematic diagram of another embodiment of the present invention; [Figure 6] is a schematic diagram of the distribution of the empty contact area of an exemplary space converter (1) of the present invention; [Fig. 7] is a schematic diagram of the distribution of the empty contact area of an exemplary space converter of the present invention (2); [Figure 8] is a schematic diagram (3) of the distribution of the empty contact area of an exemplary space converter of the present invention.
10‧‧‧探針卡 10‧‧‧Probe card
11‧‧‧電路板 11‧‧‧Circuit board
112‧‧‧電接觸點 112‧‧‧Electrical contact point
115‧‧‧空接觸點 115‧‧‧Empty touch point
13‧‧‧空間轉換器 13‧‧‧Space Converter
131‧‧‧核心層體 131‧‧‧Core layer body
1311‧‧‧中間連接區塊 1311‧‧‧Intermediate connection block
1311a‧‧‧電連接通道 1311a‧‧‧Electrical connection channel
132‧‧‧第一多層體 132‧‧‧The first multi-layer body
1321‧‧‧空間轉換區塊 1321‧‧‧Space Conversion Block
132a‧‧‧第一上接觸區 132a‧‧‧The first upper contact area
132b‧‧‧第一下接觸區 132b‧‧‧The first lower contact area
1322‧‧‧下接觸點 1322‧‧‧Lower contact point
133‧‧‧第二多層體 133‧‧‧Second multilayer body
133a‧‧‧第二上接觸區 133a‧‧‧Second upper contact area
133b‧‧‧第二下接觸區 133b‧‧‧The second lower contact area
1331‧‧‧延伸電連接區塊 1331‧‧‧Extended electrical connection block
1331a‧‧‧電連接通道 1331a‧‧‧Electrical connection channel
1332‧‧‧上接觸點 1332‧‧‧Upper contact point
135‧‧‧空接觸點 135‧‧‧Empty touch point
139‧‧‧電路布局 139‧‧‧Circuit layout
15‧‧‧探針頭 15‧‧‧Probe head
151‧‧‧探針 151‧‧‧Probe
20‧‧‧增厚層體 20‧‧‧Thickened layer body
Claims (14)
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CN201910435481.1A CN110531125B (en) | 2018-05-23 | 2019-05-23 | Space transformer, probe card and manufacturing method thereof |
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TW107117637 | 2018-05-23 | ||
TW107117637 | 2018-05-23 |
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TW202004189A TW202004189A (en) | 2020-01-16 |
TWI721424B true TWI721424B (en) | 2021-03-11 |
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TW108116979A TWI721424B (en) | 2018-05-23 | 2019-05-16 | Space transformer, probe card, and manufacturing methods thereof |
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TW (1) | TWI721424B (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201735748A (en) * | 2016-03-18 | 2017-10-01 | Kinsus Interconnect Tech Corp | Circuit test board with high test density increasing the circuit test density by virtue of the arrangement of the conducting cones |
TWI612599B (en) * | 2017-06-28 | 2018-01-21 | 中華精測科技股份有限公司 | Testing board component and manufacturing method thereof |
TW201804576A (en) * | 2016-07-21 | 2018-02-01 | 台灣積體電路製造股份有限公司 | Integrated fan-out package |
TW201805636A (en) * | 2016-05-31 | 2018-02-16 | 巨擘科技股份有限公司 | Probe card device |
TW201837478A (en) * | 2017-04-05 | 2018-10-16 | 力成科技股份有限公司 | Chip testing method |
-
2019
- 2019-05-16 TW TW108116979A patent/TWI721424B/en active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201735748A (en) * | 2016-03-18 | 2017-10-01 | Kinsus Interconnect Tech Corp | Circuit test board with high test density increasing the circuit test density by virtue of the arrangement of the conducting cones |
TW201805636A (en) * | 2016-05-31 | 2018-02-16 | 巨擘科技股份有限公司 | Probe card device |
TW201804576A (en) * | 2016-07-21 | 2018-02-01 | 台灣積體電路製造股份有限公司 | Integrated fan-out package |
TW201837478A (en) * | 2017-04-05 | 2018-10-16 | 力成科技股份有限公司 | Chip testing method |
TWI612599B (en) * | 2017-06-28 | 2018-01-21 | 中華精測科技股份有限公司 | Testing board component and manufacturing method thereof |
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TW202004189A (en) | 2020-01-16 |
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