JP2011216703A - Wafer lamination method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming a group of one or more wafers and selecting a combination in which the number of conforming wafers is larger.SOLUTION: The wafer lamination method is a method in which a three-dimensional waver laminate is manufactured by laminating n kind(s) of wafer (n is not less than 1) in which a number of chips are integrated and a three-dimensional laminated chip is manufactured by separating the three-dimensional wafer laminate for each chip, wherein as the wafers used in lamination, one wafer is selected from wafer groups the numbers of n kind(s) of wafer of which are M1, M2, ..., Mn, and when selecting wafers, the conforming wafer pattern of each wafer is compared based on the determination of whether each chip on each wafer is conforming by the previous inspection before lamination and a combination of three-dimensional chips indicating a rate of confirming wafer patterns not less than a predefined threshold is selected.

Description

  The present invention relates to a method for improving the yield rate of a three-dimensional multilayer chip at a wafer level.

  In the wafer laminating method, n-type (here, n) wafers on which a large number of LSI chips are integrated are sequentially laminated to produce a 3D wafer laminated body, and a 3D laminated LSI is produced by separating them.

  In this 3D stacking LSI at the wafer level, stacking is performed on a wafer-by-wafer basis, so it is not possible to select and stack only the non-defective LSI contained in each wafer. And it decreases significantly. For this reason, it is necessary to consider a lamination method that improves the yield rate.

`` Handbook of 3D Integration Volume 1 '' Edited by Philip Garrou, Ghristopher Bower and Peter Ramm, WILEY-VCH, Verlag GmbH & Co. KGaA, pp225 12.1.7 Yield Issue

  An object of the present invention is to provide a method of forming a group of one or more wafers, and selecting and laminating a combination that increases the number of non-defective products.

In order to solve the above-described problems, the present invention forms a three-dimensional wafer stack by stacking n types of wafers (n is 1 or more) on which a large number of chips are integrated, and separates the chips for each chip. A wafer laminating method for producing a three-dimensional multilayer chip,
As wafers to be used for stacking, select one wafer from n, M2, M2, ... Mn wafer groups.
At the time of this selection, based on the pass / fail judgment of each chip on each wafer specified by the pre-inspection before the stacking, the non-defective product ratio of each wafer is compared with a certain threshold value and the non-defective product ratio is higher than a certain threshold value. A method for selecting a combination is provided.

The figure for demonstrating the synthetic | combination problem of LSI by lamination | stacking of two wafers. Another figure for demonstrating the synthetic | combination problem of LSI by lamination | stacking of two wafers. The figure for demonstrating selection of two wafers from one wafer group according to this invention. The figure for demonstrating the sequential selection of two wafers from one wafer group. The figure for demonstrating the optimal solution of two wafer selection from one wafer group. The figure for demonstrating the approximate solution of the two wafers from one wafer group. The figure for demonstrating selection of two wafers from two wafer groups according to this invention. The figure for demonstrating the approximate solution and optimal solution selection of two wafers from two wafer groups. The figure for demonstrating the approximate solution by the selection of four wafers from four wafer groups, and the optimal lamination example. The figure which shows the example of a method of deactivating LSI. The figure which shows the redundant system example which consists only of non-defective LSI. The figure for demonstrating the case where one wafer is each selected from several wafer groups. The figure for demonstrating the case where several wafers are selected from a certain wafer group among several wafer groups.

First, in explaining the present invention,
-A method to improve the yield rate by selecting and stacking the same type of wafers from one wafer group (wafer group) consisting of a plurality of same type wafers by an appropriate method.-Multiple wafer groups with different wafer types between groups. (Wafers in one group are the same type), a method of improving the yield rate by selecting different types of wafers from each group and laminating them by an appropriate method will be considered.

  First, it is assumed that the quality of each LSI in the wafer can be judged by the wafer-level non-defective product inspection, and the LSI judged as defective is deactivated by cutting the power fuse, that is, inoperable. It is assumed that the negative effects caused by stacking are negligible.

  Here, consider the case of stacking two wafers as shown in FIGS. Next, this is expanded to improve the yield rate when three or more wafers are stacked. Each wafer shown in FIG. 1 is printed with an LSI chip having a signal line and a power supply line formed of through vias such as TSV (Through Silicon Via) in the central region and the peripheral region, respectively. At the time of stacking, the chips of each wafer are connected in the stacking direction by these through vias to form a 3D stacked LSI.

1. Definition of non-defective product When two wafers are stacked as shown in FIGS. 1 and 2, depending on whether the upper and lower corresponding LSIs, that is, the stacked LSI x, y are non-defective products (◯) or defective products (×) The following four combinations are possible.
(X, y) = (○, ○), (○, ×), (×, ○), (×, ×)

2. 2. Combination of “two wafers” 2-1. Two “same type” LSIs are stacked and operated as one LSI.
This improves the yield rate.
in this case,
Good products are (x, y) = (○, ○), (○, ×), (×, ○)
Defective product is (x, y) = (x, x)
It becomes a combination.

2-2. Two “heterogeneous” LSIs are stacked and operated independently.
Select a wafer combination that maximizes the number of non-defective stacked LSI products.
in this case,
Good products are (x, y) = (○, ○)
Defective products are (x, y) = (○, ×), (×, ○), (×, ×)
It becomes a combination.

2-3. In the case of constructing the same type of wafer, the following is assumed here.
(1) Input / output lines and power supply lines necessary for the operation of each LSI constituting the same type of wafer are connected by through electrodes, and the two wafers can be stacked and connected. In addition, when the corresponding electrode 1 and electrode 2 are output terminals, it has a mechanism that can dynamically or statically control which value is effective. If necessary, an output control line for performing this control from the outside is used.
(2) The LSIs constituting the wafer 1 and the corresponding LSIs constituting the wafer 2, i.e., directly below, are designed and manufactured so that the size, input / output specifications, operation functions, and the like are the same. Of course, one wafer may be composed of LSIs with different circuits or LSIs with different devices, and LSIs with different functions may be mixed on one wafer. It is sufficient that the upper and lower LSIs are the same between the stacked wafers.

For example, if the non-defective product rate of LSI is α (= 0 to 1), when two wafers are stacked, the probability that both upper and lower corresponding LSIs are (A) good is α ² [0.81]
(B) The probability of a combination of good and defective products is 2α (1-α) [0.18]
(C) The probability that both are defective is (1-α) ² [0.01]
(D) The probability that at least one of them is non-defective is (2α-α ² ) [0.99]
It becomes. Values in [] are values when α = 0.9, the probability of both being 0.01 is 0.01, which is sufficient as compared with the case of one wafer, and the yield rate is improved to 0.99.

The ratio between the probability that both of the corresponding LSIs on the two wafers are defective and the failure probability of the LSI on one wafer is
(1-α) ² / (1-α) = (1-α)
It becomes. In general, when n wafers are stacked, the probability that all of the corresponding LSIs are defective is (1-α) ⁿ , and the ratio of the defect probability with one wafer is:
(1-α) ⁿ / (1-α) = (1-α) ^n-1
It becomes. For example, in the above example, if n = 3, the ratio is (1-α) ² = 0.01, and the defect probability is 1/1000.

  The above is the probability when a wafer is selected at random, but according to the present invention, the yield rate can be further improved.

3. Combination of “two wafers of the same kind” from “one wafer group” As shown in FIG. 3, the wafers of the same kind are grouped into one group, and two combinations are selected from these groups. Even in a method of selecting two, for example, at random from one group, a laminated LSI chip having a high yield rate can be obtained from a two-layer laminated wafer by laminating them. If the non-defective product rate is α, the probability that both of the corresponding LSIs are defective products is (1−α) ^2. For example, when α = 0.9, the defective product rate is improved from 0.1 to 0.01.

3-1. Random selection Let us consider the case of combining wafers without sorting. That is, an arbitrary set of wafers W1 and W2 is randomly selected from one group. When the LSIi of W1 is a non-defective product, the LSIi is activated and the LSIi corresponding to W2 is deactivated and stacked. As a result, a good product combination (◯, ×) is obtained.

3-2. Sequential selection Consider a case where a wafer W2i and a wafer W2i + 1 produced next are combined. As shown in FIG. 4, it is determined whether or not each LSI is a non-defective product by W2i wafer level inspection (step 1). In this case, for the wafer W2i, the wafer W2i obtained with the non-defective product is selected as it is, and the wafer W2i obtained with the defective product is deactivated. Next, the wafer W2i + 1 combined therewith is inspected (step 2). If the corresponding W2i LSI is a non-defective product, it is deactivated unconditionally (regardless of whether it is a non-defective product) (step 2). A good product combination (◯, ×) is obtained by stacking these layers (step 3). In this case, the W2i + 1 LSI test is not required and can be deactivated at the inspection stage, thereby reducing the number of steps. After that, the wafer is divided into LSIs, and only defective LSIs are determined as defective products in steps 1 and 2 (step 4).

3-3. Optimal Solution A method of selecting N / 2 wafer combinations from a set W of N (assumed to be even) wafers so that the non-defective product is larger than the above-described random selection or sequential selection will be described. Specifically, two wafers are taken out from the Wi set W and the number of good products is counted. Next, take out two wafers from the rest of W and count the number of good products. In such a way of taking out, a combination that maximizes the number of non-defective products is found. However, in this case, when a non-defective LSI is stacked and operated, it is necessary to deactivate one of them.

  As shown in FIG. 5, consider a complete graph with Wi (i = 1, 2,..., N) as points (nodes). The weight Gij of the side (branch) connecting Wi and Wj is the number of non-defective products (or the number of defective products) when Wi and Wj are stacked. At this time, a combination that maximizes the sum of the side weights Gij is obtained. This problem is reduced to the maximum weight matching problem for general graphs, and Edmonds et al. (J. Edmonds, "Paths, trees, and flowers, Canadian Journal of Mathematics", vol.17, pp.449-467, 1965). It is known that the number of wafers N can be solved in polynomial time.

3-4. Approximate Solution As shown in FIG. 6, as in FIG. 5, a complete graph is formed with each wafer Wi (i = 1, 2,..., N) as points, and the weight Gij of the edge connecting Wi and Wj is set to Wi. And the number of good products (or the number of defective products) when Wj is laminated, a selective solution can also be obtained approximately by the following Greedy method. In this case, there is an advantage that the amount of calculation is reduced as compared with the optimal solution.
(1) Among the edges of the complete graph, select the edge with the largest weight Gij (number of non-defective products).
(2) The nodes Wi and Wj at both ends of the selected side are removed. At this time, the remaining graphs also become complete graphs.
(3) Repeat the above until the number of sides becomes 1.

Applying to the specific example of FIG.
(1) Select the edge W2-W3 (G23 = 45) with the largest weight.
(2) Select W1-W5 (G15 = 40) with the largest weight from the complete graph composed of the remaining W1, W4, W5, and W6.
(3) Since the remaining is only one pair (W4-W6), the selection operation is terminated.

  After all the pairs are determined, for each combination of (W2-W3, W1-W5, W4-W6), in these combinations, deactivate one of the corresponding non-defective LSIs and activate the other To do.

3-5. Lamination of three or more LSI chips The method of combining two wafers described above can be applied to the case where three or more (N) LSIs are selected and laminated from one group of similar wafers. Thereby, the yield rate can be further increased. In this case, the LSI included in the group needs to be a multiple of N. Random selection can be performed without computation, but the amount of calculation is large to obtain an approximate solution or an optimal solution, and the activation / deactivation processing is complicated.

4). Combination of “two identical wafers” or “two different wafers” from “two wafer groups” Here, unlike the above-described method of acquiring a combination of two wafers from one wafer group, FIG. A method for obtaining a combination of two wafers from two wafer groups as shown in FIG.

  First, an even number of wafers are divided into two wafer groups 1 (W = {Wi}) and wafer group 2 (V = {Vi}). The W wafer Wi and the V wafer Vj may be the same type or different types (the wafers in one group are the same type), but the same algorithm can be applied. However, the definition of the non-defective product is different as shown in FIG. 1 and FIG.

In the case of the same kind,
・ When grouping, either one of groups 1 and 2 can be activated and the other can be deactivated by the method of FIG. 10 or after the combination is determined, one of the groups is activated by the method of FIG. Deactivate the other

4-1. Random selection One wafer is randomly selected from two wafer groups and stacked. In the case of the same type, the same result as the above-mentioned 3-1 is obtained, and the yield rate is improved.

4-2. Optimal solution As shown in FIG. 8, a complete bipartite graph composed of a set of wafer Wi belonging to wafer group W and wafer Vj belonging to wafer group V is synthesized, and weight G of each side is assigned to wafers at both ends of the side. The number of non-defective LSIs when combined. In the case of similar wafers Wi and Vj, at least one LSI is a non-defective product, and in the case of different types of wafers Wi and Vj, both LSIs are non-defective only.

  In this case, maximizing the number of non-defective products becomes the maximum matching problem for this graph, and can be solved by, for example, the Hungarian method (HWKuhn, "The Hungarian method for the assignment problem", Naval Research Logistics Quarterly 2, pp83- 97, 1955). In the case of the same type, when two stacked LSIs are both non-defective products, it is necessary to deactivate either one statically or dynamically.

4-3. Approximate solution The combination is determined by the approximate solution of the method (Greedy method) similar to the above-mentioned 3-4, not the optimal solution by the above-mentioned 4-2. There is an advantage that the amount of calculation can be reduced.

5. Combination of “three or more wafers” from “three or more wafer groups” Here, as shown in FIG. 9, the wafers (W1, W2,. A method for configuring a system with a high yield will be described. The chips were n stacked LSI, ¹ non-defective rate of each LSI alpha, alpha ^2, ..., when the alpha ^n, the yield rate of the chip is the product of the non-defective rate of the ^{LSI: α 1 α 2 ... α} n becomes , Significantly reduced. First, by cutting the wafer and judging the quality of each LSI, combining only good products (KGD, Known Good Device), you can get a good stacked LSI, but it is better to stack at the wafer level first. Process costs can be significantly reduced. In this case, however, the yield rate of stacked LSIs becomes a problem. For example, when each α ⁱ is 0.9 and n = 10, the non-defective product ratio is reduced to about 1/4, 0.9 ¹⁰ = approximately 0.35. According to the present invention, it is possible to improve the yield rate in the case of stacking at this wafer level.

5-1. Random selection Based on the above-described 4-1 random selection method, a random selection is adopted without obtaining a solution of the maximum matching problem among the methods for obtaining the next optimal solution.

5-2. Optimal solution An optimal solution is obtained based on the idea of dynamic programming as follows. FIG. 9 shows an optimum stacking example by selecting four wafers from four wafer groups.

  (1) A set of wafers Wi of the i-th layer is denoted as {Wi}. From the combination of {W1} and {W2}, a method for solving the maximum matching problem described in 4-2 (for example, Hungarian method) is used to obtain a combination that obtains the maximum number of non-defective products. The set obtained from this result is {W1-2}. An LSI in which a set of LSIs of W1j corresponding to each wafer of W2i and each LSI of W2i is a nondefective product is defined as a nondefective product of {W1-2}. As shown in FIG. 2, the definition of good products is different between the same type and different types.

  (2) Next, from {W1-2} and {W3}, find the combination that gives the maximum good product as in 1. This combination is denoted as {W1-2-3}. At this time, the combination of {W1-2} wafer LSI combined with each LSI of {W3} wafer is regarded as a non-defective product according to FIG. It is defined as

  (3) Repeat the above procedure until the last wafer group. The resulting combination is denoted as {W1-2 -...- m}. This combination of m layers is an optimum combination having the maximum number of non-defective products at the wafer level.

5-3. Approximate solution In the above-described 5-2, instead of obtaining the optimum solution of the maximum matching problem using, for example, the Hungarian method, the above-described approximate solution is used. Thereby, the calculation amount can be reduced.

6). Activation / Deactivation Method When stacking LSIs of the same type using the method described above, if both are defective products, the stacked LSIs are also defective products, and one is a good product and the other is a defective product. Needs to activate good products and deactivate defective products. If both are good products, one must be statically or dynamically activated and the other statically or dynamically inactivated.

In summary, the following methods can be considered.
・ Deactivate defective LSIs Turn off the power (burn out the deactivated LSI fuses). Deactivation at the inspection stage is possible.
Deactivation of non-defective LSIs (necessary only for the same type)-Permanent deactivation Figure 10A, B: Power off (Blow off the fuse connected to the power line in the LSI to be deactivated)
-Controlling activation / deactivation from outside Fig. 10B: Separate power supply connection for each LSI by blowing out the fuse, and control which LSI is utilized from outside by turning on / off the power supply 10C: Separate control lines for each LSI by power gating, control which LSI is utilized from the outside, or deactivate the power converter inside the LSI

  More specifically, FIG. 10A shows a method of activating / deactivating “statically”. In the illustrated example, the fuse 2 of the LSI to be activated is disconnected and the power source is connected through the fuse 1. . The fuse 1 of the LSI to be deactivated is disconnected and the power supply Vdd is grounded. The fuse 2 is not necessary when the power supply line is grounded with high resistance, and this control can be performed by the fuse 1 alone.

  FIG. 10B and FIG. 10C show a method of “actively” activating / deactivating. In FIG. 10B, by disconnecting the fuse 1 of one LSI and disconnecting the fuse 2 of the other LSI, the external power supply is turned off. The activity / inactivity is controlled by whether or not it is supplied. That is, one fuse is disconnected so that LSIs 1 and 2 are connected to different power sources. The same applies to FIG. 10C, but in this case, an internal power supply circuit (DC converter, power gating circuit, etc.) can be controlled by a control line, and activation / inactivation is controlled from the outside. That is, one fuse is disconnected so that the LSIs 1 and 2 are connected to different control lines.

7). Redundant system When combining wafers of the same type, it is also possible to configure and operate a redundant system in which one of the non-defective LSIs is operated and the other is a standby LSI. In particular, when the non-defective product rate is high, the number of non-defective products increases, and this method becomes more effective. The following cool standby or hot standby is conceivable for each non-defective stacked LSI capable of controlling activation / deactivation from the outside.

Cool standby:
As shown in FIGS. 11A and 11B, a set of deactivated LSI and activated LSI is formed by using the dynamic deactivation method as shown in FIGS. The activity / inactivity can be controlled. Normally, only the activated LSI operates. However, when a failure is detected, the activated / inactivated LSI is inverted using a power supply or a control line. Although power consumption is small during operation, there are disadvantages that it takes time during inversion, and it is difficult to restore register values and the like, and continuous operation cannot be guaranteed, so that it is necessary to restart.

Hot standby:
As shown in FIG. 11C, both are activated, one output line is turned on, the other is turned off (floating), and the on / off of the output line is reversed when a failure is detected. Although both of them are always operating, there is a disadvantage that the power consumption is doubled. However, there is an advantage that the same data is held in a storage device such as a register and it does not take much time to continue at the time of inversion.

8). Handling of wafers that contain a lot of non-defective products For wafers with a high non-defective product rate, that is, wafers with a good product rate exceeding a preset threshold (in the extreme case, all LSIs are non-defective wafers), the target to improve the yield rate by stacking The above method is applied to the remaining wafers to improve the yield rate.

  In this case, in a selection algorithm from a group that requires an even number of wafers, the number of remaining wafers is selected. In addition, when selecting from two or more groups, an equal number is excluded from each group.

More specifically, the following method can be considered.
(1) The threshold value α _t of the non-defective product rate to be used alone is calculated by sequentially removing wafers having a high non-defective product rate so as to be equal to or higher than the highest good product rate among the wafers obtained by the combination of the remaining wafers. In this case, after inspecting all the wafers in advance, it is necessary to execute the above-described method, and it takes a long calculation time.

(2) The threshold value α _t is set in advance. A wafer including a non-defective product that is equal to or higher than the threshold value is passed through the production line as it is in the inspection stage, and the above-described method is performed on a non-defective product having a ratio of α _t or less.

9. Improvement of non-defective product rate Improvement of the non-defective product rate according to the present invention described above is summarized as follows.
(1) A three-dimensional laminated chip is produced by sequentially laminating n types (here, n pieces) of wafers on which a large number of chips are integrated to produce a three-dimensional wafer laminated body and separating the three-dimensional wafer laminated body.
(2) The wafers used for stacking are selected one by one from the wafer groups of M1, M2, and Mn for n types.
(3) Assume that the quality of each chip on each wafer is specified by prior inspection before stacking.
(4) When all the chips stacked in the stacking direction are non-defective when the wafers are stacked, a non-defective three-dimensional stacked chip is obtained.
(5) In order to improve the non-defective product rate of the three-dimensional multilayer chip, when selecting a wafer to be used for lamination from each wafer group, the non-defective pattern of each wafer is compared and the highest three-dimensional is based on the above-described various selection methods. A three-dimensional wafer lamination is performed by calculating a combination indicating the non-defective product ratio of the laminated chips.

10. Further improvement in yield rate In the present invention described above, as illustrated in FIG. 12, when one wafer is selected from each wafer group ({W1} to {Wn}) and stacked, it is inspected in advance. Based on the information on the distribution of non-defective chips of each wafer, the combination that maximizes the non-defective product rate of the laminated wafer is selected. The non-defective product rate of this laminated wafer is the worst good product rate among the configured wafers. It is easily analogized that it is governed by the wafer it has.

  Therefore, as illustrated in FIG. 13, for the wafer group {Wi} having a non-defective product rate, that is, an average good product rate lower than a preset threshold value, a plurality of wafers Wi1 to Wij (i = The wafer group number, j = wafer number) is taken out and laminated to form a wafer laminated body {Wi1 to Wij} in which the yield rate of the wafer group (for example, W1) is increased as a whole. In selecting the wafers to be laminated from the same wafer group in this case, a wafer stack {Wi1 to Wij having a non-defective product ratio equal to or greater than a predetermined threshold value is applied by applying a sum logic of non-defective products distribution in the stacking direction. } Can be configured.

  Then, the wafer laminated body {Wi1 to Wij} composed of the selected wafers is used as one wafer of this wafer group and laminated with a wafer selected from another wafer group to obtain a final laminated wafer. The final laminated wafer configuration is {W1 to Wi-1, {Wi1 to Wij}, Wi + 1 to Wn}. Of course, if there are a plurality of wafer groups with a low yield rate, a plurality of wafers are selected for each wafer group in the same manner as described above.

  In the example of FIG. 13, two wafers {W11, W12} (W12 is denoted as W1 'in the figure) are taken out from the wafer group {W1} and other wafer groups {W2}, {W3}, {W4} Each wafer is laminated with one wafer selected from the above.

Claims (3)

Wafer lamination method for producing a three-dimensional laminated chip by laminating n types (n is 1 or more) of wafers on which a large number of chips are integrated to produce a three-dimensional wafer laminated body and separating the wafers for each chip. Because
As wafers to be used for stacking, select one wafer from n, M2, M2, ... Mn wafer groups.
At the time of this selection, based on the pass / fail judgment of each chip on each wafer specified by the pre-inspection before the stacking, the non-defective product ratio of each wafer is compared with a certain threshold value and the non-defective product ratio is higher than a threshold value How to choose a combination.   The method according to claim 1, wherein a plurality of wafers are selected from a wafer group having a non-defective product ratio below a certain threshold.   The method according to claim 2, wherein the plurality of wafers are selected so that a wafer stack having a non-defective product ratio equal to or higher than a threshold value when the plurality of wafers are stacked can be configured.